4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "disas/disas.h"
26 #include "qemu-common.h"
28 #include "qemu/bitops.h"
29 #include "exec/cpu_ldst.h"
30 #include "exec/translator.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34 #include "exec/gen-icount.h"
36 #include "trace-tcg.h"
39 #define LOG_DIS(str, ...) \
40 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \
43 /* is_jmp field values */
44 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
45 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
46 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
48 typedef struct DisasContext
{
49 DisasContextBase base
;
52 uint32_t delayed_branch
;
55 /* Include the auto-generated decoder. */
56 #include "decode.inc.c"
59 static TCGv cpu_R
[32];
62 static TCGv jmp_pc
; /* l.jr/l.jalr temp pc */
64 static TCGv cpu_sr_f
; /* bf/bnf, F flag taken */
65 static TCGv cpu_sr_cy
; /* carry (unsigned overflow) */
66 static TCGv cpu_sr_ov
; /* signed overflow */
67 static TCGv cpu_lock_addr
;
68 static TCGv cpu_lock_value
;
69 static TCGv_i32 fpcsr
;
70 static TCGv_i64 cpu_mac
; /* MACHI:MACLO */
71 static TCGv_i32 cpu_dflag
;
73 void openrisc_translate_init(void)
75 static const char * const regnames
[] = {
76 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
79 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
83 cpu_sr
= tcg_global_mem_new(cpu_env
,
84 offsetof(CPUOpenRISCState
, sr
), "sr");
85 cpu_dflag
= tcg_global_mem_new_i32(cpu_env
,
86 offsetof(CPUOpenRISCState
, dflag
),
88 cpu_pc
= tcg_global_mem_new(cpu_env
,
89 offsetof(CPUOpenRISCState
, pc
), "pc");
90 cpu_ppc
= tcg_global_mem_new(cpu_env
,
91 offsetof(CPUOpenRISCState
, ppc
), "ppc");
92 jmp_pc
= tcg_global_mem_new(cpu_env
,
93 offsetof(CPUOpenRISCState
, jmp_pc
), "jmp_pc");
94 cpu_sr_f
= tcg_global_mem_new(cpu_env
,
95 offsetof(CPUOpenRISCState
, sr_f
), "sr_f");
96 cpu_sr_cy
= tcg_global_mem_new(cpu_env
,
97 offsetof(CPUOpenRISCState
, sr_cy
), "sr_cy");
98 cpu_sr_ov
= tcg_global_mem_new(cpu_env
,
99 offsetof(CPUOpenRISCState
, sr_ov
), "sr_ov");
100 cpu_lock_addr
= tcg_global_mem_new(cpu_env
,
101 offsetof(CPUOpenRISCState
, lock_addr
),
103 cpu_lock_value
= tcg_global_mem_new(cpu_env
,
104 offsetof(CPUOpenRISCState
, lock_value
),
106 fpcsr
= tcg_global_mem_new_i32(cpu_env
,
107 offsetof(CPUOpenRISCState
, fpcsr
),
109 cpu_mac
= tcg_global_mem_new_i64(cpu_env
,
110 offsetof(CPUOpenRISCState
, mac
),
112 for (i
= 0; i
< 32; i
++) {
113 cpu_R
[i
] = tcg_global_mem_new(cpu_env
,
114 offsetof(CPUOpenRISCState
,
121 static void gen_exception(DisasContext
*dc
, unsigned int excp
)
123 TCGv_i32 tmp
= tcg_const_i32(excp
);
124 gen_helper_exception(cpu_env
, tmp
);
125 tcg_temp_free_i32(tmp
);
128 static void gen_illegal_exception(DisasContext
*dc
)
130 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
131 gen_exception(dc
, EXCP_ILLEGAL
);
132 dc
->base
.is_jmp
= DISAS_NORETURN
;
135 /* not used yet, open it when we need or64. */
136 /*#ifdef TARGET_OPENRISC64
137 static void check_ob64s(DisasContext *dc)
139 if (!(dc->flags & CPUCFGR_OB64S)) {
140 gen_illegal_exception(dc);
144 static void check_of64s(DisasContext *dc)
146 if (!(dc->flags & CPUCFGR_OF64S)) {
147 gen_illegal_exception(dc);
151 static void check_ov64s(DisasContext *dc)
153 if (!(dc->flags & CPUCFGR_OV64S)) {
154 gen_illegal_exception(dc);
159 /* We're about to write to REG. On the off-chance that the user is
160 writing to R0, re-instate the architectural register. */
161 #define check_r0_write(reg) \
163 if (unlikely(reg == 0)) { \
168 static inline bool use_goto_tb(DisasContext
*dc
, target_ulong dest
)
170 if (unlikely(dc
->base
.singlestep_enabled
)) {
174 #ifndef CONFIG_USER_ONLY
175 return (dc
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
181 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
183 if (use_goto_tb(dc
, dest
)) {
184 tcg_gen_movi_tl(cpu_pc
, dest
);
186 tcg_gen_exit_tb((uintptr_t)dc
->base
.tb
+ n
);
188 tcg_gen_movi_tl(cpu_pc
, dest
);
189 if (dc
->base
.singlestep_enabled
) {
190 gen_exception(dc
, EXCP_DEBUG
);
196 static void gen_jump(DisasContext
*dc
, int32_t n26
, uint32_t reg
, uint32_t op0
)
198 target_ulong tmp_pc
= dc
->base
.pc_next
+ n26
* 4;
202 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
204 case 0x01: /* l.jal */
205 tcg_gen_movi_tl(cpu_R
[9], dc
->base
.pc_next
+ 8);
206 /* Optimize jal being used to load the PC for PIC. */
207 if (tmp_pc
== dc
->base
.pc_next
+ 8) {
210 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
212 case 0x03: /* l.bnf */
213 case 0x04: /* l.bf */
215 TCGv t_next
= tcg_const_tl(dc
->base
.pc_next
+ 8);
216 TCGv t_true
= tcg_const_tl(tmp_pc
);
217 TCGv t_zero
= tcg_const_tl(0);
219 tcg_gen_movcond_tl(op0
== 0x03 ? TCG_COND_EQ
: TCG_COND_NE
,
220 jmp_pc
, cpu_sr_f
, t_zero
, t_true
, t_next
);
222 tcg_temp_free(t_next
);
223 tcg_temp_free(t_true
);
224 tcg_temp_free(t_zero
);
227 case 0x11: /* l.jr */
228 tcg_gen_mov_tl(jmp_pc
, cpu_R
[reg
]);
230 case 0x12: /* l.jalr */
231 tcg_gen_movi_tl(cpu_R
[9], (dc
->base
.pc_next
+ 8));
232 tcg_gen_mov_tl(jmp_pc
, cpu_R
[reg
]);
235 gen_illegal_exception(dc
);
239 dc
->delayed_branch
= 2;
242 static void gen_ove_cy(DisasContext
*dc
)
244 if (dc
->tb_flags
& SR_OVE
) {
245 gen_helper_ove_cy(cpu_env
);
249 static void gen_ove_ov(DisasContext
*dc
)
251 if (dc
->tb_flags
& SR_OVE
) {
252 gen_helper_ove_ov(cpu_env
);
256 static void gen_ove_cyov(DisasContext
*dc
)
258 if (dc
->tb_flags
& SR_OVE
) {
259 gen_helper_ove_cyov(cpu_env
);
263 static void gen_add(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
265 TCGv t0
= tcg_const_tl(0);
266 TCGv res
= tcg_temp_new();
268 tcg_gen_add2_tl(res
, cpu_sr_cy
, srca
, t0
, srcb
, t0
);
269 tcg_gen_xor_tl(cpu_sr_ov
, srca
, srcb
);
270 tcg_gen_xor_tl(t0
, res
, srcb
);
271 tcg_gen_andc_tl(cpu_sr_ov
, t0
, cpu_sr_ov
);
274 tcg_gen_mov_tl(dest
, res
);
280 static void gen_addc(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
282 TCGv t0
= tcg_const_tl(0);
283 TCGv res
= tcg_temp_new();
285 tcg_gen_add2_tl(res
, cpu_sr_cy
, srca
, t0
, cpu_sr_cy
, t0
);
286 tcg_gen_add2_tl(res
, cpu_sr_cy
, res
, cpu_sr_cy
, srcb
, t0
);
287 tcg_gen_xor_tl(cpu_sr_ov
, srca
, srcb
);
288 tcg_gen_xor_tl(t0
, res
, srcb
);
289 tcg_gen_andc_tl(cpu_sr_ov
, t0
, cpu_sr_ov
);
292 tcg_gen_mov_tl(dest
, res
);
298 static void gen_sub(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
300 TCGv res
= tcg_temp_new();
302 tcg_gen_sub_tl(res
, srca
, srcb
);
303 tcg_gen_xor_tl(cpu_sr_cy
, srca
, srcb
);
304 tcg_gen_xor_tl(cpu_sr_ov
, res
, srcb
);
305 tcg_gen_and_tl(cpu_sr_ov
, cpu_sr_ov
, cpu_sr_cy
);
306 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_sr_cy
, srca
, srcb
);
308 tcg_gen_mov_tl(dest
, res
);
314 static void gen_mul(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
316 TCGv t0
= tcg_temp_new();
318 tcg_gen_muls2_tl(dest
, cpu_sr_ov
, srca
, srcb
);
319 tcg_gen_sari_tl(t0
, dest
, TARGET_LONG_BITS
- 1);
320 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_sr_ov
, cpu_sr_ov
, t0
);
323 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
327 static void gen_mulu(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
329 tcg_gen_muls2_tl(dest
, cpu_sr_cy
, srca
, srcb
);
330 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_sr_cy
, cpu_sr_cy
, 0);
335 static void gen_div(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
337 TCGv t0
= tcg_temp_new();
339 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_ov
, srcb
, 0);
340 /* The result of divide-by-zero is undefined.
341 Supress the host-side exception by dividing by 1. */
342 tcg_gen_or_tl(t0
, srcb
, cpu_sr_ov
);
343 tcg_gen_div_tl(dest
, srca
, t0
);
346 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
350 static void gen_divu(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
352 TCGv t0
= tcg_temp_new();
354 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_cy
, srcb
, 0);
355 /* The result of divide-by-zero is undefined.
356 Supress the host-side exception by dividing by 1. */
357 tcg_gen_or_tl(t0
, srcb
, cpu_sr_cy
);
358 tcg_gen_divu_tl(dest
, srca
, t0
);
364 static void gen_muld(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
366 TCGv_i64 t1
= tcg_temp_new_i64();
367 TCGv_i64 t2
= tcg_temp_new_i64();
369 tcg_gen_ext_tl_i64(t1
, srca
);
370 tcg_gen_ext_tl_i64(t2
, srcb
);
371 if (TARGET_LONG_BITS
== 32) {
372 tcg_gen_mul_i64(cpu_mac
, t1
, t2
);
373 tcg_gen_movi_tl(cpu_sr_ov
, 0);
375 TCGv_i64 high
= tcg_temp_new_i64();
377 tcg_gen_muls2_i64(cpu_mac
, high
, t1
, t2
);
378 tcg_gen_sari_i64(t1
, cpu_mac
, 63);
379 tcg_gen_setcond_i64(TCG_COND_NE
, t1
, t1
, high
);
380 tcg_temp_free_i64(high
);
381 tcg_gen_trunc_i64_tl(cpu_sr_ov
, t1
);
382 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
386 tcg_temp_free_i64(t1
);
387 tcg_temp_free_i64(t2
);
390 static void gen_muldu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
392 TCGv_i64 t1
= tcg_temp_new_i64();
393 TCGv_i64 t2
= tcg_temp_new_i64();
395 tcg_gen_extu_tl_i64(t1
, srca
);
396 tcg_gen_extu_tl_i64(t2
, srcb
);
397 if (TARGET_LONG_BITS
== 32) {
398 tcg_gen_mul_i64(cpu_mac
, t1
, t2
);
399 tcg_gen_movi_tl(cpu_sr_cy
, 0);
401 TCGv_i64 high
= tcg_temp_new_i64();
403 tcg_gen_mulu2_i64(cpu_mac
, high
, t1
, t2
);
404 tcg_gen_setcondi_i64(TCG_COND_NE
, high
, high
, 0);
405 tcg_gen_trunc_i64_tl(cpu_sr_cy
, high
);
406 tcg_temp_free_i64(high
);
410 tcg_temp_free_i64(t1
);
411 tcg_temp_free_i64(t2
);
414 static void gen_mac(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
416 TCGv_i64 t1
= tcg_temp_new_i64();
417 TCGv_i64 t2
= tcg_temp_new_i64();
419 tcg_gen_ext_tl_i64(t1
, srca
);
420 tcg_gen_ext_tl_i64(t2
, srcb
);
421 tcg_gen_mul_i64(t1
, t1
, t2
);
423 /* Note that overflow is only computed during addition stage. */
424 tcg_gen_xor_i64(t2
, cpu_mac
, t1
);
425 tcg_gen_add_i64(cpu_mac
, cpu_mac
, t1
);
426 tcg_gen_xor_i64(t1
, t1
, cpu_mac
);
427 tcg_gen_andc_i64(t1
, t1
, t2
);
428 tcg_temp_free_i64(t2
);
430 #if TARGET_LONG_BITS == 32
431 tcg_gen_extrh_i64_i32(cpu_sr_ov
, t1
);
433 tcg_gen_mov_i64(cpu_sr_ov
, t1
);
435 tcg_temp_free_i64(t1
);
440 static void gen_macu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
442 TCGv_i64 t1
= tcg_temp_new_i64();
443 TCGv_i64 t2
= tcg_temp_new_i64();
445 tcg_gen_extu_tl_i64(t1
, srca
);
446 tcg_gen_extu_tl_i64(t2
, srcb
);
447 tcg_gen_mul_i64(t1
, t1
, t2
);
448 tcg_temp_free_i64(t2
);
450 /* Note that overflow is only computed during addition stage. */
451 tcg_gen_add_i64(cpu_mac
, cpu_mac
, t1
);
452 tcg_gen_setcond_i64(TCG_COND_LTU
, t1
, cpu_mac
, t1
);
453 tcg_gen_trunc_i64_tl(cpu_sr_cy
, t1
);
454 tcg_temp_free_i64(t1
);
459 static void gen_msb(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
461 TCGv_i64 t1
= tcg_temp_new_i64();
462 TCGv_i64 t2
= tcg_temp_new_i64();
464 tcg_gen_ext_tl_i64(t1
, srca
);
465 tcg_gen_ext_tl_i64(t2
, srcb
);
466 tcg_gen_mul_i64(t1
, t1
, t2
);
468 /* Note that overflow is only computed during subtraction stage. */
469 tcg_gen_xor_i64(t2
, cpu_mac
, t1
);
470 tcg_gen_sub_i64(cpu_mac
, cpu_mac
, t1
);
471 tcg_gen_xor_i64(t1
, t1
, cpu_mac
);
472 tcg_gen_and_i64(t1
, t1
, t2
);
473 tcg_temp_free_i64(t2
);
475 #if TARGET_LONG_BITS == 32
476 tcg_gen_extrh_i64_i32(cpu_sr_ov
, t1
);
478 tcg_gen_mov_i64(cpu_sr_ov
, t1
);
480 tcg_temp_free_i64(t1
);
485 static void gen_msbu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
487 TCGv_i64 t1
= tcg_temp_new_i64();
488 TCGv_i64 t2
= tcg_temp_new_i64();
490 tcg_gen_extu_tl_i64(t1
, srca
);
491 tcg_gen_extu_tl_i64(t2
, srcb
);
492 tcg_gen_mul_i64(t1
, t1
, t2
);
494 /* Note that overflow is only computed during subtraction stage. */
495 tcg_gen_setcond_i64(TCG_COND_LTU
, t2
, cpu_mac
, t1
);
496 tcg_gen_sub_i64(cpu_mac
, cpu_mac
, t1
);
497 tcg_gen_trunc_i64_tl(cpu_sr_cy
, t2
);
498 tcg_temp_free_i64(t2
);
499 tcg_temp_free_i64(t1
);
504 static void gen_lwa(DisasContext
*dc
, TCGv rd
, TCGv ra
, int32_t ofs
)
506 TCGv ea
= tcg_temp_new();
508 tcg_gen_addi_tl(ea
, ra
, ofs
);
509 tcg_gen_qemu_ld_tl(rd
, ea
, dc
->mem_idx
, MO_TEUL
);
510 tcg_gen_mov_tl(cpu_lock_addr
, ea
);
511 tcg_gen_mov_tl(cpu_lock_value
, rd
);
515 static void gen_swa(DisasContext
*dc
, int b
, TCGv ra
, int32_t ofs
)
518 TCGLabel
*lab_fail
, *lab_done
;
521 tcg_gen_addi_tl(ea
, ra
, ofs
);
523 /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned
524 to cpu_R[0]. Since l.swa is quite often immediately followed by a
525 branch, don't bother reallocating; finish the TB using the "real" R0.
526 This also takes care of RB input across the branch. */
529 lab_fail
= gen_new_label();
530 lab_done
= gen_new_label();
531 tcg_gen_brcond_tl(TCG_COND_NE
, ea
, cpu_lock_addr
, lab_fail
);
534 val
= tcg_temp_new();
535 tcg_gen_atomic_cmpxchg_tl(val
, cpu_lock_addr
, cpu_lock_value
,
536 cpu_R
[b
], dc
->mem_idx
, MO_TEUL
);
537 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_sr_f
, val
, cpu_lock_value
);
540 tcg_gen_br(lab_done
);
542 gen_set_label(lab_fail
);
543 tcg_gen_movi_tl(cpu_sr_f
, 0);
545 gen_set_label(lab_done
);
546 tcg_gen_movi_tl(cpu_lock_addr
, -1);
549 static void dec_calc(DisasContext
*dc
, uint32_t insn
)
551 uint32_t op0
, op1
, op2
;
553 op0
= extract32(insn
, 0, 4);
554 op1
= extract32(insn
, 8, 2);
555 op2
= extract32(insn
, 6, 2);
556 ra
= extract32(insn
, 16, 5);
557 rb
= extract32(insn
, 11, 5);
558 rd
= extract32(insn
, 21, 5);
563 case 0x0: /* l.add */
564 LOG_DIS("l.add r%d, r%d, r%d\n", rd
, ra
, rb
);
565 gen_add(dc
, cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
568 case 0x1: /* l.addc */
569 LOG_DIS("l.addc r%d, r%d, r%d\n", rd
, ra
, rb
);
570 gen_addc(dc
, cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
573 case 0x2: /* l.sub */
574 LOG_DIS("l.sub r%d, r%d, r%d\n", rd
, ra
, rb
);
575 gen_sub(dc
, cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
578 case 0x3: /* l.and */
579 LOG_DIS("l.and r%d, r%d, r%d\n", rd
, ra
, rb
);
580 tcg_gen_and_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
584 LOG_DIS("l.or r%d, r%d, r%d\n", rd
, ra
, rb
);
585 tcg_gen_or_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
588 case 0x5: /* l.xor */
589 LOG_DIS("l.xor r%d, r%d, r%d\n", rd
, ra
, rb
);
590 tcg_gen_xor_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
596 LOG_DIS("l.sll r%d, r%d, r%d\n", rd
, ra
, rb
);
597 tcg_gen_shl_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
600 LOG_DIS("l.srl r%d, r%d, r%d\n", rd
, ra
, rb
);
601 tcg_gen_shr_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
604 LOG_DIS("l.sra r%d, r%d, r%d\n", rd
, ra
, rb
);
605 tcg_gen_sar_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
608 LOG_DIS("l.ror r%d, r%d, r%d\n", rd
, ra
, rb
);
609 tcg_gen_rotr_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
616 case 0: /* l.exths */
617 LOG_DIS("l.exths r%d, r%d\n", rd
, ra
);
618 tcg_gen_ext16s_tl(cpu_R
[rd
], cpu_R
[ra
]);
620 case 1: /* l.extbs */
621 LOG_DIS("l.extbs r%d, r%d\n", rd
, ra
);
622 tcg_gen_ext8s_tl(cpu_R
[rd
], cpu_R
[ra
]);
624 case 2: /* l.exthz */
625 LOG_DIS("l.exthz r%d, r%d\n", rd
, ra
);
626 tcg_gen_ext16u_tl(cpu_R
[rd
], cpu_R
[ra
]);
628 case 3: /* l.extbz */
629 LOG_DIS("l.extbz r%d, r%d\n", rd
, ra
);
630 tcg_gen_ext8u_tl(cpu_R
[rd
], cpu_R
[ra
]);
637 case 0: /* l.extws */
638 LOG_DIS("l.extws r%d, r%d\n", rd
, ra
);
639 tcg_gen_ext32s_tl(cpu_R
[rd
], cpu_R
[ra
]);
641 case 1: /* l.extwz */
642 LOG_DIS("l.extwz r%d, r%d\n", rd
, ra
);
643 tcg_gen_ext32u_tl(cpu_R
[rd
], cpu_R
[ra
]);
648 case 0xe: /* l.cmov */
649 LOG_DIS("l.cmov r%d, r%d, r%d\n", rd
, ra
, rb
);
651 TCGv zero
= tcg_const_tl(0);
652 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_R
[rd
], cpu_sr_f
, zero
,
653 cpu_R
[ra
], cpu_R
[rb
]);
658 case 0xf: /* l.ff1 */
659 LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd
, ra
, rb
);
660 tcg_gen_ctzi_tl(cpu_R
[rd
], cpu_R
[ra
], -1);
661 tcg_gen_addi_tl(cpu_R
[rd
], cpu_R
[rd
], 1);
668 case 0xf: /* l.fl1 */
669 LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd
, ra
, rb
);
670 tcg_gen_clzi_tl(cpu_R
[rd
], cpu_R
[ra
], TARGET_LONG_BITS
);
671 tcg_gen_subfi_tl(cpu_R
[rd
], TARGET_LONG_BITS
, cpu_R
[rd
]);
681 case 0x6: /* l.mul */
682 LOG_DIS("l.mul r%d, r%d, r%d\n", rd
, ra
, rb
);
683 gen_mul(dc
, cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
686 case 0x7: /* l.muld */
687 LOG_DIS("l.muld r%d, r%d\n", ra
, rb
);
688 gen_muld(dc
, cpu_R
[ra
], cpu_R
[rb
]);
691 case 0x9: /* l.div */
692 LOG_DIS("l.div r%d, r%d, r%d\n", rd
, ra
, rb
);
693 gen_div(dc
, cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
696 case 0xa: /* l.divu */
697 LOG_DIS("l.divu r%d, r%d, r%d\n", rd
, ra
, rb
);
698 gen_divu(dc
, cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
701 case 0xb: /* l.mulu */
702 LOG_DIS("l.mulu r%d, r%d, r%d\n", rd
, ra
, rb
);
703 gen_mulu(dc
, cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
706 case 0xc: /* l.muldu */
707 LOG_DIS("l.muldu r%d, r%d\n", ra
, rb
);
708 gen_muldu(dc
, cpu_R
[ra
], cpu_R
[rb
]);
713 gen_illegal_exception(dc
);
716 static void dec_misc(DisasContext
*dc
, uint32_t insn
)
720 uint32_t L6
, K5
, K16
, K5_11
;
721 int32_t I16
, I5_11
, N26
;
725 op0
= extract32(insn
, 26, 6);
726 op1
= extract32(insn
, 24, 2);
727 ra
= extract32(insn
, 16, 5);
728 rb
= extract32(insn
, 11, 5);
729 rd
= extract32(insn
, 21, 5);
730 L6
= extract32(insn
, 5, 6);
731 K5
= extract32(insn
, 0, 5);
732 K16
= extract32(insn
, 0, 16);
734 N26
= sextract32(insn
, 0, 26);
735 K5_11
= (extract32(insn
, 21, 5) << 11) | extract32(insn
, 0, 11);
736 I5_11
= (int16_t)K5_11
;
740 LOG_DIS("l.j %d\n", N26
);
741 gen_jump(dc
, N26
, 0, op0
);
744 case 0x01: /* l.jal */
745 LOG_DIS("l.jal %d\n", N26
);
746 gen_jump(dc
, N26
, 0, op0
);
749 case 0x03: /* l.bnf */
750 LOG_DIS("l.bnf %d\n", N26
);
751 gen_jump(dc
, N26
, 0, op0
);
754 case 0x04: /* l.bf */
755 LOG_DIS("l.bf %d\n", N26
);
756 gen_jump(dc
, N26
, 0, op0
);
761 case 0x01: /* l.nop */
762 LOG_DIS("l.nop %d\n", I16
);
766 gen_illegal_exception(dc
);
771 case 0x11: /* l.jr */
772 LOG_DIS("l.jr r%d\n", rb
);
773 gen_jump(dc
, 0, rb
, op0
);
776 case 0x12: /* l.jalr */
777 LOG_DIS("l.jalr r%d\n", rb
);
778 gen_jump(dc
, 0, rb
, op0
);
781 case 0x13: /* l.maci */
782 LOG_DIS("l.maci r%d, %d\n", ra
, I16
);
783 t0
= tcg_const_tl(I16
);
784 gen_mac(dc
, cpu_R
[ra
], t0
);
788 case 0x09: /* l.rfe */
791 #if defined(CONFIG_USER_ONLY)
794 if (dc
->mem_idx
== MMU_USER_IDX
) {
795 gen_illegal_exception(dc
);
798 gen_helper_rfe(cpu_env
);
799 dc
->base
.is_jmp
= DISAS_UPDATE
;
804 case 0x1b: /* l.lwa */
805 LOG_DIS("l.lwa r%d, r%d, %d\n", rd
, ra
, I16
);
807 gen_lwa(dc
, cpu_R
[rd
], cpu_R
[ra
], I16
);
810 case 0x1c: /* l.cust1 */
811 LOG_DIS("l.cust1\n");
814 case 0x1d: /* l.cust2 */
815 LOG_DIS("l.cust2\n");
818 case 0x1e: /* l.cust3 */
819 LOG_DIS("l.cust3\n");
822 case 0x1f: /* l.cust4 */
823 LOG_DIS("l.cust4\n");
826 case 0x3c: /* l.cust5 */
827 LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd
, ra
, rb
, L6
, K5
);
830 case 0x3d: /* l.cust6 */
831 LOG_DIS("l.cust6\n");
834 case 0x3e: /* l.cust7 */
835 LOG_DIS("l.cust7\n");
838 case 0x3f: /* l.cust8 */
839 LOG_DIS("l.cust8\n");
842 /* not used yet, open it when we need or64. */
843 /*#ifdef TARGET_OPENRISC64
845 LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
851 case 0x21: /* l.lwz */
852 LOG_DIS("l.lwz r%d, r%d, %d\n", rd
, ra
, I16
);
856 case 0x22: /* l.lws */
857 LOG_DIS("l.lws r%d, r%d, %d\n", rd
, ra
, I16
);
861 case 0x23: /* l.lbz */
862 LOG_DIS("l.lbz r%d, r%d, %d\n", rd
, ra
, I16
);
866 case 0x24: /* l.lbs */
867 LOG_DIS("l.lbs r%d, r%d, %d\n", rd
, ra
, I16
);
871 case 0x25: /* l.lhz */
872 LOG_DIS("l.lhz r%d, r%d, %d\n", rd
, ra
, I16
);
876 case 0x26: /* l.lhs */
877 LOG_DIS("l.lhs r%d, r%d, %d\n", rd
, ra
, I16
);
884 tcg_gen_addi_tl(t0
, cpu_R
[ra
], I16
);
885 tcg_gen_qemu_ld_tl(cpu_R
[rd
], t0
, dc
->mem_idx
, mop
);
889 case 0x27: /* l.addi */
890 LOG_DIS("l.addi r%d, r%d, %d\n", rd
, ra
, I16
);
892 t0
= tcg_const_tl(I16
);
893 gen_add(dc
, cpu_R
[rd
], cpu_R
[ra
], t0
);
897 case 0x28: /* l.addic */
898 LOG_DIS("l.addic r%d, r%d, %d\n", rd
, ra
, I16
);
900 t0
= tcg_const_tl(I16
);
901 gen_addc(dc
, cpu_R
[rd
], cpu_R
[ra
], t0
);
905 case 0x29: /* l.andi */
906 LOG_DIS("l.andi r%d, r%d, %d\n", rd
, ra
, K16
);
908 tcg_gen_andi_tl(cpu_R
[rd
], cpu_R
[ra
], K16
);
911 case 0x2a: /* l.ori */
912 LOG_DIS("l.ori r%d, r%d, %d\n", rd
, ra
, K16
);
914 tcg_gen_ori_tl(cpu_R
[rd
], cpu_R
[ra
], K16
);
917 case 0x2b: /* l.xori */
918 LOG_DIS("l.xori r%d, r%d, %d\n", rd
, ra
, I16
);
920 tcg_gen_xori_tl(cpu_R
[rd
], cpu_R
[ra
], I16
);
923 case 0x2c: /* l.muli */
924 LOG_DIS("l.muli r%d, r%d, %d\n", rd
, ra
, I16
);
926 t0
= tcg_const_tl(I16
);
927 gen_mul(dc
, cpu_R
[rd
], cpu_R
[ra
], t0
);
931 case 0x2d: /* l.mfspr */
932 LOG_DIS("l.mfspr r%d, r%d, %d\n", rd
, ra
, K16
);
935 #if defined(CONFIG_USER_ONLY)
938 TCGv_i32 ti
= tcg_const_i32(K16
);
939 if (dc
->mem_idx
== MMU_USER_IDX
) {
940 gen_illegal_exception(dc
);
943 gen_helper_mfspr(cpu_R
[rd
], cpu_env
, cpu_R
[rd
], cpu_R
[ra
], ti
);
944 tcg_temp_free_i32(ti
);
949 case 0x30: /* l.mtspr */
950 LOG_DIS("l.mtspr r%d, r%d, %d\n", ra
, rb
, K5_11
);
952 #if defined(CONFIG_USER_ONLY)
955 TCGv_i32 im
= tcg_const_i32(K5_11
);
956 if (dc
->mem_idx
== MMU_USER_IDX
) {
957 gen_illegal_exception(dc
);
960 gen_helper_mtspr(cpu_env
, cpu_R
[ra
], cpu_R
[rb
], im
);
961 tcg_temp_free_i32(im
);
966 case 0x33: /* l.swa */
967 LOG_DIS("l.swa r%d, r%d, %d\n", ra
, rb
, I5_11
);
968 gen_swa(dc
, rb
, cpu_R
[ra
], I5_11
);
971 /* not used yet, open it when we need or64. */
972 /*#ifdef TARGET_OPENRISC64
974 LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11);
980 case 0x35: /* l.sw */
981 LOG_DIS("l.sw r%d, r%d, %d\n", ra
, rb
, I5_11
);
985 case 0x36: /* l.sb */
986 LOG_DIS("l.sb r%d, r%d, %d\n", ra
, rb
, I5_11
);
990 case 0x37: /* l.sh */
991 LOG_DIS("l.sh r%d, r%d, %d\n", ra
, rb
, I5_11
);
997 TCGv t0
= tcg_temp_new();
998 tcg_gen_addi_tl(t0
, cpu_R
[ra
], I5_11
);
999 tcg_gen_qemu_st_tl(cpu_R
[rb
], t0
, dc
->mem_idx
, mop
);
1005 gen_illegal_exception(dc
);
1010 static void dec_mac(DisasContext
*dc
, uint32_t insn
)
1014 op0
= extract32(insn
, 0, 4);
1015 ra
= extract32(insn
, 16, 5);
1016 rb
= extract32(insn
, 11, 5);
1019 case 0x0001: /* l.mac */
1020 LOG_DIS("l.mac r%d, r%d\n", ra
, rb
);
1021 gen_mac(dc
, cpu_R
[ra
], cpu_R
[rb
]);
1024 case 0x0002: /* l.msb */
1025 LOG_DIS("l.msb r%d, r%d\n", ra
, rb
);
1026 gen_msb(dc
, cpu_R
[ra
], cpu_R
[rb
]);
1029 case 0x0003: /* l.macu */
1030 LOG_DIS("l.macu r%d, r%d\n", ra
, rb
);
1031 gen_macu(dc
, cpu_R
[ra
], cpu_R
[rb
]);
1034 case 0x0004: /* l.msbu */
1035 LOG_DIS("l.msbu r%d, r%d\n", ra
, rb
);
1036 gen_msbu(dc
, cpu_R
[ra
], cpu_R
[rb
]);
1040 gen_illegal_exception(dc
);
1045 static void dec_logic(DisasContext
*dc
, uint32_t insn
)
1048 uint32_t rd
, ra
, L6
, S6
;
1049 op0
= extract32(insn
, 6, 2);
1050 rd
= extract32(insn
, 21, 5);
1051 ra
= extract32(insn
, 16, 5);
1052 L6
= extract32(insn
, 0, 6);
1053 S6
= L6
& (TARGET_LONG_BITS
- 1);
1057 case 0x00: /* l.slli */
1058 LOG_DIS("l.slli r%d, r%d, %d\n", rd
, ra
, L6
);
1059 tcg_gen_shli_tl(cpu_R
[rd
], cpu_R
[ra
], S6
);
1062 case 0x01: /* l.srli */
1063 LOG_DIS("l.srli r%d, r%d, %d\n", rd
, ra
, L6
);
1064 tcg_gen_shri_tl(cpu_R
[rd
], cpu_R
[ra
], S6
);
1067 case 0x02: /* l.srai */
1068 LOG_DIS("l.srai r%d, r%d, %d\n", rd
, ra
, L6
);
1069 tcg_gen_sari_tl(cpu_R
[rd
], cpu_R
[ra
], S6
);
1072 case 0x03: /* l.rori */
1073 LOG_DIS("l.rori r%d, r%d, %d\n", rd
, ra
, L6
);
1074 tcg_gen_rotri_tl(cpu_R
[rd
], cpu_R
[ra
], S6
);
1078 gen_illegal_exception(dc
);
1083 static void dec_M(DisasContext
*dc
, uint32_t insn
)
1088 op0
= extract32(insn
, 16, 1);
1089 rd
= extract32(insn
, 21, 5);
1090 K16
= extract32(insn
, 0, 16);
1094 case 0x0: /* l.movhi */
1095 LOG_DIS("l.movhi r%d, %d\n", rd
, K16
);
1096 tcg_gen_movi_tl(cpu_R
[rd
], (K16
<< 16));
1099 case 0x1: /* l.macrc */
1100 LOG_DIS("l.macrc r%d\n", rd
);
1101 tcg_gen_trunc_i64_tl(cpu_R
[rd
], cpu_mac
);
1102 tcg_gen_movi_i64(cpu_mac
, 0);
1106 gen_illegal_exception(dc
);
1111 static void dec_comp(DisasContext
*dc
, uint32_t insn
)
1116 op0
= extract32(insn
, 21, 5);
1117 ra
= extract32(insn
, 16, 5);
1118 rb
= extract32(insn
, 11, 5);
1120 /* unsigned integers */
1121 tcg_gen_ext32u_tl(cpu_R
[ra
], cpu_R
[ra
]);
1122 tcg_gen_ext32u_tl(cpu_R
[rb
], cpu_R
[rb
]);
1125 case 0x0: /* l.sfeq */
1126 LOG_DIS("l.sfeq r%d, r%d\n", ra
, rb
);
1127 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1130 case 0x1: /* l.sfne */
1131 LOG_DIS("l.sfne r%d, r%d\n", ra
, rb
);
1132 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1135 case 0x2: /* l.sfgtu */
1136 LOG_DIS("l.sfgtu r%d, r%d\n", ra
, rb
);
1137 tcg_gen_setcond_tl(TCG_COND_GTU
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1140 case 0x3: /* l.sfgeu */
1141 LOG_DIS("l.sfgeu r%d, r%d\n", ra
, rb
);
1142 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1145 case 0x4: /* l.sfltu */
1146 LOG_DIS("l.sfltu r%d, r%d\n", ra
, rb
);
1147 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1150 case 0x5: /* l.sfleu */
1151 LOG_DIS("l.sfleu r%d, r%d\n", ra
, rb
);
1152 tcg_gen_setcond_tl(TCG_COND_LEU
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1155 case 0xa: /* l.sfgts */
1156 LOG_DIS("l.sfgts r%d, r%d\n", ra
, rb
);
1157 tcg_gen_setcond_tl(TCG_COND_GT
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1160 case 0xb: /* l.sfges */
1161 LOG_DIS("l.sfges r%d, r%d\n", ra
, rb
);
1162 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1165 case 0xc: /* l.sflts */
1166 LOG_DIS("l.sflts r%d, r%d\n", ra
, rb
);
1167 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1170 case 0xd: /* l.sfles */
1171 LOG_DIS("l.sfles r%d, r%d\n", ra
, rb
);
1172 tcg_gen_setcond_tl(TCG_COND_LE
, cpu_sr_f
, cpu_R
[ra
], cpu_R
[rb
]);
1176 gen_illegal_exception(dc
);
1181 static void dec_compi(DisasContext
*dc
, uint32_t insn
)
1186 op0
= extract32(insn
, 21, 5);
1187 ra
= extract32(insn
, 16, 5);
1188 I16
= sextract32(insn
, 0, 16);
1191 case 0x0: /* l.sfeqi */
1192 LOG_DIS("l.sfeqi r%d, %d\n", ra
, I16
);
1193 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_f
, cpu_R
[ra
], I16
);
1196 case 0x1: /* l.sfnei */
1197 LOG_DIS("l.sfnei r%d, %d\n", ra
, I16
);
1198 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_sr_f
, cpu_R
[ra
], I16
);
1201 case 0x2: /* l.sfgtui */
1202 LOG_DIS("l.sfgtui r%d, %d\n", ra
, I16
);
1203 tcg_gen_setcondi_tl(TCG_COND_GTU
, cpu_sr_f
, cpu_R
[ra
], I16
);
1206 case 0x3: /* l.sfgeui */
1207 LOG_DIS("l.sfgeui r%d, %d\n", ra
, I16
);
1208 tcg_gen_setcondi_tl(TCG_COND_GEU
, cpu_sr_f
, cpu_R
[ra
], I16
);
1211 case 0x4: /* l.sfltui */
1212 LOG_DIS("l.sfltui r%d, %d\n", ra
, I16
);
1213 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_sr_f
, cpu_R
[ra
], I16
);
1216 case 0x5: /* l.sfleui */
1217 LOG_DIS("l.sfleui r%d, %d\n", ra
, I16
);
1218 tcg_gen_setcondi_tl(TCG_COND_LEU
, cpu_sr_f
, cpu_R
[ra
], I16
);
1221 case 0xa: /* l.sfgtsi */
1222 LOG_DIS("l.sfgtsi r%d, %d\n", ra
, I16
);
1223 tcg_gen_setcondi_tl(TCG_COND_GT
, cpu_sr_f
, cpu_R
[ra
], I16
);
1226 case 0xb: /* l.sfgesi */
1227 LOG_DIS("l.sfgesi r%d, %d\n", ra
, I16
);
1228 tcg_gen_setcondi_tl(TCG_COND_GE
, cpu_sr_f
, cpu_R
[ra
], I16
);
1231 case 0xc: /* l.sfltsi */
1232 LOG_DIS("l.sfltsi r%d, %d\n", ra
, I16
);
1233 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_sr_f
, cpu_R
[ra
], I16
);
1236 case 0xd: /* l.sflesi */
1237 LOG_DIS("l.sflesi r%d, %d\n", ra
, I16
);
1238 tcg_gen_setcondi_tl(TCG_COND_LE
, cpu_sr_f
, cpu_R
[ra
], I16
);
1242 gen_illegal_exception(dc
);
1247 static bool trans_l_sys(DisasContext
*dc
, arg_l_sys
*a
, uint32_t insn
)
1249 LOG_DIS("l.sys %d\n", a
->k
);
1250 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1251 gen_exception(dc
, EXCP_SYSCALL
);
1252 dc
->base
.is_jmp
= DISAS_NORETURN
;
1256 static bool trans_l_trap(DisasContext
*dc
, arg_l_trap
*a
, uint32_t insn
)
1258 LOG_DIS("l.trap %d\n", a
->k
);
1259 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1260 gen_exception(dc
, EXCP_TRAP
);
1261 dc
->base
.is_jmp
= DISAS_NORETURN
;
1265 static bool trans_l_msync(DisasContext
*dc
, arg_l_msync
*a
, uint32_t insn
)
1267 LOG_DIS("l.msync\n");
1268 tcg_gen_mb(TCG_MO_ALL
);
1272 static bool trans_l_psync(DisasContext
*dc
, arg_l_psync
*a
, uint32_t insn
)
1274 LOG_DIS("l.psync\n");
1278 static bool trans_l_csync(DisasContext
*dc
, arg_l_csync
*a
, uint32_t insn
)
1280 LOG_DIS("l.csync\n");
1284 static void dec_float(DisasContext
*dc
, uint32_t insn
)
1287 uint32_t ra
, rb
, rd
;
1288 op0
= extract32(insn
, 0, 8);
1289 ra
= extract32(insn
, 16, 5);
1290 rb
= extract32(insn
, 11, 5);
1291 rd
= extract32(insn
, 21, 5);
1294 case 0x00: /* lf.add.s */
1295 LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1297 gen_helper_float_add_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1298 gen_helper_update_fpcsr(cpu_env
);
1301 case 0x01: /* lf.sub.s */
1302 LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1304 gen_helper_float_sub_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1305 gen_helper_update_fpcsr(cpu_env
);
1308 case 0x02: /* lf.mul.s */
1309 LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1311 gen_helper_float_mul_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1312 gen_helper_update_fpcsr(cpu_env
);
1315 case 0x03: /* lf.div.s */
1316 LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1318 gen_helper_float_div_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1319 gen_helper_update_fpcsr(cpu_env
);
1322 case 0x04: /* lf.itof.s */
1323 LOG_DIS("lf.itof r%d, r%d\n", rd
, ra
);
1325 gen_helper_itofs(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1326 gen_helper_update_fpcsr(cpu_env
);
1329 case 0x05: /* lf.ftoi.s */
1330 LOG_DIS("lf.ftoi r%d, r%d\n", rd
, ra
);
1332 gen_helper_ftois(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1333 gen_helper_update_fpcsr(cpu_env
);
1336 case 0x06: /* lf.rem.s */
1337 LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1339 gen_helper_float_rem_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1340 gen_helper_update_fpcsr(cpu_env
);
1343 case 0x07: /* lf.madd.s */
1344 LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1346 gen_helper_float_madd_s(cpu_R
[rd
], cpu_env
, cpu_R
[rd
],
1347 cpu_R
[ra
], cpu_R
[rb
]);
1348 gen_helper_update_fpcsr(cpu_env
);
1351 case 0x08: /* lf.sfeq.s */
1352 LOG_DIS("lf.sfeq.s r%d, r%d\n", ra
, rb
);
1353 gen_helper_float_eq_s(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1354 gen_helper_update_fpcsr(cpu_env
);
1357 case 0x09: /* lf.sfne.s */
1358 LOG_DIS("lf.sfne.s r%d, r%d\n", ra
, rb
);
1359 gen_helper_float_eq_s(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1360 tcg_gen_xori_tl(cpu_sr_f
, cpu_sr_f
, 1);
1361 gen_helper_update_fpcsr(cpu_env
);
1364 case 0x0a: /* lf.sfgt.s */
1365 LOG_DIS("lf.sfgt.s r%d, r%d\n", ra
, rb
);
1366 gen_helper_float_lt_s(cpu_sr_f
, cpu_env
, cpu_R
[rb
], cpu_R
[ra
]);
1367 gen_helper_update_fpcsr(cpu_env
);
1370 case 0x0b: /* lf.sfge.s */
1371 LOG_DIS("lf.sfge.s r%d, r%d\n", ra
, rb
);
1372 gen_helper_float_le_s(cpu_sr_f
, cpu_env
, cpu_R
[rb
], cpu_R
[ra
]);
1373 gen_helper_update_fpcsr(cpu_env
);
1376 case 0x0c: /* lf.sflt.s */
1377 LOG_DIS("lf.sflt.s r%d, r%d\n", ra
, rb
);
1378 gen_helper_float_lt_s(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1379 gen_helper_update_fpcsr(cpu_env
);
1382 case 0x0d: /* lf.sfle.s */
1383 LOG_DIS("lf.sfle.s r%d, r%d\n", ra
, rb
);
1384 gen_helper_float_le_s(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1385 gen_helper_update_fpcsr(cpu_env
);
1388 #ifdef TARGET_OPENRISC64
1389 case 0x10: /* lf.add.d */
1390 LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd
, ra
, rb
);
1393 gen_helper_float_add_d(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1394 gen_helper_update_fpcsr(cpu_env
);
1397 case 0x11: /* lf.sub.d */
1398 LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd
, ra
, rb
);
1401 gen_helper_float_sub_d(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1402 gen_helper_update_fpcsr(cpu_env
);
1405 case 0x12: /* lf.mul.d */
1406 LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd
, ra
, rb
);
1409 gen_helper_float_mul_d(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1410 gen_helper_update_fpcsr(cpu_env
);
1413 case 0x13: /* lf.div.d */
1414 LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd
, ra
, rb
);
1417 gen_helper_float_div_d(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1418 gen_helper_update_fpcsr(cpu_env
);
1421 case 0x14: /* lf.itof.d */
1422 LOG_DIS("lf.itof r%d, r%d\n", rd
, ra
);
1425 gen_helper_itofd(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1426 gen_helper_update_fpcsr(cpu_env
);
1429 case 0x15: /* lf.ftoi.d */
1430 LOG_DIS("lf.ftoi r%d, r%d\n", rd
, ra
);
1433 gen_helper_ftoid(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1434 gen_helper_update_fpcsr(cpu_env
);
1437 case 0x16: /* lf.rem.d */
1438 LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd
, ra
, rb
);
1441 gen_helper_float_rem_d(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1442 gen_helper_update_fpcsr(cpu_env
);
1445 case 0x17: /* lf.madd.d */
1446 LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd
, ra
, rb
);
1449 gen_helper_float_madd_d(cpu_R
[rd
], cpu_env
, cpu_R
[rd
],
1450 cpu_R
[ra
], cpu_R
[rb
]);
1451 gen_helper_update_fpcsr(cpu_env
);
1454 case 0x18: /* lf.sfeq.d */
1455 LOG_DIS("lf.sfeq.d r%d, r%d\n", ra
, rb
);
1457 gen_helper_float_eq_d(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1458 gen_helper_update_fpcsr(cpu_env
);
1461 case 0x1a: /* lf.sfgt.d */
1462 LOG_DIS("lf.sfgt.d r%d, r%d\n", ra
, rb
);
1464 gen_helper_float_lt_d(cpu_sr_f
, cpu_env
, cpu_R
[rb
], cpu_R
[ra
]);
1465 gen_helper_update_fpcsr(cpu_env
);
1468 case 0x1b: /* lf.sfge.d */
1469 LOG_DIS("lf.sfge.d r%d, r%d\n", ra
, rb
);
1471 gen_helper_float_le_d(cpu_sr_f
, cpu_env
, cpu_R
[rb
], cpu_R
[ra
]);
1472 gen_helper_update_fpcsr(cpu_env
);
1475 case 0x19: /* lf.sfne.d */
1476 LOG_DIS("lf.sfne.d r%d, r%d\n", ra
, rb
);
1478 gen_helper_float_eq_d(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1479 tcg_gen_xori_tl(cpu_sr_f
, cpu_sr_f
, 1);
1480 gen_helper_update_fpcsr(cpu_env
);
1483 case 0x1c: /* lf.sflt.d */
1484 LOG_DIS("lf.sflt.d r%d, r%d\n", ra
, rb
);
1486 gen_helper_float_lt_d(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1487 gen_helper_update_fpcsr(cpu_env
);
1490 case 0x1d: /* lf.sfle.d */
1491 LOG_DIS("lf.sfle.d r%d, r%d\n", ra
, rb
);
1493 gen_helper_float_le_d(cpu_sr_f
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1494 gen_helper_update_fpcsr(cpu_env
);
1499 gen_illegal_exception(dc
);
1504 static void disas_openrisc_insn(DisasContext
*dc
, OpenRISCCPU
*cpu
)
1507 uint32_t insn
= cpu_ldl_code(&cpu
->env
, dc
->base
.pc_next
);
1509 /* Transition to the auto-generated decoder. */
1510 if (decode(dc
, insn
)) {
1514 op0
= extract32(insn
, 26, 6);
1521 dec_logic(dc
, insn
);
1525 dec_compi(dc
, insn
);
1533 dec_float(dc
, insn
);
1550 static void openrisc_tr_init_disas_context(DisasContextBase
*dcb
, CPUState
*cs
)
1552 DisasContext
*dc
= container_of(dcb
, DisasContext
, base
);
1553 CPUOpenRISCState
*env
= cs
->env_ptr
;
1556 dc
->mem_idx
= cpu_mmu_index(env
, false);
1557 dc
->tb_flags
= dc
->base
.tb
->flags
;
1558 dc
->delayed_branch
= (dc
->tb_flags
& TB_FLAGS_DFLAG
) != 0;
1559 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
1560 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
1563 static void openrisc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
1565 DisasContext
*dc
= container_of(db
, DisasContext
, base
);
1567 /* Allow the TCG optimizer to see that R0 == 0,
1568 when it's true, which is the common case. */
1569 if (dc
->tb_flags
& TB_FLAGS_R0_0
) {
1570 cpu_R
[0] = tcg_const_tl(0);
1576 static void openrisc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
1578 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1580 tcg_gen_insn_start(dc
->base
.pc_next
, (dc
->delayed_branch
? 1 : 0)
1581 | (dc
->base
.num_insns
> 1 ? 2 : 0));
1584 static bool openrisc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
1585 const CPUBreakpoint
*bp
)
1587 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1589 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1590 gen_exception(dc
, EXCP_DEBUG
);
1591 dc
->base
.is_jmp
= DISAS_NORETURN
;
1592 /* The address covered by the breakpoint must be included in
1593 [tb->pc, tb->pc + tb->size) in order to for it to be
1594 properly cleared -- thus we increment the PC here so that
1595 the logic setting tb->size below does the right thing. */
1596 dc
->base
.pc_next
+= 4;
1600 static void openrisc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
1602 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1603 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1605 disas_openrisc_insn(dc
, cpu
);
1606 dc
->base
.pc_next
+= 4;
1609 if (dc
->delayed_branch
) {
1610 dc
->delayed_branch
--;
1611 if (!dc
->delayed_branch
) {
1612 tcg_gen_mov_tl(cpu_pc
, jmp_pc
);
1613 tcg_gen_discard_tl(jmp_pc
);
1614 dc
->base
.is_jmp
= DISAS_UPDATE
;
1620 static void openrisc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
1622 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1624 if ((dc
->tb_flags
& TB_FLAGS_DFLAG
? 1 : 0) != (dc
->delayed_branch
!= 0)) {
1625 tcg_gen_movi_i32(cpu_dflag
, dc
->delayed_branch
!= 0);
1628 tcg_gen_movi_tl(cpu_ppc
, dc
->base
.pc_next
- 4);
1629 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
1630 dc
->base
.is_jmp
= DISAS_UPDATE
;
1631 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1633 if (unlikely(dc
->base
.singlestep_enabled
)) {
1634 gen_exception(dc
, EXCP_DEBUG
);
1636 switch (dc
->base
.is_jmp
) {
1637 case DISAS_TOO_MANY
:
1638 gen_goto_tb(dc
, 0, dc
->base
.pc_next
);
1640 case DISAS_NORETURN
:
1645 /* indicate that the hash table must be used
1646 to find the next TB */
1650 g_assert_not_reached();
1655 static void openrisc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
1657 DisasContext
*s
= container_of(dcbase
, DisasContext
, base
);
1659 qemu_log("IN: %s\n", lookup_symbol(s
->base
.pc_first
));
1660 log_target_disas(cs
, s
->base
.pc_first
, s
->base
.tb
->size
);
1663 static const TranslatorOps openrisc_tr_ops
= {
1664 .init_disas_context
= openrisc_tr_init_disas_context
,
1665 .tb_start
= openrisc_tr_tb_start
,
1666 .insn_start
= openrisc_tr_insn_start
,
1667 .breakpoint_check
= openrisc_tr_breakpoint_check
,
1668 .translate_insn
= openrisc_tr_translate_insn
,
1669 .tb_stop
= openrisc_tr_tb_stop
,
1670 .disas_log
= openrisc_tr_disas_log
,
1673 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
1677 translator_loop(&openrisc_tr_ops
, &ctx
.base
, cs
, tb
);
1680 void openrisc_cpu_dump_state(CPUState
*cs
, FILE *f
,
1681 fprintf_function cpu_fprintf
,
1684 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1685 CPUOpenRISCState
*env
= &cpu
->env
;
1688 cpu_fprintf(f
, "PC=%08x\n", env
->pc
);
1689 for (i
= 0; i
< 32; ++i
) {
1690 cpu_fprintf(f
, "R%02d=%08x%c", i
, cpu_get_gpr(env
, i
),
1691 (i
% 4) == 3 ? '\n' : ' ');
1695 void restore_state_to_opc(CPUOpenRISCState
*env
, TranslationBlock
*tb
,
1699 env
->dflag
= data
[1] & 1;
1701 env
->ppc
= env
->pc
- 4;