target/ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_CPU_H
  21 #define PPC_CPU_H
  22
  23 #include "qemu-common.h"
  24 #include "qemu/int128.h"
  25
  26 //#define PPC_EMULATE_32BITS_HYPV
  27
  28 #if defined (TARGET_PPC64)
  29 /* PowerPC 64 definitions */
  30 #define TARGET_LONG_BITS 64
  31 #define TARGET_PAGE_BITS 12
  32
  33 /* Note that the official physical address space bits is 62-M where M
  34    is implementation dependent.  I've not looked up M for the set of
  35    cpus we emulate at the system level.  */
  36 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  37
  38 /* Note that the PPC environment architecture talks about 80 bit virtual
  39    addresses, with segmentation.  Obviously that's not all visible to a
  40    single process, which is all we're concerned with here.  */
  41 #ifdef TARGET_ABI32
  42 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  43 #else
  44 # define TARGET_VIRT_ADDR_SPACE_BITS 64
  45 #endif
  46
  47 #define TARGET_PAGE_BITS_64K 16
  48 #define TARGET_PAGE_BITS_16M 24
  49
  50 #else /* defined (TARGET_PPC64) */
  51 /* PowerPC 32 definitions */
  52 #define TARGET_LONG_BITS 32
  53
  54 #if defined(TARGET_PPCEMB)
  55 /* Specific definitions for PowerPC embedded */
  56 /* BookE have 36 bits physical address space */
  57 #if defined(CONFIG_USER_ONLY)
  58 /* It looks like a lot of Linux programs assume page size
  59  * is 4kB long. This is evil, but we have to deal with it...
  60  */
  61 #define TARGET_PAGE_BITS 12
  62 #else /* defined(CONFIG_USER_ONLY) */
  63 /* Pages can be 1 kB small */
  64 #define TARGET_PAGE_BITS 10
  65 #endif /* defined(CONFIG_USER_ONLY) */
  66 #else /* defined(TARGET_PPCEMB) */
  67 /* "standard" PowerPC 32 definitions */
  68 #define TARGET_PAGE_BITS 12
  69 #endif /* defined(TARGET_PPCEMB) */
  70
  71 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  73
  74 #endif /* defined (TARGET_PPC64) */
  75
  76 #define CPUArchState struct CPUPPCState
  77
  78 #include "exec/cpu-defs.h"
  79 #include "cpu-qom.h"
  80 #include "fpu/softfloat.h"
  81
  82 #if defined (TARGET_PPC64)
  83 #define PPC_ELF_MACHINE     EM_PPC64
  84 #else
  85 #define PPC_ELF_MACHINE     EM_PPC
  86 #endif
  87
  88 /*****************************************************************************/
  89 /* Exception vectors definitions                                             */
  90 enum {
  91     POWERPC_EXCP_NONE    = -1,
  92     /* The 64 first entries are used by the PowerPC embedded specification   */
  93     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  94     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  95     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  96     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  97     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  98     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  99     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 100     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 101     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 102     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 103     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 104     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 105     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 106     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 107     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 108     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 109     /* Vectors 16 to 31 are reserved                                         */
 110     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 111     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 112     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 113     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 114     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 115     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 116     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
 117     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
 118     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
 119     /* Vectors 42 to 63 are reserved                                         */
 120     /* Exceptions defined in the PowerPC server specification                */
 121     /* Server doorbell variants */
 122 #define POWERPC_EXCP_SDOOR      POWERPC_EXCP_GDOORI
 123 #define POWERPC_EXCP_SDOOR_HV   POWERPC_EXCP_DOORI
 124     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 125     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 126     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 127     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 128     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 129     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 130     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 131     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 132     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 133     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 134     /* 40x specific exceptions                                               */
 135     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 136     /* 601 specific exceptions                                               */
 137     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 138     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 139     /* 602 specific exceptions                                               */
 140     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 141     /* 602/603 specific exceptions                                           */
 142     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 143     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 144     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 145     /* Exceptions available on most PowerPC                                  */
 146     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 147     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 148     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 149     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 150     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 151     /* 7xx/74xx specific exceptions                                          */
 152     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 153     /* 74xx specific exceptions                                              */
 154     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 155     /* 970FX specific exceptions                                             */
 156     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 157     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 158     /* Freescale embedded cores specific exceptions                          */
 159     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 160     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 161     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 162     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 163     /* VSX Unavailable (Power ISA 2.06 and later)                            */
 164     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 165     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 166     /* Additional ISA 2.06 and later server exceptions                       */
 167     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 168     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 169     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 170     /* EOL                                                                   */
 171     POWERPC_EXCP_NB       = 99,
 172     /* QEMU exceptions: used internally during code translation              */
 173     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 174     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 175     /* QEMU exceptions: special cases we want to stop translation            */
 176     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 177     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 178     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
 179 };
 180
 181 /* Exceptions error codes                                                    */
 182 enum {
 183     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 184     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 185     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 186     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 187     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 188     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 189     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 190     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 191     /* FP exceptions                                                         */
 192     POWERPC_EXCP_FP            = 0x10,
 193     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 194     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 195     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 196     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 197     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 198     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 199     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 200     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 201     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 202     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 203     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 204     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 205     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 206     /* Invalid instruction                                                   */
 207     POWERPC_EXCP_INVAL         = 0x20,
 208     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 209     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 210     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 211     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 212     /* Privileged instruction                                                */
 213     POWERPC_EXCP_PRIV          = 0x30,
 214     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 215     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 216     /* Trap                                                                  */
 217     POWERPC_EXCP_TRAP          = 0x40,
 218 };
 219
 220 #define PPC_INPUT(env) (env->bus_model)
 221
 222 /*****************************************************************************/
 223 typedef struct opc_handler_t opc_handler_t;
 224
 225 /*****************************************************************************/
 226 /* Types used to describe some PowerPC registers */
 227 typedef struct DisasContext DisasContext;
 228 typedef struct ppc_spr_t ppc_spr_t;
 229 typedef union ppc_avr_t ppc_avr_t;
 230 typedef union ppc_tlb_t ppc_tlb_t;
 231
 232 /* SPR access micro-ops generations callbacks */
 233 struct ppc_spr_t {
 234     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 235     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 236 #if !defined(CONFIG_USER_ONLY)
 237     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 238     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 239     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 240     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 241 #endif
 242     const char *name;
 243     target_ulong default_value;
 244 #ifdef CONFIG_KVM
 245     /* We (ab)use the fact that all the SPRs will have ids for the
 246      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 247      * don't sync this */
 248     uint64_t one_reg_id;
 249 #endif
 250 };
 251
 252 /* Altivec registers (128 bits) */
 253 union ppc_avr_t {
 254     float32 f[4];
 255     uint8_t u8[16];
 256     uint16_t u16[8];
 257     uint32_t u32[4];
 258     int8_t s8[16];
 259     int16_t s16[8];
 260     int32_t s32[4];
 261     uint64_t u64[2];
 262     int64_t s64[2];
 263 #ifdef CONFIG_INT128
 264     __uint128_t u128;
 265 #endif
 266     Int128 s128;
 267 };
 268
 269 #if !defined(CONFIG_USER_ONLY)
 270 /* Software TLB cache */
 271 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 272 struct ppc6xx_tlb_t {
 273     target_ulong pte0;
 274     target_ulong pte1;
 275     target_ulong EPN;
 276 };
 277
 278 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 279 struct ppcemb_tlb_t {
 280     uint64_t RPN;
 281     target_ulong EPN;
 282     target_ulong PID;
 283     target_ulong size;
 284     uint32_t prot;
 285     uint32_t attr; /* Storage attributes */
 286 };
 287
 288 typedef struct ppcmas_tlb_t {
 289      uint32_t mas8;
 290      uint32_t mas1;
 291      uint64_t mas2;
 292      uint64_t mas7_3;
 293 } ppcmas_tlb_t;
 294
 295 union ppc_tlb_t {
 296     ppc6xx_tlb_t *tlb6;
 297     ppcemb_tlb_t *tlbe;
 298     ppcmas_tlb_t *tlbm;
 299 };
 300
 301 /* possible TLB variants */
 302 #define TLB_NONE               0
 303 #define TLB_6XX                1
 304 #define TLB_EMB                2
 305 #define TLB_MAS                3
 306 #endif
 307
 308 #define SDR_32_HTABORG         0xFFFF0000UL
 309 #define SDR_32_HTABMASK        0x000001FFUL
 310
 311 #if defined(TARGET_PPC64)
 312 #define SDR_64_HTABORG         0xFFFFFFFFFFFC0000ULL
 313 #define SDR_64_HTABSIZE        0x000000000000001FULL
 314 #endif /* defined(TARGET_PPC64 */
 315
 316 typedef struct ppc_slb_t ppc_slb_t;
 317 struct ppc_slb_t {
 318     uint64_t esid;
 319     uint64_t vsid;
 320     const struct ppc_one_seg_page_size *sps;
 321 };
 322
 323 #define MAX_SLB_ENTRIES         64
 324 #define SEGMENT_SHIFT_256M      28
 325 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 326
 327 #define SEGMENT_SHIFT_1T        40
 328 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 329
 330
 331 /*****************************************************************************/
 332 /* Machine state register bits definition                                    */
 333 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 334 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 335 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 336 #define MSR_SHV  60 /* hypervisor state                               hflags */
 337 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 338 #define MSR_TS1  33
 339 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 340 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 341 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 342 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 343 #define MSR_GS   28 /* guest state for BookE                                 */
 344 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 345 #define MSR_VR   25 /* altivec available                            x hflags */
 346 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 347 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 348 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 349 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 350 #define MSR_KEY  19 /* key bit on 603e                                       */
 351 #define MSR_POW  18 /* Power management                                      */
 352 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 353 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 354 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 355 #define MSR_EE   15 /* External interrupt enable                             */
 356 #define MSR_PR   14 /* Problem state                                  hflags */
 357 #define MSR_FP   13 /* Floating point available                       hflags */
 358 #define MSR_ME   12 /* Machine check interrupt enable                        */
 359 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 360 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 361 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 362 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 363 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 364 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 365 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 366 #define MSR_AL   7  /* AL bit on POWER                                       */
 367 #define MSR_EP   6  /* Exception prefix on 601                               */
 368 #define MSR_IR   5  /* Instruction relocate                                  */
 369 #define MSR_DR   4  /* Data relocate                                         */
 370 #define MSR_IS   5  /* Instruction address space (BookE)                     */
 371 #define MSR_DS   4  /* Data address space (BookE)                            */
 372 #define MSR_PE   3  /* Protection enable on 403                              */
 373 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 374 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 375 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 376 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 377
 378 /* LPCR bits */
 379 #define LPCR_VPM0         (1ull << (63 - 0))
 380 #define LPCR_VPM1         (1ull << (63 - 1))
 381 #define LPCR_ISL          (1ull << (63 - 2))
 382 #define LPCR_KBV          (1ull << (63 - 3))
 383 #define LPCR_DPFD_SHIFT   (63 - 11)
 384 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 385 #define LPCR_VRMASD_SHIFT (63 - 16)
 386 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 387 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
 388 #define LPCR_PECE_U_SHIFT (63 - 19)
 389 #define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
 390 #define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
 391 #define LPCR_RMLS_SHIFT   (63 - 37)
 392 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 393 #define LPCR_ILE          (1ull << (63 - 38))
 394 #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
 395 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 396 #define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process Table */
 397 #define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced Virtualisation */
 398 #define LPCR_ONL          (1ull << (63 - 45))
 399 #define LPCR_LD           (1ull << (63 - 46)) /* Large Decrementer */
 400 #define LPCR_P7_PECE0     (1ull << (63 - 49))
 401 #define LPCR_P7_PECE1     (1ull << (63 - 50))
 402 #define LPCR_P7_PECE2     (1ull << (63 - 51))
 403 #define LPCR_P8_PECE0     (1ull << (63 - 47))
 404 #define LPCR_P8_PECE1     (1ull << (63 - 48))
 405 #define LPCR_P8_PECE2     (1ull << (63 - 49))
 406 #define LPCR_P8_PECE3     (1ull << (63 - 50))
 407 #define LPCR_P8_PECE4     (1ull << (63 - 51))
 408 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
 409 #define LPCR_PECE_L_SHIFT (63 - 51)
 410 #define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
 411 #define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
 412 #define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
 413 #define LPCR_EEE          (1ull << (63 - 49)) /* External Exit Enable        */
 414 #define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer Exit Enable     */
 415 #define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit Enable           */
 416 #define LPCR_MER          (1ull << (63 - 52))
 417 #define LPCR_GTSE         (1ull << (63 - 53)) /* Guest Translation Shootdown */
 418 #define LPCR_TC           (1ull << (63 - 54))
 419 #define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern Interrupt Control */
 420 #define LPCR_LPES0        (1ull << (63 - 60))
 421 #define LPCR_LPES1        (1ull << (63 - 61))
 422 #define LPCR_RMI          (1ull << (63 - 62))
 423 #define LPCR_HVICE        (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
 424 #define LPCR_HDICE        (1ull << (63 - 63))
 425
 426 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 427 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 428 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 429 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 430 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 431 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 432 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 433 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 434 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 435 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 436 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 437 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 438 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 439 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 440 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 441 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 442 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 443 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 444 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 445 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 446 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 447 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 448 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 449 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 450 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 451 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 452 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 453 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 454 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 455 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 456 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 457 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 458 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 459 #define msr_is   ((env->msr >> MSR_IS)   & 1)
 460 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
 461 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 462 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 463 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 464 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 465 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 466 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 467 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
 468
 469 /* Hypervisor bit is more specific */
 470 #if defined(TARGET_PPC64)
 471 #define MSR_HVB (1ULL << MSR_SHV)
 472 #define msr_hv  msr_shv
 473 #else
 474 #if defined(PPC_EMULATE_32BITS_HYPV)
 475 #define MSR_HVB (1ULL << MSR_THV)
 476 #define msr_hv  msr_thv
 477 #else
 478 #define MSR_HVB (0ULL)
 479 #define msr_hv  (0)
 480 #endif
 481 #endif
 482
 483 /* Facility Status and Control (FSCR) bits */
 484 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 485 #define FSCR_TAR        (63 - 55) /* Target Address Register */
 486 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 487 #define FSCR_IC_MASK    (0xFFULL)
 488 #define FSCR_IC_POS     (63 - 7)
 489 #define FSCR_IC_DSCR_SPR3   2
 490 #define FSCR_IC_PMU         3
 491 #define FSCR_IC_BHRB        4
 492 #define FSCR_IC_TM          5
 493 #define FSCR_IC_EBB         7
 494 #define FSCR_IC_TAR         8
 495
 496 /* Exception state register bits definition                                  */
 497 #define ESR_PIL   (1 << (63 - 36)) /* Illegal Instruction                    */
 498 #define ESR_PPR   (1 << (63 - 37)) /* Privileged Instruction                 */
 499 #define ESR_PTR   (1 << (63 - 38)) /* Trap                                   */
 500 #define ESR_FP    (1 << (63 - 39)) /* Floating-Point Operation               */
 501 #define ESR_ST    (1 << (63 - 40)) /* Store Operation                        */
 502 #define ESR_AP    (1 << (63 - 44)) /* Auxiliary Processor Operation          */
 503 #define ESR_PUO   (1 << (63 - 45)) /* Unimplemented Operation                */
 504 #define ESR_BO    (1 << (63 - 46)) /* Byte Ordering                          */
 505 #define ESR_PIE   (1 << (63 - 47)) /* Imprecise exception                    */
 506 #define ESR_DATA  (1 << (63 - 53)) /* Data Access (Embedded page table)      */
 507 #define ESR_TLBI  (1 << (63 - 54)) /* TLB Ineligible (Embedded page table)   */
 508 #define ESR_PT    (1 << (63 - 55)) /* Page Table (Embedded page table)       */
 509 #define ESR_SPV   (1 << (63 - 56)) /* SPE/VMX operation                      */
 510 #define ESR_EPID  (1 << (63 - 57)) /* External Process ID operation          */
 511 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */
 512 #define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */
 513
 514 /* Transaction EXception And Summary Register bits                           */
 515 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 516 #define TEXASR_DISALLOWED                        (63 - 8)
 517 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 518 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 519 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 520 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 521 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 522 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 523 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 524 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 525 #define TEXASR_ABORT                             (63 - 31)
 526 #define TEXASR_SUSPENDED                         (63 - 32)
 527 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
 528 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
 529 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 530 #define TEXASR_TFIAR_EXACT                       (63 - 37)
 531 #define TEXASR_ROT                               (63 - 38)
 532 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 533
 534 enum {
 535     POWERPC_FLAG_NONE     = 0x00000000,
 536     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 537     POWERPC_FLAG_SPE      = 0x00000001,
 538     POWERPC_FLAG_VRE      = 0x00000002,
 539     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 540     POWERPC_FLAG_TGPR     = 0x00000004,
 541     POWERPC_FLAG_CE       = 0x00000008,
 542     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 543     POWERPC_FLAG_SE       = 0x00000010,
 544     POWERPC_FLAG_DWE      = 0x00000020,
 545     POWERPC_FLAG_UBLE     = 0x00000040,
 546     /* Flag for MSR bit 9 signification (BE/DE)                              */
 547     POWERPC_FLAG_BE       = 0x00000080,
 548     POWERPC_FLAG_DE       = 0x00000100,
 549     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 550     POWERPC_FLAG_PX       = 0x00000200,
 551     POWERPC_FLAG_PMM      = 0x00000400,
 552     /* Flag for special features                                             */
 553     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 554     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 555     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 556     /* Has CFAR                                                              */
 557     POWERPC_FLAG_CFAR     = 0x00040000,
 558     /* Has VSX                                                               */
 559     POWERPC_FLAG_VSX      = 0x00080000,
 560     /* Has Transaction Memory (ISA 2.07)                                     */
 561     POWERPC_FLAG_TM       = 0x00100000,
 562 };
 563
 564 /*****************************************************************************/
 565 /* Floating point status and control register                                */
 566 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 567 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 568 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 569 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 570 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 571 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 572 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 573 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 574 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 575 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 576 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 577 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 578 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 579 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 580 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 581 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 582 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 583 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 584 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 585 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 586 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 587 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 588 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 589 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 590 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 591 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 592 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 593 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 594 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 595 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 596 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 597 #define FPSCR_RN1    1
 598 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 599 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 600 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 601 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 602 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 603 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 604 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 605 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 606 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 607 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 608 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 609 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 610 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 611 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 612 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 613 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 614 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 615 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 616 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 617 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 618 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 619 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 620 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 621 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 622 /* Invalid operation exception summary */
 623 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 624                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 625                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 626                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 627                                   (1 << FPSCR_VXCVI)))
 628 /* exception summary */
 629 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 630 /* enabled exception summary */
 631 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 632                    0x1F)
 633
 634 #define FP_FX           (1ull << FPSCR_FX)
 635 #define FP_FEX          (1ull << FPSCR_FEX)
 636 #define FP_VX           (1ull << FPSCR_VX)
 637 #define FP_OX           (1ull << FPSCR_OX)
 638 #define FP_UX           (1ull << FPSCR_UX)
 639 #define FP_ZX           (1ull << FPSCR_ZX)
 640 #define FP_XX           (1ull << FPSCR_XX)
 641 #define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 642 #define FP_VXISI        (1ull << FPSCR_VXISI)
 643 #define FP_VXIDI        (1ull << FPSCR_VXIDI)
 644 #define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 645 #define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 646 #define FP_VXVC         (1ull << FPSCR_VXVC)
 647 #define FP_FR           (1ull << FSPCR_FR)
 648 #define FP_FI           (1ull << FPSCR_FI)
 649 #define FP_C            (1ull << FPSCR_C)
 650 #define FP_FL           (1ull << FPSCR_FL)
 651 #define FP_FG           (1ull << FPSCR_FG)
 652 #define FP_FE           (1ull << FPSCR_FE)
 653 #define FP_FU           (1ull << FPSCR_FU)
 654 #define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 655 #define FP_FPRF         (FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
 656 #define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 657 #define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 658 #define FP_VXCVI        (1ull << FPSCR_VXCVI)
 659 #define FP_VE           (1ull << FPSCR_VE)
 660 #define FP_OE           (1ull << FPSCR_OE)
 661 #define FP_UE           (1ull << FPSCR_UE)
 662 #define FP_ZE           (1ull << FPSCR_ZE)
 663 #define FP_XE           (1ull << FPSCR_XE)
 664 #define FP_NI           (1ull << FPSCR_NI)
 665 #define FP_RN1          (1ull << FPSCR_RN1)
 666 #define FP_RN           (1ull << FPSCR_RN)
 667
 668 /* the exception bits which can be cleared by mcrfs - includes FX */
 669 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 670                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 671                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 672                           FP_VXSQRT | FP_VXCVI)
 673
 674 /*****************************************************************************/
 675 /* Vector status and control register */
 676 #define VSCR_NJ         16 /* Vector non-java */
 677 #define VSCR_SAT        0 /* Vector saturation */
 678 #define vscr_nj         (((env->vscr) >> VSCR_NJ)       & 0x1)
 679 #define vscr_sat        (((env->vscr) >> VSCR_SAT)      & 0x1)
 680
 681 /*****************************************************************************/
 682 /* BookE e500 MMU registers */
 683
 684 #define MAS0_NV_SHIFT      0
 685 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 686
 687 #define MAS0_WQ_SHIFT      12
 688 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 689 /* Write TLB entry regardless of reservation */
 690 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 691 /* Write TLB entry only already in use */
 692 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 693 /* Clear TLB entry */
 694 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 695
 696 #define MAS0_HES_SHIFT     14
 697 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
 698
 699 #define MAS0_ESEL_SHIFT    16
 700 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 701
 702 #define MAS0_TLBSEL_SHIFT  28
 703 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 704 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 705 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 706 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 707 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 708
 709 #define MAS0_ATSEL_SHIFT   31
 710 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 711 #define MAS0_ATSEL_TLB     0
 712 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 713
 714 #define MAS1_TSIZE_SHIFT   7
 715 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 716
 717 #define MAS1_TS_SHIFT      12
 718 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
 719
 720 #define MAS1_IND_SHIFT     13
 721 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
 722
 723 #define MAS1_TID_SHIFT     16
 724 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 725
 726 #define MAS1_IPROT_SHIFT   30
 727 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 728
 729 #define MAS1_VALID_SHIFT   31
 730 #define MAS1_VALID         0x80000000
 731
 732 #define MAS2_EPN_SHIFT     12
 733 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 734
 735 #define MAS2_ACM_SHIFT     6
 736 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 737
 738 #define MAS2_VLE_SHIFT     5
 739 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 740
 741 #define MAS2_W_SHIFT       4
 742 #define MAS2_W             (1 << MAS2_W_SHIFT)
 743
 744 #define MAS2_I_SHIFT       3
 745 #define MAS2_I             (1 << MAS2_I_SHIFT)
 746
 747 #define MAS2_M_SHIFT       2
 748 #define MAS2_M             (1 << MAS2_M_SHIFT)
 749
 750 #define MAS2_G_SHIFT       1
 751 #define MAS2_G             (1 << MAS2_G_SHIFT)
 752
 753 #define MAS2_E_SHIFT       0
 754 #define MAS2_E             (1 << MAS2_E_SHIFT)
 755
 756 #define MAS3_RPN_SHIFT     12
 757 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 758
 759 #define MAS3_U0                 0x00000200
 760 #define MAS3_U1                 0x00000100
 761 #define MAS3_U2                 0x00000080
 762 #define MAS3_U3                 0x00000040
 763 #define MAS3_UX                 0x00000020
 764 #define MAS3_SX                 0x00000010
 765 #define MAS3_UW                 0x00000008
 766 #define MAS3_SW                 0x00000004
 767 #define MAS3_UR                 0x00000002
 768 #define MAS3_SR                 0x00000001
 769 #define MAS3_SPSIZE_SHIFT       1
 770 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 771
 772 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 773 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 774 #define MAS4_TIDSELD_MASK       0x00030000
 775 #define MAS4_TIDSELD_PID0       0x00000000
 776 #define MAS4_TIDSELD_PID1       0x00010000
 777 #define MAS4_TIDSELD_PID2       0x00020000
 778 #define MAS4_TIDSELD_PIDZ       0x00030000
 779 #define MAS4_INDD               0x00008000      /* Default IND */
 780 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 781 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 782 #define MAS4_ACMD               0x00000040
 783 #define MAS4_VLED               0x00000020
 784 #define MAS4_WD                 0x00000010
 785 #define MAS4_ID                 0x00000008
 786 #define MAS4_MD                 0x00000004
 787 #define MAS4_GD                 0x00000002
 788 #define MAS4_ED                 0x00000001
 789 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 790 #define MAS4_WIMGED_SHIFT       0
 791
 792 #define MAS5_SGS                0x80000000
 793 #define MAS5_SLPID_MASK         0x00000fff
 794
 795 #define MAS6_SPID0              0x3fff0000
 796 #define MAS6_SPID1              0x00007ffe
 797 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 798 #define MAS6_SAS                0x00000001
 799 #define MAS6_SPID               MAS6_SPID0
 800 #define MAS6_SIND               0x00000002      /* Indirect page */
 801 #define MAS6_SIND_SHIFT         1
 802 #define MAS6_SPID_MASK          0x3fff0000
 803 #define MAS6_SPID_SHIFT         16
 804 #define MAS6_ISIZE_MASK         0x00000f80
 805 #define MAS6_ISIZE_SHIFT        7
 806
 807 #define MAS7_RPN                0xffffffff
 808
 809 #define MAS8_TGS                0x80000000
 810 #define MAS8_VF                 0x40000000
 811 #define MAS8_TLBPID             0x00000fff
 812
 813 /* Bit definitions for MMUCFG */
 814 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 815 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 816 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 817 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 818 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 819 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 820 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 821 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 822 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 823
 824 /* Bit definitions for MMUCSR0 */
 825 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 826 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 827 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 828 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 829 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 830                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 831 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 832 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 833 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 834 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 835
 836 /* TLBnCFG encoding */
 837 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 838 #define TLBnCFG_HES             0x00002000      /* HW select supported */
 839 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 840 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 841 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 842 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 843 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
 844 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 845 #define TLBnCFG_MINSIZE_SHIFT   20
 846 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 847 #define TLBnCFG_MAXSIZE_SHIFT   16
 848 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 849 #define TLBnCFG_ASSOC_SHIFT     24
 850
 851 /* TLBnPS encoding */
 852 #define TLBnPS_4K               0x00000004
 853 #define TLBnPS_8K               0x00000008
 854 #define TLBnPS_16K              0x00000010
 855 #define TLBnPS_32K              0x00000020
 856 #define TLBnPS_64K              0x00000040
 857 #define TLBnPS_128K             0x00000080
 858 #define TLBnPS_256K             0x00000100
 859 #define TLBnPS_512K             0x00000200
 860 #define TLBnPS_1M               0x00000400
 861 #define TLBnPS_2M               0x00000800
 862 #define TLBnPS_4M               0x00001000
 863 #define TLBnPS_8M               0x00002000
 864 #define TLBnPS_16M              0x00004000
 865 #define TLBnPS_32M              0x00008000
 866 #define TLBnPS_64M              0x00010000
 867 #define TLBnPS_128M             0x00020000
 868 #define TLBnPS_256M             0x00040000
 869 #define TLBnPS_512M             0x00080000
 870 #define TLBnPS_1G               0x00100000
 871 #define TLBnPS_2G               0x00200000
 872 #define TLBnPS_4G               0x00400000
 873 #define TLBnPS_8G               0x00800000
 874 #define TLBnPS_16G              0x01000000
 875 #define TLBnPS_32G              0x02000000
 876 #define TLBnPS_64G              0x04000000
 877 #define TLBnPS_128G             0x08000000
 878 #define TLBnPS_256G             0x10000000
 879
 880 /* tlbilx action encoding */
 881 #define TLBILX_T_ALL                    0
 882 #define TLBILX_T_TID                    1
 883 #define TLBILX_T_FULLMATCH              3
 884 #define TLBILX_T_CLASS0                 4
 885 #define TLBILX_T_CLASS1                 5
 886 #define TLBILX_T_CLASS2                 6
 887 #define TLBILX_T_CLASS3                 7
 888
 889 /* BookE 2.06 helper defines */
 890
 891 #define BOOKE206_FLUSH_TLB0    (1 << 0)
 892 #define BOOKE206_FLUSH_TLB1    (1 << 1)
 893 #define BOOKE206_FLUSH_TLB2    (1 << 2)
 894 #define BOOKE206_FLUSH_TLB3    (1 << 3)
 895
 896 /* number of possible TLBs */
 897 #define BOOKE206_MAX_TLBN      4
 898
 899 /*****************************************************************************/
 900 /* Embedded.Processor Control */
 901
 902 #define DBELL_TYPE_SHIFT               27
 903 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 904 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 905 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 906 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 907 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 908 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 909
 910 #define DBELL_BRDCAST                  (1 << 26)
 911 #define DBELL_LPIDTAG_SHIFT            14
 912 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 913 #define DBELL_PIRTAG_MASK              0x3fff
 914
 915 /*****************************************************************************/
 916 /* Segment page size information, used by recent hash MMUs
 917  * The format of this structure mirrors kvm_ppc_smmu_info
 918  */
 919
 920 #define PPC_PAGE_SIZES_MAX_SZ   8
 921
 922 struct ppc_one_page_size {
 923     uint32_t page_shift;  /* Page shift (or 0) */
 924     uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
 925 };
 926
 927 struct ppc_one_seg_page_size {
 928     uint32_t page_shift;  /* Base page shift of segment (or 0) */
 929     uint32_t slb_enc;     /* SLB encoding for BookS */
 930     struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
 931 };
 932
 933 struct ppc_segment_page_sizes {
 934     struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
 935 };
 936
 937
 938 /*****************************************************************************/
 939 /* The whole PowerPC CPU context */
 940 #define NB_MMU_MODES    8
 941
 942 #define PPC_CPU_OPCODES_LEN          0x40
 943 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 944
 945 struct CPUPPCState {
 946     /* First are the most commonly used resources
 947      * during translated code execution
 948      */
 949     /* general purpose registers */
 950     target_ulong gpr[32];
 951     /* Storage for GPR MSB, used by the SPE extension */
 952     target_ulong gprh[32];
 953     /* LR */
 954     target_ulong lr;
 955     /* CTR */
 956     target_ulong ctr;
 957     /* condition register */
 958     uint32_t crf[8];
 959 #if defined(TARGET_PPC64)
 960     /* CFAR */
 961     target_ulong cfar;
 962 #endif
 963     /* XER (with SO, OV, CA split out) */
 964     target_ulong xer;
 965     target_ulong so;
 966     target_ulong ov;
 967     target_ulong ca;
 968     /* Reservation address */
 969     target_ulong reserve_addr;
 970     /* Reservation value */
 971     target_ulong reserve_val;
 972     target_ulong reserve_val2;
 973     /* Reservation store address */
 974     target_ulong reserve_ea;
 975     /* Reserved store source register and size */
 976     target_ulong reserve_info;
 977
 978     /* Those ones are used in supervisor mode only */
 979     /* machine state register */
 980     target_ulong msr;
 981     /* temporary general purpose registers */
 982     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
 983
 984     /* Floating point execution context */
 985     float_status fp_status;
 986     /* floating point registers */
 987     float64 fpr[32];
 988     /* floating point status and control register */
 989     target_ulong fpscr;
 990
 991     /* Next instruction pointer */
 992     target_ulong nip;
 993
 994     int access_type; /* when a memory exception occurs, the access
 995                         type is stored here */
 996
 997     CPU_COMMON
 998
 999     /* MMU context - only relevant for full system emulation */
1000 #if !defined(CONFIG_USER_ONLY)
1001 #if defined(TARGET_PPC64)
1002     /* PowerPC 64 SLB area */
1003     ppc_slb_t slb[MAX_SLB_ENTRIES];
1004     int32_t slb_nr;
1005     /* tcg TLB needs flush (deferred slb inval instruction typically) */
1006 #endif
1007     /* segment registers */
1008     hwaddr htab_base;
1009     /* mask used to normalize hash value to PTEG index */
1010     hwaddr htab_mask;
1011     target_ulong sr[32];
1012     /* externally stored hash table */
1013     uint8_t *external_htab;
1014     /* BATs */
1015     uint32_t nb_BATs;
1016     target_ulong DBAT[2][8];
1017     target_ulong IBAT[2][8];
1018     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1019     int32_t nb_tlb;      /* Total number of TLB                              */
1020     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1021     int nb_ways;     /* Number of ways in the TLB set                        */
1022     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1023     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1024     int nb_pids;     /* Number of available PID registers                    */
1025     int tlb_type;    /* Type of TLB we're dealing with                       */
1026     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1027     /* 403 dedicated access protection registers */
1028     target_ulong pb[4];
1029     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1030     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1031     uint32_t tlb_need_flush; /* Delayed flush needed */
1032 #define TLB_NEED_LOCAL_FLUSH   0x1
1033 #define TLB_NEED_GLOBAL_FLUSH  0x2
1034 #endif
1035
1036     /* Other registers */
1037     /* Special purpose registers */
1038     target_ulong spr[1024];
1039     ppc_spr_t spr_cb[1024];
1040     /* Altivec registers */
1041     ppc_avr_t avr[32];
1042     uint32_t vscr;
1043     /* VSX registers */
1044     uint64_t vsr[32];
1045     /* SPE registers */
1046     uint64_t spe_acc;
1047     uint32_t spe_fscr;
1048     /* SPE and Altivec can share a status since they will never be used
1049      * simultaneously */
1050     float_status vec_status;
1051
1052     /* Internal devices resources */
1053     /* Time base and decrementer */
1054     ppc_tb_t *tb_env;
1055     /* Device control registers */
1056     ppc_dcr_t *dcr_env;
1057
1058     int dcache_line_size;
1059     int icache_line_size;
1060
1061     /* Those resources are used during exception processing */
1062     /* CPU model definition */
1063     target_ulong msr_mask;
1064     powerpc_mmu_t mmu_model;
1065     powerpc_excp_t excp_model;
1066     powerpc_input_t bus_model;
1067     int bfd_mach;
1068     uint32_t flags;
1069     uint64_t insns_flags;
1070     uint64_t insns_flags2;
1071 #if defined(TARGET_PPC64)
1072     struct ppc_segment_page_sizes sps;
1073     ppc_slb_t vrma_slb;
1074     target_ulong rmls;
1075     bool ci_large_pages;
1076 #endif
1077
1078 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1079     uint64_t vpa_addr;
1080     uint64_t slb_shadow_addr, slb_shadow_size;
1081     uint64_t dtl_addr, dtl_size;
1082 #endif /* TARGET_PPC64 */
1083
1084     int error_code;
1085     uint32_t pending_interrupts;
1086 #if !defined(CONFIG_USER_ONLY)
1087     /* This is the IRQ controller, which is implementation dependent
1088      * and only relevant when emulating a complete machine.
1089      */
1090     uint32_t irq_input_state;
1091     void **irq_inputs;
1092     /* Exception vectors */
1093     target_ulong excp_vectors[POWERPC_EXCP_NB];
1094     target_ulong excp_prefix;
1095     target_ulong ivor_mask;
1096     target_ulong ivpr_mask;
1097     target_ulong hreset_vector;
1098     hwaddr mpic_iack;
1099     /* true when the external proxy facility mode is enabled */
1100     bool mpic_proxy;
1101     /* set when the processor has an HV mode, thus HV priv
1102      * instructions and SPRs are diallowed if MSR:HV is 0
1103      */
1104     bool has_hv_mode;
1105     /* On P7/P8, set when in PM state, we need to handle resume
1106      * in a special way (such as routing some resume causes to
1107      * 0x100), so flag this here.
1108      */
1109     bool in_pm_state;
1110 #endif
1111
1112     /* Those resources are used only during code translation */
1113     /* opcode handlers */
1114     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1115
1116     /* Those resources are used only in QEMU core */
1117     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1118     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1119     int immu_idx;         /* precomputed MMU index to speed up insn access */
1120     int dmmu_idx;         /* precomputed MMU index to speed up data accesses */
1121
1122     /* Power management */
1123     int (*check_pow)(CPUPPCState *env);
1124
1125 #if !defined(CONFIG_USER_ONLY)
1126     void *load_info;    /* Holds boot loading state.  */
1127 #endif
1128
1129     /* booke timers */
1130
1131     /* Specifies bit locations of the Time Base used to signal a fixed timer
1132      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1133      *
1134      * 0 selects the least significant bit.
1135      * 63 selects the most significant bit.
1136      */
1137     uint8_t fit_period[4];
1138     uint8_t wdt_period[4];
1139
1140     /* Transactional memory state */
1141     target_ulong tm_gpr[32];
1142     ppc_avr_t tm_vsr[64];
1143     uint64_t tm_cr;
1144     uint64_t tm_lr;
1145     uint64_t tm_ctr;
1146     uint64_t tm_fpscr;
1147     uint64_t tm_amr;
1148     uint64_t tm_ppr;
1149     uint64_t tm_vrsave;
1150     uint32_t tm_vscr;
1151     uint64_t tm_dscr;
1152     uint64_t tm_tar;
1153 };
1154
1155 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1156 do {                                            \
1157     env->fit_period[0] = (a_);                  \
1158     env->fit_period[1] = (b_);                  \
1159     env->fit_period[2] = (c_);                  \
1160     env->fit_period[3] = (d_);                  \
1161  } while (0)
1162
1163 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1164 do {                                            \
1165     env->wdt_period[0] = (a_);                  \
1166     env->wdt_period[1] = (b_);                  \
1167     env->wdt_period[2] = (c_);                  \
1168     env->wdt_period[3] = (d_);                  \
1169  } while (0)
1170
1171 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1172 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1173
1174 /**
1175  * PowerPCCPU:
1176  * @env: #CPUPPCState
1177  * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
1178  * @max_compat: Maximal supported logical PVR from the command line
1179  * @compat_pvr: Current logical PVR, zero if in "raw" mode
1180  *
1181  * A PowerPC CPU.
1182  */
1183 struct PowerPCCPU {
1184     /*< private >*/
1185     CPUState parent_obj;
1186     /*< public >*/
1187
1188     CPUPPCState env;
1189     int cpu_dt_id;
1190     uint32_t max_compat;
1191     uint32_t compat_pvr;
1192     PPCVirtualHypervisor *vhyp;
1193
1194     /* Fields related to migration compatibility hacks */
1195     bool pre_2_8_migration;
1196     target_ulong mig_msr_mask;
1197     uint64_t mig_insns_flags;
1198     uint64_t mig_insns_flags2;
1199     uint32_t mig_nb_BATs;
1200 };
1201
1202 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1203 {
1204     return container_of(env, PowerPCCPU, env);
1205 }
1206
1207 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1208
1209 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1210
1211 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1212 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1213
1214 struct PPCVirtualHypervisor {
1215     Object parent;
1216 };
1217
1218 struct PPCVirtualHypervisorClass {
1219     InterfaceClass parent;
1220     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1221 };
1222
1223 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1224 #define PPC_VIRTUAL_HYPERVISOR(obj)                 \
1225     OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1226 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass)         \
1227     OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1228                        TYPE_PPC_VIRTUAL_HYPERVISOR)
1229 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1230     OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1231                      TYPE_PPC_VIRTUAL_HYPERVISOR)
1232
1233 void ppc_cpu_do_interrupt(CPUState *cpu);
1234 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1235 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1236                         int flags);
1237 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1238                              fprintf_function cpu_fprintf, int flags);
1239 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1240 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1241 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1242 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1243 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1244 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1245                                int cpuid, void *opaque);
1246 #ifndef CONFIG_USER_ONLY
1247 void ppc_cpu_do_system_reset(CPUState *cs);
1248 extern const struct VMStateDescription vmstate_ppc_cpu;
1249 #endif
1250
1251 /*****************************************************************************/
1252 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1253 void ppc_translate_init(void);
1254 const char *ppc_cpu_lookup_alias(const char *alias);
1255 /* you can call this signal handler from your SIGBUS and SIGSEGV
1256    signal handlers to inform the virtual CPU of exceptions. non zero
1257    is returned if the signal was handled by the virtual CPU.  */
1258 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1259                             void *puc);
1260 #if defined(CONFIG_USER_ONLY)
1261 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1262                              int mmu_idx);
1263 #endif
1264
1265 #if !defined(CONFIG_USER_ONLY)
1266 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1267 #endif /* !defined(CONFIG_USER_ONLY) */
1268 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1269
1270 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1271 #if defined(TARGET_PPC64)
1272 #endif
1273
1274 /* Time-base and decrementer management */
1275 #ifndef NO_CPU_IO_DEFS
1276 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1277 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1278 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1279 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1280 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1281 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1282 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1283 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1284 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1285 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1286 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1287 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1288 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1289 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1290 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1291 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1292 #if !defined(CONFIG_USER_ONLY)
1293 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1294 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1295 target_ulong load_40x_pit (CPUPPCState *env);
1296 void store_40x_pit (CPUPPCState *env, target_ulong val);
1297 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1298 void store_40x_sler (CPUPPCState *env, uint32_t val);
1299 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1300 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1301 void ppc_tlb_invalidate_all (CPUPPCState *env);
1302 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1303 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1304 void cpu_ppc_set_papr(PowerPCCPU *cpu);
1305 #endif
1306 #endif
1307
1308 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1309
1310 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1311 {
1312     uint64_t gprv;
1313
1314     gprv = env->gpr[gprn];
1315     if (env->flags & POWERPC_FLAG_SPE) {
1316         /* If the CPU implements the SPE extension, we have to get the
1317          * high bits of the GPR from the gprh storage area
1318          */
1319         gprv &= 0xFFFFFFFFULL;
1320         gprv |= (uint64_t)env->gprh[gprn] << 32;
1321     }
1322
1323     return gprv;
1324 }
1325
1326 /* Device control registers */
1327 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1328 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1329
1330 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1331
1332 #define cpu_signal_handler cpu_ppc_signal_handler
1333 #define cpu_list ppc_cpu_list
1334
1335 /* MMU modes definitions */
1336 #define MMU_USER_IDX 0
1337 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1338 {
1339     return ifetch ? env->immu_idx : env->dmmu_idx;
1340 }
1341
1342 /* Compatibility modes */
1343 #if defined(TARGET_PPC64)
1344 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1345                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1346 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1347 #if !defined(CONFIG_USER_ONLY)
1348 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1349 #endif
1350 int ppc_compat_max_threads(PowerPCCPU *cpu);
1351 #endif /* defined(TARGET_PPC64) */
1352
1353 #include "exec/cpu-all.h"
1354
1355 /*****************************************************************************/
1356 /* CRF definitions */
1357 #define CRF_LT_BIT    3
1358 #define CRF_GT_BIT    2
1359 #define CRF_EQ_BIT    1
1360 #define CRF_SO_BIT    0
1361 #define CRF_LT        (1 << CRF_LT_BIT)
1362 #define CRF_GT        (1 << CRF_GT_BIT)
1363 #define CRF_EQ        (1 << CRF_EQ_BIT)
1364 #define CRF_SO        (1 << CRF_SO_BIT)
1365 /* For SPE extensions */
1366 #define CRF_CH        (1 << CRF_LT_BIT)
1367 #define CRF_CL        (1 << CRF_GT_BIT)
1368 #define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1369 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1370
1371 /* XER definitions */
1372 #define XER_SO  31
1373 #define XER_OV  30
1374 #define XER_CA  29
1375 #define XER_CMP  8
1376 #define XER_BC   0
1377 #define xer_so  (env->so)
1378 #define xer_ov  (env->ov)
1379 #define xer_ca  (env->ca)
1380 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1381 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1382
1383 /* SPR definitions */
1384 #define SPR_MQ                (0x000)
1385 #define SPR_XER               (0x001)
1386 #define SPR_601_VRTCU         (0x004)
1387 #define SPR_601_VRTCL         (0x005)
1388 #define SPR_601_UDECR         (0x006)
1389 #define SPR_LR                (0x008)
1390 #define SPR_CTR               (0x009)
1391 #define SPR_UAMR              (0x00C)
1392 #define SPR_DSCR              (0x011)
1393 #define SPR_DSISR             (0x012)
1394 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1395 #define SPR_601_RTCU          (0x014)
1396 #define SPR_601_RTCL          (0x015)
1397 #define SPR_DECR              (0x016)
1398 #define SPR_SDR1              (0x019)
1399 #define SPR_SRR0              (0x01A)
1400 #define SPR_SRR1              (0x01B)
1401 #define SPR_CFAR              (0x01C)
1402 #define SPR_AMR               (0x01D)
1403 #define SPR_ACOP              (0x01F)
1404 #define SPR_BOOKE_PID         (0x030)
1405 #define SPR_BOOKS_PID         (0x030)
1406 #define SPR_BOOKE_DECAR       (0x036)
1407 #define SPR_BOOKE_CSRR0       (0x03A)
1408 #define SPR_BOOKE_CSRR1       (0x03B)
1409 #define SPR_BOOKE_DEAR        (0x03D)
1410 #define SPR_IAMR              (0x03D)
1411 #define SPR_BOOKE_ESR         (0x03E)
1412 #define SPR_BOOKE_IVPR        (0x03F)
1413 #define SPR_MPC_EIE           (0x050)
1414 #define SPR_MPC_EID           (0x051)
1415 #define SPR_MPC_NRI           (0x052)
1416 #define SPR_TFHAR             (0x080)
1417 #define SPR_TFIAR             (0x081)
1418 #define SPR_TEXASR            (0x082)
1419 #define SPR_TEXASRU           (0x083)
1420 #define SPR_UCTRL             (0x088)
1421 #define SPR_MPC_CMPA          (0x090)
1422 #define SPR_MPC_CMPB          (0x091)
1423 #define SPR_MPC_CMPC          (0x092)
1424 #define SPR_MPC_CMPD          (0x093)
1425 #define SPR_MPC_ECR           (0x094)
1426 #define SPR_MPC_DER           (0x095)
1427 #define SPR_MPC_COUNTA        (0x096)
1428 #define SPR_MPC_COUNTB        (0x097)
1429 #define SPR_CTRL              (0x098)
1430 #define SPR_MPC_CMPE          (0x098)
1431 #define SPR_MPC_CMPF          (0x099)
1432 #define SPR_FSCR              (0x099)
1433 #define SPR_MPC_CMPG          (0x09A)
1434 #define SPR_MPC_CMPH          (0x09B)
1435 #define SPR_MPC_LCTRL1        (0x09C)
1436 #define SPR_MPC_LCTRL2        (0x09D)
1437 #define SPR_UAMOR             (0x09D)
1438 #define SPR_MPC_ICTRL         (0x09E)
1439 #define SPR_MPC_BAR           (0x09F)
1440 #define SPR_PSPB              (0x09F)
1441 #define SPR_DAWR              (0x0B4)
1442 #define SPR_RPR               (0x0BA)
1443 #define SPR_CIABR             (0x0BB)
1444 #define SPR_DAWRX             (0x0BC)
1445 #define SPR_HFSCR             (0x0BE)
1446 #define SPR_VRSAVE            (0x100)
1447 #define SPR_USPRG0            (0x100)
1448 #define SPR_USPRG1            (0x101)
1449 #define SPR_USPRG2            (0x102)
1450 #define SPR_USPRG3            (0x103)
1451 #define SPR_USPRG4            (0x104)
1452 #define SPR_USPRG5            (0x105)
1453 #define SPR_USPRG6            (0x106)
1454 #define SPR_USPRG7            (0x107)
1455 #define SPR_VTBL              (0x10C)
1456 #define SPR_VTBU              (0x10D)
1457 #define SPR_SPRG0             (0x110)
1458 #define SPR_SPRG1             (0x111)
1459 #define SPR_SPRG2             (0x112)
1460 #define SPR_SPRG3             (0x113)
1461 #define SPR_SPRG4             (0x114)
1462 #define SPR_SCOMC             (0x114)
1463 #define SPR_SPRG5             (0x115)
1464 #define SPR_SCOMD             (0x115)
1465 #define SPR_SPRG6             (0x116)
1466 #define SPR_SPRG7             (0x117)
1467 #define SPR_ASR               (0x118)
1468 #define SPR_EAR               (0x11A)
1469 #define SPR_TBL               (0x11C)
1470 #define SPR_TBU               (0x11D)
1471 #define SPR_TBU40             (0x11E)
1472 #define SPR_SVR               (0x11E)
1473 #define SPR_BOOKE_PIR         (0x11E)
1474 #define SPR_PVR               (0x11F)
1475 #define SPR_HSPRG0            (0x130)
1476 #define SPR_BOOKE_DBSR        (0x130)
1477 #define SPR_HSPRG1            (0x131)
1478 #define SPR_HDSISR            (0x132)
1479 #define SPR_HDAR              (0x133)
1480 #define SPR_BOOKE_EPCR        (0x133)
1481 #define SPR_SPURR             (0x134)
1482 #define SPR_BOOKE_DBCR0       (0x134)
1483 #define SPR_IBCR              (0x135)
1484 #define SPR_PURR              (0x135)
1485 #define SPR_BOOKE_DBCR1       (0x135)
1486 #define SPR_DBCR              (0x136)
1487 #define SPR_HDEC              (0x136)
1488 #define SPR_BOOKE_DBCR2       (0x136)
1489 #define SPR_HIOR              (0x137)
1490 #define SPR_MBAR              (0x137)
1491 #define SPR_RMOR              (0x138)
1492 #define SPR_BOOKE_IAC1        (0x138)
1493 #define SPR_HRMOR             (0x139)
1494 #define SPR_BOOKE_IAC2        (0x139)
1495 #define SPR_HSRR0             (0x13A)
1496 #define SPR_BOOKE_IAC3        (0x13A)
1497 #define SPR_HSRR1             (0x13B)
1498 #define SPR_BOOKE_IAC4        (0x13B)
1499 #define SPR_BOOKE_DAC1        (0x13C)
1500 #define SPR_MMCRH             (0x13C)
1501 #define SPR_DABR2             (0x13D)
1502 #define SPR_BOOKE_DAC2        (0x13D)
1503 #define SPR_TFMR              (0x13D)
1504 #define SPR_BOOKE_DVC1        (0x13E)
1505 #define SPR_LPCR              (0x13E)
1506 #define SPR_BOOKE_DVC2        (0x13F)
1507 #define SPR_LPIDR             (0x13F)
1508 #define SPR_BOOKE_TSR         (0x150)
1509 #define SPR_HMER              (0x150)
1510 #define SPR_HMEER             (0x151)
1511 #define SPR_PCR               (0x152)
1512 #define SPR_BOOKE_LPIDR       (0x152)
1513 #define SPR_BOOKE_TCR         (0x154)
1514 #define SPR_BOOKE_TLB0PS      (0x158)
1515 #define SPR_BOOKE_TLB1PS      (0x159)
1516 #define SPR_BOOKE_TLB2PS      (0x15A)
1517 #define SPR_BOOKE_TLB3PS      (0x15B)
1518 #define SPR_AMOR              (0x15D)
1519 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1520 #define SPR_BOOKE_IVOR0       (0x190)
1521 #define SPR_BOOKE_IVOR1       (0x191)
1522 #define SPR_BOOKE_IVOR2       (0x192)
1523 #define SPR_BOOKE_IVOR3       (0x193)
1524 #define SPR_BOOKE_IVOR4       (0x194)
1525 #define SPR_BOOKE_IVOR5       (0x195)
1526 #define SPR_BOOKE_IVOR6       (0x196)
1527 #define SPR_BOOKE_IVOR7       (0x197)
1528 #define SPR_BOOKE_IVOR8       (0x198)
1529 #define SPR_BOOKE_IVOR9       (0x199)
1530 #define SPR_BOOKE_IVOR10      (0x19A)
1531 #define SPR_BOOKE_IVOR11      (0x19B)
1532 #define SPR_BOOKE_IVOR12      (0x19C)
1533 #define SPR_BOOKE_IVOR13      (0x19D)
1534 #define SPR_BOOKE_IVOR14      (0x19E)
1535 #define SPR_BOOKE_IVOR15      (0x19F)
1536 #define SPR_BOOKE_IVOR38      (0x1B0)
1537 #define SPR_BOOKE_IVOR39      (0x1B1)
1538 #define SPR_BOOKE_IVOR40      (0x1B2)
1539 #define SPR_BOOKE_IVOR41      (0x1B3)
1540 #define SPR_BOOKE_IVOR42      (0x1B4)
1541 #define SPR_BOOKE_GIVOR2      (0x1B8)
1542 #define SPR_BOOKE_GIVOR3      (0x1B9)
1543 #define SPR_BOOKE_GIVOR4      (0x1BA)
1544 #define SPR_BOOKE_GIVOR8      (0x1BB)
1545 #define SPR_BOOKE_GIVOR13     (0x1BC)
1546 #define SPR_BOOKE_GIVOR14     (0x1BD)
1547 #define SPR_TIR               (0x1BE)
1548 #define SPR_BOOKE_SPEFSCR     (0x200)
1549 #define SPR_Exxx_BBEAR        (0x201)
1550 #define SPR_Exxx_BBTAR        (0x202)
1551 #define SPR_Exxx_L1CFG0       (0x203)
1552 #define SPR_Exxx_L1CFG1       (0x204)
1553 #define SPR_Exxx_NPIDR        (0x205)
1554 #define SPR_ATBL              (0x20E)
1555 #define SPR_ATBU              (0x20F)
1556 #define SPR_IBAT0U            (0x210)
1557 #define SPR_BOOKE_IVOR32      (0x210)
1558 #define SPR_RCPU_MI_GRA       (0x210)
1559 #define SPR_IBAT0L            (0x211)
1560 #define SPR_BOOKE_IVOR33      (0x211)
1561 #define SPR_IBAT1U            (0x212)
1562 #define SPR_BOOKE_IVOR34      (0x212)
1563 #define SPR_IBAT1L            (0x213)
1564 #define SPR_BOOKE_IVOR35      (0x213)
1565 #define SPR_IBAT2U            (0x214)
1566 #define SPR_BOOKE_IVOR36      (0x214)
1567 #define SPR_IBAT2L            (0x215)
1568 #define SPR_BOOKE_IVOR37      (0x215)
1569 #define SPR_IBAT3U            (0x216)
1570 #define SPR_IBAT3L            (0x217)
1571 #define SPR_DBAT0U            (0x218)
1572 #define SPR_RCPU_L2U_GRA      (0x218)
1573 #define SPR_DBAT0L            (0x219)
1574 #define SPR_DBAT1U            (0x21A)
1575 #define SPR_DBAT1L            (0x21B)
1576 #define SPR_DBAT2U            (0x21C)
1577 #define SPR_DBAT2L            (0x21D)
1578 #define SPR_DBAT3U            (0x21E)
1579 #define SPR_DBAT3L            (0x21F)
1580 #define SPR_IBAT4U            (0x230)
1581 #define SPR_RPCU_BBCMCR       (0x230)
1582 #define SPR_MPC_IC_CST        (0x230)
1583 #define SPR_Exxx_CTXCR        (0x230)
1584 #define SPR_IBAT4L            (0x231)
1585 #define SPR_MPC_IC_ADR        (0x231)
1586 #define SPR_Exxx_DBCR3        (0x231)
1587 #define SPR_IBAT5U            (0x232)
1588 #define SPR_MPC_IC_DAT        (0x232)
1589 #define SPR_Exxx_DBCNT        (0x232)
1590 #define SPR_IBAT5L            (0x233)
1591 #define SPR_IBAT6U            (0x234)
1592 #define SPR_IBAT6L            (0x235)
1593 #define SPR_IBAT7U            (0x236)
1594 #define SPR_IBAT7L            (0x237)
1595 #define SPR_DBAT4U            (0x238)
1596 #define SPR_RCPU_L2U_MCR      (0x238)
1597 #define SPR_MPC_DC_CST        (0x238)
1598 #define SPR_Exxx_ALTCTXCR     (0x238)
1599 #define SPR_DBAT4L            (0x239)
1600 #define SPR_MPC_DC_ADR        (0x239)
1601 #define SPR_DBAT5U            (0x23A)
1602 #define SPR_BOOKE_MCSRR0      (0x23A)
1603 #define SPR_MPC_DC_DAT        (0x23A)
1604 #define SPR_DBAT5L            (0x23B)
1605 #define SPR_BOOKE_MCSRR1      (0x23B)
1606 #define SPR_DBAT6U            (0x23C)
1607 #define SPR_BOOKE_MCSR        (0x23C)
1608 #define SPR_DBAT6L            (0x23D)
1609 #define SPR_Exxx_MCAR         (0x23D)
1610 #define SPR_DBAT7U            (0x23E)
1611 #define SPR_BOOKE_DSRR0       (0x23E)
1612 #define SPR_DBAT7L            (0x23F)
1613 #define SPR_BOOKE_DSRR1       (0x23F)
1614 #define SPR_BOOKE_SPRG8       (0x25C)
1615 #define SPR_BOOKE_SPRG9       (0x25D)
1616 #define SPR_BOOKE_MAS0        (0x270)
1617 #define SPR_BOOKE_MAS1        (0x271)
1618 #define SPR_BOOKE_MAS2        (0x272)
1619 #define SPR_BOOKE_MAS3        (0x273)
1620 #define SPR_BOOKE_MAS4        (0x274)
1621 #define SPR_BOOKE_MAS5        (0x275)
1622 #define SPR_BOOKE_MAS6        (0x276)
1623 #define SPR_BOOKE_PID1        (0x279)
1624 #define SPR_BOOKE_PID2        (0x27A)
1625 #define SPR_MPC_DPDR          (0x280)
1626 #define SPR_MPC_IMMR          (0x288)
1627 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1628 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1629 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1630 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1631 #define SPR_BOOKE_EPR         (0x2BE)
1632 #define SPR_PERF0             (0x300)
1633 #define SPR_RCPU_MI_RBA0      (0x300)
1634 #define SPR_MPC_MI_CTR        (0x300)
1635 #define SPR_POWER_USIER       (0x300)
1636 #define SPR_PERF1             (0x301)
1637 #define SPR_RCPU_MI_RBA1      (0x301)
1638 #define SPR_POWER_UMMCR2      (0x301)
1639 #define SPR_PERF2             (0x302)
1640 #define SPR_RCPU_MI_RBA2      (0x302)
1641 #define SPR_MPC_MI_AP         (0x302)
1642 #define SPR_POWER_UMMCRA      (0x302)
1643 #define SPR_PERF3             (0x303)
1644 #define SPR_RCPU_MI_RBA3      (0x303)
1645 #define SPR_MPC_MI_EPN        (0x303)
1646 #define SPR_POWER_UPMC1       (0x303)
1647 #define SPR_PERF4             (0x304)
1648 #define SPR_POWER_UPMC2       (0x304)
1649 #define SPR_PERF5             (0x305)
1650 #define SPR_MPC_MI_TWC        (0x305)
1651 #define SPR_POWER_UPMC3       (0x305)
1652 #define SPR_PERF6             (0x306)
1653 #define SPR_MPC_MI_RPN        (0x306)
1654 #define SPR_POWER_UPMC4       (0x306)
1655 #define SPR_PERF7             (0x307)
1656 #define SPR_POWER_UPMC5       (0x307)
1657 #define SPR_PERF8             (0x308)
1658 #define SPR_RCPU_L2U_RBA0     (0x308)
1659 #define SPR_MPC_MD_CTR        (0x308)
1660 #define SPR_POWER_UPMC6       (0x308)
1661 #define SPR_PERF9             (0x309)
1662 #define SPR_RCPU_L2U_RBA1     (0x309)
1663 #define SPR_MPC_MD_CASID      (0x309)
1664 #define SPR_970_UPMC7         (0X309)
1665 #define SPR_PERFA             (0x30A)
1666 #define SPR_RCPU_L2U_RBA2     (0x30A)
1667 #define SPR_MPC_MD_AP         (0x30A)
1668 #define SPR_970_UPMC8         (0X30A)
1669 #define SPR_PERFB             (0x30B)
1670 #define SPR_RCPU_L2U_RBA3     (0x30B)
1671 #define SPR_MPC_MD_EPN        (0x30B)
1672 #define SPR_POWER_UMMCR0      (0X30B)
1673 #define SPR_PERFC             (0x30C)
1674 #define SPR_MPC_MD_TWB        (0x30C)
1675 #define SPR_POWER_USIAR       (0X30C)
1676 #define SPR_PERFD             (0x30D)
1677 #define SPR_MPC_MD_TWC        (0x30D)
1678 #define SPR_POWER_USDAR       (0X30D)
1679 #define SPR_PERFE             (0x30E)
1680 #define SPR_MPC_MD_RPN        (0x30E)
1681 #define SPR_POWER_UMMCR1      (0X30E)
1682 #define SPR_PERFF             (0x30F)
1683 #define SPR_MPC_MD_TW         (0x30F)
1684 #define SPR_UPERF0            (0x310)
1685 #define SPR_POWER_SIER        (0x310)
1686 #define SPR_UPERF1            (0x311)
1687 #define SPR_POWER_MMCR2       (0x311)
1688 #define SPR_UPERF2            (0x312)
1689 #define SPR_POWER_MMCRA       (0X312)
1690 #define SPR_UPERF3            (0x313)
1691 #define SPR_POWER_PMC1        (0X313)
1692 #define SPR_UPERF4            (0x314)
1693 #define SPR_POWER_PMC2        (0X314)
1694 #define SPR_UPERF5            (0x315)
1695 #define SPR_POWER_PMC3        (0X315)
1696 #define SPR_UPERF6            (0x316)
1697 #define SPR_POWER_PMC4        (0X316)
1698 #define SPR_UPERF7            (0x317)
1699 #define SPR_POWER_PMC5        (0X317)
1700 #define SPR_UPERF8            (0x318)
1701 #define SPR_POWER_PMC6        (0X318)
1702 #define SPR_UPERF9            (0x319)
1703 #define SPR_970_PMC7          (0X319)
1704 #define SPR_UPERFA            (0x31A)
1705 #define SPR_970_PMC8          (0X31A)
1706 #define SPR_UPERFB            (0x31B)
1707 #define SPR_POWER_MMCR0       (0X31B)
1708 #define SPR_UPERFC            (0x31C)
1709 #define SPR_POWER_SIAR        (0X31C)
1710 #define SPR_UPERFD            (0x31D)
1711 #define SPR_POWER_SDAR        (0X31D)
1712 #define SPR_UPERFE            (0x31E)
1713 #define SPR_POWER_MMCR1       (0X31E)
1714 #define SPR_UPERFF            (0x31F)
1715 #define SPR_RCPU_MI_RA0       (0x320)
1716 #define SPR_MPC_MI_DBCAM      (0x320)
1717 #define SPR_BESCRS            (0x320)
1718 #define SPR_RCPU_MI_RA1       (0x321)
1719 #define SPR_MPC_MI_DBRAM0     (0x321)
1720 #define SPR_BESCRSU           (0x321)
1721 #define SPR_RCPU_MI_RA2       (0x322)
1722 #define SPR_MPC_MI_DBRAM1     (0x322)
1723 #define SPR_BESCRR            (0x322)
1724 #define SPR_RCPU_MI_RA3       (0x323)
1725 #define SPR_BESCRRU           (0x323)
1726 #define SPR_EBBHR             (0x324)
1727 #define SPR_EBBRR             (0x325)
1728 #define SPR_BESCR             (0x326)
1729 #define SPR_RCPU_L2U_RA0      (0x328)
1730 #define SPR_MPC_MD_DBCAM      (0x328)
1731 #define SPR_RCPU_L2U_RA1      (0x329)
1732 #define SPR_MPC_MD_DBRAM0     (0x329)
1733 #define SPR_RCPU_L2U_RA2      (0x32A)
1734 #define SPR_MPC_MD_DBRAM1     (0x32A)
1735 #define SPR_RCPU_L2U_RA3      (0x32B)
1736 #define SPR_TAR               (0x32F)
1737 #define SPR_IC                (0x350)
1738 #define SPR_VTB               (0x351)
1739 #define SPR_MMCRC             (0x353)
1740 #define SPR_440_INV0          (0x370)
1741 #define SPR_440_INV1          (0x371)
1742 #define SPR_440_INV2          (0x372)
1743 #define SPR_440_INV3          (0x373)
1744 #define SPR_440_ITV0          (0x374)
1745 #define SPR_440_ITV1          (0x375)
1746 #define SPR_440_ITV2          (0x376)
1747 #define SPR_440_ITV3          (0x377)
1748 #define SPR_440_CCR1          (0x378)
1749 #define SPR_TACR              (0x378)
1750 #define SPR_TCSCR             (0x379)
1751 #define SPR_CSIGR             (0x37a)
1752 #define SPR_DCRIPR            (0x37B)
1753 #define SPR_POWER_SPMC1       (0x37C)
1754 #define SPR_POWER_SPMC2       (0x37D)
1755 #define SPR_POWER_MMCRS       (0x37E)
1756 #define SPR_WORT              (0x37F)
1757 #define SPR_PPR               (0x380)
1758 #define SPR_750_GQR0          (0x390)
1759 #define SPR_440_DNV0          (0x390)
1760 #define SPR_750_GQR1          (0x391)
1761 #define SPR_440_DNV1          (0x391)
1762 #define SPR_750_GQR2          (0x392)
1763 #define SPR_440_DNV2          (0x392)
1764 #define SPR_750_GQR3          (0x393)
1765 #define SPR_440_DNV3          (0x393)
1766 #define SPR_750_GQR4          (0x394)
1767 #define SPR_440_DTV0          (0x394)
1768 #define SPR_750_GQR5          (0x395)
1769 #define SPR_440_DTV1          (0x395)
1770 #define SPR_750_GQR6          (0x396)
1771 #define SPR_440_DTV2          (0x396)
1772 #define SPR_750_GQR7          (0x397)
1773 #define SPR_440_DTV3          (0x397)
1774 #define SPR_750_THRM4         (0x398)
1775 #define SPR_750CL_HID2        (0x398)
1776 #define SPR_440_DVLIM         (0x398)
1777 #define SPR_750_WPAR          (0x399)
1778 #define SPR_440_IVLIM         (0x399)
1779 #define SPR_TSCR              (0x399)
1780 #define SPR_750_DMAU          (0x39A)
1781 #define SPR_750_DMAL          (0x39B)
1782 #define SPR_440_RSTCFG        (0x39B)
1783 #define SPR_BOOKE_DCDBTRL     (0x39C)
1784 #define SPR_BOOKE_DCDBTRH     (0x39D)
1785 #define SPR_BOOKE_ICDBTRL     (0x39E)
1786 #define SPR_BOOKE_ICDBTRH     (0x39F)
1787 #define SPR_74XX_UMMCR2       (0x3A0)
1788 #define SPR_7XX_UPMC5         (0x3A1)
1789 #define SPR_7XX_UPMC6         (0x3A2)
1790 #define SPR_UBAMR             (0x3A7)
1791 #define SPR_7XX_UMMCR0        (0x3A8)
1792 #define SPR_7XX_UPMC1         (0x3A9)
1793 #define SPR_7XX_UPMC2         (0x3AA)
1794 #define SPR_7XX_USIAR         (0x3AB)
1795 #define SPR_7XX_UMMCR1        (0x3AC)
1796 #define SPR_7XX_UPMC3         (0x3AD)
1797 #define SPR_7XX_UPMC4         (0x3AE)
1798 #define SPR_USDA              (0x3AF)
1799 #define SPR_40x_ZPR           (0x3B0)
1800 #define SPR_BOOKE_MAS7        (0x3B0)
1801 #define SPR_74XX_MMCR2        (0x3B0)
1802 #define SPR_7XX_PMC5          (0x3B1)
1803 #define SPR_40x_PID           (0x3B1)
1804 #define SPR_7XX_PMC6          (0x3B2)
1805 #define SPR_440_MMUCR         (0x3B2)
1806 #define SPR_4xx_CCR0          (0x3B3)
1807 #define SPR_BOOKE_EPLC        (0x3B3)
1808 #define SPR_405_IAC3          (0x3B4)
1809 #define SPR_BOOKE_EPSC        (0x3B4)
1810 #define SPR_405_IAC4          (0x3B5)
1811 #define SPR_405_DVC1          (0x3B6)
1812 #define SPR_405_DVC2          (0x3B7)
1813 #define SPR_BAMR              (0x3B7)
1814 #define SPR_7XX_MMCR0         (0x3B8)
1815 #define SPR_7XX_PMC1          (0x3B9)
1816 #define SPR_40x_SGR           (0x3B9)
1817 #define SPR_7XX_PMC2          (0x3BA)
1818 #define SPR_40x_DCWR          (0x3BA)
1819 #define SPR_7XX_SIAR          (0x3BB)
1820 #define SPR_405_SLER          (0x3BB)
1821 #define SPR_7XX_MMCR1         (0x3BC)
1822 #define SPR_405_SU0R          (0x3BC)
1823 #define SPR_401_SKR           (0x3BC)
1824 #define SPR_7XX_PMC3          (0x3BD)
1825 #define SPR_405_DBCR1         (0x3BD)
1826 #define SPR_7XX_PMC4          (0x3BE)
1827 #define SPR_SDA               (0x3BF)
1828 #define SPR_403_VTBL          (0x3CC)
1829 #define SPR_403_VTBU          (0x3CD)
1830 #define SPR_DMISS             (0x3D0)
1831 #define SPR_DCMP              (0x3D1)
1832 #define SPR_HASH1             (0x3D2)
1833 #define SPR_HASH2             (0x3D3)
1834 #define SPR_BOOKE_ICDBDR      (0x3D3)
1835 #define SPR_TLBMISS           (0x3D4)
1836 #define SPR_IMISS             (0x3D4)
1837 #define SPR_40x_ESR           (0x3D4)
1838 #define SPR_PTEHI             (0x3D5)
1839 #define SPR_ICMP              (0x3D5)
1840 #define SPR_40x_DEAR          (0x3D5)
1841 #define SPR_PTELO             (0x3D6)
1842 #define SPR_RPA               (0x3D6)
1843 #define SPR_40x_EVPR          (0x3D6)
1844 #define SPR_L3PM              (0x3D7)
1845 #define SPR_403_CDBCR         (0x3D7)
1846 #define SPR_L3ITCR0           (0x3D8)
1847 #define SPR_TCR               (0x3D8)
1848 #define SPR_40x_TSR           (0x3D8)
1849 #define SPR_IBR               (0x3DA)
1850 #define SPR_40x_TCR           (0x3DA)
1851 #define SPR_ESASRR            (0x3DB)
1852 #define SPR_40x_PIT           (0x3DB)
1853 #define SPR_403_TBL           (0x3DC)
1854 #define SPR_403_TBU           (0x3DD)
1855 #define SPR_SEBR              (0x3DE)
1856 #define SPR_40x_SRR2          (0x3DE)
1857 #define SPR_SER               (0x3DF)
1858 #define SPR_40x_SRR3          (0x3DF)
1859 #define SPR_L3OHCR            (0x3E8)
1860 #define SPR_L3ITCR1           (0x3E9)
1861 #define SPR_L3ITCR2           (0x3EA)
1862 #define SPR_L3ITCR3           (0x3EB)
1863 #define SPR_HID0              (0x3F0)
1864 #define SPR_40x_DBSR          (0x3F0)
1865 #define SPR_HID1              (0x3F1)
1866 #define SPR_IABR              (0x3F2)
1867 #define SPR_40x_DBCR0         (0x3F2)
1868 #define SPR_601_HID2          (0x3F2)
1869 #define SPR_Exxx_L1CSR0       (0x3F2)
1870 #define SPR_ICTRL             (0x3F3)
1871 #define SPR_HID2              (0x3F3)
1872 #define SPR_750CL_HID4        (0x3F3)
1873 #define SPR_Exxx_L1CSR1       (0x3F3)
1874 #define SPR_440_DBDR          (0x3F3)
1875 #define SPR_LDSTDB            (0x3F4)
1876 #define SPR_750_TDCL          (0x3F4)
1877 #define SPR_40x_IAC1          (0x3F4)
1878 #define SPR_MMUCSR0           (0x3F4)
1879 #define SPR_970_HID4          (0x3F4)
1880 #define SPR_DABR              (0x3F5)
1881 #define DABR_MASK (~(target_ulong)0x7)
1882 #define SPR_Exxx_BUCSR        (0x3F5)
1883 #define SPR_40x_IAC2          (0x3F5)
1884 #define SPR_601_HID5          (0x3F5)
1885 #define SPR_40x_DAC1          (0x3F6)
1886 #define SPR_MSSCR0            (0x3F6)
1887 #define SPR_970_HID5          (0x3F6)
1888 #define SPR_MSSSR0            (0x3F7)
1889 #define SPR_MSSCR1            (0x3F7)
1890 #define SPR_DABRX             (0x3F7)
1891 #define SPR_40x_DAC2          (0x3F7)
1892 #define SPR_MMUCFG            (0x3F7)
1893 #define SPR_LDSTCR            (0x3F8)
1894 #define SPR_L2PMCR            (0x3F8)
1895 #define SPR_750FX_HID2        (0x3F8)
1896 #define SPR_Exxx_L1FINV0      (0x3F8)
1897 #define SPR_L2CR              (0x3F9)
1898 #define SPR_L3CR              (0x3FA)
1899 #define SPR_750_TDCH          (0x3FA)
1900 #define SPR_IABR2             (0x3FA)
1901 #define SPR_40x_DCCR          (0x3FA)
1902 #define SPR_ICTC              (0x3FB)
1903 #define SPR_40x_ICCR          (0x3FB)
1904 #define SPR_THRM1             (0x3FC)
1905 #define SPR_403_PBL1          (0x3FC)
1906 #define SPR_SP                (0x3FD)
1907 #define SPR_THRM2             (0x3FD)
1908 #define SPR_403_PBU1          (0x3FD)
1909 #define SPR_604_HID13         (0x3FD)
1910 #define SPR_LT                (0x3FE)
1911 #define SPR_THRM3             (0x3FE)
1912 #define SPR_RCPU_FPECR        (0x3FE)
1913 #define SPR_403_PBL2          (0x3FE)
1914 #define SPR_PIR               (0x3FF)
1915 #define SPR_403_PBU2          (0x3FF)
1916 #define SPR_601_HID15         (0x3FF)
1917 #define SPR_604_HID15         (0x3FF)
1918 #define SPR_E500_SVR          (0x3FF)
1919
1920 /* Disable MAS Interrupt Updates for Hypervisor */
1921 #define EPCR_DMIUH            (1 << 22)
1922 /* Disable Guest TLB Management Instructions */
1923 #define EPCR_DGTMI            (1 << 23)
1924 /* Guest Interrupt Computation Mode */
1925 #define EPCR_GICM             (1 << 24)
1926 /* Interrupt Computation Mode */
1927 #define EPCR_ICM              (1 << 25)
1928 /* Disable Embedded Hypervisor Debug */
1929 #define EPCR_DUVD             (1 << 26)
1930 /* Instruction Storage Interrupt Directed to Guest State */
1931 #define EPCR_ISIGS            (1 << 27)
1932 /* Data Storage Interrupt Directed to Guest State */
1933 #define EPCR_DSIGS            (1 << 28)
1934 /* Instruction TLB Error Interrupt Directed to Guest State */
1935 #define EPCR_ITLBGS           (1 << 29)
1936 /* Data TLB Error Interrupt Directed to Guest State */
1937 #define EPCR_DTLBGS           (1 << 30)
1938 /* External Input Interrupt Directed to Guest State */
1939 #define EPCR_EXTGS            (1 << 31)
1940
1941 #define   L1CSR0_CPE            0x00010000      /* Data Cache Parity Enable */
1942 #define   L1CSR0_CUL            0x00000400      /* (D-)Cache Unable to Lock */
1943 #define   L1CSR0_DCLFR          0x00000100      /* D-Cache Lock Flash Reset */
1944 #define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
1945 #define   L1CSR0_DCE            0x00000001      /* Data Cache Enable */
1946
1947 #define   L1CSR1_CPE            0x00010000      /* Instruction Cache Parity Enable */
1948 #define   L1CSR1_ICUL           0x00000400      /* I-Cache Unable to Lock */
1949 #define   L1CSR1_ICLFR          0x00000100      /* I-Cache Lock Flash Reset */
1950 #define   L1CSR1_ICFI           0x00000002      /* Instruction Cache Flash Invalidate */
1951 #define   L1CSR1_ICE            0x00000001      /* Instruction Cache Enable */
1952
1953 /* HID0 bits */
1954 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
1955 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
1956 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
1957 #define HID0_HILE           (1ull << (63 - 19)) /* POWER8 */
1958
1959 /*****************************************************************************/
1960 /* PowerPC Instructions types definitions                                    */
1961 enum {
1962     PPC_NONE           = 0x0000000000000000ULL,
1963     /* PowerPC base instructions set                                         */
1964     PPC_INSNS_BASE     = 0x0000000000000001ULL,
1965     /*   integer operations instructions                                     */
1966 #define PPC_INTEGER PPC_INSNS_BASE
1967     /*   flow control instructions                                           */
1968 #define PPC_FLOW    PPC_INSNS_BASE
1969     /*   virtual memory instructions                                         */
1970 #define PPC_MEM     PPC_INSNS_BASE
1971     /*   ld/st with reservation instructions                                 */
1972 #define PPC_RES     PPC_INSNS_BASE
1973     /*   spr/msr access instructions                                         */
1974 #define PPC_MISC    PPC_INSNS_BASE
1975     /* Deprecated instruction sets                                           */
1976     /*   Original POWER instruction set                                      */
1977     PPC_POWER          = 0x0000000000000002ULL,
1978     /*   POWER2 instruction set extension                                    */
1979     PPC_POWER2         = 0x0000000000000004ULL,
1980     /*   Power RTC support                                                   */
1981     PPC_POWER_RTC      = 0x0000000000000008ULL,
1982     /*   Power-to-PowerPC bridge (601)                                       */
1983     PPC_POWER_BR       = 0x0000000000000010ULL,
1984     /* 64 bits PowerPC instruction set                                       */
1985     PPC_64B            = 0x0000000000000020ULL,
1986     /*   New 64 bits extensions (PowerPC 2.0x)                               */
1987     PPC_64BX           = 0x0000000000000040ULL,
1988     /*   64 bits hypervisor extensions                                       */
1989     PPC_64H            = 0x0000000000000080ULL,
1990     /*   New wait instruction (PowerPC 2.0x)                                 */
1991     PPC_WAIT           = 0x0000000000000100ULL,
1992     /*   Time base mftb instruction                                          */
1993     PPC_MFTB           = 0x0000000000000200ULL,
1994
1995     /* Fixed-point unit extensions                                           */
1996     /*   PowerPC 602 specific                                                */
1997     PPC_602_SPEC       = 0x0000000000000400ULL,
1998     /*   isel instruction                                                    */
1999     PPC_ISEL           = 0x0000000000000800ULL,
2000     /*   popcntb instruction                                                 */
2001     PPC_POPCNTB        = 0x0000000000001000ULL,
2002     /*   string load / store                                                 */
2003     PPC_STRING         = 0x0000000000002000ULL,
2004     /*   real mode cache inhibited load / store                              */
2005     PPC_CILDST         = 0x0000000000004000ULL,
2006
2007     /* Floating-point unit extensions                                        */
2008     /*   Optional floating point instructions                                */
2009     PPC_FLOAT          = 0x0000000000010000ULL,
2010     /* New floating-point extensions (PowerPC 2.0x)                          */
2011     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2012     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2013     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2014     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2015     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2016     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2017     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2018
2019     /* Vector/SIMD extensions                                                */
2020     /*   Altivec support                                                     */
2021     PPC_ALTIVEC        = 0x0000000001000000ULL,
2022     /*   PowerPC 2.03 SPE extension                                          */
2023     PPC_SPE            = 0x0000000002000000ULL,
2024     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2025     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2026     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2027     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2028
2029     /* Optional memory control instructions                                  */
2030     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2031     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2032     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2033     /*   sync instruction                                                    */
2034     PPC_MEM_SYNC       = 0x0000000080000000ULL,
2035     /*   eieio instruction                                                   */
2036     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2037
2038     /* Cache control instructions                                            */
2039     PPC_CACHE          = 0x0000000200000000ULL,
2040     /*   icbi instruction                                                    */
2041     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2042     /*   dcbz instruction                                                    */
2043     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2044     /*   dcba instruction                                                    */
2045     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2046     /*   Freescale cache locking instructions                                */
2047     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2048
2049     /* MMU related extensions                                                */
2050     /*   external control instructions                                       */
2051     PPC_EXTERN         = 0x0000010000000000ULL,
2052     /*   segment register access instructions                                */
2053     PPC_SEGMENT        = 0x0000020000000000ULL,
2054     /*   PowerPC 6xx TLB management instructions                             */
2055     PPC_6xx_TLB        = 0x0000040000000000ULL,
2056     /* PowerPC 74xx TLB management instructions                              */
2057     PPC_74xx_TLB       = 0x0000080000000000ULL,
2058     /*   PowerPC 40x TLB management instructions                             */
2059     PPC_40x_TLB        = 0x0000100000000000ULL,
2060     /*   segment register access instructions for PowerPC 64 "bridge"        */
2061     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2062     /*   SLB management                                                      */
2063     PPC_SLBI           = 0x0000400000000000ULL,
2064
2065     /* Embedded PowerPC dedicated instructions                               */
2066     PPC_WRTEE          = 0x0001000000000000ULL,
2067     /* PowerPC 40x exception model                                           */
2068     PPC_40x_EXCP       = 0x0002000000000000ULL,
2069     /* PowerPC 405 Mac instructions                                          */
2070     PPC_405_MAC        = 0x0004000000000000ULL,
2071     /* PowerPC 440 specific instructions                                     */
2072     PPC_440_SPEC       = 0x0008000000000000ULL,
2073     /* BookE (embedded) PowerPC specification                                */
2074     PPC_BOOKE          = 0x0010000000000000ULL,
2075     /* mfapidi instruction                                                   */
2076     PPC_MFAPIDI        = 0x0020000000000000ULL,
2077     /* tlbiva instruction                                                    */
2078     PPC_TLBIVA         = 0x0040000000000000ULL,
2079     /* tlbivax instruction                                                   */
2080     PPC_TLBIVAX        = 0x0080000000000000ULL,
2081     /* PowerPC 4xx dedicated instructions                                    */
2082     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2083     /* PowerPC 40x ibct instructions                                         */
2084     PPC_40x_ICBT       = 0x0200000000000000ULL,
2085     /* rfmci is not implemented in all BookE PowerPC                         */
2086     PPC_RFMCI          = 0x0400000000000000ULL,
2087     /* rfdi instruction                                                      */
2088     PPC_RFDI           = 0x0800000000000000ULL,
2089     /* DCR accesses                                                          */
2090     PPC_DCR            = 0x1000000000000000ULL,
2091     /* DCR extended accesse                                                  */
2092     PPC_DCRX           = 0x2000000000000000ULL,
2093     /* user-mode DCR access, implemented in PowerPC 460                      */
2094     PPC_DCRUX          = 0x4000000000000000ULL,
2095     /* popcntw and popcntd instructions                                      */
2096     PPC_POPCNTWD       = 0x8000000000000000ULL,
2097
2098 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2099                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2100                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2101                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2102                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2103                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2104                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2105                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2106                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2107                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2108                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2109                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2110                         | PPC_CACHE | PPC_CACHE_ICBI \
2111                         | PPC_CACHE_DCBZ \
2112                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2113                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2114                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2115                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2116                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2117                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2118                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2119                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2120                         | PPC_POPCNTWD | PPC_CILDST)
2121
2122     /* extended type values */
2123
2124     /* BookE 2.06 PowerPC specification                                      */
2125     PPC2_BOOKE206      = 0x0000000000000001ULL,
2126     /* VSX (extensions to Altivec / VMX)                                     */
2127     PPC2_VSX           = 0x0000000000000002ULL,
2128     /* Decimal Floating Point (DFP)                                          */
2129     PPC2_DFP           = 0x0000000000000004ULL,
2130     /* Embedded.Processor Control                                            */
2131     PPC2_PRCNTL        = 0x0000000000000008ULL,
2132     /* Byte-reversed, indexed, double-word load and store                    */
2133     PPC2_DBRX          = 0x0000000000000010ULL,
2134     /* Book I 2.05 PowerPC specification                                     */
2135     PPC2_ISA205        = 0x0000000000000020ULL,
2136     /* VSX additions in ISA 2.07                                             */
2137     PPC2_VSX207        = 0x0000000000000040ULL,
2138     /* ISA 2.06B bpermd                                                      */
2139     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2140     /* ISA 2.06B divide extended variants                                    */
2141     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2142     /* ISA 2.06B larx/stcx. instructions                                     */
2143     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2144     /* ISA 2.06B floating point integer conversion                           */
2145     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2146     /* ISA 2.06B floating point test instructions                            */
2147     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2148     /* ISA 2.07 bctar instruction                                            */
2149     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2150     /* ISA 2.07 load/store quadword                                          */
2151     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2152     /* ISA 2.07 Altivec                                                      */
2153     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2154     /* PowerISA 2.07 Book3s specification                                    */
2155     PPC2_ISA207S       = 0x0000000000008000ULL,
2156     /* Double precision floating point conversion for signed integer 64      */
2157     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2158     /* Transactional Memory (ISA 2.07, Book II)                              */
2159     PPC2_TM            = 0x0000000000020000ULL,
2160     /* Server PM instructgions (ISA 2.06, Book III)                          */
2161     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2162     /* POWER ISA 3.0                                                         */
2163     PPC2_ISA300        = 0x0000000000080000ULL,
2164
2165 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2166                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2167                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2168                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2169                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2170                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2171                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2172                         PPC2_ISA300)
2173 };
2174
2175 /*****************************************************************************/
2176 /* Memory access type :
2177  * may be needed for precise access rights control and precise exceptions.
2178  */
2179 enum {
2180     /* 1 bit to define user level / supervisor access */
2181     ACCESS_USER  = 0x00,
2182     ACCESS_SUPER = 0x01,
2183     /* Type of instruction that generated the access */
2184     ACCESS_CODE  = 0x10, /* Code fetch access                */
2185     ACCESS_INT   = 0x20, /* Integer load/store access        */
2186     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2187     ACCESS_RES   = 0x40, /* load/store with reservation      */
2188     ACCESS_EXT   = 0x50, /* external access                  */
2189     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2190 };
2191
2192 /* Hardware interruption sources:
2193  * all those exception can be raised simulteaneously
2194  */
2195 /* Input pins definitions */
2196 enum {
2197     /* 6xx bus input pins */
2198     PPC6xx_INPUT_HRESET     = 0,
2199     PPC6xx_INPUT_SRESET     = 1,
2200     PPC6xx_INPUT_CKSTP_IN   = 2,
2201     PPC6xx_INPUT_MCP        = 3,
2202     PPC6xx_INPUT_SMI        = 4,
2203     PPC6xx_INPUT_INT        = 5,
2204     PPC6xx_INPUT_TBEN       = 6,
2205     PPC6xx_INPUT_WAKEUP     = 7,
2206     PPC6xx_INPUT_NB,
2207 };
2208
2209 enum {
2210     /* Embedded PowerPC input pins */
2211     PPCBookE_INPUT_HRESET     = 0,
2212     PPCBookE_INPUT_SRESET     = 1,
2213     PPCBookE_INPUT_CKSTP_IN   = 2,
2214     PPCBookE_INPUT_MCP        = 3,
2215     PPCBookE_INPUT_SMI        = 4,
2216     PPCBookE_INPUT_INT        = 5,
2217     PPCBookE_INPUT_CINT       = 6,
2218     PPCBookE_INPUT_NB,
2219 };
2220
2221 enum {
2222     /* PowerPC E500 input pins */
2223     PPCE500_INPUT_RESET_CORE = 0,
2224     PPCE500_INPUT_MCK        = 1,
2225     PPCE500_INPUT_CINT       = 3,
2226     PPCE500_INPUT_INT        = 4,
2227     PPCE500_INPUT_DEBUG      = 6,
2228     PPCE500_INPUT_NB,
2229 };
2230
2231 enum {
2232     /* PowerPC 40x input pins */
2233     PPC40x_INPUT_RESET_CORE = 0,
2234     PPC40x_INPUT_RESET_CHIP = 1,
2235     PPC40x_INPUT_RESET_SYS  = 2,
2236     PPC40x_INPUT_CINT       = 3,
2237     PPC40x_INPUT_INT        = 4,
2238     PPC40x_INPUT_HALT       = 5,
2239     PPC40x_INPUT_DEBUG      = 6,
2240     PPC40x_INPUT_NB,
2241 };
2242
2243 enum {
2244     /* RCPU input pins */
2245     PPCRCPU_INPUT_PORESET   = 0,
2246     PPCRCPU_INPUT_HRESET    = 1,
2247     PPCRCPU_INPUT_SRESET    = 2,
2248     PPCRCPU_INPUT_IRQ0      = 3,
2249     PPCRCPU_INPUT_IRQ1      = 4,
2250     PPCRCPU_INPUT_IRQ2      = 5,
2251     PPCRCPU_INPUT_IRQ3      = 6,
2252     PPCRCPU_INPUT_IRQ4      = 7,
2253     PPCRCPU_INPUT_IRQ5      = 8,
2254     PPCRCPU_INPUT_IRQ6      = 9,
2255     PPCRCPU_INPUT_IRQ7      = 10,
2256     PPCRCPU_INPUT_NB,
2257 };
2258
2259 #if defined(TARGET_PPC64)
2260 enum {
2261     /* PowerPC 970 input pins */
2262     PPC970_INPUT_HRESET     = 0,
2263     PPC970_INPUT_SRESET     = 1,
2264     PPC970_INPUT_CKSTP      = 2,
2265     PPC970_INPUT_TBEN       = 3,
2266     PPC970_INPUT_MCP        = 4,
2267     PPC970_INPUT_INT        = 5,
2268     PPC970_INPUT_THINT      = 6,
2269     PPC970_INPUT_NB,
2270 };
2271
2272 enum {
2273     /* POWER7 input pins */
2274     POWER7_INPUT_INT        = 0,
2275     /* POWER7 probably has other inputs, but we don't care about them
2276      * for any existing machine.  We can wire these up when we need
2277      * them */
2278     POWER7_INPUT_NB,
2279 };
2280 #endif
2281
2282 /* Hardware exceptions definitions */
2283 enum {
2284     /* External hardware exception sources */
2285     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2286     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2287     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2288     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2289     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2290     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2291     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2292     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2293     /* Internal hardware exception sources */
2294     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2295     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2296     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2297     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2298     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2299     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2300     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2301     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2302     PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
2303     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2304 };
2305
2306 /* Processor Compatibility mask (PCR) */
2307 enum {
2308     PCR_COMPAT_2_05     = 1ull << (63-62),
2309     PCR_COMPAT_2_06     = 1ull << (63-61),
2310     PCR_COMPAT_2_07     = 1ull << (63-60),
2311     PCR_COMPAT_3_00     = 1ull << (63-59),
2312     PCR_VEC_DIS         = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2313     PCR_VSX_DIS         = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2314     PCR_TM_DIS          = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2315 };
2316
2317 /* HMER/HMEER */
2318 enum {
2319     HMER_MALFUNCTION_ALERT      = 1ull << (63 - 0),
2320     HMER_PROC_RECV_DONE         = 1ull << (63 - 2),
2321     HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2322     HMER_TFAC_ERROR             = 1ull << (63 - 4),
2323     HMER_TFMR_PARITY_ERROR      = 1ull << (63 - 5),
2324     HMER_XSCOM_FAIL             = 1ull << (63 - 8),
2325     HMER_XSCOM_DONE             = 1ull << (63 - 9),
2326     HMER_PROC_RECV_AGAIN        = 1ull << (63 - 11),
2327     HMER_WARN_RISE              = 1ull << (63 - 14),
2328     HMER_WARN_FALL              = 1ull << (63 - 15),
2329     HMER_SCOM_FIR_HMI           = 1ull << (63 - 16),
2330     HMER_TRIG_FIR_HMI           = 1ull << (63 - 17),
2331     HMER_HYP_RESOURCE_ERR       = 1ull << (63 - 20),
2332     HMER_XSCOM_STATUS_MASK      = 7ull << (63 - 23),
2333     HMER_XSCOM_STATUS_LSH       = (63 - 23),
2334 };
2335
2336 /* Alternate Interrupt Location (AIL) */
2337 enum {
2338     AIL_NONE                = 0,
2339     AIL_RESERVED            = 1,
2340     AIL_0001_8000           = 2,
2341     AIL_C000_0000_0000_4000 = 3,
2342 };
2343
2344 /*****************************************************************************/
2345
2346 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2347 {
2348     return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2349 }
2350
2351 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2352 {
2353     env->so = (xer >> XER_SO) & 1;
2354     env->ov = (xer >> XER_OV) & 1;
2355     env->ca = (xer >> XER_CA) & 1;
2356     env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2357 }
2358
2359 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2360                                         target_ulong *cs_base, uint32_t *flags)
2361 {
2362     *pc = env->nip;
2363     *cs_base = 0;
2364     *flags = env->hflags;
2365 }
2366
2367 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2368 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2369                                       uintptr_t raddr);
2370 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2371                                        uint32_t error_code);
2372 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2373                                           uint32_t error_code, uintptr_t raddr);
2374
2375 #if !defined(CONFIG_USER_ONLY)
2376 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2377 {
2378     uintptr_t tlbml = (uintptr_t)tlbm;
2379     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2380
2381     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2382 }
2383
2384 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2385 {
2386     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2387     int r = tlbncfg & TLBnCFG_N_ENTRY;
2388     return r;
2389 }
2390
2391 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2392 {
2393     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2394     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2395     return r;
2396 }
2397
2398 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2399 {
2400     int id = booke206_tlbm_id(env, tlbm);
2401     int end = 0;
2402     int i;
2403
2404     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2405         end += booke206_tlb_size(env, i);
2406         if (id < end) {
2407             return i;
2408         }
2409     }
2410
2411     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2412     return 0;
2413 }
2414
2415 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2416 {
2417     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2418     int tlbid = booke206_tlbm_id(env, tlb);
2419     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2420 }
2421
2422 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2423                                               target_ulong ea, int way)
2424 {
2425     int r;
2426     uint32_t ways = booke206_tlb_ways(env, tlbn);
2427     int ways_bits = ctz32(ways);
2428     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2429     int i;
2430
2431     way &= ways - 1;
2432     ea >>= MAS2_EPN_SHIFT;
2433     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2434     r = (ea << ways_bits) | way;
2435
2436     if (r >= booke206_tlb_size(env, tlbn)) {
2437         return NULL;
2438     }
2439
2440     /* bump up to tlbn index */
2441     for (i = 0; i < tlbn; i++) {
2442         r += booke206_tlb_size(env, i);
2443     }
2444
2445     return &env->tlb.tlbm[r];
2446 }
2447
2448 /* returns bitmap of supported page sizes for a given TLB */
2449 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2450 {
2451     bool mav2 = false;
2452     uint32_t ret = 0;
2453
2454     if (mav2) {
2455         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2456     } else {
2457         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2458         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2459         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2460         int i;
2461         for (i = min; i <= max; i++) {
2462             ret |= (1 << (i << 1));
2463         }
2464     }
2465
2466     return ret;
2467 }
2468
2469 #endif
2470
2471 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2472 {
2473     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2474         return msr & (1ULL << MSR_CM);
2475     }
2476
2477     return msr & (1ULL << MSR_SF);
2478 }
2479
2480 /**
2481  * Check whether register rx is in the range between start and
2482  * start + nregs (as needed by the LSWX and LSWI instructions)
2483  */
2484 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2485 {
2486     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2487            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2488 }
2489
2490 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2491
2492 /**
2493  * ppc_get_vcpu_dt_id:
2494  * @cs: a PowerPCCPU struct.
2495  *
2496  * Returns a device-tree ID for a CPU.
2497  */
2498 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2499
2500 /**
2501  * ppc_get_vcpu_by_dt_id:
2502  * @cpu_dt_id: a device tree id
2503  *
2504  * Searches for a CPU by @cpu_dt_id.
2505  *
2506  * Returns: a PowerPCCPU struct
2507  */
2508 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2509
2510 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2511 #endif /* PPC_CPU_H */