2 * PowerPC emulation cpu definitions for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/int128.h"
24 #include "exec/cpu-defs.h"
26 #include "qom/object.h"
28 #define TCG_GUEST_DEFAULT_MO 0
30 #define TARGET_PAGE_BITS_64K 16
31 #define TARGET_PAGE_BITS_16M 24
33 #if defined(TARGET_PPC64)
34 #define PPC_ELF_MACHINE EM_PPC64
36 #define PPC_ELF_MACHINE EM_PPC
39 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
40 #define PPC_BIT32(bit) (0x80000000 >> (bit))
41 #define PPC_BIT8(bit) (0x80 >> (bit))
42 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
43 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
45 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
47 /*****************************************************************************/
48 /* Exception vectors definitions */
50 POWERPC_EXCP_NONE
= -1,
51 /* The 64 first entries are used by the PowerPC embedded specification */
52 POWERPC_EXCP_CRITICAL
= 0, /* Critical input */
53 POWERPC_EXCP_MCHECK
= 1, /* Machine check exception */
54 POWERPC_EXCP_DSI
= 2, /* Data storage exception */
55 POWERPC_EXCP_ISI
= 3, /* Instruction storage exception */
56 POWERPC_EXCP_EXTERNAL
= 4, /* External input */
57 POWERPC_EXCP_ALIGN
= 5, /* Alignment exception */
58 POWERPC_EXCP_PROGRAM
= 6, /* Program exception */
59 POWERPC_EXCP_FPU
= 7, /* Floating-point unavailable exception */
60 POWERPC_EXCP_SYSCALL
= 8, /* System call exception */
61 POWERPC_EXCP_APU
= 9, /* Auxiliary processor unavailable */
62 POWERPC_EXCP_DECR
= 10, /* Decrementer exception */
63 POWERPC_EXCP_FIT
= 11, /* Fixed-interval timer interrupt */
64 POWERPC_EXCP_WDT
= 12, /* Watchdog timer interrupt */
65 POWERPC_EXCP_DTLB
= 13, /* Data TLB miss */
66 POWERPC_EXCP_ITLB
= 14, /* Instruction TLB miss */
67 POWERPC_EXCP_DEBUG
= 15, /* Debug interrupt */
68 /* Vectors 16 to 31 are reserved */
69 POWERPC_EXCP_SPEU
= 32, /* SPE/embedded floating-point unavailable */
70 POWERPC_EXCP_EFPDI
= 33, /* Embedded floating-point data interrupt */
71 POWERPC_EXCP_EFPRI
= 34, /* Embedded floating-point round interrupt */
72 POWERPC_EXCP_EPERFM
= 35, /* Embedded performance monitor interrupt */
73 POWERPC_EXCP_DOORI
= 36, /* Embedded doorbell interrupt */
74 POWERPC_EXCP_DOORCI
= 37, /* Embedded doorbell critical interrupt */
75 POWERPC_EXCP_GDOORI
= 38, /* Embedded guest doorbell interrupt */
76 POWERPC_EXCP_GDOORCI
= 39, /* Embedded guest doorbell critical interrupt*/
77 POWERPC_EXCP_HYPPRIV
= 41, /* Embedded hypervisor priv instruction */
78 /* Vectors 42 to 63 are reserved */
79 /* Exceptions defined in the PowerPC server specification */
80 POWERPC_EXCP_RESET
= 64, /* System reset exception */
81 POWERPC_EXCP_DSEG
= 65, /* Data segment exception */
82 POWERPC_EXCP_ISEG
= 66, /* Instruction segment exception */
83 POWERPC_EXCP_HDECR
= 67, /* Hypervisor decrementer exception */
84 POWERPC_EXCP_TRACE
= 68, /* Trace exception */
85 POWERPC_EXCP_HDSI
= 69, /* Hypervisor data storage exception */
86 POWERPC_EXCP_HISI
= 70, /* Hypervisor instruction storage exception */
87 POWERPC_EXCP_HDSEG
= 71, /* Hypervisor data segment exception */
88 POWERPC_EXCP_HISEG
= 72, /* Hypervisor instruction segment exception */
89 POWERPC_EXCP_VPU
= 73, /* Vector unavailable exception */
90 /* 40x specific exceptions */
91 POWERPC_EXCP_PIT
= 74, /* Programmable interval timer interrupt */
92 /* 601 specific exceptions */
93 POWERPC_EXCP_IO
= 75, /* IO error exception */
94 POWERPC_EXCP_RUNM
= 76, /* Run mode exception */
95 /* 602 specific exceptions */
96 POWERPC_EXCP_EMUL
= 77, /* Emulation trap exception */
97 /* 602/603 specific exceptions */
98 POWERPC_EXCP_IFTLB
= 78, /* Instruction fetch TLB miss */
99 POWERPC_EXCP_DLTLB
= 79, /* Data load TLB miss */
100 POWERPC_EXCP_DSTLB
= 80, /* Data store TLB miss */
101 /* Exceptions available on most PowerPC */
102 POWERPC_EXCP_FPA
= 81, /* Floating-point assist exception */
103 POWERPC_EXCP_DABR
= 82, /* Data address breakpoint */
104 POWERPC_EXCP_IABR
= 83, /* Instruction address breakpoint */
105 POWERPC_EXCP_SMI
= 84, /* System management interrupt */
106 POWERPC_EXCP_PERFM
= 85, /* Embedded performance monitor interrupt */
107 /* 7xx/74xx specific exceptions */
108 POWERPC_EXCP_THERM
= 86, /* Thermal interrupt */
109 /* 74xx specific exceptions */
110 POWERPC_EXCP_VPUA
= 87, /* Vector assist exception */
111 /* 970FX specific exceptions */
112 POWERPC_EXCP_SOFTP
= 88, /* Soft patch exception */
113 POWERPC_EXCP_MAINT
= 89, /* Maintenance exception */
114 /* Freescale embedded cores specific exceptions */
115 POWERPC_EXCP_MEXTBR
= 90, /* Maskable external breakpoint */
116 POWERPC_EXCP_NMEXTBR
= 91, /* Non maskable external breakpoint */
117 POWERPC_EXCP_ITLBE
= 92, /* Instruction TLB error */
118 POWERPC_EXCP_DTLBE
= 93, /* Data TLB error */
119 /* VSX Unavailable (Power ISA 2.06 and later) */
120 POWERPC_EXCP_VSXU
= 94, /* VSX Unavailable */
121 POWERPC_EXCP_FU
= 95, /* Facility Unavailable */
122 /* Additional ISA 2.06 and later server exceptions */
123 POWERPC_EXCP_HV_EMU
= 96, /* HV emulation assistance */
124 POWERPC_EXCP_HV_MAINT
= 97, /* HMI */
125 POWERPC_EXCP_HV_FU
= 98, /* Hypervisor Facility unavailable */
126 /* Server doorbell variants */
127 POWERPC_EXCP_SDOOR
= 99,
128 POWERPC_EXCP_SDOOR_HV
= 100,
129 /* ISA 3.00 additions */
130 POWERPC_EXCP_HVIRT
= 101,
131 POWERPC_EXCP_SYSCALL_VECTORED
= 102, /* scv exception */
133 POWERPC_EXCP_NB
= 103,
134 /* QEMU exceptions: special cases we want to stop translation */
135 POWERPC_EXCP_SYSCALL_USER
= 0x203, /* System call in user mode only */
138 /* Exceptions error codes */
140 /* Exception subtypes for POWERPC_EXCP_ALIGN */
141 POWERPC_EXCP_ALIGN_FP
= 0x01, /* FP alignment exception */
142 POWERPC_EXCP_ALIGN_LST
= 0x02, /* Unaligned mult/extern load/store */
143 POWERPC_EXCP_ALIGN_LE
= 0x03, /* Multiple little-endian access */
144 POWERPC_EXCP_ALIGN_PROT
= 0x04, /* Access cross protection boundary */
145 POWERPC_EXCP_ALIGN_BAT
= 0x05, /* Access cross a BAT/seg boundary */
146 POWERPC_EXCP_ALIGN_CACHE
= 0x06, /* Impossible dcbz access */
147 POWERPC_EXCP_ALIGN_INSN
= 0x07, /* Pref. insn x-ing 64-byte boundary */
148 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
150 POWERPC_EXCP_FP
= 0x10,
151 POWERPC_EXCP_FP_OX
= 0x01, /* FP overflow */
152 POWERPC_EXCP_FP_UX
= 0x02, /* FP underflow */
153 POWERPC_EXCP_FP_ZX
= 0x03, /* FP divide by zero */
154 POWERPC_EXCP_FP_XX
= 0x04, /* FP inexact */
155 POWERPC_EXCP_FP_VXSNAN
= 0x05, /* FP invalid SNaN op */
156 POWERPC_EXCP_FP_VXISI
= 0x06, /* FP invalid infinite subtraction */
157 POWERPC_EXCP_FP_VXIDI
= 0x07, /* FP invalid infinite divide */
158 POWERPC_EXCP_FP_VXZDZ
= 0x08, /* FP invalid zero divide */
159 POWERPC_EXCP_FP_VXIMZ
= 0x09, /* FP invalid infinite * zero */
160 POWERPC_EXCP_FP_VXVC
= 0x0A, /* FP invalid compare */
161 POWERPC_EXCP_FP_VXSOFT
= 0x0B, /* FP invalid operation */
162 POWERPC_EXCP_FP_VXSQRT
= 0x0C, /* FP invalid square root */
163 POWERPC_EXCP_FP_VXCVI
= 0x0D, /* FP invalid integer conversion */
164 /* Invalid instruction */
165 POWERPC_EXCP_INVAL
= 0x20,
166 POWERPC_EXCP_INVAL_INVAL
= 0x01, /* Invalid instruction */
167 POWERPC_EXCP_INVAL_LSWX
= 0x02, /* Invalid lswx instruction */
168 POWERPC_EXCP_INVAL_SPR
= 0x03, /* Invalid SPR access */
169 POWERPC_EXCP_INVAL_FP
= 0x04, /* Unimplemented mandatory fp instr */
170 /* Privileged instruction */
171 POWERPC_EXCP_PRIV
= 0x30,
172 POWERPC_EXCP_PRIV_OPC
= 0x01, /* Privileged operation exception */
173 POWERPC_EXCP_PRIV_REG
= 0x02, /* Privileged register exception */
175 POWERPC_EXCP_TRAP
= 0x40,
178 #define PPC_INPUT(env) ((env)->bus_model)
180 /*****************************************************************************/
181 typedef struct opc_handler_t opc_handler_t
;
183 /*****************************************************************************/
184 /* Types used to describe some PowerPC registers etc. */
185 typedef struct DisasContext DisasContext
;
186 typedef struct ppc_spr_t ppc_spr_t
;
187 typedef union ppc_tlb_t ppc_tlb_t
;
188 typedef struct ppc_hash_pte64 ppc_hash_pte64_t
;
190 /* SPR access micro-ops generations callbacks */
193 target_ulong default_value
;
194 #ifndef CONFIG_USER_ONLY
198 void (*uea_read
)(DisasContext
*ctx
, int gpr_num
, int spr_num
);
199 void (*uea_write
)(DisasContext
*ctx
, int spr_num
, int gpr_num
);
200 # ifndef CONFIG_USER_ONLY
201 void (*oea_read
)(DisasContext
*ctx
, int gpr_num
, int spr_num
);
202 void (*oea_write
)(DisasContext
*ctx
, int spr_num
, int gpr_num
);
203 void (*hea_read
)(DisasContext
*ctx
, int gpr_num
, int spr_num
);
204 void (*hea_write
)(DisasContext
*ctx
, int spr_num
, int gpr_num
);
209 * We (ab)use the fact that all the SPRs will have ids for the
210 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
217 /* VSX/Altivec registers (128 bits) */
218 typedef union _ppc_vsr_t
{
236 typedef ppc_vsr_t ppc_avr_t
;
237 typedef ppc_vsr_t ppc_fprp_t
;
239 #if !defined(CONFIG_USER_ONLY)
240 /* Software TLB cache */
241 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t
;
242 struct ppc6xx_tlb_t
{
248 typedef struct ppcemb_tlb_t ppcemb_tlb_t
;
249 struct ppcemb_tlb_t
{
255 uint32_t attr
; /* Storage attributes */
258 typedef struct ppcmas_tlb_t
{
271 /* possible TLB variants */
278 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes
;
280 typedef struct ppc_slb_t ppc_slb_t
;
284 const PPCHash64SegmentPageSizes
*sps
;
287 #define MAX_SLB_ENTRIES 64
288 #define SEGMENT_SHIFT_256M 28
289 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
291 #define SEGMENT_SHIFT_1T 40
292 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
294 typedef struct ppc_v3_pate_t
{
299 /*****************************************************************************/
300 /* Machine state register bits definition */
301 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
302 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
303 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
304 #define MSR_HV 60 /* hypervisor state hflags */
305 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
307 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
308 #define MSR_CM 31 /* Computation mode for BookE hflags */
309 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
310 #define MSR_GS 28 /* guest state for BookE */
311 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
312 #define MSR_VR 25 /* altivec available x hflags */
313 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
314 #define MSR_AP 23 /* Access privilege state on 602 hflags */
315 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
316 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
317 #define MSR_S 22 /* Secure state */
318 #define MSR_KEY 19 /* key bit on 603e */
319 #define MSR_POW 18 /* Power management */
320 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
321 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
322 #define MSR_ILE 16 /* Interrupt little-endian mode */
323 #define MSR_EE 15 /* External interrupt enable */
324 #define MSR_PR 14 /* Problem state hflags */
325 #define MSR_FP 13 /* Floating point available hflags */
326 #define MSR_ME 12 /* Machine check interrupt enable */
327 #define MSR_FE0 11 /* Floating point exception mode 0 */
328 #define MSR_SE 10 /* Single-step trace enable x hflags */
329 #define MSR_DWE 10 /* Debug wait enable on 405 x */
330 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
331 #define MSR_BE 9 /* Branch trace enable x hflags */
332 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
333 #define MSR_FE1 8 /* Floating point exception mode 1 */
334 #define MSR_AL 7 /* AL bit on POWER */
335 #define MSR_EP 6 /* Exception prefix on 601 */
336 #define MSR_IR 5 /* Instruction relocate */
337 #define MSR_DR 4 /* Data relocate */
338 #define MSR_IS 5 /* Instruction address space (BookE) */
339 #define MSR_DS 4 /* Data address space (BookE) */
340 #define MSR_PE 3 /* Protection enable on 403 */
341 #define MSR_PX 2 /* Protection exclusive on 403 x */
342 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
343 #define MSR_RI 1 /* Recoverable interrupt 1 */
344 #define MSR_LE 0 /* Little-endian mode 1 hflags */
347 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
348 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */
349 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
350 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
351 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
352 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
353 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
354 /* MMCR0 userspace r/w mask */
355 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
356 /* MMCR2 userspace r/w mask */
357 #define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
358 #define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
359 #define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
360 #define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
361 #define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
362 #define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
363 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
364 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
367 #define LPCR_VPM0 PPC_BIT(0)
368 #define LPCR_VPM1 PPC_BIT(1)
369 #define LPCR_ISL PPC_BIT(2)
370 #define LPCR_KBV PPC_BIT(3)
371 #define LPCR_DPFD_SHIFT (63 - 11)
372 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
373 #define LPCR_VRMASD_SHIFT (63 - 16)
374 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
375 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
376 #define LPCR_PECE_U_SHIFT (63 - 19)
377 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
378 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
379 #define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
380 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
381 #define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
382 #define LPCR_ILE PPC_BIT(38)
383 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
384 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
385 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
386 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
387 #define LPCR_HR PPC_BIT(43) /* Host Radix */
388 #define LPCR_ONL PPC_BIT(45)
389 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
390 #define LPCR_P7_PECE0 PPC_BIT(49)
391 #define LPCR_P7_PECE1 PPC_BIT(50)
392 #define LPCR_P7_PECE2 PPC_BIT(51)
393 #define LPCR_P8_PECE0 PPC_BIT(47)
394 #define LPCR_P8_PECE1 PPC_BIT(48)
395 #define LPCR_P8_PECE2 PPC_BIT(49)
396 #define LPCR_P8_PECE3 PPC_BIT(50)
397 #define LPCR_P8_PECE4 PPC_BIT(51)
398 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
399 #define LPCR_PECE_L_SHIFT (63 - 51)
400 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
401 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
402 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
403 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
404 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
405 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
406 #define LPCR_MER PPC_BIT(52)
407 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
408 #define LPCR_TC PPC_BIT(54)
409 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
410 #define LPCR_LPES0 PPC_BIT(60)
411 #define LPCR_LPES1 PPC_BIT(61)
412 #define LPCR_RMI PPC_BIT(62)
413 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
414 #define LPCR_HDICE PPC_BIT(63)
417 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
418 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
421 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
422 #define HFSCR_IC_MSGP 0xA
424 #define msr_sf ((env->msr >> MSR_SF) & 1)
425 #define msr_isf ((env->msr >> MSR_ISF) & 1)
426 #if defined(TARGET_PPC64)
427 #define msr_hv ((env->msr >> MSR_HV) & 1)
431 #define msr_cm ((env->msr >> MSR_CM) & 1)
432 #define msr_icm ((env->msr >> MSR_ICM) & 1)
433 #define msr_gs ((env->msr >> MSR_GS) & 1)
434 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
435 #define msr_vr ((env->msr >> MSR_VR) & 1)
436 #define msr_spe ((env->msr >> MSR_SPE) & 1)
437 #define msr_ap ((env->msr >> MSR_AP) & 1)
438 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
439 #define msr_sa ((env->msr >> MSR_SA) & 1)
440 #define msr_key ((env->msr >> MSR_KEY) & 1)
441 #define msr_pow ((env->msr >> MSR_POW) & 1)
442 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
443 #define msr_ce ((env->msr >> MSR_CE) & 1)
444 #define msr_ile ((env->msr >> MSR_ILE) & 1)
445 #define msr_ee ((env->msr >> MSR_EE) & 1)
446 #define msr_pr ((env->msr >> MSR_PR) & 1)
447 #define msr_fp ((env->msr >> MSR_FP) & 1)
448 #define msr_me ((env->msr >> MSR_ME) & 1)
449 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
450 #define msr_se ((env->msr >> MSR_SE) & 1)
451 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
452 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
453 #define msr_be ((env->msr >> MSR_BE) & 1)
454 #define msr_de ((env->msr >> MSR_DE) & 1)
455 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
456 #define msr_al ((env->msr >> MSR_AL) & 1)
457 #define msr_ep ((env->msr >> MSR_EP) & 1)
458 #define msr_ir ((env->msr >> MSR_IR) & 1)
459 #define msr_dr ((env->msr >> MSR_DR) & 1)
460 #define msr_is ((env->msr >> MSR_IS) & 1)
461 #define msr_ds ((env->msr >> MSR_DS) & 1)
462 #define msr_pe ((env->msr >> MSR_PE) & 1)
463 #define msr_px ((env->msr >> MSR_PX) & 1)
464 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
465 #define msr_ri ((env->msr >> MSR_RI) & 1)
466 #define msr_le ((env->msr >> MSR_LE) & 1)
467 #define msr_ts ((env->msr >> MSR_TS1) & 3)
468 #define msr_tm ((env->msr >> MSR_TM) & 1)
470 #define DBCR0_ICMP (1 << 27)
471 #define DBCR0_BRT (1 << 26)
472 #define DBSR_ICMP (1 << 27)
473 #define DBSR_BRT (1 << 26)
475 /* Hypervisor bit is more specific */
476 #if defined(TARGET_PPC64)
477 #define MSR_HVB (1ULL << MSR_HV)
479 #define MSR_HVB (0ULL)
483 #define DSISR_NOPTE 0x40000000
484 /* Not permitted by access authority of encoded access authority */
485 #define DSISR_PROTFAULT 0x08000000
486 #define DSISR_ISSTORE 0x02000000
487 /* Not permitted by virtual page class key protection */
488 #define DSISR_AMR 0x00200000
489 /* Unsupported Radix Tree Configuration */
490 #define DSISR_R_BADCONFIG 0x00080000
491 #define DSISR_ATOMIC_RC 0x00040000
492 /* Unable to translate address of (guest) pde or process/page table entry */
493 #define DSISR_PRTABLE_FAULT 0x00020000
495 /* SRR1 error code fields */
497 #define SRR1_NOPTE DSISR_NOPTE
498 /* Not permitted due to no-execute or guard bit set */
499 #define SRR1_NOEXEC_GUARD 0x10000000
500 #define SRR1_PROTFAULT DSISR_PROTFAULT
501 #define SRR1_IAMR DSISR_AMR
503 /* SRR1[42:45] wakeup fields for System Reset Interrupt */
505 #define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
507 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
508 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
509 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
510 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
511 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
512 #define SRR1_WAKERESET 0x00100000 /* System reset */
513 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
514 #define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
516 /* SRR1[46:47] power-saving exit mode */
518 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
520 #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
521 #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
522 #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
524 /* Facility Status and Control (FSCR) bits */
525 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
526 #define FSCR_TAR (63 - 55) /* Target Address Register */
527 #define FSCR_SCV (63 - 51) /* System call vectored */
528 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
529 #define FSCR_IC_MASK (0xFFULL)
530 #define FSCR_IC_POS (63 - 7)
531 #define FSCR_IC_DSCR_SPR3 2
532 #define FSCR_IC_PMU 3
533 #define FSCR_IC_BHRB 4
535 #define FSCR_IC_EBB 7
536 #define FSCR_IC_TAR 8
537 #define FSCR_IC_SCV 12
539 /* Exception state register bits definition */
540 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
541 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
542 #define ESR_PTR PPC_BIT(38) /* Trap */
543 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
544 #define ESR_ST PPC_BIT(40) /* Store Operation */
545 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
546 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
547 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
548 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
549 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
550 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
551 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
552 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
553 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
554 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
555 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
557 /* Transaction EXception And Summary Register bits */
558 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
559 #define TEXASR_DISALLOWED (63 - 8)
560 #define TEXASR_NESTING_OVERFLOW (63 - 9)
561 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
562 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
563 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
564 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
565 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
566 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
567 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
568 #define TEXASR_ABORT (63 - 31)
569 #define TEXASR_SUSPENDED (63 - 32)
570 #define TEXASR_PRIVILEGE_HV (63 - 34)
571 #define TEXASR_PRIVILEGE_PR (63 - 35)
572 #define TEXASR_FAILURE_SUMMARY (63 - 36)
573 #define TEXASR_TFIAR_EXACT (63 - 37)
574 #define TEXASR_ROT (63 - 38)
575 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
578 POWERPC_FLAG_NONE
= 0x00000000,
579 /* Flag for MSR bit 25 signification (VRE/SPE) */
580 POWERPC_FLAG_SPE
= 0x00000001,
581 POWERPC_FLAG_VRE
= 0x00000002,
582 /* Flag for MSR bit 17 signification (TGPR/CE) */
583 POWERPC_FLAG_TGPR
= 0x00000004,
584 POWERPC_FLAG_CE
= 0x00000008,
585 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
586 POWERPC_FLAG_SE
= 0x00000010,
587 POWERPC_FLAG_DWE
= 0x00000020,
588 POWERPC_FLAG_UBLE
= 0x00000040,
589 /* Flag for MSR bit 9 signification (BE/DE) */
590 POWERPC_FLAG_BE
= 0x00000080,
591 POWERPC_FLAG_DE
= 0x00000100,
592 /* Flag for MSR bit 2 signification (PX/PMM) */
593 POWERPC_FLAG_PX
= 0x00000200,
594 POWERPC_FLAG_PMM
= 0x00000400,
595 /* Flag for special features */
596 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
597 POWERPC_FLAG_RTC_CLK
= 0x00010000,
598 POWERPC_FLAG_BUS_CLK
= 0x00020000,
600 POWERPC_FLAG_CFAR
= 0x00040000,
602 POWERPC_FLAG_VSX
= 0x00080000,
603 /* Has Transaction Memory (ISA 2.07) */
604 POWERPC_FLAG_TM
= 0x00100000,
605 /* Has SCV (ISA 3.00) */
606 POWERPC_FLAG_SCV
= 0x00200000,
607 /* Has HID0 for LE bit (601) */
608 POWERPC_FLAG_HID0_LE
= 0x00400000,
612 * Bits for env->hflags.
614 * Most of these bits overlap with corresponding bits in MSR,
615 * but some come from other sources. Those that do come from
616 * the MSR are validated in hreg_compute_hflags.
619 HFLAGS_LE
= 0, /* MSR_LE -- comes from elsewhere on 601 */
620 HFLAGS_HV
= 1, /* computed from MSR_HV and other state */
621 HFLAGS_64
= 2, /* computed from MSR_CE and MSR_SF */
622 HFLAGS_GTSE
= 3, /* computed from SPR_LPCR[GTSE] */
623 HFLAGS_DR
= 4, /* MSR_DR */
624 HFLAGS_HR
= 5, /* computed from SPR_LPCR[HR] */
625 HFLAGS_SPE
= 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
626 HFLAGS_TM
= 8, /* computed from MSR_TM */
627 HFLAGS_BE
= 9, /* MSR_BE -- from elsewhere on embedded ppc */
628 HFLAGS_SE
= 10, /* MSR_SE -- from elsewhere on embedded ppc */
629 HFLAGS_FP
= 13, /* MSR_FP */
630 HFLAGS_PR
= 14, /* MSR_PR */
631 HFLAGS_PMCC0
= 15, /* MMCR0 PMCC bit 0 */
632 HFLAGS_PMCC1
= 16, /* MMCR0 PMCC bit 1 */
633 HFLAGS_VSX
= 23, /* MSR_VSX if cpu has VSX */
634 HFLAGS_VR
= 25, /* MSR_VR if cpu has VRE */
636 HFLAGS_IMMU_IDX
= 26, /* 26..28 -- the composite immu_idx */
637 HFLAGS_DMMU_IDX
= 29, /* 29..31 -- the composite dmmu_idx */
640 /*****************************************************************************/
641 /* Floating point status and control register */
642 #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
643 #define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
644 #define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
645 #define FPSCR_FX 31 /* Floating-point exception summary */
646 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
647 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
648 #define FPSCR_OX 28 /* Floating-point overflow exception */
649 #define FPSCR_UX 27 /* Floating-point underflow exception */
650 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
651 #define FPSCR_XX 25 /* Floating-point inexact exception */
652 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
653 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
654 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
655 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
656 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
657 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
658 #define FPSCR_FR 18 /* Floating-point fraction rounded */
659 #define FPSCR_FI 17 /* Floating-point fraction inexact */
660 #define FPSCR_C 16 /* Floating-point result class descriptor */
661 #define FPSCR_FL 15 /* Floating-point less than or negative */
662 #define FPSCR_FG 14 /* Floating-point greater than or negative */
663 #define FPSCR_FE 13 /* Floating-point equal or zero */
664 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
665 #define FPSCR_FPCC 12 /* Floating-point condition code */
666 #define FPSCR_FPRF 12 /* Floating-point result flags */
667 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
668 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
669 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
670 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
671 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
672 #define FPSCR_UE 5 /* Floating-point underflow exception enable */
673 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
674 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
675 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
677 #define FPSCR_RN0 0 /* Floating-point rounding control */
678 #define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
679 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
680 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
681 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
682 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
683 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
684 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
685 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
686 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
687 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
688 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
689 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
690 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
691 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
692 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
693 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
694 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
695 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
696 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
697 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
698 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
699 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
700 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
701 #define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)
702 /* Invalid operation exception summary */
703 #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
704 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
705 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
706 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
708 /* exception summary */
709 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
710 /* enabled exception summary */
711 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
714 #define FP_DRN2 (1ull << FPSCR_DRN2)
715 #define FP_DRN1 (1ull << FPSCR_DRN1)
716 #define FP_DRN0 (1ull << FPSCR_DRN0)
717 #define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
718 #define FP_FX (1ull << FPSCR_FX)
719 #define FP_FEX (1ull << FPSCR_FEX)
720 #define FP_VX (1ull << FPSCR_VX)
721 #define FP_OX (1ull << FPSCR_OX)
722 #define FP_UX (1ull << FPSCR_UX)
723 #define FP_ZX (1ull << FPSCR_ZX)
724 #define FP_XX (1ull << FPSCR_XX)
725 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
726 #define FP_VXISI (1ull << FPSCR_VXISI)
727 #define FP_VXIDI (1ull << FPSCR_VXIDI)
728 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
729 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
730 #define FP_VXVC (1ull << FPSCR_VXVC)
731 #define FP_FR (1ull << FPSCR_FR)
732 #define FP_FI (1ull << FPSCR_FI)
733 #define FP_C (1ull << FPSCR_C)
734 #define FP_FL (1ull << FPSCR_FL)
735 #define FP_FG (1ull << FPSCR_FG)
736 #define FP_FE (1ull << FPSCR_FE)
737 #define FP_FU (1ull << FPSCR_FU)
738 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
739 #define FP_FPRF (FP_C | FP_FPCC)
740 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
741 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
742 #define FP_VXCVI (1ull << FPSCR_VXCVI)
743 #define FP_VE (1ull << FPSCR_VE)
744 #define FP_OE (1ull << FPSCR_OE)
745 #define FP_UE (1ull << FPSCR_UE)
746 #define FP_ZE (1ull << FPSCR_ZE)
747 #define FP_XE (1ull << FPSCR_XE)
748 #define FP_NI (1ull << FPSCR_NI)
749 #define FP_RN1 (1ull << FPSCR_RN1)
750 #define FP_RN0 (1ull << FPSCR_RN0)
751 #define FP_RN (FP_RN1 | FP_RN0)
753 #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
754 #define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
756 /* the exception bits which can be cleared by mcrfs - includes FX */
757 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
758 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
759 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
760 FP_VXSQRT | FP_VXCVI)
762 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
763 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
764 FP_FEX | FP_VX | PPC_BIT(52)))
766 /*****************************************************************************/
767 /* Vector status and control register */
768 #define VSCR_NJ 16 /* Vector non-java */
769 #define VSCR_SAT 0 /* Vector saturation */
771 /*****************************************************************************/
772 /* BookE e500 MMU registers */
774 #define MAS0_NV_SHIFT 0
775 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
777 #define MAS0_WQ_SHIFT 12
778 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
779 /* Write TLB entry regardless of reservation */
780 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
781 /* Write TLB entry only already in use */
782 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
783 /* Clear TLB entry */
784 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
786 #define MAS0_HES_SHIFT 14
787 #define MAS0_HES (1 << MAS0_HES_SHIFT)
789 #define MAS0_ESEL_SHIFT 16
790 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
792 #define MAS0_TLBSEL_SHIFT 28
793 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
794 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
795 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
796 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
797 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
799 #define MAS0_ATSEL_SHIFT 31
800 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
801 #define MAS0_ATSEL_TLB 0
802 #define MAS0_ATSEL_LRAT MAS0_ATSEL
804 #define MAS1_TSIZE_SHIFT 7
805 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
807 #define MAS1_TS_SHIFT 12
808 #define MAS1_TS (1 << MAS1_TS_SHIFT)
810 #define MAS1_IND_SHIFT 13
811 #define MAS1_IND (1 << MAS1_IND_SHIFT)
813 #define MAS1_TID_SHIFT 16
814 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
816 #define MAS1_IPROT_SHIFT 30
817 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
819 #define MAS1_VALID_SHIFT 31
820 #define MAS1_VALID 0x80000000
822 #define MAS2_EPN_SHIFT 12
823 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
825 #define MAS2_ACM_SHIFT 6
826 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
828 #define MAS2_VLE_SHIFT 5
829 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
831 #define MAS2_W_SHIFT 4
832 #define MAS2_W (1 << MAS2_W_SHIFT)
834 #define MAS2_I_SHIFT 3
835 #define MAS2_I (1 << MAS2_I_SHIFT)
837 #define MAS2_M_SHIFT 2
838 #define MAS2_M (1 << MAS2_M_SHIFT)
840 #define MAS2_G_SHIFT 1
841 #define MAS2_G (1 << MAS2_G_SHIFT)
843 #define MAS2_E_SHIFT 0
844 #define MAS2_E (1 << MAS2_E_SHIFT)
846 #define MAS3_RPN_SHIFT 12
847 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
849 #define MAS3_U0 0x00000200
850 #define MAS3_U1 0x00000100
851 #define MAS3_U2 0x00000080
852 #define MAS3_U3 0x00000040
853 #define MAS3_UX 0x00000020
854 #define MAS3_SX 0x00000010
855 #define MAS3_UW 0x00000008
856 #define MAS3_SW 0x00000004
857 #define MAS3_UR 0x00000002
858 #define MAS3_SR 0x00000001
859 #define MAS3_SPSIZE_SHIFT 1
860 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
862 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
863 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
864 #define MAS4_TIDSELD_MASK 0x00030000
865 #define MAS4_TIDSELD_PID0 0x00000000
866 #define MAS4_TIDSELD_PID1 0x00010000
867 #define MAS4_TIDSELD_PID2 0x00020000
868 #define MAS4_TIDSELD_PIDZ 0x00030000
869 #define MAS4_INDD 0x00008000 /* Default IND */
870 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
871 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
872 #define MAS4_ACMD 0x00000040
873 #define MAS4_VLED 0x00000020
874 #define MAS4_WD 0x00000010
875 #define MAS4_ID 0x00000008
876 #define MAS4_MD 0x00000004
877 #define MAS4_GD 0x00000002
878 #define MAS4_ED 0x00000001
879 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
880 #define MAS4_WIMGED_SHIFT 0
882 #define MAS5_SGS 0x80000000
883 #define MAS5_SLPID_MASK 0x00000fff
885 #define MAS6_SPID0 0x3fff0000
886 #define MAS6_SPID1 0x00007ffe
887 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
888 #define MAS6_SAS 0x00000001
889 #define MAS6_SPID MAS6_SPID0
890 #define MAS6_SIND 0x00000002 /* Indirect page */
891 #define MAS6_SIND_SHIFT 1
892 #define MAS6_SPID_MASK 0x3fff0000
893 #define MAS6_SPID_SHIFT 16
894 #define MAS6_ISIZE_MASK 0x00000f80
895 #define MAS6_ISIZE_SHIFT 7
897 #define MAS7_RPN 0xffffffff
899 #define MAS8_TGS 0x80000000
900 #define MAS8_VF 0x40000000
901 #define MAS8_TLBPID 0x00000fff
903 /* Bit definitions for MMUCFG */
904 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
905 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
906 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
907 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
908 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
909 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
910 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
911 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
912 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
914 /* Bit definitions for MMUCSR0 */
915 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
916 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
917 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
918 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
919 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
920 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
921 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
922 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
923 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
924 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
926 /* TLBnCFG encoding */
927 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
928 #define TLBnCFG_HES 0x00002000 /* HW select supported */
929 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
930 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
931 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
932 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
933 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
934 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
935 #define TLBnCFG_MINSIZE_SHIFT 20
936 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
937 #define TLBnCFG_MAXSIZE_SHIFT 16
938 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
939 #define TLBnCFG_ASSOC_SHIFT 24
941 /* TLBnPS encoding */
942 #define TLBnPS_4K 0x00000004
943 #define TLBnPS_8K 0x00000008
944 #define TLBnPS_16K 0x00000010
945 #define TLBnPS_32K 0x00000020
946 #define TLBnPS_64K 0x00000040
947 #define TLBnPS_128K 0x00000080
948 #define TLBnPS_256K 0x00000100
949 #define TLBnPS_512K 0x00000200
950 #define TLBnPS_1M 0x00000400
951 #define TLBnPS_2M 0x00000800
952 #define TLBnPS_4M 0x00001000
953 #define TLBnPS_8M 0x00002000
954 #define TLBnPS_16M 0x00004000
955 #define TLBnPS_32M 0x00008000
956 #define TLBnPS_64M 0x00010000
957 #define TLBnPS_128M 0x00020000
958 #define TLBnPS_256M 0x00040000
959 #define TLBnPS_512M 0x00080000
960 #define TLBnPS_1G 0x00100000
961 #define TLBnPS_2G 0x00200000
962 #define TLBnPS_4G 0x00400000
963 #define TLBnPS_8G 0x00800000
964 #define TLBnPS_16G 0x01000000
965 #define TLBnPS_32G 0x02000000
966 #define TLBnPS_64G 0x04000000
967 #define TLBnPS_128G 0x08000000
968 #define TLBnPS_256G 0x10000000
970 /* tlbilx action encoding */
971 #define TLBILX_T_ALL 0
972 #define TLBILX_T_TID 1
973 #define TLBILX_T_FULLMATCH 3
974 #define TLBILX_T_CLASS0 4
975 #define TLBILX_T_CLASS1 5
976 #define TLBILX_T_CLASS2 6
977 #define TLBILX_T_CLASS3 7
979 /* BookE 2.06 helper defines */
981 #define BOOKE206_FLUSH_TLB0 (1 << 0)
982 #define BOOKE206_FLUSH_TLB1 (1 << 1)
983 #define BOOKE206_FLUSH_TLB2 (1 << 2)
984 #define BOOKE206_FLUSH_TLB3 (1 << 3)
986 /* number of possible TLBs */
987 #define BOOKE206_MAX_TLBN 4
989 #define EPID_EPID_SHIFT 0x0
990 #define EPID_EPID 0xFF
991 #define EPID_ELPID_SHIFT 0x10
992 #define EPID_ELPID 0x3F0000
993 #define EPID_EGS 0x20000000
994 #define EPID_EGS_SHIFT 29
995 #define EPID_EAS 0x40000000
996 #define EPID_EAS_SHIFT 30
997 #define EPID_EPR 0x80000000
998 #define EPID_EPR_SHIFT 31
999 /* We don't support EGS and ELPID */
1000 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1002 /*****************************************************************************/
1003 /* Server and Embedded Processor Control */
1005 #define DBELL_TYPE_SHIFT 27
1006 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
1007 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
1008 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1009 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1010 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1011 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1013 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1015 #define DBELL_BRDCAST PPC_BIT(37)
1016 #define DBELL_LPIDTAG_SHIFT 14
1017 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1018 #define DBELL_PIRTAG_MASK 0x3fff
1020 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1022 #define PPC_PAGE_SIZES_MAX_SZ 8
1024 struct ppc_radix_page_info
{
1026 uint32_t entries
[PPC_PAGE_SIZES_MAX_SZ
];
1029 /*****************************************************************************/
1030 /* The whole PowerPC CPU context */
1033 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1034 * + real/paged mode combinations. The other two modes are for
1035 * external PID load/store.
1037 #define PPC_TLB_EPID_LOAD 8
1038 #define PPC_TLB_EPID_STORE 9
1040 #define PPC_CPU_OPCODES_LEN 0x40
1041 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1043 struct CPUPPCState
{
1044 /* Most commonly used resources during translated code execution first */
1045 target_ulong gpr
[32]; /* general purpose registers */
1046 target_ulong gprh
[32]; /* storage for GPR MSB, used by the SPE extension */
1049 uint32_t crf
[8]; /* condition register */
1050 #if defined(TARGET_PPC64)
1053 target_ulong xer
; /* XER (with SO, OV, CA split out) */
1060 target_ulong reserve_addr
; /* Reservation address */
1061 target_ulong reserve_val
; /* Reservation value */
1062 target_ulong reserve_val2
;
1064 /* These are used in supervisor mode only */
1065 target_ulong msr
; /* machine state register */
1066 target_ulong tgpr
[4]; /* temporary general purpose registers, */
1067 /* used to speed-up TLB assist handlers */
1069 target_ulong nip
; /* next instruction pointer */
1070 uint64_t retxh
; /* high part of 128-bit helper return */
1072 /* when a memory exception occurs, the access type is stored here */
1075 #if !defined(CONFIG_USER_ONLY)
1076 /* MMU context, only relevant for full system emulation */
1077 #if defined(TARGET_PPC64)
1078 ppc_slb_t slb
[MAX_SLB_ENTRIES
]; /* PowerPC 64 SLB area */
1080 target_ulong sr
[32]; /* segment registers */
1081 uint32_t nb_BATs
; /* number of BATs */
1082 target_ulong DBAT
[2][8];
1083 target_ulong IBAT
[2][8];
1084 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1085 int32_t nb_tlb
; /* Total number of TLB */
1086 int tlb_per_way
; /* Speed-up helper: used to avoid divisions at run time */
1087 int nb_ways
; /* Number of ways in the TLB set */
1088 int last_way
; /* Last used way used to allocate TLB in a LRU way */
1089 int id_tlbs
; /* If 1, MMU has separated TLBs for instructions & data */
1090 int nb_pids
; /* Number of available PID registers */
1091 int tlb_type
; /* Type of TLB we're dealing with */
1092 ppc_tlb_t tlb
; /* TLB is optional. Allocate them only if needed */
1093 target_ulong pb
[4]; /* 403 dedicated access protection registers */
1094 bool tlb_dirty
; /* Set to non-zero when modifying TLB */
1095 bool kvm_sw_tlb
; /* non-zero if KVM SW TLB API is active */
1096 uint32_t tlb_need_flush
; /* Delayed flush needed */
1097 #define TLB_NEED_LOCAL_FLUSH 0x1
1098 #define TLB_NEED_GLOBAL_FLUSH 0x2
1101 /* Other registers */
1102 target_ulong spr
[1024]; /* special purpose registers */
1103 ppc_spr_t spr_cb
[1024];
1104 /* Vector status and control register, minus VSCR_SAT */
1106 /* VSX registers (including FP and AVR) */
1107 ppc_vsr_t vsr
[64] QEMU_ALIGNED(16);
1108 /* Non-zero if and only if VSCR_SAT should be set */
1109 ppc_vsr_t vscr_sat
QEMU_ALIGNED(16);
1113 /* SPE and Altivec share status as they'll never be used simultaneously */
1114 float_status vec_status
;
1115 float_status fp_status
; /* Floating point execution context */
1116 target_ulong fpscr
; /* Floating point status and control register */
1118 /* Internal devices resources */
1119 ppc_tb_t
*tb_env
; /* Time base and decrementer */
1120 ppc_dcr_t
*dcr_env
; /* Device control registers */
1122 int dcache_line_size
;
1123 int icache_line_size
;
1125 /* These resources are used during exception processing */
1126 /* CPU model definition */
1127 target_ulong msr_mask
;
1128 powerpc_mmu_t mmu_model
;
1129 powerpc_excp_t excp_model
;
1130 powerpc_input_t bus_model
;
1133 uint64_t insns_flags
;
1134 uint64_t insns_flags2
;
1137 uint32_t pending_interrupts
;
1138 #if !defined(CONFIG_USER_ONLY)
1140 * This is the IRQ controller, which is implementation dependent and only
1141 * relevant when emulating a complete machine. Note that this isn't used
1142 * by recent Book3s compatible CPUs (POWER7 and newer).
1144 uint32_t irq_input_state
;
1147 target_ulong excp_vectors
[POWERPC_EXCP_NB
]; /* Exception vectors */
1148 target_ulong excp_prefix
;
1149 target_ulong ivor_mask
;
1150 target_ulong ivpr_mask
;
1151 target_ulong hreset_vector
;
1153 bool mpic_proxy
; /* true if the external proxy facility mode is enabled */
1154 bool has_hv_mode
; /* set when the processor has an HV mode, thus HV priv */
1155 /* instructions and SPRs are diallowed if MSR:HV is 0 */
1157 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1158 * special way (such as routing some resume causes to 0x100, i.e. sreset).
1160 bool resume_as_sreset
;
1163 /* These resources are used only in TCG */
1165 target_ulong hflags_compat_nmsr
; /* for migration compatibility */
1167 /* Power management */
1168 int (*check_pow
)(CPUPPCState
*env
);
1170 #if !defined(CONFIG_USER_ONLY)
1171 void *load_info
; /* holds boot loading state */
1177 * Specifies bit locations of the Time Base used to signal a fixed timer
1178 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1180 * 0 selects the least significant bit, 63 selects the most significant bit
1182 uint8_t fit_period
[4];
1183 uint8_t wdt_period
[4];
1185 /* Transactional memory state */
1186 target_ulong tm_gpr
[32];
1187 ppc_avr_t tm_vsr
[64];
1200 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1202 env->fit_period[0] = (a_); \
1203 env->fit_period[1] = (b_); \
1204 env->fit_period[2] = (c_); \
1205 env->fit_period[3] = (d_); \
1208 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1210 env->wdt_period[0] = (a_); \
1211 env->wdt_period[1] = (b_); \
1212 env->wdt_period[2] = (c_); \
1213 env->wdt_period[3] = (d_); \
1216 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor
;
1217 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass
;
1221 * @env: #CPUPPCState
1222 * @vcpu_id: vCPU identifier given to KVM
1223 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1229 CPUState parent_obj
;
1232 CPUNegativeOffsetState neg
;
1236 uint32_t compat_pvr
;
1237 PPCVirtualHypervisor
*vhyp
;
1239 int32_t node_id
; /* NUMA node this CPU belongs to */
1240 PPCHash64Options
*hash64_opts
;
1242 /* Those resources are used only during code translation */
1243 /* opcode handlers */
1244 opc_handler_t
*opcodes
[PPC_CPU_OPCODES_LEN
];
1246 /* Fields related to migration compatibility hacks */
1247 bool pre_2_8_migration
;
1248 target_ulong mig_msr_mask
;
1249 uint64_t mig_insns_flags
;
1250 uint64_t mig_insns_flags2
;
1251 uint32_t mig_nb_BATs
;
1252 bool pre_2_10_migration
;
1253 bool pre_3_0_migration
;
1258 PowerPCCPUClass
*ppc_cpu_class_by_pvr(uint32_t pvr
);
1259 PowerPCCPUClass
*ppc_cpu_class_by_pvr_mask(uint32_t pvr
);
1260 PowerPCCPUClass
*ppc_cpu_get_family_class(PowerPCCPUClass
*pcc
);
1262 #ifndef CONFIG_USER_ONLY
1263 struct PPCVirtualHypervisorClass
{
1264 InterfaceClass parent
;
1265 void (*hypercall
)(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
);
1266 hwaddr (*hpt_mask
)(PPCVirtualHypervisor
*vhyp
);
1267 const ppc_hash_pte64_t
*(*map_hptes
)(PPCVirtualHypervisor
*vhyp
,
1268 hwaddr ptex
, int n
);
1269 void (*unmap_hptes
)(PPCVirtualHypervisor
*vhyp
,
1270 const ppc_hash_pte64_t
*hptes
,
1271 hwaddr ptex
, int n
);
1272 void (*hpte_set_c
)(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
, uint64_t pte1
);
1273 void (*hpte_set_r
)(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
, uint64_t pte1
);
1274 void (*get_pate
)(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
);
1275 target_ulong (*encode_hpt_for_kvm_pr
)(PPCVirtualHypervisor
*vhyp
);
1276 void (*cpu_exec_enter
)(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
);
1277 void (*cpu_exec_exit
)(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
);
1280 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1281 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor
, PPCVirtualHypervisorClass
,
1282 PPC_VIRTUAL_HYPERVISOR
, TYPE_PPC_VIRTUAL_HYPERVISOR
)
1283 #endif /* CONFIG_USER_ONLY */
1285 void ppc_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
1286 hwaddr
ppc_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
1287 int ppc_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
1288 int ppc_cpu_gdb_read_register_apple(CPUState
*cpu
, GByteArray
*buf
, int reg
);
1289 int ppc_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
1290 int ppc_cpu_gdb_write_register_apple(CPUState
*cpu
, uint8_t *buf
, int reg
);
1291 #ifndef CONFIG_USER_ONLY
1292 void ppc_gdb_gen_spr_xml(PowerPCCPU
*cpu
);
1293 const char *ppc_gdb_get_dynamic_xml(CPUState
*cs
, const char *xml_name
);
1295 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cs
,
1296 int cpuid
, void *opaque
);
1297 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cs
,
1298 int cpuid
, void *opaque
);
1299 #ifndef CONFIG_USER_ONLY
1300 void ppc_cpu_do_interrupt(CPUState
*cpu
);
1301 bool ppc_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
1302 void ppc_cpu_do_system_reset(CPUState
*cs
);
1303 void ppc_cpu_do_fwnmi_machine_check(CPUState
*cs
, target_ulong vector
);
1304 extern const VMStateDescription vmstate_ppc_cpu
;
1307 /*****************************************************************************/
1308 void ppc_translate_init(void);
1310 #if !defined(CONFIG_USER_ONLY)
1311 void ppc_store_sdr1(CPUPPCState
*env
, target_ulong value
);
1312 #endif /* !defined(CONFIG_USER_ONLY) */
1313 void ppc_store_msr(CPUPPCState
*env
, target_ulong value
);
1314 void ppc_store_lpcr(PowerPCCPU
*cpu
, target_ulong val
);
1316 void ppc_cpu_list(void);
1318 /* Time-base and decrementer management */
1319 #ifndef NO_CPU_IO_DEFS
1320 uint64_t cpu_ppc_load_tbl(CPUPPCState
*env
);
1321 uint32_t cpu_ppc_load_tbu(CPUPPCState
*env
);
1322 void cpu_ppc_store_tbu(CPUPPCState
*env
, uint32_t value
);
1323 void cpu_ppc_store_tbl(CPUPPCState
*env
, uint32_t value
);
1324 uint64_t cpu_ppc_load_atbl(CPUPPCState
*env
);
1325 uint32_t cpu_ppc_load_atbu(CPUPPCState
*env
);
1326 void cpu_ppc_store_atbl(CPUPPCState
*env
, uint32_t value
);
1327 void cpu_ppc_store_atbu(CPUPPCState
*env
, uint32_t value
);
1328 uint64_t cpu_ppc_load_vtb(CPUPPCState
*env
);
1329 void cpu_ppc_store_vtb(CPUPPCState
*env
, uint64_t value
);
1330 bool ppc_decr_clear_on_delivery(CPUPPCState
*env
);
1331 target_ulong
cpu_ppc_load_decr(CPUPPCState
*env
);
1332 void cpu_ppc_store_decr(CPUPPCState
*env
, target_ulong value
);
1333 target_ulong
cpu_ppc_load_hdecr(CPUPPCState
*env
);
1334 void cpu_ppc_store_hdecr(CPUPPCState
*env
, target_ulong value
);
1335 void cpu_ppc_store_tbu40(CPUPPCState
*env
, uint64_t value
);
1336 uint64_t cpu_ppc_load_purr(CPUPPCState
*env
);
1337 void cpu_ppc_store_purr(CPUPPCState
*env
, uint64_t value
);
1338 uint32_t cpu_ppc601_load_rtcl(CPUPPCState
*env
);
1339 uint32_t cpu_ppc601_load_rtcu(CPUPPCState
*env
);
1340 #if !defined(CONFIG_USER_ONLY)
1341 void cpu_ppc601_store_rtcl(CPUPPCState
*env
, uint32_t value
);
1342 void cpu_ppc601_store_rtcu(CPUPPCState
*env
, uint32_t value
);
1343 target_ulong
load_40x_pit(CPUPPCState
*env
);
1344 void store_40x_pit(CPUPPCState
*env
, target_ulong val
);
1345 void store_40x_dbcr0(CPUPPCState
*env
, uint32_t val
);
1346 void store_40x_sler(CPUPPCState
*env
, uint32_t val
);
1347 void store_booke_tcr(CPUPPCState
*env
, target_ulong val
);
1348 void store_booke_tsr(CPUPPCState
*env
, target_ulong val
);
1349 void ppc_tlb_invalidate_all(CPUPPCState
*env
);
1350 void ppc_tlb_invalidate_one(CPUPPCState
*env
, target_ulong addr
);
1351 void cpu_ppc_set_vhyp(PowerPCCPU
*cpu
, PPCVirtualHypervisor
*vhyp
);
1352 int ppcmas_tlb_check(CPUPPCState
*env
, ppcmas_tlb_t
*tlb
,
1353 hwaddr
*raddrp
, target_ulong address
,
1355 int ppcemb_tlb_check(CPUPPCState
*env
, ppcemb_tlb_t
*tlb
,
1357 target_ulong address
, uint32_t pid
, int ext
,
1359 hwaddr
booke206_tlb_to_page_size(CPUPPCState
*env
,
1364 void ppc_store_fpscr(CPUPPCState
*env
, target_ulong val
);
1365 void helper_hfscr_facility_check(CPUPPCState
*env
, uint32_t bit
,
1366 const char *caller
, uint32_t cause
);
1368 static inline uint64_t ppc_dump_gpr(CPUPPCState
*env
, int gprn
)
1372 gprv
= env
->gpr
[gprn
];
1373 if (env
->flags
& POWERPC_FLAG_SPE
) {
1375 * If the CPU implements the SPE extension, we have to get the
1376 * high bits of the GPR from the gprh storage area
1378 gprv
&= 0xFFFFFFFFULL
;
1379 gprv
|= (uint64_t)env
->gprh
[gprn
] << 32;
1385 /* Device control registers */
1386 int ppc_dcr_read(ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
);
1387 int ppc_dcr_write(ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
);
1389 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1390 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1391 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1393 #define cpu_list ppc_cpu_list
1395 /* MMU modes definitions */
1396 #define MMU_USER_IDX 0
1397 static inline int cpu_mmu_index(CPUPPCState
*env
, bool ifetch
)
1399 #ifdef CONFIG_USER_ONLY
1400 return MMU_USER_IDX
;
1402 return (env
->hflags
>> (ifetch
? HFLAGS_IMMU_IDX
: HFLAGS_DMMU_IDX
)) & 7;
1406 /* Compatibility modes */
1407 #if defined(TARGET_PPC64)
1408 bool ppc_check_compat(PowerPCCPU
*cpu
, uint32_t compat_pvr
,
1409 uint32_t min_compat_pvr
, uint32_t max_compat_pvr
);
1410 bool ppc_type_check_compat(const char *cputype
, uint32_t compat_pvr
,
1411 uint32_t min_compat_pvr
, uint32_t max_compat_pvr
);
1413 int ppc_set_compat(PowerPCCPU
*cpu
, uint32_t compat_pvr
, Error
**errp
);
1415 #if !defined(CONFIG_USER_ONLY)
1416 int ppc_set_compat_all(uint32_t compat_pvr
, Error
**errp
);
1418 int ppc_compat_max_vthreads(PowerPCCPU
*cpu
);
1419 void ppc_compat_add_property(Object
*obj
, const char *name
,
1420 uint32_t *compat_pvr
, const char *basedesc
);
1421 #endif /* defined(TARGET_PPC64) */
1423 typedef CPUPPCState CPUArchState
;
1424 typedef PowerPCCPU ArchCPU
;
1426 #include "exec/cpu-all.h"
1428 /*****************************************************************************/
1429 /* CRF definitions */
1430 #define CRF_LT_BIT 3
1431 #define CRF_GT_BIT 2
1432 #define CRF_EQ_BIT 1
1433 #define CRF_SO_BIT 0
1434 #define CRF_LT (1 << CRF_LT_BIT)
1435 #define CRF_GT (1 << CRF_GT_BIT)
1436 #define CRF_EQ (1 << CRF_EQ_BIT)
1437 #define CRF_SO (1 << CRF_SO_BIT)
1438 /* For SPE extensions */
1439 #define CRF_CH (1 << CRF_LT_BIT)
1440 #define CRF_CL (1 << CRF_GT_BIT)
1441 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1442 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1444 /* XER definitions */
1452 #define xer_so (env->so)
1453 #define xer_ov (env->ov)
1454 #define xer_ca (env->ca)
1455 #define xer_ov32 (env->ov)
1456 #define xer_ca32 (env->ca)
1457 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1458 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1460 /* SPR definitions */
1461 #define SPR_MQ (0x000)
1462 #define SPR_XER (0x001)
1463 #define SPR_601_VRTCU (0x004)
1464 #define SPR_601_VRTCL (0x005)
1465 #define SPR_601_UDECR (0x006)
1466 #define SPR_LR (0x008)
1467 #define SPR_CTR (0x009)
1468 #define SPR_UAMR (0x00D)
1469 #define SPR_DSCR (0x011)
1470 #define SPR_DSISR (0x012)
1471 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1472 #define SPR_601_RTCU (0x014)
1473 #define SPR_601_RTCL (0x015)
1474 #define SPR_DECR (0x016)
1475 #define SPR_SDR1 (0x019)
1476 #define SPR_SRR0 (0x01A)
1477 #define SPR_SRR1 (0x01B)
1478 #define SPR_CFAR (0x01C)
1479 #define SPR_AMR (0x01D)
1480 #define SPR_ACOP (0x01F)
1481 #define SPR_BOOKE_PID (0x030)
1482 #define SPR_BOOKS_PID (0x030)
1483 #define SPR_BOOKE_DECAR (0x036)
1484 #define SPR_BOOKE_CSRR0 (0x03A)
1485 #define SPR_BOOKE_CSRR1 (0x03B)
1486 #define SPR_BOOKE_DEAR (0x03D)
1487 #define SPR_IAMR (0x03D)
1488 #define SPR_BOOKE_ESR (0x03E)
1489 #define SPR_BOOKE_IVPR (0x03F)
1490 #define SPR_MPC_EIE (0x050)
1491 #define SPR_MPC_EID (0x051)
1492 #define SPR_MPC_NRI (0x052)
1493 #define SPR_TFHAR (0x080)
1494 #define SPR_TFIAR (0x081)
1495 #define SPR_TEXASR (0x082)
1496 #define SPR_TEXASRU (0x083)
1497 #define SPR_UCTRL (0x088)
1498 #define SPR_TIDR (0x090)
1499 #define SPR_MPC_CMPA (0x090)
1500 #define SPR_MPC_CMPB (0x091)
1501 #define SPR_MPC_CMPC (0x092)
1502 #define SPR_MPC_CMPD (0x093)
1503 #define SPR_MPC_ECR (0x094)
1504 #define SPR_MPC_DER (0x095)
1505 #define SPR_MPC_COUNTA (0x096)
1506 #define SPR_MPC_COUNTB (0x097)
1507 #define SPR_CTRL (0x098)
1508 #define SPR_MPC_CMPE (0x098)
1509 #define SPR_MPC_CMPF (0x099)
1510 #define SPR_FSCR (0x099)
1511 #define SPR_MPC_CMPG (0x09A)
1512 #define SPR_MPC_CMPH (0x09B)
1513 #define SPR_MPC_LCTRL1 (0x09C)
1514 #define SPR_MPC_LCTRL2 (0x09D)
1515 #define SPR_UAMOR (0x09D)
1516 #define SPR_MPC_ICTRL (0x09E)
1517 #define SPR_MPC_BAR (0x09F)
1518 #define SPR_PSPB (0x09F)
1519 #define SPR_DPDES (0x0B0)
1520 #define SPR_DAWR0 (0x0B4)
1521 #define SPR_RPR (0x0BA)
1522 #define SPR_CIABR (0x0BB)
1523 #define SPR_DAWRX0 (0x0BC)
1524 #define SPR_HFSCR (0x0BE)
1525 #define SPR_VRSAVE (0x100)
1526 #define SPR_USPRG0 (0x100)
1527 #define SPR_USPRG1 (0x101)
1528 #define SPR_USPRG2 (0x102)
1529 #define SPR_USPRG3 (0x103)
1530 #define SPR_USPRG4 (0x104)
1531 #define SPR_USPRG5 (0x105)
1532 #define SPR_USPRG6 (0x106)
1533 #define SPR_USPRG7 (0x107)
1534 #define SPR_VTBL (0x10C)
1535 #define SPR_VTBU (0x10D)
1536 #define SPR_SPRG0 (0x110)
1537 #define SPR_SPRG1 (0x111)
1538 #define SPR_SPRG2 (0x112)
1539 #define SPR_SPRG3 (0x113)
1540 #define SPR_SPRG4 (0x114)
1541 #define SPR_SCOMC (0x114)
1542 #define SPR_SPRG5 (0x115)
1543 #define SPR_SCOMD (0x115)
1544 #define SPR_SPRG6 (0x116)
1545 #define SPR_SPRG7 (0x117)
1546 #define SPR_ASR (0x118)
1547 #define SPR_EAR (0x11A)
1548 #define SPR_TBL (0x11C)
1549 #define SPR_TBU (0x11D)
1550 #define SPR_TBU40 (0x11E)
1551 #define SPR_SVR (0x11E)
1552 #define SPR_BOOKE_PIR (0x11E)
1553 #define SPR_PVR (0x11F)
1554 #define SPR_HSPRG0 (0x130)
1555 #define SPR_BOOKE_DBSR (0x130)
1556 #define SPR_HSPRG1 (0x131)
1557 #define SPR_HDSISR (0x132)
1558 #define SPR_HDAR (0x133)
1559 #define SPR_BOOKE_EPCR (0x133)
1560 #define SPR_SPURR (0x134)
1561 #define SPR_BOOKE_DBCR0 (0x134)
1562 #define SPR_IBCR (0x135)
1563 #define SPR_PURR (0x135)
1564 #define SPR_BOOKE_DBCR1 (0x135)
1565 #define SPR_DBCR (0x136)
1566 #define SPR_HDEC (0x136)
1567 #define SPR_BOOKE_DBCR2 (0x136)
1568 #define SPR_HIOR (0x137)
1569 #define SPR_MBAR (0x137)
1570 #define SPR_RMOR (0x138)
1571 #define SPR_BOOKE_IAC1 (0x138)
1572 #define SPR_HRMOR (0x139)
1573 #define SPR_BOOKE_IAC2 (0x139)
1574 #define SPR_HSRR0 (0x13A)
1575 #define SPR_BOOKE_IAC3 (0x13A)
1576 #define SPR_HSRR1 (0x13B)
1577 #define SPR_BOOKE_IAC4 (0x13B)
1578 #define SPR_BOOKE_DAC1 (0x13C)
1579 #define SPR_MMCRH (0x13C)
1580 #define SPR_DABR2 (0x13D)
1581 #define SPR_BOOKE_DAC2 (0x13D)
1582 #define SPR_TFMR (0x13D)
1583 #define SPR_BOOKE_DVC1 (0x13E)
1584 #define SPR_LPCR (0x13E)
1585 #define SPR_BOOKE_DVC2 (0x13F)
1586 #define SPR_LPIDR (0x13F)
1587 #define SPR_BOOKE_TSR (0x150)
1588 #define SPR_HMER (0x150)
1589 #define SPR_HMEER (0x151)
1590 #define SPR_PCR (0x152)
1591 #define SPR_BOOKE_LPIDR (0x152)
1592 #define SPR_BOOKE_TCR (0x154)
1593 #define SPR_BOOKE_TLB0PS (0x158)
1594 #define SPR_BOOKE_TLB1PS (0x159)
1595 #define SPR_BOOKE_TLB2PS (0x15A)
1596 #define SPR_BOOKE_TLB3PS (0x15B)
1597 #define SPR_AMOR (0x15D)
1598 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1599 #define SPR_BOOKE_IVOR0 (0x190)
1600 #define SPR_BOOKE_IVOR1 (0x191)
1601 #define SPR_BOOKE_IVOR2 (0x192)
1602 #define SPR_BOOKE_IVOR3 (0x193)
1603 #define SPR_BOOKE_IVOR4 (0x194)
1604 #define SPR_BOOKE_IVOR5 (0x195)
1605 #define SPR_BOOKE_IVOR6 (0x196)
1606 #define SPR_BOOKE_IVOR7 (0x197)
1607 #define SPR_BOOKE_IVOR8 (0x198)
1608 #define SPR_BOOKE_IVOR9 (0x199)
1609 #define SPR_BOOKE_IVOR10 (0x19A)
1610 #define SPR_BOOKE_IVOR11 (0x19B)
1611 #define SPR_BOOKE_IVOR12 (0x19C)
1612 #define SPR_BOOKE_IVOR13 (0x19D)
1613 #define SPR_BOOKE_IVOR14 (0x19E)
1614 #define SPR_BOOKE_IVOR15 (0x19F)
1615 #define SPR_BOOKE_IVOR38 (0x1B0)
1616 #define SPR_BOOKE_IVOR39 (0x1B1)
1617 #define SPR_BOOKE_IVOR40 (0x1B2)
1618 #define SPR_BOOKE_IVOR41 (0x1B3)
1619 #define SPR_BOOKE_IVOR42 (0x1B4)
1620 #define SPR_BOOKE_GIVOR2 (0x1B8)
1621 #define SPR_BOOKE_GIVOR3 (0x1B9)
1622 #define SPR_BOOKE_GIVOR4 (0x1BA)
1623 #define SPR_BOOKE_GIVOR8 (0x1BB)
1624 #define SPR_BOOKE_GIVOR13 (0x1BC)
1625 #define SPR_BOOKE_GIVOR14 (0x1BD)
1626 #define SPR_TIR (0x1BE)
1627 #define SPR_PTCR (0x1D0)
1628 #define SPR_BOOKE_SPEFSCR (0x200)
1629 #define SPR_Exxx_BBEAR (0x201)
1630 #define SPR_Exxx_BBTAR (0x202)
1631 #define SPR_Exxx_L1CFG0 (0x203)
1632 #define SPR_Exxx_L1CFG1 (0x204)
1633 #define SPR_Exxx_NPIDR (0x205)
1634 #define SPR_ATBL (0x20E)
1635 #define SPR_ATBU (0x20F)
1636 #define SPR_IBAT0U (0x210)
1637 #define SPR_BOOKE_IVOR32 (0x210)
1638 #define SPR_RCPU_MI_GRA (0x210)
1639 #define SPR_IBAT0L (0x211)
1640 #define SPR_BOOKE_IVOR33 (0x211)
1641 #define SPR_IBAT1U (0x212)
1642 #define SPR_BOOKE_IVOR34 (0x212)
1643 #define SPR_IBAT1L (0x213)
1644 #define SPR_BOOKE_IVOR35 (0x213)
1645 #define SPR_IBAT2U (0x214)
1646 #define SPR_BOOKE_IVOR36 (0x214)
1647 #define SPR_IBAT2L (0x215)
1648 #define SPR_BOOKE_IVOR37 (0x215)
1649 #define SPR_IBAT3U (0x216)
1650 #define SPR_IBAT3L (0x217)
1651 #define SPR_DBAT0U (0x218)
1652 #define SPR_RCPU_L2U_GRA (0x218)
1653 #define SPR_DBAT0L (0x219)
1654 #define SPR_DBAT1U (0x21A)
1655 #define SPR_DBAT1L (0x21B)
1656 #define SPR_DBAT2U (0x21C)
1657 #define SPR_DBAT2L (0x21D)
1658 #define SPR_DBAT3U (0x21E)
1659 #define SPR_DBAT3L (0x21F)
1660 #define SPR_IBAT4U (0x230)
1661 #define SPR_RPCU_BBCMCR (0x230)
1662 #define SPR_MPC_IC_CST (0x230)
1663 #define SPR_Exxx_CTXCR (0x230)
1664 #define SPR_IBAT4L (0x231)
1665 #define SPR_MPC_IC_ADR (0x231)
1666 #define SPR_Exxx_DBCR3 (0x231)
1667 #define SPR_IBAT5U (0x232)
1668 #define SPR_MPC_IC_DAT (0x232)
1669 #define SPR_Exxx_DBCNT (0x232)
1670 #define SPR_IBAT5L (0x233)
1671 #define SPR_IBAT6U (0x234)
1672 #define SPR_IBAT6L (0x235)
1673 #define SPR_IBAT7U (0x236)
1674 #define SPR_IBAT7L (0x237)
1675 #define SPR_DBAT4U (0x238)
1676 #define SPR_RCPU_L2U_MCR (0x238)
1677 #define SPR_MPC_DC_CST (0x238)
1678 #define SPR_Exxx_ALTCTXCR (0x238)
1679 #define SPR_DBAT4L (0x239)
1680 #define SPR_MPC_DC_ADR (0x239)
1681 #define SPR_DBAT5U (0x23A)
1682 #define SPR_BOOKE_MCSRR0 (0x23A)
1683 #define SPR_MPC_DC_DAT (0x23A)
1684 #define SPR_DBAT5L (0x23B)
1685 #define SPR_BOOKE_MCSRR1 (0x23B)
1686 #define SPR_DBAT6U (0x23C)
1687 #define SPR_BOOKE_MCSR (0x23C)
1688 #define SPR_DBAT6L (0x23D)
1689 #define SPR_Exxx_MCAR (0x23D)
1690 #define SPR_DBAT7U (0x23E)
1691 #define SPR_BOOKE_DSRR0 (0x23E)
1692 #define SPR_DBAT7L (0x23F)
1693 #define SPR_BOOKE_DSRR1 (0x23F)
1694 #define SPR_BOOKE_SPRG8 (0x25C)
1695 #define SPR_BOOKE_SPRG9 (0x25D)
1696 #define SPR_BOOKE_MAS0 (0x270)
1697 #define SPR_BOOKE_MAS1 (0x271)
1698 #define SPR_BOOKE_MAS2 (0x272)
1699 #define SPR_BOOKE_MAS3 (0x273)
1700 #define SPR_BOOKE_MAS4 (0x274)
1701 #define SPR_BOOKE_MAS5 (0x275)
1702 #define SPR_BOOKE_MAS6 (0x276)
1703 #define SPR_BOOKE_PID1 (0x279)
1704 #define SPR_BOOKE_PID2 (0x27A)
1705 #define SPR_MPC_DPDR (0x280)
1706 #define SPR_MPC_IMMR (0x288)
1707 #define SPR_BOOKE_TLB0CFG (0x2B0)
1708 #define SPR_BOOKE_TLB1CFG (0x2B1)
1709 #define SPR_BOOKE_TLB2CFG (0x2B2)
1710 #define SPR_BOOKE_TLB3CFG (0x2B3)
1711 #define SPR_BOOKE_EPR (0x2BE)
1712 #define SPR_PERF0 (0x300)
1713 #define SPR_RCPU_MI_RBA0 (0x300)
1714 #define SPR_MPC_MI_CTR (0x300)
1715 #define SPR_POWER_USIER (0x300)
1716 #define SPR_PERF1 (0x301)
1717 #define SPR_RCPU_MI_RBA1 (0x301)
1718 #define SPR_POWER_UMMCR2 (0x301)
1719 #define SPR_PERF2 (0x302)
1720 #define SPR_RCPU_MI_RBA2 (0x302)
1721 #define SPR_MPC_MI_AP (0x302)
1722 #define SPR_POWER_UMMCRA (0x302)
1723 #define SPR_PERF3 (0x303)
1724 #define SPR_RCPU_MI_RBA3 (0x303)
1725 #define SPR_MPC_MI_EPN (0x303)
1726 #define SPR_POWER_UPMC1 (0x303)
1727 #define SPR_PERF4 (0x304)
1728 #define SPR_POWER_UPMC2 (0x304)
1729 #define SPR_PERF5 (0x305)
1730 #define SPR_MPC_MI_TWC (0x305)
1731 #define SPR_POWER_UPMC3 (0x305)
1732 #define SPR_PERF6 (0x306)
1733 #define SPR_MPC_MI_RPN (0x306)
1734 #define SPR_POWER_UPMC4 (0x306)
1735 #define SPR_PERF7 (0x307)
1736 #define SPR_POWER_UPMC5 (0x307)
1737 #define SPR_PERF8 (0x308)
1738 #define SPR_RCPU_L2U_RBA0 (0x308)
1739 #define SPR_MPC_MD_CTR (0x308)
1740 #define SPR_POWER_UPMC6 (0x308)
1741 #define SPR_PERF9 (0x309)
1742 #define SPR_RCPU_L2U_RBA1 (0x309)
1743 #define SPR_MPC_MD_CASID (0x309)
1744 #define SPR_970_UPMC7 (0X309)
1745 #define SPR_PERFA (0x30A)
1746 #define SPR_RCPU_L2U_RBA2 (0x30A)
1747 #define SPR_MPC_MD_AP (0x30A)
1748 #define SPR_970_UPMC8 (0X30A)
1749 #define SPR_PERFB (0x30B)
1750 #define SPR_RCPU_L2U_RBA3 (0x30B)
1751 #define SPR_MPC_MD_EPN (0x30B)
1752 #define SPR_POWER_UMMCR0 (0X30B)
1753 #define SPR_PERFC (0x30C)
1754 #define SPR_MPC_MD_TWB (0x30C)
1755 #define SPR_POWER_USIAR (0X30C)
1756 #define SPR_PERFD (0x30D)
1757 #define SPR_MPC_MD_TWC (0x30D)
1758 #define SPR_POWER_USDAR (0X30D)
1759 #define SPR_PERFE (0x30E)
1760 #define SPR_MPC_MD_RPN (0x30E)
1761 #define SPR_POWER_UMMCR1 (0X30E)
1762 #define SPR_PERFF (0x30F)
1763 #define SPR_MPC_MD_TW (0x30F)
1764 #define SPR_UPERF0 (0x310)
1765 #define SPR_POWER_SIER (0x310)
1766 #define SPR_UPERF1 (0x311)
1767 #define SPR_POWER_MMCR2 (0x311)
1768 #define SPR_UPERF2 (0x312)
1769 #define SPR_POWER_MMCRA (0X312)
1770 #define SPR_UPERF3 (0x313)
1771 #define SPR_POWER_PMC1 (0X313)
1772 #define SPR_UPERF4 (0x314)
1773 #define SPR_POWER_PMC2 (0X314)
1774 #define SPR_UPERF5 (0x315)
1775 #define SPR_POWER_PMC3 (0X315)
1776 #define SPR_UPERF6 (0x316)
1777 #define SPR_POWER_PMC4 (0X316)
1778 #define SPR_UPERF7 (0x317)
1779 #define SPR_POWER_PMC5 (0X317)
1780 #define SPR_UPERF8 (0x318)
1781 #define SPR_POWER_PMC6 (0X318)
1782 #define SPR_UPERF9 (0x319)
1783 #define SPR_970_PMC7 (0X319)
1784 #define SPR_UPERFA (0x31A)
1785 #define SPR_970_PMC8 (0X31A)
1786 #define SPR_UPERFB (0x31B)
1787 #define SPR_POWER_MMCR0 (0X31B)
1788 #define SPR_UPERFC (0x31C)
1789 #define SPR_POWER_SIAR (0X31C)
1790 #define SPR_UPERFD (0x31D)
1791 #define SPR_POWER_SDAR (0X31D)
1792 #define SPR_UPERFE (0x31E)
1793 #define SPR_POWER_MMCR1 (0X31E)
1794 #define SPR_UPERFF (0x31F)
1795 #define SPR_RCPU_MI_RA0 (0x320)
1796 #define SPR_MPC_MI_DBCAM (0x320)
1797 #define SPR_BESCRS (0x320)
1798 #define SPR_RCPU_MI_RA1 (0x321)
1799 #define SPR_MPC_MI_DBRAM0 (0x321)
1800 #define SPR_BESCRSU (0x321)
1801 #define SPR_RCPU_MI_RA2 (0x322)
1802 #define SPR_MPC_MI_DBRAM1 (0x322)
1803 #define SPR_BESCRR (0x322)
1804 #define SPR_RCPU_MI_RA3 (0x323)
1805 #define SPR_BESCRRU (0x323)
1806 #define SPR_EBBHR (0x324)
1807 #define SPR_EBBRR (0x325)
1808 #define SPR_BESCR (0x326)
1809 #define SPR_RCPU_L2U_RA0 (0x328)
1810 #define SPR_MPC_MD_DBCAM (0x328)
1811 #define SPR_RCPU_L2U_RA1 (0x329)
1812 #define SPR_MPC_MD_DBRAM0 (0x329)
1813 #define SPR_RCPU_L2U_RA2 (0x32A)
1814 #define SPR_MPC_MD_DBRAM1 (0x32A)
1815 #define SPR_RCPU_L2U_RA3 (0x32B)
1816 #define SPR_TAR (0x32F)
1817 #define SPR_ASDR (0x330)
1818 #define SPR_IC (0x350)
1819 #define SPR_VTB (0x351)
1820 #define SPR_MMCRC (0x353)
1821 #define SPR_PSSCR (0x357)
1822 #define SPR_440_INV0 (0x370)
1823 #define SPR_440_INV1 (0x371)
1824 #define SPR_440_INV2 (0x372)
1825 #define SPR_440_INV3 (0x373)
1826 #define SPR_440_ITV0 (0x374)
1827 #define SPR_440_ITV1 (0x375)
1828 #define SPR_440_ITV2 (0x376)
1829 #define SPR_440_ITV3 (0x377)
1830 #define SPR_440_CCR1 (0x378)
1831 #define SPR_TACR (0x378)
1832 #define SPR_TCSCR (0x379)
1833 #define SPR_CSIGR (0x37a)
1834 #define SPR_DCRIPR (0x37B)
1835 #define SPR_POWER_SPMC1 (0x37C)
1836 #define SPR_POWER_SPMC2 (0x37D)
1837 #define SPR_POWER_MMCRS (0x37E)
1838 #define SPR_WORT (0x37F)
1839 #define SPR_PPR (0x380)
1840 #define SPR_750_GQR0 (0x390)
1841 #define SPR_440_DNV0 (0x390)
1842 #define SPR_750_GQR1 (0x391)
1843 #define SPR_440_DNV1 (0x391)
1844 #define SPR_750_GQR2 (0x392)
1845 #define SPR_440_DNV2 (0x392)
1846 #define SPR_750_GQR3 (0x393)
1847 #define SPR_440_DNV3 (0x393)
1848 #define SPR_750_GQR4 (0x394)
1849 #define SPR_440_DTV0 (0x394)
1850 #define SPR_750_GQR5 (0x395)
1851 #define SPR_440_DTV1 (0x395)
1852 #define SPR_750_GQR6 (0x396)
1853 #define SPR_440_DTV2 (0x396)
1854 #define SPR_750_GQR7 (0x397)
1855 #define SPR_440_DTV3 (0x397)
1856 #define SPR_750_THRM4 (0x398)
1857 #define SPR_750CL_HID2 (0x398)
1858 #define SPR_440_DVLIM (0x398)
1859 #define SPR_750_WPAR (0x399)
1860 #define SPR_440_IVLIM (0x399)
1861 #define SPR_TSCR (0x399)
1862 #define SPR_750_DMAU (0x39A)
1863 #define SPR_750_DMAL (0x39B)
1864 #define SPR_440_RSTCFG (0x39B)
1865 #define SPR_BOOKE_DCDBTRL (0x39C)
1866 #define SPR_BOOKE_DCDBTRH (0x39D)
1867 #define SPR_BOOKE_ICDBTRL (0x39E)
1868 #define SPR_BOOKE_ICDBTRH (0x39F)
1869 #define SPR_74XX_UMMCR2 (0x3A0)
1870 #define SPR_7XX_UPMC5 (0x3A1)
1871 #define SPR_7XX_UPMC6 (0x3A2)
1872 #define SPR_UBAMR (0x3A7)
1873 #define SPR_7XX_UMMCR0 (0x3A8)
1874 #define SPR_7XX_UPMC1 (0x3A9)
1875 #define SPR_7XX_UPMC2 (0x3AA)
1876 #define SPR_7XX_USIAR (0x3AB)
1877 #define SPR_7XX_UMMCR1 (0x3AC)
1878 #define SPR_7XX_UPMC3 (0x3AD)
1879 #define SPR_7XX_UPMC4 (0x3AE)
1880 #define SPR_USDA (0x3AF)
1881 #define SPR_40x_ZPR (0x3B0)
1882 #define SPR_BOOKE_MAS7 (0x3B0)
1883 #define SPR_74XX_MMCR2 (0x3B0)
1884 #define SPR_7XX_PMC5 (0x3B1)
1885 #define SPR_40x_PID (0x3B1)
1886 #define SPR_7XX_PMC6 (0x3B2)
1887 #define SPR_440_MMUCR (0x3B2)
1888 #define SPR_4xx_CCR0 (0x3B3)
1889 #define SPR_BOOKE_EPLC (0x3B3)
1890 #define SPR_405_IAC3 (0x3B4)
1891 #define SPR_BOOKE_EPSC (0x3B4)
1892 #define SPR_405_IAC4 (0x3B5)
1893 #define SPR_405_DVC1 (0x3B6)
1894 #define SPR_405_DVC2 (0x3B7)
1895 #define SPR_BAMR (0x3B7)
1896 #define SPR_7XX_MMCR0 (0x3B8)
1897 #define SPR_7XX_PMC1 (0x3B9)
1898 #define SPR_40x_SGR (0x3B9)
1899 #define SPR_7XX_PMC2 (0x3BA)
1900 #define SPR_40x_DCWR (0x3BA)
1901 #define SPR_7XX_SIAR (0x3BB)
1902 #define SPR_405_SLER (0x3BB)
1903 #define SPR_7XX_MMCR1 (0x3BC)
1904 #define SPR_405_SU0R (0x3BC)
1905 #define SPR_401_SKR (0x3BC)
1906 #define SPR_7XX_PMC3 (0x3BD)
1907 #define SPR_405_DBCR1 (0x3BD)
1908 #define SPR_7XX_PMC4 (0x3BE)
1909 #define SPR_SDA (0x3BF)
1910 #define SPR_403_VTBL (0x3CC)
1911 #define SPR_403_VTBU (0x3CD)
1912 #define SPR_DMISS (0x3D0)
1913 #define SPR_DCMP (0x3D1)
1914 #define SPR_HASH1 (0x3D2)
1915 #define SPR_HASH2 (0x3D3)
1916 #define SPR_BOOKE_ICDBDR (0x3D3)
1917 #define SPR_TLBMISS (0x3D4)
1918 #define SPR_IMISS (0x3D4)
1919 #define SPR_40x_ESR (0x3D4)
1920 #define SPR_PTEHI (0x3D5)
1921 #define SPR_ICMP (0x3D5)
1922 #define SPR_40x_DEAR (0x3D5)
1923 #define SPR_PTELO (0x3D6)
1924 #define SPR_RPA (0x3D6)
1925 #define SPR_40x_EVPR (0x3D6)
1926 #define SPR_L3PM (0x3D7)
1927 #define SPR_403_CDBCR (0x3D7)
1928 #define SPR_L3ITCR0 (0x3D8)
1929 #define SPR_TCR (0x3D8)
1930 #define SPR_40x_TSR (0x3D8)
1931 #define SPR_IBR (0x3DA)
1932 #define SPR_40x_TCR (0x3DA)
1933 #define SPR_ESASRR (0x3DB)
1934 #define SPR_40x_PIT (0x3DB)
1935 #define SPR_403_TBL (0x3DC)
1936 #define SPR_403_TBU (0x3DD)
1937 #define SPR_SEBR (0x3DE)
1938 #define SPR_40x_SRR2 (0x3DE)
1939 #define SPR_SER (0x3DF)
1940 #define SPR_40x_SRR3 (0x3DF)
1941 #define SPR_L3OHCR (0x3E8)
1942 #define SPR_L3ITCR1 (0x3E9)
1943 #define SPR_L3ITCR2 (0x3EA)
1944 #define SPR_L3ITCR3 (0x3EB)
1945 #define SPR_HID0 (0x3F0)
1946 #define SPR_40x_DBSR (0x3F0)
1947 #define SPR_HID1 (0x3F1)
1948 #define SPR_IABR (0x3F2)
1949 #define SPR_40x_DBCR0 (0x3F2)
1950 #define SPR_601_HID2 (0x3F2)
1951 #define SPR_Exxx_L1CSR0 (0x3F2)
1952 #define SPR_ICTRL (0x3F3)
1953 #define SPR_HID2 (0x3F3)
1954 #define SPR_750CL_HID4 (0x3F3)
1955 #define SPR_Exxx_L1CSR1 (0x3F3)
1956 #define SPR_440_DBDR (0x3F3)
1957 #define SPR_LDSTDB (0x3F4)
1958 #define SPR_750_TDCL (0x3F4)
1959 #define SPR_40x_IAC1 (0x3F4)
1960 #define SPR_MMUCSR0 (0x3F4)
1961 #define SPR_970_HID4 (0x3F4)
1962 #define SPR_DABR (0x3F5)
1963 #define DABR_MASK (~(target_ulong)0x7)
1964 #define SPR_Exxx_BUCSR (0x3F5)
1965 #define SPR_40x_IAC2 (0x3F5)
1966 #define SPR_601_HID5 (0x3F5)
1967 #define SPR_40x_DAC1 (0x3F6)
1968 #define SPR_MSSCR0 (0x3F6)
1969 #define SPR_970_HID5 (0x3F6)
1970 #define SPR_MSSSR0 (0x3F7)
1971 #define SPR_MSSCR1 (0x3F7)
1972 #define SPR_DABRX (0x3F7)
1973 #define SPR_40x_DAC2 (0x3F7)
1974 #define SPR_MMUCFG (0x3F7)
1975 #define SPR_LDSTCR (0x3F8)
1976 #define SPR_L2PMCR (0x3F8)
1977 #define SPR_750FX_HID2 (0x3F8)
1978 #define SPR_Exxx_L1FINV0 (0x3F8)
1979 #define SPR_L2CR (0x3F9)
1980 #define SPR_Exxx_L2CSR0 (0x3F9)
1981 #define SPR_L3CR (0x3FA)
1982 #define SPR_750_TDCH (0x3FA)
1983 #define SPR_IABR2 (0x3FA)
1984 #define SPR_40x_DCCR (0x3FA)
1985 #define SPR_ICTC (0x3FB)
1986 #define SPR_40x_ICCR (0x3FB)
1987 #define SPR_THRM1 (0x3FC)
1988 #define SPR_403_PBL1 (0x3FC)
1989 #define SPR_SP (0x3FD)
1990 #define SPR_THRM2 (0x3FD)
1991 #define SPR_403_PBU1 (0x3FD)
1992 #define SPR_604_HID13 (0x3FD)
1993 #define SPR_LT (0x3FE)
1994 #define SPR_THRM3 (0x3FE)
1995 #define SPR_RCPU_FPECR (0x3FE)
1996 #define SPR_403_PBL2 (0x3FE)
1997 #define SPR_PIR (0x3FF)
1998 #define SPR_403_PBU2 (0x3FF)
1999 #define SPR_601_HID15 (0x3FF)
2000 #define SPR_604_HID15 (0x3FF)
2001 #define SPR_E500_SVR (0x3FF)
2003 /* Disable MAS Interrupt Updates for Hypervisor */
2004 #define EPCR_DMIUH (1 << 22)
2005 /* Disable Guest TLB Management Instructions */
2006 #define EPCR_DGTMI (1 << 23)
2007 /* Guest Interrupt Computation Mode */
2008 #define EPCR_GICM (1 << 24)
2009 /* Interrupt Computation Mode */
2010 #define EPCR_ICM (1 << 25)
2011 /* Disable Embedded Hypervisor Debug */
2012 #define EPCR_DUVD (1 << 26)
2013 /* Instruction Storage Interrupt Directed to Guest State */
2014 #define EPCR_ISIGS (1 << 27)
2015 /* Data Storage Interrupt Directed to Guest State */
2016 #define EPCR_DSIGS (1 << 28)
2017 /* Instruction TLB Error Interrupt Directed to Guest State */
2018 #define EPCR_ITLBGS (1 << 29)
2019 /* Data TLB Error Interrupt Directed to Guest State */
2020 #define EPCR_DTLBGS (1 << 30)
2021 /* External Input Interrupt Directed to Guest State */
2022 #define EPCR_EXTGS (1 << 31)
2024 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2025 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2026 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2027 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2028 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
2030 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2031 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2032 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2033 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2034 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2037 #define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
2038 #define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
2039 #define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
2042 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2043 #define HID0_DOZE (1 << 23) /* pre-2.06 */
2044 #define HID0_NAP (1 << 22) /* pre-2.06 */
2045 #define HID0_HILE PPC_BIT(19) /* POWER8 */
2046 #define HID0_POWER9_HILE PPC_BIT(4)
2048 /*****************************************************************************/
2049 /* PowerPC Instructions types definitions */
2051 PPC_NONE
= 0x0000000000000000ULL
,
2052 /* PowerPC base instructions set */
2053 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
2054 /* integer operations instructions */
2055 #define PPC_INTEGER PPC_INSNS_BASE
2056 /* flow control instructions */
2057 #define PPC_FLOW PPC_INSNS_BASE
2058 /* virtual memory instructions */
2059 #define PPC_MEM PPC_INSNS_BASE
2060 /* ld/st with reservation instructions */
2061 #define PPC_RES PPC_INSNS_BASE
2062 /* spr/msr access instructions */
2063 #define PPC_MISC PPC_INSNS_BASE
2064 /* Deprecated instruction sets */
2065 /* Original POWER instruction set */
2066 PPC_POWER
= 0x0000000000000002ULL
,
2067 /* POWER2 instruction set extension */
2068 PPC_POWER2
= 0x0000000000000004ULL
,
2069 /* Power RTC support */
2070 PPC_POWER_RTC
= 0x0000000000000008ULL
,
2071 /* Power-to-PowerPC bridge (601) */
2072 PPC_POWER_BR
= 0x0000000000000010ULL
,
2073 /* 64 bits PowerPC instruction set */
2074 PPC_64B
= 0x0000000000000020ULL
,
2075 /* New 64 bits extensions (PowerPC 2.0x) */
2076 PPC_64BX
= 0x0000000000000040ULL
,
2077 /* 64 bits hypervisor extensions */
2078 PPC_64H
= 0x0000000000000080ULL
,
2079 /* New wait instruction (PowerPC 2.0x) */
2080 PPC_WAIT
= 0x0000000000000100ULL
,
2081 /* Time base mftb instruction */
2082 PPC_MFTB
= 0x0000000000000200ULL
,
2084 /* Fixed-point unit extensions */
2085 /* PowerPC 602 specific */
2086 PPC_602_SPEC
= 0x0000000000000400ULL
,
2087 /* isel instruction */
2088 PPC_ISEL
= 0x0000000000000800ULL
,
2089 /* popcntb instruction */
2090 PPC_POPCNTB
= 0x0000000000001000ULL
,
2091 /* string load / store */
2092 PPC_STRING
= 0x0000000000002000ULL
,
2093 /* real mode cache inhibited load / store */
2094 PPC_CILDST
= 0x0000000000004000ULL
,
2096 /* Floating-point unit extensions */
2097 /* Optional floating point instructions */
2098 PPC_FLOAT
= 0x0000000000010000ULL
,
2099 /* New floating-point extensions (PowerPC 2.0x) */
2100 PPC_FLOAT_EXT
= 0x0000000000020000ULL
,
2101 PPC_FLOAT_FSQRT
= 0x0000000000040000ULL
,
2102 PPC_FLOAT_FRES
= 0x0000000000080000ULL
,
2103 PPC_FLOAT_FRSQRTE
= 0x0000000000100000ULL
,
2104 PPC_FLOAT_FRSQRTES
= 0x0000000000200000ULL
,
2105 PPC_FLOAT_FSEL
= 0x0000000000400000ULL
,
2106 PPC_FLOAT_STFIWX
= 0x0000000000800000ULL
,
2108 /* Vector/SIMD extensions */
2109 /* Altivec support */
2110 PPC_ALTIVEC
= 0x0000000001000000ULL
,
2111 /* PowerPC 2.03 SPE extension */
2112 PPC_SPE
= 0x0000000002000000ULL
,
2113 /* PowerPC 2.03 SPE single-precision floating-point extension */
2114 PPC_SPE_SINGLE
= 0x0000000004000000ULL
,
2115 /* PowerPC 2.03 SPE double-precision floating-point extension */
2116 PPC_SPE_DOUBLE
= 0x0000000008000000ULL
,
2118 /* Optional memory control instructions */
2119 PPC_MEM_TLBIA
= 0x0000000010000000ULL
,
2120 PPC_MEM_TLBIE
= 0x0000000020000000ULL
,
2121 PPC_MEM_TLBSYNC
= 0x0000000040000000ULL
,
2122 /* sync instruction */
2123 PPC_MEM_SYNC
= 0x0000000080000000ULL
,
2124 /* eieio instruction */
2125 PPC_MEM_EIEIO
= 0x0000000100000000ULL
,
2127 /* Cache control instructions */
2128 PPC_CACHE
= 0x0000000200000000ULL
,
2129 /* icbi instruction */
2130 PPC_CACHE_ICBI
= 0x0000000400000000ULL
,
2131 /* dcbz instruction */
2132 PPC_CACHE_DCBZ
= 0x0000000800000000ULL
,
2133 /* dcba instruction */
2134 PPC_CACHE_DCBA
= 0x0000002000000000ULL
,
2135 /* Freescale cache locking instructions */
2136 PPC_CACHE_LOCK
= 0x0000004000000000ULL
,
2138 /* MMU related extensions */
2139 /* external control instructions */
2140 PPC_EXTERN
= 0x0000010000000000ULL
,
2141 /* segment register access instructions */
2142 PPC_SEGMENT
= 0x0000020000000000ULL
,
2143 /* PowerPC 6xx TLB management instructions */
2144 PPC_6xx_TLB
= 0x0000040000000000ULL
,
2145 /* PowerPC 74xx TLB management instructions */
2146 PPC_74xx_TLB
= 0x0000080000000000ULL
,
2147 /* PowerPC 40x TLB management instructions */
2148 PPC_40x_TLB
= 0x0000100000000000ULL
,
2149 /* segment register access instructions for PowerPC 64 "bridge" */
2150 PPC_SEGMENT_64B
= 0x0000200000000000ULL
,
2151 /* SLB management */
2152 PPC_SLBI
= 0x0000400000000000ULL
,
2154 /* Embedded PowerPC dedicated instructions */
2155 PPC_WRTEE
= 0x0001000000000000ULL
,
2156 /* PowerPC 40x exception model */
2157 PPC_40x_EXCP
= 0x0002000000000000ULL
,
2158 /* PowerPC 405 Mac instructions */
2159 PPC_405_MAC
= 0x0004000000000000ULL
,
2160 /* PowerPC 440 specific instructions */
2161 PPC_440_SPEC
= 0x0008000000000000ULL
,
2162 /* BookE (embedded) PowerPC specification */
2163 PPC_BOOKE
= 0x0010000000000000ULL
,
2164 /* mfapidi instruction */
2165 PPC_MFAPIDI
= 0x0020000000000000ULL
,
2166 /* tlbiva instruction */
2167 PPC_TLBIVA
= 0x0040000000000000ULL
,
2168 /* tlbivax instruction */
2169 PPC_TLBIVAX
= 0x0080000000000000ULL
,
2170 /* PowerPC 4xx dedicated instructions */
2171 PPC_4xx_COMMON
= 0x0100000000000000ULL
,
2172 /* PowerPC 40x ibct instructions */
2173 PPC_40x_ICBT
= 0x0200000000000000ULL
,
2174 /* rfmci is not implemented in all BookE PowerPC */
2175 PPC_RFMCI
= 0x0400000000000000ULL
,
2176 /* rfdi instruction */
2177 PPC_RFDI
= 0x0800000000000000ULL
,
2179 PPC_DCR
= 0x1000000000000000ULL
,
2180 /* DCR extended accesse */
2181 PPC_DCRX
= 0x2000000000000000ULL
,
2182 /* user-mode DCR access, implemented in PowerPC 460 */
2183 PPC_DCRUX
= 0x4000000000000000ULL
,
2184 /* popcntw and popcntd instructions */
2185 PPC_POPCNTWD
= 0x8000000000000000ULL
,
2187 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2188 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2189 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2190 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2191 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2192 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2193 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2194 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2195 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2196 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2197 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2198 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2199 | PPC_CACHE | PPC_CACHE_ICBI \
2201 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2202 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2203 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2204 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2205 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2206 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2207 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2208 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2209 | PPC_POPCNTWD | PPC_CILDST)
2211 /* extended type values */
2213 /* BookE 2.06 PowerPC specification */
2214 PPC2_BOOKE206
= 0x0000000000000001ULL
,
2215 /* VSX (extensions to Altivec / VMX) */
2216 PPC2_VSX
= 0x0000000000000002ULL
,
2217 /* Decimal Floating Point (DFP) */
2218 PPC2_DFP
= 0x0000000000000004ULL
,
2219 /* Embedded.Processor Control */
2220 PPC2_PRCNTL
= 0x0000000000000008ULL
,
2221 /* Byte-reversed, indexed, double-word load and store */
2222 PPC2_DBRX
= 0x0000000000000010ULL
,
2223 /* Book I 2.05 PowerPC specification */
2224 PPC2_ISA205
= 0x0000000000000020ULL
,
2225 /* VSX additions in ISA 2.07 */
2226 PPC2_VSX207
= 0x0000000000000040ULL
,
2227 /* ISA 2.06B bpermd */
2228 PPC2_PERM_ISA206
= 0x0000000000000080ULL
,
2229 /* ISA 2.06B divide extended variants */
2230 PPC2_DIVE_ISA206
= 0x0000000000000100ULL
,
2231 /* ISA 2.06B larx/stcx. instructions */
2232 PPC2_ATOMIC_ISA206
= 0x0000000000000200ULL
,
2233 /* ISA 2.06B floating point integer conversion */
2234 PPC2_FP_CVT_ISA206
= 0x0000000000000400ULL
,
2235 /* ISA 2.06B floating point test instructions */
2236 PPC2_FP_TST_ISA206
= 0x0000000000000800ULL
,
2237 /* ISA 2.07 bctar instruction */
2238 PPC2_BCTAR_ISA207
= 0x0000000000001000ULL
,
2239 /* ISA 2.07 load/store quadword */
2240 PPC2_LSQ_ISA207
= 0x0000000000002000ULL
,
2241 /* ISA 2.07 Altivec */
2242 PPC2_ALTIVEC_207
= 0x0000000000004000ULL
,
2243 /* PowerISA 2.07 Book3s specification */
2244 PPC2_ISA207S
= 0x0000000000008000ULL
,
2245 /* Double precision floating point conversion for signed integer 64 */
2246 PPC2_FP_CVT_S64
= 0x0000000000010000ULL
,
2247 /* Transactional Memory (ISA 2.07, Book II) */
2248 PPC2_TM
= 0x0000000000020000ULL
,
2249 /* Server PM instructgions (ISA 2.06, Book III) */
2250 PPC2_PM_ISA206
= 0x0000000000040000ULL
,
2252 PPC2_ISA300
= 0x0000000000080000ULL
,
2254 PPC2_ISA310
= 0x0000000000100000ULL
,
2256 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2257 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2258 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2259 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2260 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2261 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2262 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2263 PPC2_ISA300 | PPC2_ISA310)
2266 /*****************************************************************************/
2268 * Memory access type :
2269 * may be needed for precise access rights control and precise exceptions.
2272 /* Type of instruction that generated the access */
2273 ACCESS_CODE
= 0x10, /* Code fetch access */
2274 ACCESS_INT
= 0x20, /* Integer load/store access */
2275 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
2276 ACCESS_RES
= 0x40, /* load/store with reservation */
2277 ACCESS_EXT
= 0x50, /* external access */
2278 ACCESS_CACHE
= 0x60, /* Cache manipulation */
2282 * Hardware interrupt sources:
2283 * all those exception can be raised simulteaneously
2285 /* Input pins definitions */
2287 /* 6xx bus input pins */
2288 PPC6xx_INPUT_HRESET
= 0,
2289 PPC6xx_INPUT_SRESET
= 1,
2290 PPC6xx_INPUT_CKSTP_IN
= 2,
2291 PPC6xx_INPUT_MCP
= 3,
2292 PPC6xx_INPUT_SMI
= 4,
2293 PPC6xx_INPUT_INT
= 5,
2294 PPC6xx_INPUT_TBEN
= 6,
2295 PPC6xx_INPUT_WAKEUP
= 7,
2300 /* Embedded PowerPC input pins */
2301 PPCBookE_INPUT_HRESET
= 0,
2302 PPCBookE_INPUT_SRESET
= 1,
2303 PPCBookE_INPUT_CKSTP_IN
= 2,
2304 PPCBookE_INPUT_MCP
= 3,
2305 PPCBookE_INPUT_SMI
= 4,
2306 PPCBookE_INPUT_INT
= 5,
2307 PPCBookE_INPUT_CINT
= 6,
2312 /* PowerPC E500 input pins */
2313 PPCE500_INPUT_RESET_CORE
= 0,
2314 PPCE500_INPUT_MCK
= 1,
2315 PPCE500_INPUT_CINT
= 3,
2316 PPCE500_INPUT_INT
= 4,
2317 PPCE500_INPUT_DEBUG
= 6,
2322 /* PowerPC 40x input pins */
2323 PPC40x_INPUT_RESET_CORE
= 0,
2324 PPC40x_INPUT_RESET_CHIP
= 1,
2325 PPC40x_INPUT_RESET_SYS
= 2,
2326 PPC40x_INPUT_CINT
= 3,
2327 PPC40x_INPUT_INT
= 4,
2328 PPC40x_INPUT_HALT
= 5,
2329 PPC40x_INPUT_DEBUG
= 6,
2334 /* RCPU input pins */
2335 PPCRCPU_INPUT_PORESET
= 0,
2336 PPCRCPU_INPUT_HRESET
= 1,
2337 PPCRCPU_INPUT_SRESET
= 2,
2338 PPCRCPU_INPUT_IRQ0
= 3,
2339 PPCRCPU_INPUT_IRQ1
= 4,
2340 PPCRCPU_INPUT_IRQ2
= 5,
2341 PPCRCPU_INPUT_IRQ3
= 6,
2342 PPCRCPU_INPUT_IRQ4
= 7,
2343 PPCRCPU_INPUT_IRQ5
= 8,
2344 PPCRCPU_INPUT_IRQ6
= 9,
2345 PPCRCPU_INPUT_IRQ7
= 10,
2349 #if defined(TARGET_PPC64)
2351 /* PowerPC 970 input pins */
2352 PPC970_INPUT_HRESET
= 0,
2353 PPC970_INPUT_SRESET
= 1,
2354 PPC970_INPUT_CKSTP
= 2,
2355 PPC970_INPUT_TBEN
= 3,
2356 PPC970_INPUT_MCP
= 4,
2357 PPC970_INPUT_INT
= 5,
2358 PPC970_INPUT_THINT
= 6,
2363 /* POWER7 input pins */
2364 POWER7_INPUT_INT
= 0,
2366 * POWER7 probably has other inputs, but we don't care about them
2367 * for any existing machine. We can wire these up when we need
2374 /* POWER9 input pins */
2375 POWER9_INPUT_INT
= 0,
2376 POWER9_INPUT_HINT
= 1,
2381 /* Hardware exceptions definitions */
2383 /* External hardware exception sources */
2384 PPC_INTERRUPT_RESET
= 0, /* Reset exception */
2385 PPC_INTERRUPT_WAKEUP
, /* Wakeup exception */
2386 PPC_INTERRUPT_MCK
, /* Machine check exception */
2387 PPC_INTERRUPT_EXT
, /* External interrupt */
2388 PPC_INTERRUPT_SMI
, /* System management interrupt */
2389 PPC_INTERRUPT_CEXT
, /* Critical external interrupt */
2390 PPC_INTERRUPT_DEBUG
, /* External debug exception */
2391 PPC_INTERRUPT_THERM
, /* Thermal exception */
2392 /* Internal hardware exception sources */
2393 PPC_INTERRUPT_DECR
, /* Decrementer exception */
2394 PPC_INTERRUPT_HDECR
, /* Hypervisor decrementer exception */
2395 PPC_INTERRUPT_PIT
, /* Programmable interval timer interrupt */
2396 PPC_INTERRUPT_FIT
, /* Fixed interval timer interrupt */
2397 PPC_INTERRUPT_WDT
, /* Watchdog timer interrupt */
2398 PPC_INTERRUPT_CDOORBELL
, /* Critical doorbell interrupt */
2399 PPC_INTERRUPT_DOORBELL
, /* Doorbell interrupt */
2400 PPC_INTERRUPT_PERFM
, /* Performance monitor interrupt */
2401 PPC_INTERRUPT_HMI
, /* Hypervisor Maintenance interrupt */
2402 PPC_INTERRUPT_HDOORBELL
, /* Hypervisor Doorbell interrupt */
2403 PPC_INTERRUPT_HVIRT
, /* Hypervisor virtualization interrupt */
2406 /* Processor Compatibility mask (PCR) */
2408 PCR_COMPAT_2_05
= PPC_BIT(62),
2409 PCR_COMPAT_2_06
= PPC_BIT(61),
2410 PCR_COMPAT_2_07
= PPC_BIT(60),
2411 PCR_COMPAT_3_00
= PPC_BIT(59),
2412 PCR_COMPAT_3_10
= PPC_BIT(58),
2413 PCR_VEC_DIS
= PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2414 PCR_VSX_DIS
= PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2415 PCR_TM_DIS
= PPC_BIT(2), /* Trans. memory disable (POWER8) */
2420 HMER_MALFUNCTION_ALERT
= PPC_BIT(0),
2421 HMER_PROC_RECV_DONE
= PPC_BIT(2),
2422 HMER_PROC_RECV_ERROR_MASKED
= PPC_BIT(3),
2423 HMER_TFAC_ERROR
= PPC_BIT(4),
2424 HMER_TFMR_PARITY_ERROR
= PPC_BIT(5),
2425 HMER_XSCOM_FAIL
= PPC_BIT(8),
2426 HMER_XSCOM_DONE
= PPC_BIT(9),
2427 HMER_PROC_RECV_AGAIN
= PPC_BIT(11),
2428 HMER_WARN_RISE
= PPC_BIT(14),
2429 HMER_WARN_FALL
= PPC_BIT(15),
2430 HMER_SCOM_FIR_HMI
= PPC_BIT(16),
2431 HMER_TRIG_FIR_HMI
= PPC_BIT(17),
2432 HMER_HYP_RESOURCE_ERR
= PPC_BIT(20),
2433 HMER_XSCOM_STATUS_MASK
= PPC_BITMASK(21, 23),
2436 /*****************************************************************************/
2438 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2439 target_ulong
cpu_read_xer(const CPUPPCState
*env
);
2440 void cpu_write_xer(CPUPPCState
*env
, target_ulong xer
);
2443 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2444 * have PPC_SEGMENT_64B.
2446 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2448 #ifdef CONFIG_DEBUG_TCG
2449 void cpu_get_tb_cpu_state(CPUPPCState
*env
, target_ulong
*pc
,
2450 target_ulong
*cs_base
, uint32_t *flags
);
2452 static inline void cpu_get_tb_cpu_state(CPUPPCState
*env
, target_ulong
*pc
,
2453 target_ulong
*cs_base
, uint32_t *flags
)
2457 *flags
= env
->hflags
;
2461 void QEMU_NORETURN
raise_exception(CPUPPCState
*env
, uint32_t exception
);
2462 void QEMU_NORETURN
raise_exception_ra(CPUPPCState
*env
, uint32_t exception
,
2464 void QEMU_NORETURN
raise_exception_err(CPUPPCState
*env
, uint32_t exception
,
2465 uint32_t error_code
);
2466 void QEMU_NORETURN
raise_exception_err_ra(CPUPPCState
*env
, uint32_t exception
,
2467 uint32_t error_code
, uintptr_t raddr
);
2469 #if !defined(CONFIG_USER_ONLY)
2470 static inline int booke206_tlbm_id(CPUPPCState
*env
, ppcmas_tlb_t
*tlbm
)
2472 uintptr_t tlbml
= (uintptr_t)tlbm
;
2473 uintptr_t tlbl
= (uintptr_t)env
->tlb
.tlbm
;
2475 return (tlbml
- tlbl
) / sizeof(env
->tlb
.tlbm
[0]);
2478 static inline int booke206_tlb_size(CPUPPCState
*env
, int tlbn
)
2480 uint32_t tlbncfg
= env
->spr
[SPR_BOOKE_TLB0CFG
+ tlbn
];
2481 int r
= tlbncfg
& TLBnCFG_N_ENTRY
;
2485 static inline int booke206_tlb_ways(CPUPPCState
*env
, int tlbn
)
2487 uint32_t tlbncfg
= env
->spr
[SPR_BOOKE_TLB0CFG
+ tlbn
];
2488 int r
= tlbncfg
>> TLBnCFG_ASSOC_SHIFT
;
2492 static inline int booke206_tlbm_to_tlbn(CPUPPCState
*env
, ppcmas_tlb_t
*tlbm
)
2494 int id
= booke206_tlbm_id(env
, tlbm
);
2498 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
2499 end
+= booke206_tlb_size(env
, i
);
2505 cpu_abort(env_cpu(env
), "Unknown TLBe: %d\n", id
);
2509 static inline int booke206_tlbm_to_way(CPUPPCState
*env
, ppcmas_tlb_t
*tlb
)
2511 int tlbn
= booke206_tlbm_to_tlbn(env
, tlb
);
2512 int tlbid
= booke206_tlbm_id(env
, tlb
);
2513 return tlbid
& (booke206_tlb_ways(env
, tlbn
) - 1);
2516 static inline ppcmas_tlb_t
*booke206_get_tlbm(CPUPPCState
*env
, const int tlbn
,
2517 target_ulong ea
, int way
)
2520 uint32_t ways
= booke206_tlb_ways(env
, tlbn
);
2521 int ways_bits
= ctz32(ways
);
2522 int tlb_bits
= ctz32(booke206_tlb_size(env
, tlbn
));
2526 ea
>>= MAS2_EPN_SHIFT
;
2527 ea
&= (1 << (tlb_bits
- ways_bits
)) - 1;
2528 r
= (ea
<< ways_bits
) | way
;
2530 if (r
>= booke206_tlb_size(env
, tlbn
)) {
2534 /* bump up to tlbn index */
2535 for (i
= 0; i
< tlbn
; i
++) {
2536 r
+= booke206_tlb_size(env
, i
);
2539 return &env
->tlb
.tlbm
[r
];
2542 /* returns bitmap of supported page sizes for a given TLB */
2543 static inline uint32_t booke206_tlbnps(CPUPPCState
*env
, const int tlbn
)
2547 if ((env
->spr
[SPR_MMUCFG
] & MMUCFG_MAVN
) == MMUCFG_MAVN_V2
) {
2549 ret
= env
->spr
[SPR_BOOKE_TLB0PS
+ tlbn
];
2551 uint32_t tlbncfg
= env
->spr
[SPR_BOOKE_TLB0CFG
+ tlbn
];
2552 uint32_t min
= (tlbncfg
& TLBnCFG_MINSIZE
) >> TLBnCFG_MINSIZE_SHIFT
;
2553 uint32_t max
= (tlbncfg
& TLBnCFG_MAXSIZE
) >> TLBnCFG_MAXSIZE_SHIFT
;
2555 for (i
= min
; i
<= max
; i
++) {
2556 ret
|= (1 << (i
<< 1));
2563 static inline void booke206_fixed_size_tlbn(CPUPPCState
*env
, const int tlbn
,
2569 for (i
= 0; i
< 32; i
++) {
2570 if ((env
->spr
[SPR_BOOKE_TLB0PS
+ tlbn
]) & (1ULL << i
)) {
2579 /* TLBnPS unimplemented? Odd.. */
2580 assert(tsize
!= -1);
2581 tlb
->mas1
&= ~MAS1_TSIZE_MASK
;
2582 tlb
->mas1
|= ((uint32_t)tsize
) << MAS1_TSIZE_SHIFT
;
2587 static inline bool msr_is_64bit(CPUPPCState
*env
, target_ulong msr
)
2589 if (env
->mmu_model
== POWERPC_MMU_BOOKE206
) {
2590 return msr
& (1ULL << MSR_CM
);
2593 return msr
& (1ULL << MSR_SF
);
2597 * Check whether register rx is in the range between start and
2598 * start + nregs (as needed by the LSWX and LSWI instructions)
2600 static inline bool lsw_reg_in_range(int start
, int nregs
, int rx
)
2602 return (start
+ nregs
<= 32 && rx
>= start
&& rx
< start
+ nregs
) ||
2603 (start
+ nregs
> 32 && (rx
>= start
|| rx
< start
+ nregs
- 32));
2606 /* Accessors for FP, VMX and VSX registers */
2607 #if defined(HOST_WORDS_BIGENDIAN)
2608 #define VsrB(i) u8[i]
2609 #define VsrSB(i) s8[i]
2610 #define VsrH(i) u16[i]
2611 #define VsrSH(i) s16[i]
2612 #define VsrW(i) u32[i]
2613 #define VsrSW(i) s32[i]
2614 #define VsrD(i) u64[i]
2615 #define VsrSD(i) s64[i]
2617 #define VsrB(i) u8[15 - (i)]
2618 #define VsrSB(i) s8[15 - (i)]
2619 #define VsrH(i) u16[7 - (i)]
2620 #define VsrSH(i) s16[7 - (i)]
2621 #define VsrW(i) u32[3 - (i)]
2622 #define VsrSW(i) s32[3 - (i)]
2623 #define VsrD(i) u64[1 - (i)]
2624 #define VsrSD(i) s64[1 - (i)]
2627 static inline int vsr64_offset(int i
, bool high
)
2629 return offsetof(CPUPPCState
, vsr
[i
].VsrD(high
? 0 : 1));
2632 static inline int vsr_full_offset(int i
)
2634 return offsetof(CPUPPCState
, vsr
[i
].u64
[0]);
2637 static inline int fpr_offset(int i
)
2639 return vsr64_offset(i
, true);
2642 static inline uint64_t *cpu_fpr_ptr(CPUPPCState
*env
, int i
)
2644 return (uint64_t *)((uintptr_t)env
+ fpr_offset(i
));
2647 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState
*env
, int i
)
2649 return (uint64_t *)((uintptr_t)env
+ vsr64_offset(i
, false));
2652 static inline long avr64_offset(int i
, bool high
)
2654 return vsr64_offset(i
+ 32, high
);
2657 static inline int avr_full_offset(int i
)
2659 return vsr_full_offset(i
+ 32);
2662 static inline ppc_avr_t
*cpu_avr_ptr(CPUPPCState
*env
, int i
)
2664 return (ppc_avr_t
*)((uintptr_t)env
+ avr_full_offset(i
));
2667 static inline bool ppc_has_spr(PowerPCCPU
*cpu
, int spr
)
2669 /* We can test whether the SPR is defined by checking for a valid name */
2670 return cpu
->env
.spr_cb
[spr
].name
!= NULL
;
2673 static inline bool ppc_interrupts_little_endian(PowerPCCPU
*cpu
)
2675 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
2678 * Only models that have an LPCR and know about LPCR_ILE can do little
2681 if (pcc
->lpcr_mask
& LPCR_ILE
) {
2682 return !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_ILE
);
2688 void dump_mmu(CPUPPCState
*env
);
2690 void ppc_maybe_bswap_register(CPUPPCState
*env
, uint8_t *mem_buf
, int len
);
2691 void ppc_store_vscr(CPUPPCState
*env
, uint32_t vscr
);
2692 uint32_t ppc_get_vscr(CPUPPCState
*env
);
2693 #endif /* PPC_CPU_H */