target/ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_CPU_H
  21 #define PPC_CPU_H
  22
  23 #include "qemu-common.h"
  24 #include "qemu/int128.h"
  25
  26 /* #define PPC_EMULATE_32BITS_HYPV */
  27
  28 #if defined(TARGET_PPC64)
  29 /* PowerPC 64 definitions */
  30 #define TARGET_LONG_BITS 64
  31 #define TARGET_PAGE_BITS 12
  32
  33 #define TCG_GUEST_DEFAULT_MO 0
  34
  35 /*
  36  * Note that the official physical address space bits is 62-M where M
  37  * is implementation dependent.  I've not looked up M for the set of
  38  * cpus we emulate at the system level.
  39  */
  40 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  41
  42 /*
  43  * Note that the PPC environment architecture talks about 80 bit
  44  * virtual addresses, with segmentation.  Obviously that's not all
  45  * visible to a single process, which is all we're concerned with
  46  * here.
  47  */
  48 #ifdef TARGET_ABI32
  49 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  50 #else
  51 # define TARGET_VIRT_ADDR_SPACE_BITS 64
  52 #endif
  53
  54 #define TARGET_PAGE_BITS_64K 16
  55 #define TARGET_PAGE_BITS_16M 24
  56
  57 #else /* defined(TARGET_PPC64) */
  58 /* PowerPC 32 definitions */
  59 #define TARGET_LONG_BITS 32
  60 #define TARGET_PAGE_BITS 12
  61
  62 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  63 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  64
  65 #endif /* defined(TARGET_PPC64) */
  66
  67 #define CPUArchState struct CPUPPCState
  68
  69 #include "exec/cpu-defs.h"
  70 #include "cpu-qom.h"
  71
  72 #if defined(TARGET_PPC64)
  73 #define PPC_ELF_MACHINE     EM_PPC64
  74 #else
  75 #define PPC_ELF_MACHINE     EM_PPC
  76 #endif
  77
  78 #define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
  79 #define PPC_BIT32(bit)          (0x80000000 >> (bit))
  80 #define PPC_BIT8(bit)           (0x80 >> (bit))
  81 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
  82 #define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
  83                                  PPC_BIT32(bs))
  84 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
  85
  86 /*****************************************************************************/
  87 /* Exception vectors definitions                                             */
  88 enum {
  89     POWERPC_EXCP_NONE    = -1,
  90     /* The 64 first entries are used by the PowerPC embedded specification   */
  91     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  92     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  93     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  94     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  95     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  96     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  97     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
  98     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
  99     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 100     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 101     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 102     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 103     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 104     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 105     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 106     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 107     /* Vectors 16 to 31 are reserved                                         */
 108     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 109     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 110     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 111     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 112     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 113     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 114     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
 115     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
 116     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
 117     /* Vectors 42 to 63 are reserved                                         */
 118     /* Exceptions defined in the PowerPC server specification                */
 119     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 120     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 121     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 122     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 123     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 124     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 125     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 126     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 127     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 128     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 129     /* 40x specific exceptions                                               */
 130     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 131     /* 601 specific exceptions                                               */
 132     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 133     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 134     /* 602 specific exceptions                                               */
 135     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 136     /* 602/603 specific exceptions                                           */
 137     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 138     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 139     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 140     /* Exceptions available on most PowerPC                                  */
 141     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 142     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 143     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 144     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 145     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 146     /* 7xx/74xx specific exceptions                                          */
 147     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 148     /* 74xx specific exceptions                                              */
 149     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 150     /* 970FX specific exceptions                                             */
 151     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 152     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 153     /* Freescale embedded cores specific exceptions                          */
 154     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 155     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 156     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 157     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 158     /* VSX Unavailable (Power ISA 2.06 and later)                            */
 159     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 160     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 161     /* Additional ISA 2.06 and later server exceptions                       */
 162     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 163     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 164     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 165     /* Server doorbell variants */
 166     POWERPC_EXCP_SDOOR    = 99,
 167     POWERPC_EXCP_SDOOR_HV = 100,
 168     /* ISA 3.00 additions */
 169     POWERPC_EXCP_HVIRT    = 101,
 170     /* EOL                                                                   */
 171     POWERPC_EXCP_NB       = 102,
 172     /* QEMU exceptions: used internally during code translation              */
 173     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 174     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 175     /* QEMU exceptions: special cases we want to stop translation            */
 176     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 177     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 178 };
 179
 180 /* Exceptions error codes                                                    */
 181 enum {
 182     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 183     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 184     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 185     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 186     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 187     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 188     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 189     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 190     /* FP exceptions                                                         */
 191     POWERPC_EXCP_FP            = 0x10,
 192     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 193     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 194     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 195     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 196     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 197     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 198     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 199     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 200     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 201     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 202     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 203     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 204     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 205     /* Invalid instruction                                                   */
 206     POWERPC_EXCP_INVAL         = 0x20,
 207     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 208     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 209     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 210     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 211     /* Privileged instruction                                                */
 212     POWERPC_EXCP_PRIV          = 0x30,
 213     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 214     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 215     /* Trap                                                                  */
 216     POWERPC_EXCP_TRAP          = 0x40,
 217 };
 218
 219 #define PPC_INPUT(env) (env->bus_model)
 220
 221 /*****************************************************************************/
 222 typedef struct opc_handler_t opc_handler_t;
 223
 224 /*****************************************************************************/
 225 /* Types used to describe some PowerPC registers etc. */
 226 typedef struct DisasContext DisasContext;
 227 typedef struct ppc_spr_t ppc_spr_t;
 228 typedef union ppc_tlb_t ppc_tlb_t;
 229 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
 230
 231 /* SPR access micro-ops generations callbacks */
 232 struct ppc_spr_t {
 233     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 234     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 235 #if !defined(CONFIG_USER_ONLY)
 236     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 237     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 238     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 239     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 240     unsigned int gdb_id;
 241 #endif
 242     const char *name;
 243     target_ulong default_value;
 244 #ifdef CONFIG_KVM
 245     /*
 246      * We (ab)use the fact that all the SPRs will have ids for the
 247      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 248      * don't sync this
 249      */
 250     uint64_t one_reg_id;
 251 #endif
 252 };
 253
 254 /* VSX/Altivec registers (128 bits) */
 255 typedef union _ppc_vsr_t {
 256     uint8_t u8[16];
 257     uint16_t u16[8];
 258     uint32_t u32[4];
 259     uint64_t u64[2];
 260     int8_t s8[16];
 261     int16_t s16[8];
 262     int32_t s32[4];
 263     int64_t s64[2];
 264     float32 f32[4];
 265     float64 f64[2];
 266     float128 f128;
 267 #ifdef CONFIG_INT128
 268     __uint128_t u128;
 269 #endif
 270     Int128  s128;
 271 } ppc_vsr_t;
 272
 273 typedef ppc_vsr_t ppc_avr_t;
 274
 275 #if !defined(CONFIG_USER_ONLY)
 276 /* Software TLB cache */
 277 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 278 struct ppc6xx_tlb_t {
 279     target_ulong pte0;
 280     target_ulong pte1;
 281     target_ulong EPN;
 282 };
 283
 284 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 285 struct ppcemb_tlb_t {
 286     uint64_t RPN;
 287     target_ulong EPN;
 288     target_ulong PID;
 289     target_ulong size;
 290     uint32_t prot;
 291     uint32_t attr; /* Storage attributes */
 292 };
 293
 294 typedef struct ppcmas_tlb_t {
 295      uint32_t mas8;
 296      uint32_t mas1;
 297      uint64_t mas2;
 298      uint64_t mas7_3;
 299 } ppcmas_tlb_t;
 300
 301 union ppc_tlb_t {
 302     ppc6xx_tlb_t *tlb6;
 303     ppcemb_tlb_t *tlbe;
 304     ppcmas_tlb_t *tlbm;
 305 };
 306
 307 /* possible TLB variants */
 308 #define TLB_NONE               0
 309 #define TLB_6XX                1
 310 #define TLB_EMB                2
 311 #define TLB_MAS                3
 312 #endif
 313
 314 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
 315
 316 typedef struct ppc_slb_t ppc_slb_t;
 317 struct ppc_slb_t {
 318     uint64_t esid;
 319     uint64_t vsid;
 320     const PPCHash64SegmentPageSizes *sps;
 321 };
 322
 323 #define MAX_SLB_ENTRIES         64
 324 #define SEGMENT_SHIFT_256M      28
 325 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 326
 327 #define SEGMENT_SHIFT_1T        40
 328 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 329
 330 typedef struct ppc_v3_pate_t {
 331     uint64_t dw0;
 332     uint64_t dw1;
 333 } ppc_v3_pate_t;
 334
 335 /*****************************************************************************/
 336 /* Machine state register bits definition                                    */
 337 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 338 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 339 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 340 #define MSR_SHV  60 /* hypervisor state                               hflags */
 341 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 342 #define MSR_TS1  33
 343 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 344 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 345 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 346 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 347 #define MSR_GS   28 /* guest state for BookE                                 */
 348 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 349 #define MSR_VR   25 /* altivec available                            x hflags */
 350 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 351 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 352 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 353 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 354 #define MSR_KEY  19 /* key bit on 603e                                       */
 355 #define MSR_POW  18 /* Power management                                      */
 356 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 357 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 358 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 359 #define MSR_EE   15 /* External interrupt enable                             */
 360 #define MSR_PR   14 /* Problem state                                  hflags */
 361 #define MSR_FP   13 /* Floating point available                       hflags */
 362 #define MSR_ME   12 /* Machine check interrupt enable                        */
 363 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 364 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 365 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 366 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 367 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 368 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 369 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 370 #define MSR_AL   7  /* AL bit on POWER                                       */
 371 #define MSR_EP   6  /* Exception prefix on 601                               */
 372 #define MSR_IR   5  /* Instruction relocate                                  */
 373 #define MSR_DR   4  /* Data relocate                                         */
 374 #define MSR_IS   5  /* Instruction address space (BookE)                     */
 375 #define MSR_DS   4  /* Data address space (BookE)                            */
 376 #define MSR_PE   3  /* Protection enable on 403                              */
 377 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 378 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 379 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 380 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 381
 382 /* LPCR bits */
 383 #define LPCR_VPM0         PPC_BIT(0)
 384 #define LPCR_VPM1         PPC_BIT(1)
 385 #define LPCR_ISL          PPC_BIT(2)
 386 #define LPCR_KBV          PPC_BIT(3)
 387 #define LPCR_DPFD_SHIFT   (63 - 11)
 388 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 389 #define LPCR_VRMASD_SHIFT (63 - 16)
 390 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 391 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
 392 #define LPCR_PECE_U_SHIFT (63 - 19)
 393 #define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
 394 #define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
 395 #define LPCR_RMLS_SHIFT   (63 - 37)
 396 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 397 #define LPCR_ILE          PPC_BIT(38)
 398 #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
 399 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 400 #define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
 401 #define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
 402 #define LPCR_HR           PPC_BIT(43) /* Host Radix */
 403 #define LPCR_ONL          PPC_BIT(45)
 404 #define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
 405 #define LPCR_P7_PECE0     PPC_BIT(49)
 406 #define LPCR_P7_PECE1     PPC_BIT(50)
 407 #define LPCR_P7_PECE2     PPC_BIT(51)
 408 #define LPCR_P8_PECE0     PPC_BIT(47)
 409 #define LPCR_P8_PECE1     PPC_BIT(48)
 410 #define LPCR_P8_PECE2     PPC_BIT(49)
 411 #define LPCR_P8_PECE3     PPC_BIT(50)
 412 #define LPCR_P8_PECE4     PPC_BIT(51)
 413 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
 414 #define LPCR_PECE_L_SHIFT (63 - 51)
 415 #define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
 416 #define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
 417 #define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
 418 #define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
 419 #define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
 420 #define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
 421 #define LPCR_MER          PPC_BIT(52)
 422 #define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
 423 #define LPCR_TC           PPC_BIT(54)
 424 #define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
 425 #define LPCR_LPES0        PPC_BIT(60)
 426 #define LPCR_LPES1        PPC_BIT(61)
 427 #define LPCR_RMI          PPC_BIT(62)
 428 #define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
 429 #define LPCR_HDICE        PPC_BIT(63)
 430
 431 /* PSSCR bits */
 432 #define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
 433 #define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
 434
 435 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 436 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 437 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 438 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 439 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 440 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 441 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 442 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 443 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 444 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 445 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 446 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 447 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 448 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 449 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 450 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 451 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 452 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 453 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 454 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 455 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 456 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 457 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 458 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 459 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 460 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 461 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 462 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 463 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 464 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 465 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 466 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 467 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 468 #define msr_is   ((env->msr >> MSR_IS)   & 1)
 469 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
 470 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 471 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 472 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 473 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 474 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 475 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 476 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
 477
 478 #define DBCR0_ICMP (1 << 27)
 479 #define DBCR0_BRT (1 << 26)
 480 #define DBSR_ICMP (1 << 27)
 481 #define DBSR_BRT (1 << 26)
 482
 483 /* Hypervisor bit is more specific */
 484 #if defined(TARGET_PPC64)
 485 #define MSR_HVB (1ULL << MSR_SHV)
 486 #define msr_hv  msr_shv
 487 #else
 488 #if defined(PPC_EMULATE_32BITS_HYPV)
 489 #define MSR_HVB (1ULL << MSR_THV)
 490 #define msr_hv  msr_thv
 491 #else
 492 #define MSR_HVB (0ULL)
 493 #define msr_hv  (0)
 494 #endif
 495 #endif
 496
 497 /* DSISR */
 498 #define DSISR_NOPTE              0x40000000
 499 /* Not permitted by access authority of encoded access authority */
 500 #define DSISR_PROTFAULT          0x08000000
 501 #define DSISR_ISSTORE            0x02000000
 502 /* Not permitted by virtual page class key protection */
 503 #define DSISR_AMR                0x00200000
 504 /* Unsupported Radix Tree Configuration */
 505 #define DSISR_R_BADCONFIG        0x00080000
 506
 507 /* SRR1 error code fields */
 508
 509 #define SRR1_NOPTE               DSISR_NOPTE
 510 /* Not permitted due to no-execute or guard bit set */
 511 #define SRR1_NOEXEC_GUARD        0x10000000
 512 #define SRR1_PROTFAULT           DSISR_PROTFAULT
 513 #define SRR1_IAMR                DSISR_AMR
 514
 515 /* Facility Status and Control (FSCR) bits */
 516 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 517 #define FSCR_TAR        (63 - 55) /* Target Address Register */
 518 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 519 #define FSCR_IC_MASK    (0xFFULL)
 520 #define FSCR_IC_POS     (63 - 7)
 521 #define FSCR_IC_DSCR_SPR3   2
 522 #define FSCR_IC_PMU         3
 523 #define FSCR_IC_BHRB        4
 524 #define FSCR_IC_TM          5
 525 #define FSCR_IC_EBB         7
 526 #define FSCR_IC_TAR         8
 527
 528 /* Exception state register bits definition                                  */
 529 #define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
 530 #define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
 531 #define ESR_PTR   PPC_BIT(38) /* Trap                                   */
 532 #define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
 533 #define ESR_ST    PPC_BIT(40) /* Store Operation                        */
 534 #define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
 535 #define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
 536 #define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
 537 #define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
 538 #define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
 539 #define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
 540 #define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
 541 #define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
 542 #define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
 543 #define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
 544 #define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
 545
 546 /* Transaction EXception And Summary Register bits                           */
 547 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 548 #define TEXASR_DISALLOWED                        (63 - 8)
 549 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 550 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 551 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 552 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 553 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 554 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 555 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 556 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 557 #define TEXASR_ABORT                             (63 - 31)
 558 #define TEXASR_SUSPENDED                         (63 - 32)
 559 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
 560 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
 561 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 562 #define TEXASR_TFIAR_EXACT                       (63 - 37)
 563 #define TEXASR_ROT                               (63 - 38)
 564 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 565
 566 enum {
 567     POWERPC_FLAG_NONE     = 0x00000000,
 568     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 569     POWERPC_FLAG_SPE      = 0x00000001,
 570     POWERPC_FLAG_VRE      = 0x00000002,
 571     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 572     POWERPC_FLAG_TGPR     = 0x00000004,
 573     POWERPC_FLAG_CE       = 0x00000008,
 574     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 575     POWERPC_FLAG_SE       = 0x00000010,
 576     POWERPC_FLAG_DWE      = 0x00000020,
 577     POWERPC_FLAG_UBLE     = 0x00000040,
 578     /* Flag for MSR bit 9 signification (BE/DE)                              */
 579     POWERPC_FLAG_BE       = 0x00000080,
 580     POWERPC_FLAG_DE       = 0x00000100,
 581     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 582     POWERPC_FLAG_PX       = 0x00000200,
 583     POWERPC_FLAG_PMM      = 0x00000400,
 584     /* Flag for special features                                             */
 585     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 586     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 587     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 588     /* Has CFAR                                                              */
 589     POWERPC_FLAG_CFAR     = 0x00040000,
 590     /* Has VSX                                                               */
 591     POWERPC_FLAG_VSX      = 0x00080000,
 592     /* Has Transaction Memory (ISA 2.07)                                     */
 593     POWERPC_FLAG_TM       = 0x00100000,
 594 };
 595
 596 /*****************************************************************************/
 597 /* Floating point status and control register                                */
 598 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 599 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 600 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 601 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 602 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 603 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 604 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 605 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 606 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 607 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 608 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 609 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 610 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 611 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 612 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 613 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 614 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 615 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 616 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 617 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 618 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 619 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 620 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 621 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 622 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 623 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 624 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 625 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 626 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 627 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 628 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 629 #define FPSCR_RN1    1
 630 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 631 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 632 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 633 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 634 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 635 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 636 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 637 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 638 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 639 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 640 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 641 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 642 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 643 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 644 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 645 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 646 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 647 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 648 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 649 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 650 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 651 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 652 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 653 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 654 /* Invalid operation exception summary */
 655 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 656                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 657                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 658                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 659                                   (1 << FPSCR_VXCVI)))
 660 /* exception summary */
 661 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 662 /* enabled exception summary */
 663 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 664                    0x1F)
 665
 666 #define FP_FX           (1ull << FPSCR_FX)
 667 #define FP_FEX          (1ull << FPSCR_FEX)
 668 #define FP_VX           (1ull << FPSCR_VX)
 669 #define FP_OX           (1ull << FPSCR_OX)
 670 #define FP_UX           (1ull << FPSCR_UX)
 671 #define FP_ZX           (1ull << FPSCR_ZX)
 672 #define FP_XX           (1ull << FPSCR_XX)
 673 #define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 674 #define FP_VXISI        (1ull << FPSCR_VXISI)
 675 #define FP_VXIDI        (1ull << FPSCR_VXIDI)
 676 #define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 677 #define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 678 #define FP_VXVC         (1ull << FPSCR_VXVC)
 679 #define FP_FR           (1ull << FSPCR_FR)
 680 #define FP_FI           (1ull << FPSCR_FI)
 681 #define FP_C            (1ull << FPSCR_C)
 682 #define FP_FL           (1ull << FPSCR_FL)
 683 #define FP_FG           (1ull << FPSCR_FG)
 684 #define FP_FE           (1ull << FPSCR_FE)
 685 #define FP_FU           (1ull << FPSCR_FU)
 686 #define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 687 #define FP_FPRF         (FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
 688 #define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 689 #define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 690 #define FP_VXCVI        (1ull << FPSCR_VXCVI)
 691 #define FP_VE           (1ull << FPSCR_VE)
 692 #define FP_OE           (1ull << FPSCR_OE)
 693 #define FP_UE           (1ull << FPSCR_UE)
 694 #define FP_ZE           (1ull << FPSCR_ZE)
 695 #define FP_XE           (1ull << FPSCR_XE)
 696 #define FP_NI           (1ull << FPSCR_NI)
 697 #define FP_RN1          (1ull << FPSCR_RN1)
 698 #define FP_RN           (1ull << FPSCR_RN)
 699
 700 /* the exception bits which can be cleared by mcrfs - includes FX */
 701 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 702                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 703                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 704                           FP_VXSQRT | FP_VXCVI)
 705
 706 /*****************************************************************************/
 707 /* Vector status and control register */
 708 #define VSCR_NJ         16 /* Vector non-java */
 709 #define VSCR_SAT        0 /* Vector saturation */
 710
 711 /*****************************************************************************/
 712 /* BookE e500 MMU registers */
 713
 714 #define MAS0_NV_SHIFT      0
 715 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 716
 717 #define MAS0_WQ_SHIFT      12
 718 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 719 /* Write TLB entry regardless of reservation */
 720 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 721 /* Write TLB entry only already in use */
 722 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 723 /* Clear TLB entry */
 724 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 725
 726 #define MAS0_HES_SHIFT     14
 727 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
 728
 729 #define MAS0_ESEL_SHIFT    16
 730 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 731
 732 #define MAS0_TLBSEL_SHIFT  28
 733 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 734 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 735 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 736 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 737 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 738
 739 #define MAS0_ATSEL_SHIFT   31
 740 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 741 #define MAS0_ATSEL_TLB     0
 742 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 743
 744 #define MAS1_TSIZE_SHIFT   7
 745 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 746
 747 #define MAS1_TS_SHIFT      12
 748 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
 749
 750 #define MAS1_IND_SHIFT     13
 751 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
 752
 753 #define MAS1_TID_SHIFT     16
 754 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 755
 756 #define MAS1_IPROT_SHIFT   30
 757 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 758
 759 #define MAS1_VALID_SHIFT   31
 760 #define MAS1_VALID         0x80000000
 761
 762 #define MAS2_EPN_SHIFT     12
 763 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 764
 765 #define MAS2_ACM_SHIFT     6
 766 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 767
 768 #define MAS2_VLE_SHIFT     5
 769 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 770
 771 #define MAS2_W_SHIFT       4
 772 #define MAS2_W             (1 << MAS2_W_SHIFT)
 773
 774 #define MAS2_I_SHIFT       3
 775 #define MAS2_I             (1 << MAS2_I_SHIFT)
 776
 777 #define MAS2_M_SHIFT       2
 778 #define MAS2_M             (1 << MAS2_M_SHIFT)
 779
 780 #define MAS2_G_SHIFT       1
 781 #define MAS2_G             (1 << MAS2_G_SHIFT)
 782
 783 #define MAS2_E_SHIFT       0
 784 #define MAS2_E             (1 << MAS2_E_SHIFT)
 785
 786 #define MAS3_RPN_SHIFT     12
 787 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 788
 789 #define MAS3_U0                 0x00000200
 790 #define MAS3_U1                 0x00000100
 791 #define MAS3_U2                 0x00000080
 792 #define MAS3_U3                 0x00000040
 793 #define MAS3_UX                 0x00000020
 794 #define MAS3_SX                 0x00000010
 795 #define MAS3_UW                 0x00000008
 796 #define MAS3_SW                 0x00000004
 797 #define MAS3_UR                 0x00000002
 798 #define MAS3_SR                 0x00000001
 799 #define MAS3_SPSIZE_SHIFT       1
 800 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 801
 802 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 803 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 804 #define MAS4_TIDSELD_MASK       0x00030000
 805 #define MAS4_TIDSELD_PID0       0x00000000
 806 #define MAS4_TIDSELD_PID1       0x00010000
 807 #define MAS4_TIDSELD_PID2       0x00020000
 808 #define MAS4_TIDSELD_PIDZ       0x00030000
 809 #define MAS4_INDD               0x00008000      /* Default IND */
 810 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 811 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 812 #define MAS4_ACMD               0x00000040
 813 #define MAS4_VLED               0x00000020
 814 #define MAS4_WD                 0x00000010
 815 #define MAS4_ID                 0x00000008
 816 #define MAS4_MD                 0x00000004
 817 #define MAS4_GD                 0x00000002
 818 #define MAS4_ED                 0x00000001
 819 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 820 #define MAS4_WIMGED_SHIFT       0
 821
 822 #define MAS5_SGS                0x80000000
 823 #define MAS5_SLPID_MASK         0x00000fff
 824
 825 #define MAS6_SPID0              0x3fff0000
 826 #define MAS6_SPID1              0x00007ffe
 827 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 828 #define MAS6_SAS                0x00000001
 829 #define MAS6_SPID               MAS6_SPID0
 830 #define MAS6_SIND               0x00000002      /* Indirect page */
 831 #define MAS6_SIND_SHIFT         1
 832 #define MAS6_SPID_MASK          0x3fff0000
 833 #define MAS6_SPID_SHIFT         16
 834 #define MAS6_ISIZE_MASK         0x00000f80
 835 #define MAS6_ISIZE_SHIFT        7
 836
 837 #define MAS7_RPN                0xffffffff
 838
 839 #define MAS8_TGS                0x80000000
 840 #define MAS8_VF                 0x40000000
 841 #define MAS8_TLBPID             0x00000fff
 842
 843 /* Bit definitions for MMUCFG */
 844 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 845 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 846 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 847 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 848 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 849 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 850 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 851 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 852 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 853
 854 /* Bit definitions for MMUCSR0 */
 855 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 856 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 857 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 858 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 859 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 860                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 861 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 862 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 863 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 864 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 865
 866 /* TLBnCFG encoding */
 867 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 868 #define TLBnCFG_HES             0x00002000      /* HW select supported */
 869 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 870 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 871 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 872 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 873 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
 874 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 875 #define TLBnCFG_MINSIZE_SHIFT   20
 876 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 877 #define TLBnCFG_MAXSIZE_SHIFT   16
 878 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 879 #define TLBnCFG_ASSOC_SHIFT     24
 880
 881 /* TLBnPS encoding */
 882 #define TLBnPS_4K               0x00000004
 883 #define TLBnPS_8K               0x00000008
 884 #define TLBnPS_16K              0x00000010
 885 #define TLBnPS_32K              0x00000020
 886 #define TLBnPS_64K              0x00000040
 887 #define TLBnPS_128K             0x00000080
 888 #define TLBnPS_256K             0x00000100
 889 #define TLBnPS_512K             0x00000200
 890 #define TLBnPS_1M               0x00000400
 891 #define TLBnPS_2M               0x00000800
 892 #define TLBnPS_4M               0x00001000
 893 #define TLBnPS_8M               0x00002000
 894 #define TLBnPS_16M              0x00004000
 895 #define TLBnPS_32M              0x00008000
 896 #define TLBnPS_64M              0x00010000
 897 #define TLBnPS_128M             0x00020000
 898 #define TLBnPS_256M             0x00040000
 899 #define TLBnPS_512M             0x00080000
 900 #define TLBnPS_1G               0x00100000
 901 #define TLBnPS_2G               0x00200000
 902 #define TLBnPS_4G               0x00400000
 903 #define TLBnPS_8G               0x00800000
 904 #define TLBnPS_16G              0x01000000
 905 #define TLBnPS_32G              0x02000000
 906 #define TLBnPS_64G              0x04000000
 907 #define TLBnPS_128G             0x08000000
 908 #define TLBnPS_256G             0x10000000
 909
 910 /* tlbilx action encoding */
 911 #define TLBILX_T_ALL                    0
 912 #define TLBILX_T_TID                    1
 913 #define TLBILX_T_FULLMATCH              3
 914 #define TLBILX_T_CLASS0                 4
 915 #define TLBILX_T_CLASS1                 5
 916 #define TLBILX_T_CLASS2                 6
 917 #define TLBILX_T_CLASS3                 7
 918
 919 /* BookE 2.06 helper defines */
 920
 921 #define BOOKE206_FLUSH_TLB0    (1 << 0)
 922 #define BOOKE206_FLUSH_TLB1    (1 << 1)
 923 #define BOOKE206_FLUSH_TLB2    (1 << 2)
 924 #define BOOKE206_FLUSH_TLB3    (1 << 3)
 925
 926 /* number of possible TLBs */
 927 #define BOOKE206_MAX_TLBN      4
 928
 929 #define EPID_EPID_SHIFT 0x0
 930 #define EPID_EPID 0xFF
 931 #define EPID_ELPID_SHIFT 0x10
 932 #define EPID_ELPID 0x3F0000
 933 #define EPID_EGS 0x20000000
 934 #define EPID_EGS_SHIFT 29
 935 #define EPID_EAS 0x40000000
 936 #define EPID_EAS_SHIFT 30
 937 #define EPID_EPR 0x80000000
 938 #define EPID_EPR_SHIFT 31
 939 /* We don't support EGS and ELPID */
 940 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
 941
 942 /*****************************************************************************/
 943 /* Server and Embedded Processor Control */
 944
 945 #define DBELL_TYPE_SHIFT               27
 946 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 947 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 948 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 949 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 950 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 951 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 952
 953 #define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
 954
 955 #define DBELL_BRDCAST                  PPC_BIT(37)
 956 #define DBELL_LPIDTAG_SHIFT            14
 957 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 958 #define DBELL_PIRTAG_MASK              0x3fff
 959
 960 #define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
 961
 962 #define PPC_PAGE_SIZES_MAX_SZ   8
 963
 964 struct ppc_radix_page_info {
 965     uint32_t count;
 966     uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
 967 };
 968
 969 /*****************************************************************************/
 970 /* The whole PowerPC CPU context */
 971
 972 /*
 973  * PowerPC needs eight modes for different hypervisor/supervisor/guest
 974  * + real/paged mode combinations. The other two modes are for
 975  * external PID load/store.
 976  */
 977 #define NB_MMU_MODES    10
 978 #define MMU_MODE8_SUFFIX _epl
 979 #define MMU_MODE9_SUFFIX _eps
 980 #define PPC_TLB_EPID_LOAD 8
 981 #define PPC_TLB_EPID_STORE 9
 982
 983 #define PPC_CPU_OPCODES_LEN          0x40
 984 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 985
 986 struct CPUPPCState {
 987     /*
 988      * First are the most commonly used resources during translated
 989      * code execution
 990      */
 991     /* general purpose registers */
 992     target_ulong gpr[32];
 993     /* Storage for GPR MSB, used by the SPE extension */
 994     target_ulong gprh[32];
 995     /* LR */
 996     target_ulong lr;
 997     /* CTR */
 998     target_ulong ctr;
 999     /* condition register */
1000     uint32_t crf[8];
1001 #if defined(TARGET_PPC64)
1002     /* CFAR */
1003     target_ulong cfar;
1004 #endif
1005     /* XER (with SO, OV, CA split out) */
1006     target_ulong xer;
1007     target_ulong so;
1008     target_ulong ov;
1009     target_ulong ca;
1010     target_ulong ov32;
1011     target_ulong ca32;
1012     /* Reservation address */
1013     target_ulong reserve_addr;
1014     /* Reservation value */
1015     target_ulong reserve_val;
1016     target_ulong reserve_val2;
1017
1018     /* Those ones are used in supervisor mode only */
1019     /* machine state register */
1020     target_ulong msr;
1021     /* temporary general purpose registers */
1022     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1023
1024     /* Floating point execution context */
1025     float_status fp_status;
1026     /* floating point status and control register */
1027     target_ulong fpscr;
1028
1029     /* Next instruction pointer */
1030     target_ulong nip;
1031
1032     /* High part of 128-bit helper return.  */
1033     uint64_t retxh;
1034
1035     /* when a memory exception occurs, the access type is stored here */
1036     int access_type;
1037
1038     CPU_COMMON
1039
1040     /* MMU context - only relevant for full system emulation */
1041 #if !defined(CONFIG_USER_ONLY)
1042 #if defined(TARGET_PPC64)
1043     /* PowerPC 64 SLB area */
1044     ppc_slb_t slb[MAX_SLB_ENTRIES];
1045     /* tcg TLB needs flush (deferred slb inval instruction typically) */
1046 #endif
1047     /* segment registers */
1048     target_ulong sr[32];
1049     /* BATs */
1050     uint32_t nb_BATs;
1051     target_ulong DBAT[2][8];
1052     target_ulong IBAT[2][8];
1053     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1054     int32_t nb_tlb;      /* Total number of TLB                              */
1055     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1056     int nb_ways;     /* Number of ways in the TLB set                        */
1057     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1058     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1059     int nb_pids;     /* Number of available PID registers                    */
1060     int tlb_type;    /* Type of TLB we're dealing with                       */
1061     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1062     /* 403 dedicated access protection registers */
1063     target_ulong pb[4];
1064     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1065     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1066     uint32_t tlb_need_flush; /* Delayed flush needed */
1067 #define TLB_NEED_LOCAL_FLUSH   0x1
1068 #define TLB_NEED_GLOBAL_FLUSH  0x2
1069 #endif
1070
1071     /* Other registers */
1072     /* Special purpose registers */
1073     target_ulong spr[1024];
1074     ppc_spr_t spr_cb[1024];
1075     /* Vector status and control register, minus VSCR_SAT.  */
1076     uint32_t vscr;
1077     /* VSX registers (including FP and AVR) */
1078     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1079     /* Non-zero if and only if VSCR_SAT should be set.  */
1080     ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1081     /* SPE registers */
1082     uint64_t spe_acc;
1083     uint32_t spe_fscr;
1084     /*
1085      * SPE and Altivec can share a status since they will never be
1086      * used simultaneously
1087      */
1088     float_status vec_status;
1089
1090     /* Internal devices resources */
1091     /* Time base and decrementer */
1092     ppc_tb_t *tb_env;
1093     /* Device control registers */
1094     ppc_dcr_t *dcr_env;
1095
1096     int dcache_line_size;
1097     int icache_line_size;
1098
1099     /* Those resources are used during exception processing */
1100     /* CPU model definition */
1101     target_ulong msr_mask;
1102     powerpc_mmu_t mmu_model;
1103     powerpc_excp_t excp_model;
1104     powerpc_input_t bus_model;
1105     int bfd_mach;
1106     uint32_t flags;
1107     uint64_t insns_flags;
1108     uint64_t insns_flags2;
1109 #if defined(TARGET_PPC64)
1110     ppc_slb_t vrma_slb;
1111     target_ulong rmls;
1112 #endif
1113
1114     int error_code;
1115     uint32_t pending_interrupts;
1116 #if !defined(CONFIG_USER_ONLY)
1117     /*
1118      * This is the IRQ controller, which is implementation dependent
1119      * and only relevant when emulating a complete machine.
1120      */
1121     uint32_t irq_input_state;
1122     void **irq_inputs;
1123     /* Exception vectors */
1124     target_ulong excp_vectors[POWERPC_EXCP_NB];
1125     target_ulong excp_prefix;
1126     target_ulong ivor_mask;
1127     target_ulong ivpr_mask;
1128     target_ulong hreset_vector;
1129     hwaddr mpic_iack;
1130     /* true when the external proxy facility mode is enabled */
1131     bool mpic_proxy;
1132     /*
1133      * set when the processor has an HV mode, thus HV priv
1134      * instructions and SPRs are diallowed if MSR:HV is 0
1135      */
1136     bool has_hv_mode;
1137
1138     /*
1139      * On P7/P8/P9, set when in PM state, we need to handle resume in
1140      * a special way (such as routing some resume causes to 0x100, ie,
1141      * sreset), so flag this here.
1142      */
1143     bool resume_as_sreset;
1144 #endif
1145
1146     /* Those resources are used only during code translation */
1147     /* opcode handlers */
1148     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1149
1150     /* Those resources are used only in QEMU core */
1151     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1152     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1153     int immu_idx;         /* precomputed MMU index to speed up insn access */
1154     int dmmu_idx;         /* precomputed MMU index to speed up data accesses */
1155
1156     /* Power management */
1157     int (*check_pow)(CPUPPCState *env);
1158
1159 #if !defined(CONFIG_USER_ONLY)
1160     void *load_info;    /* Holds boot loading state.  */
1161 #endif
1162
1163     /* booke timers */
1164
1165     /*
1166      * Specifies bit locations of the Time Base used to signal a fixed
1167      * timer exception on a transition from 0 to 1. (watchdog or
1168      * fixed-interval timer)
1169      *
1170      * 0 selects the least significant bit.
1171      * 63 selects the most significant bit.
1172      */
1173     uint8_t fit_period[4];
1174     uint8_t wdt_period[4];
1175
1176     /* Transactional memory state */
1177     target_ulong tm_gpr[32];
1178     ppc_avr_t tm_vsr[64];
1179     uint64_t tm_cr;
1180     uint64_t tm_lr;
1181     uint64_t tm_ctr;
1182     uint64_t tm_fpscr;
1183     uint64_t tm_amr;
1184     uint64_t tm_ppr;
1185     uint64_t tm_vrsave;
1186     uint32_t tm_vscr;
1187     uint64_t tm_dscr;
1188     uint64_t tm_tar;
1189 };
1190
1191 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1192 do {                                            \
1193     env->fit_period[0] = (a_);                  \
1194     env->fit_period[1] = (b_);                  \
1195     env->fit_period[2] = (c_);                  \
1196     env->fit_period[3] = (d_);                  \
1197  } while (0)
1198
1199 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1200 do {                                            \
1201     env->wdt_period[0] = (a_);                  \
1202     env->wdt_period[1] = (b_);                  \
1203     env->wdt_period[2] = (c_);                  \
1204     env->wdt_period[3] = (d_);                  \
1205  } while (0)
1206
1207 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1208 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1209
1210 /**
1211  * PowerPCCPU:
1212  * @env: #CPUPPCState
1213  * @vcpu_id: vCPU identifier given to KVM
1214  * @compat_pvr: Current logical PVR, zero if in "raw" mode
1215  *
1216  * A PowerPC CPU.
1217  */
1218 struct PowerPCCPU {
1219     /*< private >*/
1220     CPUState parent_obj;
1221     /*< public >*/
1222
1223     CPUPPCState env;
1224     int vcpu_id;
1225     uint32_t compat_pvr;
1226     PPCVirtualHypervisor *vhyp;
1227     void *machine_data;
1228     int32_t node_id; /* NUMA node this CPU belongs to */
1229     PPCHash64Options *hash64_opts;
1230
1231     /* Fields related to migration compatibility hacks */
1232     bool pre_2_8_migration;
1233     target_ulong mig_msr_mask;
1234     uint64_t mig_insns_flags;
1235     uint64_t mig_insns_flags2;
1236     uint32_t mig_nb_BATs;
1237     bool pre_2_10_migration;
1238     bool pre_3_0_migration;
1239     int32_t mig_slb_nr;
1240 };
1241
1242 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1243 {
1244     return container_of(env, PowerPCCPU, env);
1245 }
1246
1247 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1248
1249 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1250
1251 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1252 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1253 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1254
1255 struct PPCVirtualHypervisor {
1256     Object parent;
1257 };
1258
1259 struct PPCVirtualHypervisorClass {
1260     InterfaceClass parent;
1261     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1262     hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1263     const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1264                                          hwaddr ptex, int n);
1265     void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1266                         const ppc_hash_pte64_t *hptes,
1267                         hwaddr ptex, int n);
1268     void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1269     void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1270     void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1271     target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1272 };
1273
1274 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1275 #define PPC_VIRTUAL_HYPERVISOR(obj)                 \
1276     OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1277 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass)         \
1278     OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1279                        TYPE_PPC_VIRTUAL_HYPERVISOR)
1280 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1281     OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1282                      TYPE_PPC_VIRTUAL_HYPERVISOR)
1283
1284 void ppc_cpu_do_interrupt(CPUState *cpu);
1285 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1286 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1287 void ppc_cpu_dump_statistics(CPUState *cpu, int flags);
1288 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1289 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1290 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1291 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1292 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1293 #ifndef CONFIG_USER_ONLY
1294 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1295 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1296 #endif
1297 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1298                                int cpuid, void *opaque);
1299 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1300                                int cpuid, void *opaque);
1301 #ifndef CONFIG_USER_ONLY
1302 void ppc_cpu_do_system_reset(CPUState *cs);
1303 extern const struct VMStateDescription vmstate_ppc_cpu;
1304 #endif
1305
1306 /*****************************************************************************/
1307 void ppc_translate_init(void);
1308 /*
1309  * you can call this signal handler from your SIGBUS and SIGSEGV
1310  * signal handlers to inform the virtual CPU of exceptions. non zero
1311  * is returned if the signal was handled by the virtual CPU.
1312  */
1313 int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
1314 #if defined(CONFIG_USER_ONLY)
1315 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
1316                              int mmu_idx);
1317 #endif
1318
1319 #if !defined(CONFIG_USER_ONLY)
1320 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1321 void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
1322 #endif /* !defined(CONFIG_USER_ONLY) */
1323 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1324
1325 void ppc_cpu_list(void);
1326
1327 /* Time-base and decrementer management */
1328 #ifndef NO_CPU_IO_DEFS
1329 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1330 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1331 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1332 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1333 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1334 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1335 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1336 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1337 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1338 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1339 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1340 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1341 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1342 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1343 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1344 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
1345 #if !defined(CONFIG_USER_ONLY)
1346 void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1347 void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1348 target_ulong load_40x_pit(CPUPPCState *env);
1349 void store_40x_pit(CPUPPCState *env, target_ulong val);
1350 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1351 void store_40x_sler(CPUPPCState *env, uint32_t val);
1352 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1353 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1354 void ppc_tlb_invalidate_all(CPUPPCState *env);
1355 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1356 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1357 #endif
1358 #endif
1359
1360 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1361
1362 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1363 {
1364     uint64_t gprv;
1365
1366     gprv = env->gpr[gprn];
1367     if (env->flags & POWERPC_FLAG_SPE) {
1368         /*
1369          * If the CPU implements the SPE extension, we have to get the
1370          * high bits of the GPR from the gprh storage area
1371          */
1372         gprv &= 0xFFFFFFFFULL;
1373         gprv |= (uint64_t)env->gprh[gprn] << 32;
1374     }
1375
1376     return gprv;
1377 }
1378
1379 /* Device control registers */
1380 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1381 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1382
1383 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1384 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1385 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1386
1387 #define cpu_signal_handler cpu_ppc_signal_handler
1388 #define cpu_list ppc_cpu_list
1389
1390 /* MMU modes definitions */
1391 #define MMU_USER_IDX 0
1392 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1393 {
1394     return ifetch ? env->immu_idx : env->dmmu_idx;
1395 }
1396
1397 /* Compatibility modes */
1398 #if defined(TARGET_PPC64)
1399 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1400                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1401 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1402                            uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1403
1404 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1405
1406 #if !defined(CONFIG_USER_ONLY)
1407 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1408 #endif
1409 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1410 void ppc_compat_add_property(Object *obj, const char *name,
1411                              uint32_t *compat_pvr, const char *basedesc,
1412                              Error **errp);
1413 #endif /* defined(TARGET_PPC64) */
1414
1415 #include "exec/cpu-all.h"
1416
1417 /*****************************************************************************/
1418 /* CRF definitions */
1419 #define CRF_LT_BIT    3
1420 #define CRF_GT_BIT    2
1421 #define CRF_EQ_BIT    1
1422 #define CRF_SO_BIT    0
1423 #define CRF_LT        (1 << CRF_LT_BIT)
1424 #define CRF_GT        (1 << CRF_GT_BIT)
1425 #define CRF_EQ        (1 << CRF_EQ_BIT)
1426 #define CRF_SO        (1 << CRF_SO_BIT)
1427 /* For SPE extensions */
1428 #define CRF_CH        (1 << CRF_LT_BIT)
1429 #define CRF_CL        (1 << CRF_GT_BIT)
1430 #define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1431 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1432
1433 /* XER definitions */
1434 #define XER_SO  31
1435 #define XER_OV  30
1436 #define XER_CA  29
1437 #define XER_OV32  19
1438 #define XER_CA32  18
1439 #define XER_CMP  8
1440 #define XER_BC   0
1441 #define xer_so  (env->so)
1442 #define xer_ov  (env->ov)
1443 #define xer_ca  (env->ca)
1444 #define xer_ov32  (env->ov)
1445 #define xer_ca32  (env->ca)
1446 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1447 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1448
1449 /* SPR definitions */
1450 #define SPR_MQ                (0x000)
1451 #define SPR_XER               (0x001)
1452 #define SPR_601_VRTCU         (0x004)
1453 #define SPR_601_VRTCL         (0x005)
1454 #define SPR_601_UDECR         (0x006)
1455 #define SPR_LR                (0x008)
1456 #define SPR_CTR               (0x009)
1457 #define SPR_UAMR              (0x00D)
1458 #define SPR_DSCR              (0x011)
1459 #define SPR_DSISR             (0x012)
1460 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1461 #define SPR_601_RTCU          (0x014)
1462 #define SPR_601_RTCL          (0x015)
1463 #define SPR_DECR              (0x016)
1464 #define SPR_SDR1              (0x019)
1465 #define SPR_SRR0              (0x01A)
1466 #define SPR_SRR1              (0x01B)
1467 #define SPR_CFAR              (0x01C)
1468 #define SPR_AMR               (0x01D)
1469 #define SPR_ACOP              (0x01F)
1470 #define SPR_BOOKE_PID         (0x030)
1471 #define SPR_BOOKS_PID         (0x030)
1472 #define SPR_BOOKE_DECAR       (0x036)
1473 #define SPR_BOOKE_CSRR0       (0x03A)
1474 #define SPR_BOOKE_CSRR1       (0x03B)
1475 #define SPR_BOOKE_DEAR        (0x03D)
1476 #define SPR_IAMR              (0x03D)
1477 #define SPR_BOOKE_ESR         (0x03E)
1478 #define SPR_BOOKE_IVPR        (0x03F)
1479 #define SPR_MPC_EIE           (0x050)
1480 #define SPR_MPC_EID           (0x051)
1481 #define SPR_MPC_NRI           (0x052)
1482 #define SPR_TFHAR             (0x080)
1483 #define SPR_TFIAR             (0x081)
1484 #define SPR_TEXASR            (0x082)
1485 #define SPR_TEXASRU           (0x083)
1486 #define SPR_UCTRL             (0x088)
1487 #define SPR_TIDR              (0x090)
1488 #define SPR_MPC_CMPA          (0x090)
1489 #define SPR_MPC_CMPB          (0x091)
1490 #define SPR_MPC_CMPC          (0x092)
1491 #define SPR_MPC_CMPD          (0x093)
1492 #define SPR_MPC_ECR           (0x094)
1493 #define SPR_MPC_DER           (0x095)
1494 #define SPR_MPC_COUNTA        (0x096)
1495 #define SPR_MPC_COUNTB        (0x097)
1496 #define SPR_CTRL              (0x098)
1497 #define SPR_MPC_CMPE          (0x098)
1498 #define SPR_MPC_CMPF          (0x099)
1499 #define SPR_FSCR              (0x099)
1500 #define SPR_MPC_CMPG          (0x09A)
1501 #define SPR_MPC_CMPH          (0x09B)
1502 #define SPR_MPC_LCTRL1        (0x09C)
1503 #define SPR_MPC_LCTRL2        (0x09D)
1504 #define SPR_UAMOR             (0x09D)
1505 #define SPR_MPC_ICTRL         (0x09E)
1506 #define SPR_MPC_BAR           (0x09F)
1507 #define SPR_PSPB              (0x09F)
1508 #define SPR_DAWR              (0x0B4)
1509 #define SPR_RPR               (0x0BA)
1510 #define SPR_CIABR             (0x0BB)
1511 #define SPR_DAWRX             (0x0BC)
1512 #define SPR_HFSCR             (0x0BE)
1513 #define SPR_VRSAVE            (0x100)
1514 #define SPR_USPRG0            (0x100)
1515 #define SPR_USPRG1            (0x101)
1516 #define SPR_USPRG2            (0x102)
1517 #define SPR_USPRG3            (0x103)
1518 #define SPR_USPRG4            (0x104)
1519 #define SPR_USPRG5            (0x105)
1520 #define SPR_USPRG6            (0x106)
1521 #define SPR_USPRG7            (0x107)
1522 #define SPR_VTBL              (0x10C)
1523 #define SPR_VTBU              (0x10D)
1524 #define SPR_SPRG0             (0x110)
1525 #define SPR_SPRG1             (0x111)
1526 #define SPR_SPRG2             (0x112)
1527 #define SPR_SPRG3             (0x113)
1528 #define SPR_SPRG4             (0x114)
1529 #define SPR_SCOMC             (0x114)
1530 #define SPR_SPRG5             (0x115)
1531 #define SPR_SCOMD             (0x115)
1532 #define SPR_SPRG6             (0x116)
1533 #define SPR_SPRG7             (0x117)
1534 #define SPR_ASR               (0x118)
1535 #define SPR_EAR               (0x11A)
1536 #define SPR_TBL               (0x11C)
1537 #define SPR_TBU               (0x11D)
1538 #define SPR_TBU40             (0x11E)
1539 #define SPR_SVR               (0x11E)
1540 #define SPR_BOOKE_PIR         (0x11E)
1541 #define SPR_PVR               (0x11F)
1542 #define SPR_HSPRG0            (0x130)
1543 #define SPR_BOOKE_DBSR        (0x130)
1544 #define SPR_HSPRG1            (0x131)
1545 #define SPR_HDSISR            (0x132)
1546 #define SPR_HDAR              (0x133)
1547 #define SPR_BOOKE_EPCR        (0x133)
1548 #define SPR_SPURR             (0x134)
1549 #define SPR_BOOKE_DBCR0       (0x134)
1550 #define SPR_IBCR              (0x135)
1551 #define SPR_PURR              (0x135)
1552 #define SPR_BOOKE_DBCR1       (0x135)
1553 #define SPR_DBCR              (0x136)
1554 #define SPR_HDEC              (0x136)
1555 #define SPR_BOOKE_DBCR2       (0x136)
1556 #define SPR_HIOR              (0x137)
1557 #define SPR_MBAR              (0x137)
1558 #define SPR_RMOR              (0x138)
1559 #define SPR_BOOKE_IAC1        (0x138)
1560 #define SPR_HRMOR             (0x139)
1561 #define SPR_BOOKE_IAC2        (0x139)
1562 #define SPR_HSRR0             (0x13A)
1563 #define SPR_BOOKE_IAC3        (0x13A)
1564 #define SPR_HSRR1             (0x13B)
1565 #define SPR_BOOKE_IAC4        (0x13B)
1566 #define SPR_BOOKE_DAC1        (0x13C)
1567 #define SPR_MMCRH             (0x13C)
1568 #define SPR_DABR2             (0x13D)
1569 #define SPR_BOOKE_DAC2        (0x13D)
1570 #define SPR_TFMR              (0x13D)
1571 #define SPR_BOOKE_DVC1        (0x13E)
1572 #define SPR_LPCR              (0x13E)
1573 #define SPR_BOOKE_DVC2        (0x13F)
1574 #define SPR_LPIDR             (0x13F)
1575 #define SPR_BOOKE_TSR         (0x150)
1576 #define SPR_HMER              (0x150)
1577 #define SPR_HMEER             (0x151)
1578 #define SPR_PCR               (0x152)
1579 #define SPR_BOOKE_LPIDR       (0x152)
1580 #define SPR_BOOKE_TCR         (0x154)
1581 #define SPR_BOOKE_TLB0PS      (0x158)
1582 #define SPR_BOOKE_TLB1PS      (0x159)
1583 #define SPR_BOOKE_TLB2PS      (0x15A)
1584 #define SPR_BOOKE_TLB3PS      (0x15B)
1585 #define SPR_AMOR              (0x15D)
1586 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1587 #define SPR_BOOKE_IVOR0       (0x190)
1588 #define SPR_BOOKE_IVOR1       (0x191)
1589 #define SPR_BOOKE_IVOR2       (0x192)
1590 #define SPR_BOOKE_IVOR3       (0x193)
1591 #define SPR_BOOKE_IVOR4       (0x194)
1592 #define SPR_BOOKE_IVOR5       (0x195)
1593 #define SPR_BOOKE_IVOR6       (0x196)
1594 #define SPR_BOOKE_IVOR7       (0x197)
1595 #define SPR_BOOKE_IVOR8       (0x198)
1596 #define SPR_BOOKE_IVOR9       (0x199)
1597 #define SPR_BOOKE_IVOR10      (0x19A)
1598 #define SPR_BOOKE_IVOR11      (0x19B)
1599 #define SPR_BOOKE_IVOR12      (0x19C)
1600 #define SPR_BOOKE_IVOR13      (0x19D)
1601 #define SPR_BOOKE_IVOR14      (0x19E)
1602 #define SPR_BOOKE_IVOR15      (0x19F)
1603 #define SPR_BOOKE_IVOR38      (0x1B0)
1604 #define SPR_BOOKE_IVOR39      (0x1B1)
1605 #define SPR_BOOKE_IVOR40      (0x1B2)
1606 #define SPR_BOOKE_IVOR41      (0x1B3)
1607 #define SPR_BOOKE_IVOR42      (0x1B4)
1608 #define SPR_BOOKE_GIVOR2      (0x1B8)
1609 #define SPR_BOOKE_GIVOR3      (0x1B9)
1610 #define SPR_BOOKE_GIVOR4      (0x1BA)
1611 #define SPR_BOOKE_GIVOR8      (0x1BB)
1612 #define SPR_BOOKE_GIVOR13     (0x1BC)
1613 #define SPR_BOOKE_GIVOR14     (0x1BD)
1614 #define SPR_TIR               (0x1BE)
1615 #define SPR_PTCR              (0x1D0)
1616 #define SPR_BOOKE_SPEFSCR     (0x200)
1617 #define SPR_Exxx_BBEAR        (0x201)
1618 #define SPR_Exxx_BBTAR        (0x202)
1619 #define SPR_Exxx_L1CFG0       (0x203)
1620 #define SPR_Exxx_L1CFG1       (0x204)
1621 #define SPR_Exxx_NPIDR        (0x205)
1622 #define SPR_ATBL              (0x20E)
1623 #define SPR_ATBU              (0x20F)
1624 #define SPR_IBAT0U            (0x210)
1625 #define SPR_BOOKE_IVOR32      (0x210)
1626 #define SPR_RCPU_MI_GRA       (0x210)
1627 #define SPR_IBAT0L            (0x211)
1628 #define SPR_BOOKE_IVOR33      (0x211)
1629 #define SPR_IBAT1U            (0x212)
1630 #define SPR_BOOKE_IVOR34      (0x212)
1631 #define SPR_IBAT1L            (0x213)
1632 #define SPR_BOOKE_IVOR35      (0x213)
1633 #define SPR_IBAT2U            (0x214)
1634 #define SPR_BOOKE_IVOR36      (0x214)
1635 #define SPR_IBAT2L            (0x215)
1636 #define SPR_BOOKE_IVOR37      (0x215)
1637 #define SPR_IBAT3U            (0x216)
1638 #define SPR_IBAT3L            (0x217)
1639 #define SPR_DBAT0U            (0x218)
1640 #define SPR_RCPU_L2U_GRA      (0x218)
1641 #define SPR_DBAT0L            (0x219)
1642 #define SPR_DBAT1U            (0x21A)
1643 #define SPR_DBAT1L            (0x21B)
1644 #define SPR_DBAT2U            (0x21C)
1645 #define SPR_DBAT2L            (0x21D)
1646 #define SPR_DBAT3U            (0x21E)
1647 #define SPR_DBAT3L            (0x21F)
1648 #define SPR_IBAT4U            (0x230)
1649 #define SPR_RPCU_BBCMCR       (0x230)
1650 #define SPR_MPC_IC_CST        (0x230)
1651 #define SPR_Exxx_CTXCR        (0x230)
1652 #define SPR_IBAT4L            (0x231)
1653 #define SPR_MPC_IC_ADR        (0x231)
1654 #define SPR_Exxx_DBCR3        (0x231)
1655 #define SPR_IBAT5U            (0x232)
1656 #define SPR_MPC_IC_DAT        (0x232)
1657 #define SPR_Exxx_DBCNT        (0x232)
1658 #define SPR_IBAT5L            (0x233)
1659 #define SPR_IBAT6U            (0x234)
1660 #define SPR_IBAT6L            (0x235)
1661 #define SPR_IBAT7U            (0x236)
1662 #define SPR_IBAT7L            (0x237)
1663 #define SPR_DBAT4U            (0x238)
1664 #define SPR_RCPU_L2U_MCR      (0x238)
1665 #define SPR_MPC_DC_CST        (0x238)
1666 #define SPR_Exxx_ALTCTXCR     (0x238)
1667 #define SPR_DBAT4L            (0x239)
1668 #define SPR_MPC_DC_ADR        (0x239)
1669 #define SPR_DBAT5U            (0x23A)
1670 #define SPR_BOOKE_MCSRR0      (0x23A)
1671 #define SPR_MPC_DC_DAT        (0x23A)
1672 #define SPR_DBAT5L            (0x23B)
1673 #define SPR_BOOKE_MCSRR1      (0x23B)
1674 #define SPR_DBAT6U            (0x23C)
1675 #define SPR_BOOKE_MCSR        (0x23C)
1676 #define SPR_DBAT6L            (0x23D)
1677 #define SPR_Exxx_MCAR         (0x23D)
1678 #define SPR_DBAT7U            (0x23E)
1679 #define SPR_BOOKE_DSRR0       (0x23E)
1680 #define SPR_DBAT7L            (0x23F)
1681 #define SPR_BOOKE_DSRR1       (0x23F)
1682 #define SPR_BOOKE_SPRG8       (0x25C)
1683 #define SPR_BOOKE_SPRG9       (0x25D)
1684 #define SPR_BOOKE_MAS0        (0x270)
1685 #define SPR_BOOKE_MAS1        (0x271)
1686 #define SPR_BOOKE_MAS2        (0x272)
1687 #define SPR_BOOKE_MAS3        (0x273)
1688 #define SPR_BOOKE_MAS4        (0x274)
1689 #define SPR_BOOKE_MAS5        (0x275)
1690 #define SPR_BOOKE_MAS6        (0x276)
1691 #define SPR_BOOKE_PID1        (0x279)
1692 #define SPR_BOOKE_PID2        (0x27A)
1693 #define SPR_MPC_DPDR          (0x280)
1694 #define SPR_MPC_IMMR          (0x288)
1695 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1696 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1697 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1698 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1699 #define SPR_BOOKE_EPR         (0x2BE)
1700 #define SPR_PERF0             (0x300)
1701 #define SPR_RCPU_MI_RBA0      (0x300)
1702 #define SPR_MPC_MI_CTR        (0x300)
1703 #define SPR_POWER_USIER       (0x300)
1704 #define SPR_PERF1             (0x301)
1705 #define SPR_RCPU_MI_RBA1      (0x301)
1706 #define SPR_POWER_UMMCR2      (0x301)
1707 #define SPR_PERF2             (0x302)
1708 #define SPR_RCPU_MI_RBA2      (0x302)
1709 #define SPR_MPC_MI_AP         (0x302)
1710 #define SPR_POWER_UMMCRA      (0x302)
1711 #define SPR_PERF3             (0x303)
1712 #define SPR_RCPU_MI_RBA3      (0x303)
1713 #define SPR_MPC_MI_EPN        (0x303)
1714 #define SPR_POWER_UPMC1       (0x303)
1715 #define SPR_PERF4             (0x304)
1716 #define SPR_POWER_UPMC2       (0x304)
1717 #define SPR_PERF5             (0x305)
1718 #define SPR_MPC_MI_TWC        (0x305)
1719 #define SPR_POWER_UPMC3       (0x305)
1720 #define SPR_PERF6             (0x306)
1721 #define SPR_MPC_MI_RPN        (0x306)
1722 #define SPR_POWER_UPMC4       (0x306)
1723 #define SPR_PERF7             (0x307)
1724 #define SPR_POWER_UPMC5       (0x307)
1725 #define SPR_PERF8             (0x308)
1726 #define SPR_RCPU_L2U_RBA0     (0x308)
1727 #define SPR_MPC_MD_CTR        (0x308)
1728 #define SPR_POWER_UPMC6       (0x308)
1729 #define SPR_PERF9             (0x309)
1730 #define SPR_RCPU_L2U_RBA1     (0x309)
1731 #define SPR_MPC_MD_CASID      (0x309)
1732 #define SPR_970_UPMC7         (0X309)
1733 #define SPR_PERFA             (0x30A)
1734 #define SPR_RCPU_L2U_RBA2     (0x30A)
1735 #define SPR_MPC_MD_AP         (0x30A)
1736 #define SPR_970_UPMC8         (0X30A)
1737 #define SPR_PERFB             (0x30B)
1738 #define SPR_RCPU_L2U_RBA3     (0x30B)
1739 #define SPR_MPC_MD_EPN        (0x30B)
1740 #define SPR_POWER_UMMCR0      (0X30B)
1741 #define SPR_PERFC             (0x30C)
1742 #define SPR_MPC_MD_TWB        (0x30C)
1743 #define SPR_POWER_USIAR       (0X30C)
1744 #define SPR_PERFD             (0x30D)
1745 #define SPR_MPC_MD_TWC        (0x30D)
1746 #define SPR_POWER_USDAR       (0X30D)
1747 #define SPR_PERFE             (0x30E)
1748 #define SPR_MPC_MD_RPN        (0x30E)
1749 #define SPR_POWER_UMMCR1      (0X30E)
1750 #define SPR_PERFF             (0x30F)
1751 #define SPR_MPC_MD_TW         (0x30F)
1752 #define SPR_UPERF0            (0x310)
1753 #define SPR_POWER_SIER        (0x310)
1754 #define SPR_UPERF1            (0x311)
1755 #define SPR_POWER_MMCR2       (0x311)
1756 #define SPR_UPERF2            (0x312)
1757 #define SPR_POWER_MMCRA       (0X312)
1758 #define SPR_UPERF3            (0x313)
1759 #define SPR_POWER_PMC1        (0X313)
1760 #define SPR_UPERF4            (0x314)
1761 #define SPR_POWER_PMC2        (0X314)
1762 #define SPR_UPERF5            (0x315)
1763 #define SPR_POWER_PMC3        (0X315)
1764 #define SPR_UPERF6            (0x316)
1765 #define SPR_POWER_PMC4        (0X316)
1766 #define SPR_UPERF7            (0x317)
1767 #define SPR_POWER_PMC5        (0X317)
1768 #define SPR_UPERF8            (0x318)
1769 #define SPR_POWER_PMC6        (0X318)
1770 #define SPR_UPERF9            (0x319)
1771 #define SPR_970_PMC7          (0X319)
1772 #define SPR_UPERFA            (0x31A)
1773 #define SPR_970_PMC8          (0X31A)
1774 #define SPR_UPERFB            (0x31B)
1775 #define SPR_POWER_MMCR0       (0X31B)
1776 #define SPR_UPERFC            (0x31C)
1777 #define SPR_POWER_SIAR        (0X31C)
1778 #define SPR_UPERFD            (0x31D)
1779 #define SPR_POWER_SDAR        (0X31D)
1780 #define SPR_UPERFE            (0x31E)
1781 #define SPR_POWER_MMCR1       (0X31E)
1782 #define SPR_UPERFF            (0x31F)
1783 #define SPR_RCPU_MI_RA0       (0x320)
1784 #define SPR_MPC_MI_DBCAM      (0x320)
1785 #define SPR_BESCRS            (0x320)
1786 #define SPR_RCPU_MI_RA1       (0x321)
1787 #define SPR_MPC_MI_DBRAM0     (0x321)
1788 #define SPR_BESCRSU           (0x321)
1789 #define SPR_RCPU_MI_RA2       (0x322)
1790 #define SPR_MPC_MI_DBRAM1     (0x322)
1791 #define SPR_BESCRR            (0x322)
1792 #define SPR_RCPU_MI_RA3       (0x323)
1793 #define SPR_BESCRRU           (0x323)
1794 #define SPR_EBBHR             (0x324)
1795 #define SPR_EBBRR             (0x325)
1796 #define SPR_BESCR             (0x326)
1797 #define SPR_RCPU_L2U_RA0      (0x328)
1798 #define SPR_MPC_MD_DBCAM      (0x328)
1799 #define SPR_RCPU_L2U_RA1      (0x329)
1800 #define SPR_MPC_MD_DBRAM0     (0x329)
1801 #define SPR_RCPU_L2U_RA2      (0x32A)
1802 #define SPR_MPC_MD_DBRAM1     (0x32A)
1803 #define SPR_RCPU_L2U_RA3      (0x32B)
1804 #define SPR_TAR               (0x32F)
1805 #define SPR_IC                (0x350)
1806 #define SPR_VTB               (0x351)
1807 #define SPR_MMCRC             (0x353)
1808 #define SPR_PSSCR             (0x357)
1809 #define SPR_440_INV0          (0x370)
1810 #define SPR_440_INV1          (0x371)
1811 #define SPR_440_INV2          (0x372)
1812 #define SPR_440_INV3          (0x373)
1813 #define SPR_440_ITV0          (0x374)
1814 #define SPR_440_ITV1          (0x375)
1815 #define SPR_440_ITV2          (0x376)
1816 #define SPR_440_ITV3          (0x377)
1817 #define SPR_440_CCR1          (0x378)
1818 #define SPR_TACR              (0x378)
1819 #define SPR_TCSCR             (0x379)
1820 #define SPR_CSIGR             (0x37a)
1821 #define SPR_DCRIPR            (0x37B)
1822 #define SPR_POWER_SPMC1       (0x37C)
1823 #define SPR_POWER_SPMC2       (0x37D)
1824 #define SPR_POWER_MMCRS       (0x37E)
1825 #define SPR_WORT              (0x37F)
1826 #define SPR_PPR               (0x380)
1827 #define SPR_750_GQR0          (0x390)
1828 #define SPR_440_DNV0          (0x390)
1829 #define SPR_750_GQR1          (0x391)
1830 #define SPR_440_DNV1          (0x391)
1831 #define SPR_750_GQR2          (0x392)
1832 #define SPR_440_DNV2          (0x392)
1833 #define SPR_750_GQR3          (0x393)
1834 #define SPR_440_DNV3          (0x393)
1835 #define SPR_750_GQR4          (0x394)
1836 #define SPR_440_DTV0          (0x394)
1837 #define SPR_750_GQR5          (0x395)
1838 #define SPR_440_DTV1          (0x395)
1839 #define SPR_750_GQR6          (0x396)
1840 #define SPR_440_DTV2          (0x396)
1841 #define SPR_750_GQR7          (0x397)
1842 #define SPR_440_DTV3          (0x397)
1843 #define SPR_750_THRM4         (0x398)
1844 #define SPR_750CL_HID2        (0x398)
1845 #define SPR_440_DVLIM         (0x398)
1846 #define SPR_750_WPAR          (0x399)
1847 #define SPR_440_IVLIM         (0x399)
1848 #define SPR_TSCR              (0x399)
1849 #define SPR_750_DMAU          (0x39A)
1850 #define SPR_750_DMAL          (0x39B)
1851 #define SPR_440_RSTCFG        (0x39B)
1852 #define SPR_BOOKE_DCDBTRL     (0x39C)
1853 #define SPR_BOOKE_DCDBTRH     (0x39D)
1854 #define SPR_BOOKE_ICDBTRL     (0x39E)
1855 #define SPR_BOOKE_ICDBTRH     (0x39F)
1856 #define SPR_74XX_UMMCR2       (0x3A0)
1857 #define SPR_7XX_UPMC5         (0x3A1)
1858 #define SPR_7XX_UPMC6         (0x3A2)
1859 #define SPR_UBAMR             (0x3A7)
1860 #define SPR_7XX_UMMCR0        (0x3A8)
1861 #define SPR_7XX_UPMC1         (0x3A9)
1862 #define SPR_7XX_UPMC2         (0x3AA)
1863 #define SPR_7XX_USIAR         (0x3AB)
1864 #define SPR_7XX_UMMCR1        (0x3AC)
1865 #define SPR_7XX_UPMC3         (0x3AD)
1866 #define SPR_7XX_UPMC4         (0x3AE)
1867 #define SPR_USDA              (0x3AF)
1868 #define SPR_40x_ZPR           (0x3B0)
1869 #define SPR_BOOKE_MAS7        (0x3B0)
1870 #define SPR_74XX_MMCR2        (0x3B0)
1871 #define SPR_7XX_PMC5          (0x3B1)
1872 #define SPR_40x_PID           (0x3B1)
1873 #define SPR_7XX_PMC6          (0x3B2)
1874 #define SPR_440_MMUCR         (0x3B2)
1875 #define SPR_4xx_CCR0          (0x3B3)
1876 #define SPR_BOOKE_EPLC        (0x3B3)
1877 #define SPR_405_IAC3          (0x3B4)
1878 #define SPR_BOOKE_EPSC        (0x3B4)
1879 #define SPR_405_IAC4          (0x3B5)
1880 #define SPR_405_DVC1          (0x3B6)
1881 #define SPR_405_DVC2          (0x3B7)
1882 #define SPR_BAMR              (0x3B7)
1883 #define SPR_7XX_MMCR0         (0x3B8)
1884 #define SPR_7XX_PMC1          (0x3B9)
1885 #define SPR_40x_SGR           (0x3B9)
1886 #define SPR_7XX_PMC2          (0x3BA)
1887 #define SPR_40x_DCWR          (0x3BA)
1888 #define SPR_7XX_SIAR          (0x3BB)
1889 #define SPR_405_SLER          (0x3BB)
1890 #define SPR_7XX_MMCR1         (0x3BC)
1891 #define SPR_405_SU0R          (0x3BC)
1892 #define SPR_401_SKR           (0x3BC)
1893 #define SPR_7XX_PMC3          (0x3BD)
1894 #define SPR_405_DBCR1         (0x3BD)
1895 #define SPR_7XX_PMC4          (0x3BE)
1896 #define SPR_SDA               (0x3BF)
1897 #define SPR_403_VTBL          (0x3CC)
1898 #define SPR_403_VTBU          (0x3CD)
1899 #define SPR_DMISS             (0x3D0)
1900 #define SPR_DCMP              (0x3D1)
1901 #define SPR_HASH1             (0x3D2)
1902 #define SPR_HASH2             (0x3D3)
1903 #define SPR_BOOKE_ICDBDR      (0x3D3)
1904 #define SPR_TLBMISS           (0x3D4)
1905 #define SPR_IMISS             (0x3D4)
1906 #define SPR_40x_ESR           (0x3D4)
1907 #define SPR_PTEHI             (0x3D5)
1908 #define SPR_ICMP              (0x3D5)
1909 #define SPR_40x_DEAR          (0x3D5)
1910 #define SPR_PTELO             (0x3D6)
1911 #define SPR_RPA               (0x3D6)
1912 #define SPR_40x_EVPR          (0x3D6)
1913 #define SPR_L3PM              (0x3D7)
1914 #define SPR_403_CDBCR         (0x3D7)
1915 #define SPR_L3ITCR0           (0x3D8)
1916 #define SPR_TCR               (0x3D8)
1917 #define SPR_40x_TSR           (0x3D8)
1918 #define SPR_IBR               (0x3DA)
1919 #define SPR_40x_TCR           (0x3DA)
1920 #define SPR_ESASRR            (0x3DB)
1921 #define SPR_40x_PIT           (0x3DB)
1922 #define SPR_403_TBL           (0x3DC)
1923 #define SPR_403_TBU           (0x3DD)
1924 #define SPR_SEBR              (0x3DE)
1925 #define SPR_40x_SRR2          (0x3DE)
1926 #define SPR_SER               (0x3DF)
1927 #define SPR_40x_SRR3          (0x3DF)
1928 #define SPR_L3OHCR            (0x3E8)
1929 #define SPR_L3ITCR1           (0x3E9)
1930 #define SPR_L3ITCR2           (0x3EA)
1931 #define SPR_L3ITCR3           (0x3EB)
1932 #define SPR_HID0              (0x3F0)
1933 #define SPR_40x_DBSR          (0x3F0)
1934 #define SPR_HID1              (0x3F1)
1935 #define SPR_IABR              (0x3F2)
1936 #define SPR_40x_DBCR0         (0x3F2)
1937 #define SPR_601_HID2          (0x3F2)
1938 #define SPR_Exxx_L1CSR0       (0x3F2)
1939 #define SPR_ICTRL             (0x3F3)
1940 #define SPR_HID2              (0x3F3)
1941 #define SPR_750CL_HID4        (0x3F3)
1942 #define SPR_Exxx_L1CSR1       (0x3F3)
1943 #define SPR_440_DBDR          (0x3F3)
1944 #define SPR_LDSTDB            (0x3F4)
1945 #define SPR_750_TDCL          (0x3F4)
1946 #define SPR_40x_IAC1          (0x3F4)
1947 #define SPR_MMUCSR0           (0x3F4)
1948 #define SPR_970_HID4          (0x3F4)
1949 #define SPR_DABR              (0x3F5)
1950 #define DABR_MASK (~(target_ulong)0x7)
1951 #define SPR_Exxx_BUCSR        (0x3F5)
1952 #define SPR_40x_IAC2          (0x3F5)
1953 #define SPR_601_HID5          (0x3F5)
1954 #define SPR_40x_DAC1          (0x3F6)
1955 #define SPR_MSSCR0            (0x3F6)
1956 #define SPR_970_HID5          (0x3F6)
1957 #define SPR_MSSSR0            (0x3F7)
1958 #define SPR_MSSCR1            (0x3F7)
1959 #define SPR_DABRX             (0x3F7)
1960 #define SPR_40x_DAC2          (0x3F7)
1961 #define SPR_MMUCFG            (0x3F7)
1962 #define SPR_LDSTCR            (0x3F8)
1963 #define SPR_L2PMCR            (0x3F8)
1964 #define SPR_750FX_HID2        (0x3F8)
1965 #define SPR_Exxx_L1FINV0      (0x3F8)
1966 #define SPR_L2CR              (0x3F9)
1967 #define SPR_L3CR              (0x3FA)
1968 #define SPR_750_TDCH          (0x3FA)
1969 #define SPR_IABR2             (0x3FA)
1970 #define SPR_40x_DCCR          (0x3FA)
1971 #define SPR_ICTC              (0x3FB)
1972 #define SPR_40x_ICCR          (0x3FB)
1973 #define SPR_THRM1             (0x3FC)
1974 #define SPR_403_PBL1          (0x3FC)
1975 #define SPR_SP                (0x3FD)
1976 #define SPR_THRM2             (0x3FD)
1977 #define SPR_403_PBU1          (0x3FD)
1978 #define SPR_604_HID13         (0x3FD)
1979 #define SPR_LT                (0x3FE)
1980 #define SPR_THRM3             (0x3FE)
1981 #define SPR_RCPU_FPECR        (0x3FE)
1982 #define SPR_403_PBL2          (0x3FE)
1983 #define SPR_PIR               (0x3FF)
1984 #define SPR_403_PBU2          (0x3FF)
1985 #define SPR_601_HID15         (0x3FF)
1986 #define SPR_604_HID15         (0x3FF)
1987 #define SPR_E500_SVR          (0x3FF)
1988
1989 /* Disable MAS Interrupt Updates for Hypervisor */
1990 #define EPCR_DMIUH            (1 << 22)
1991 /* Disable Guest TLB Management Instructions */
1992 #define EPCR_DGTMI            (1 << 23)
1993 /* Guest Interrupt Computation Mode */
1994 #define EPCR_GICM             (1 << 24)
1995 /* Interrupt Computation Mode */
1996 #define EPCR_ICM              (1 << 25)
1997 /* Disable Embedded Hypervisor Debug */
1998 #define EPCR_DUVD             (1 << 26)
1999 /* Instruction Storage Interrupt Directed to Guest State */
2000 #define EPCR_ISIGS            (1 << 27)
2001 /* Data Storage Interrupt Directed to Guest State */
2002 #define EPCR_DSIGS            (1 << 28)
2003 /* Instruction TLB Error Interrupt Directed to Guest State */
2004 #define EPCR_ITLBGS           (1 << 29)
2005 /* Data TLB Error Interrupt Directed to Guest State */
2006 #define EPCR_DTLBGS           (1 << 30)
2007 /* External Input Interrupt Directed to Guest State */
2008 #define EPCR_EXTGS            (1 << 31)
2009
2010 #define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
2011 #define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
2012 #define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
2013 #define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */
2014 #define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
2015
2016 #define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
2017 #define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
2018 #define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
2019 #define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
2020 #define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
2021
2022 /* HID0 bits */
2023 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
2024 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
2025 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
2026 #define HID0_HILE           PPC_BIT(19) /* POWER8 */
2027 #define HID0_POWER9_HILE    PPC_BIT(4)
2028
2029 /*****************************************************************************/
2030 /* PowerPC Instructions types definitions                                    */
2031 enum {
2032     PPC_NONE           = 0x0000000000000000ULL,
2033     /* PowerPC base instructions set                                         */
2034     PPC_INSNS_BASE     = 0x0000000000000001ULL,
2035     /*   integer operations instructions                                     */
2036 #define PPC_INTEGER PPC_INSNS_BASE
2037     /*   flow control instructions                                           */
2038 #define PPC_FLOW    PPC_INSNS_BASE
2039     /*   virtual memory instructions                                         */
2040 #define PPC_MEM     PPC_INSNS_BASE
2041     /*   ld/st with reservation instructions                                 */
2042 #define PPC_RES     PPC_INSNS_BASE
2043     /*   spr/msr access instructions                                         */
2044 #define PPC_MISC    PPC_INSNS_BASE
2045     /* Deprecated instruction sets                                           */
2046     /*   Original POWER instruction set                                      */
2047     PPC_POWER          = 0x0000000000000002ULL,
2048     /*   POWER2 instruction set extension                                    */
2049     PPC_POWER2         = 0x0000000000000004ULL,
2050     /*   Power RTC support                                                   */
2051     PPC_POWER_RTC      = 0x0000000000000008ULL,
2052     /*   Power-to-PowerPC bridge (601)                                       */
2053     PPC_POWER_BR       = 0x0000000000000010ULL,
2054     /* 64 bits PowerPC instruction set                                       */
2055     PPC_64B            = 0x0000000000000020ULL,
2056     /*   New 64 bits extensions (PowerPC 2.0x)                               */
2057     PPC_64BX           = 0x0000000000000040ULL,
2058     /*   64 bits hypervisor extensions                                       */
2059     PPC_64H            = 0x0000000000000080ULL,
2060     /*   New wait instruction (PowerPC 2.0x)                                 */
2061     PPC_WAIT           = 0x0000000000000100ULL,
2062     /*   Time base mftb instruction                                          */
2063     PPC_MFTB           = 0x0000000000000200ULL,
2064
2065     /* Fixed-point unit extensions                                           */
2066     /*   PowerPC 602 specific                                                */
2067     PPC_602_SPEC       = 0x0000000000000400ULL,
2068     /*   isel instruction                                                    */
2069     PPC_ISEL           = 0x0000000000000800ULL,
2070     /*   popcntb instruction                                                 */
2071     PPC_POPCNTB        = 0x0000000000001000ULL,
2072     /*   string load / store                                                 */
2073     PPC_STRING         = 0x0000000000002000ULL,
2074     /*   real mode cache inhibited load / store                              */
2075     PPC_CILDST         = 0x0000000000004000ULL,
2076
2077     /* Floating-point unit extensions                                        */
2078     /*   Optional floating point instructions                                */
2079     PPC_FLOAT          = 0x0000000000010000ULL,
2080     /* New floating-point extensions (PowerPC 2.0x)                          */
2081     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2082     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2083     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2084     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2085     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2086     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2087     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2088
2089     /* Vector/SIMD extensions                                                */
2090     /*   Altivec support                                                     */
2091     PPC_ALTIVEC        = 0x0000000001000000ULL,
2092     /*   PowerPC 2.03 SPE extension                                          */
2093     PPC_SPE            = 0x0000000002000000ULL,
2094     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2095     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2096     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2097     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2098
2099     /* Optional memory control instructions                                  */
2100     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2101     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2102     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2103     /*   sync instruction                                                    */
2104     PPC_MEM_SYNC       = 0x0000000080000000ULL,
2105     /*   eieio instruction                                                   */
2106     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2107
2108     /* Cache control instructions                                            */
2109     PPC_CACHE          = 0x0000000200000000ULL,
2110     /*   icbi instruction                                                    */
2111     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2112     /*   dcbz instruction                                                    */
2113     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2114     /*   dcba instruction                                                    */
2115     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2116     /*   Freescale cache locking instructions                                */
2117     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2118
2119     /* MMU related extensions                                                */
2120     /*   external control instructions                                       */
2121     PPC_EXTERN         = 0x0000010000000000ULL,
2122     /*   segment register access instructions                                */
2123     PPC_SEGMENT        = 0x0000020000000000ULL,
2124     /*   PowerPC 6xx TLB management instructions                             */
2125     PPC_6xx_TLB        = 0x0000040000000000ULL,
2126     /* PowerPC 74xx TLB management instructions                              */
2127     PPC_74xx_TLB       = 0x0000080000000000ULL,
2128     /*   PowerPC 40x TLB management instructions                             */
2129     PPC_40x_TLB        = 0x0000100000000000ULL,
2130     /*   segment register access instructions for PowerPC 64 "bridge"        */
2131     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2132     /*   SLB management                                                      */
2133     PPC_SLBI           = 0x0000400000000000ULL,
2134
2135     /* Embedded PowerPC dedicated instructions                               */
2136     PPC_WRTEE          = 0x0001000000000000ULL,
2137     /* PowerPC 40x exception model                                           */
2138     PPC_40x_EXCP       = 0x0002000000000000ULL,
2139     /* PowerPC 405 Mac instructions                                          */
2140     PPC_405_MAC        = 0x0004000000000000ULL,
2141     /* PowerPC 440 specific instructions                                     */
2142     PPC_440_SPEC       = 0x0008000000000000ULL,
2143     /* BookE (embedded) PowerPC specification                                */
2144     PPC_BOOKE          = 0x0010000000000000ULL,
2145     /* mfapidi instruction                                                   */
2146     PPC_MFAPIDI        = 0x0020000000000000ULL,
2147     /* tlbiva instruction                                                    */
2148     PPC_TLBIVA         = 0x0040000000000000ULL,
2149     /* tlbivax instruction                                                   */
2150     PPC_TLBIVAX        = 0x0080000000000000ULL,
2151     /* PowerPC 4xx dedicated instructions                                    */
2152     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2153     /* PowerPC 40x ibct instructions                                         */
2154     PPC_40x_ICBT       = 0x0200000000000000ULL,
2155     /* rfmci is not implemented in all BookE PowerPC                         */
2156     PPC_RFMCI          = 0x0400000000000000ULL,
2157     /* rfdi instruction                                                      */
2158     PPC_RFDI           = 0x0800000000000000ULL,
2159     /* DCR accesses                                                          */
2160     PPC_DCR            = 0x1000000000000000ULL,
2161     /* DCR extended accesse                                                  */
2162     PPC_DCRX           = 0x2000000000000000ULL,
2163     /* user-mode DCR access, implemented in PowerPC 460                      */
2164     PPC_DCRUX          = 0x4000000000000000ULL,
2165     /* popcntw and popcntd instructions                                      */
2166     PPC_POPCNTWD       = 0x8000000000000000ULL,
2167
2168 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2169                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2170                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2171                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2172                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2173                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2174                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2175                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2176                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2177                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2178                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2179                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2180                         | PPC_CACHE | PPC_CACHE_ICBI \
2181                         | PPC_CACHE_DCBZ \
2182                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2183                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2184                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2185                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2186                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2187                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2188                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2189                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2190                         | PPC_POPCNTWD | PPC_CILDST)
2191
2192     /* extended type values */
2193
2194     /* BookE 2.06 PowerPC specification                                      */
2195     PPC2_BOOKE206      = 0x0000000000000001ULL,
2196     /* VSX (extensions to Altivec / VMX)                                     */
2197     PPC2_VSX           = 0x0000000000000002ULL,
2198     /* Decimal Floating Point (DFP)                                          */
2199     PPC2_DFP           = 0x0000000000000004ULL,
2200     /* Embedded.Processor Control                                            */
2201     PPC2_PRCNTL        = 0x0000000000000008ULL,
2202     /* Byte-reversed, indexed, double-word load and store                    */
2203     PPC2_DBRX          = 0x0000000000000010ULL,
2204     /* Book I 2.05 PowerPC specification                                     */
2205     PPC2_ISA205        = 0x0000000000000020ULL,
2206     /* VSX additions in ISA 2.07                                             */
2207     PPC2_VSX207        = 0x0000000000000040ULL,
2208     /* ISA 2.06B bpermd                                                      */
2209     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2210     /* ISA 2.06B divide extended variants                                    */
2211     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2212     /* ISA 2.06B larx/stcx. instructions                                     */
2213     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2214     /* ISA 2.06B floating point integer conversion                           */
2215     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2216     /* ISA 2.06B floating point test instructions                            */
2217     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2218     /* ISA 2.07 bctar instruction                                            */
2219     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2220     /* ISA 2.07 load/store quadword                                          */
2221     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2222     /* ISA 2.07 Altivec                                                      */
2223     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2224     /* PowerISA 2.07 Book3s specification                                    */
2225     PPC2_ISA207S       = 0x0000000000008000ULL,
2226     /* Double precision floating point conversion for signed integer 64      */
2227     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2228     /* Transactional Memory (ISA 2.07, Book II)                              */
2229     PPC2_TM            = 0x0000000000020000ULL,
2230     /* Server PM instructgions (ISA 2.06, Book III)                          */
2231     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2232     /* POWER ISA 3.0                                                         */
2233     PPC2_ISA300        = 0x0000000000080000ULL,
2234
2235 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2236                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2237                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2238                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2239                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2240                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2241                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2242                         PPC2_ISA300)
2243 };
2244
2245 /*****************************************************************************/
2246 /*
2247  * Memory access type :
2248  * may be needed for precise access rights control and precise exceptions.
2249  */
2250 enum {
2251     /* 1 bit to define user level / supervisor access */
2252     ACCESS_USER  = 0x00,
2253     ACCESS_SUPER = 0x01,
2254     /* Type of instruction that generated the access */
2255     ACCESS_CODE  = 0x10, /* Code fetch access                */
2256     ACCESS_INT   = 0x20, /* Integer load/store access        */
2257     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2258     ACCESS_RES   = 0x40, /* load/store with reservation      */
2259     ACCESS_EXT   = 0x50, /* external access                  */
2260     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2261 };
2262
2263 /*
2264  * Hardware interrupt sources:
2265  *   all those exception can be raised simulteaneously
2266  */
2267 /* Input pins definitions */
2268 enum {
2269     /* 6xx bus input pins */
2270     PPC6xx_INPUT_HRESET     = 0,
2271     PPC6xx_INPUT_SRESET     = 1,
2272     PPC6xx_INPUT_CKSTP_IN   = 2,
2273     PPC6xx_INPUT_MCP        = 3,
2274     PPC6xx_INPUT_SMI        = 4,
2275     PPC6xx_INPUT_INT        = 5,
2276     PPC6xx_INPUT_TBEN       = 6,
2277     PPC6xx_INPUT_WAKEUP     = 7,
2278     PPC6xx_INPUT_NB,
2279 };
2280
2281 enum {
2282     /* Embedded PowerPC input pins */
2283     PPCBookE_INPUT_HRESET     = 0,
2284     PPCBookE_INPUT_SRESET     = 1,
2285     PPCBookE_INPUT_CKSTP_IN   = 2,
2286     PPCBookE_INPUT_MCP        = 3,
2287     PPCBookE_INPUT_SMI        = 4,
2288     PPCBookE_INPUT_INT        = 5,
2289     PPCBookE_INPUT_CINT       = 6,
2290     PPCBookE_INPUT_NB,
2291 };
2292
2293 enum {
2294     /* PowerPC E500 input pins */
2295     PPCE500_INPUT_RESET_CORE = 0,
2296     PPCE500_INPUT_MCK        = 1,
2297     PPCE500_INPUT_CINT       = 3,
2298     PPCE500_INPUT_INT        = 4,
2299     PPCE500_INPUT_DEBUG      = 6,
2300     PPCE500_INPUT_NB,
2301 };
2302
2303 enum {
2304     /* PowerPC 40x input pins */
2305     PPC40x_INPUT_RESET_CORE = 0,
2306     PPC40x_INPUT_RESET_CHIP = 1,
2307     PPC40x_INPUT_RESET_SYS  = 2,
2308     PPC40x_INPUT_CINT       = 3,
2309     PPC40x_INPUT_INT        = 4,
2310     PPC40x_INPUT_HALT       = 5,
2311     PPC40x_INPUT_DEBUG      = 6,
2312     PPC40x_INPUT_NB,
2313 };
2314
2315 enum {
2316     /* RCPU input pins */
2317     PPCRCPU_INPUT_PORESET   = 0,
2318     PPCRCPU_INPUT_HRESET    = 1,
2319     PPCRCPU_INPUT_SRESET    = 2,
2320     PPCRCPU_INPUT_IRQ0      = 3,
2321     PPCRCPU_INPUT_IRQ1      = 4,
2322     PPCRCPU_INPUT_IRQ2      = 5,
2323     PPCRCPU_INPUT_IRQ3      = 6,
2324     PPCRCPU_INPUT_IRQ4      = 7,
2325     PPCRCPU_INPUT_IRQ5      = 8,
2326     PPCRCPU_INPUT_IRQ6      = 9,
2327     PPCRCPU_INPUT_IRQ7      = 10,
2328     PPCRCPU_INPUT_NB,
2329 };
2330
2331 #if defined(TARGET_PPC64)
2332 enum {
2333     /* PowerPC 970 input pins */
2334     PPC970_INPUT_HRESET     = 0,
2335     PPC970_INPUT_SRESET     = 1,
2336     PPC970_INPUT_CKSTP      = 2,
2337     PPC970_INPUT_TBEN       = 3,
2338     PPC970_INPUT_MCP        = 4,
2339     PPC970_INPUT_INT        = 5,
2340     PPC970_INPUT_THINT      = 6,
2341     PPC970_INPUT_NB,
2342 };
2343
2344 enum {
2345     /* POWER7 input pins */
2346     POWER7_INPUT_INT        = 0,
2347     /*
2348      * POWER7 probably has other inputs, but we don't care about them
2349      * for any existing machine.  We can wire these up when we need
2350      * them
2351      */
2352     POWER7_INPUT_NB,
2353 };
2354
2355 enum {
2356     /* POWER9 input pins */
2357     POWER9_INPUT_INT        = 0,
2358     POWER9_INPUT_HINT       = 1,
2359     POWER9_INPUT_NB,
2360 };
2361 #endif
2362
2363 /* Hardware exceptions definitions */
2364 enum {
2365     /* External hardware exception sources */
2366     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2367     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2368     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2369     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2370     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2371     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2372     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2373     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2374     /* Internal hardware exception sources */
2375     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2376     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2377     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2378     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2379     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2380     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2381     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2382     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2383     PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
2384     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2385     PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
2386 };
2387
2388 /* Processor Compatibility mask (PCR) */
2389 enum {
2390     PCR_COMPAT_2_05     = PPC_BIT(62),
2391     PCR_COMPAT_2_06     = PPC_BIT(61),
2392     PCR_COMPAT_2_07     = PPC_BIT(60),
2393     PCR_COMPAT_3_00     = PPC_BIT(59),
2394     PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2395     PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2396     PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2397 };
2398
2399 /* HMER/HMEER */
2400 enum {
2401     HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2402     HMER_PROC_RECV_DONE         = PPC_BIT(2),
2403     HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2404     HMER_TFAC_ERROR             = PPC_BIT(4),
2405     HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2406     HMER_XSCOM_FAIL             = PPC_BIT(8),
2407     HMER_XSCOM_DONE             = PPC_BIT(9),
2408     HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2409     HMER_WARN_RISE              = PPC_BIT(14),
2410     HMER_WARN_FALL              = PPC_BIT(15),
2411     HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2412     HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2413     HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2414     HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2415 };
2416
2417 /* Alternate Interrupt Location (AIL) */
2418 enum {
2419     AIL_NONE                = 0,
2420     AIL_RESERVED            = 1,
2421     AIL_0001_8000           = 2,
2422     AIL_C000_0000_0000_4000 = 3,
2423 };
2424
2425 /*****************************************************************************/
2426
2427 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2428 target_ulong cpu_read_xer(CPUPPCState *env);
2429 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2430
2431 /*
2432  * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2433  * have PPC_SEGMENT_64B.
2434  */
2435 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2436
2437 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2438                                         target_ulong *cs_base, uint32_t *flags)
2439 {
2440     *pc = env->nip;
2441     *cs_base = 0;
2442     *flags = env->hflags;
2443 }
2444
2445 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2446 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2447                                       uintptr_t raddr);
2448 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2449                                        uint32_t error_code);
2450 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2451                                           uint32_t error_code, uintptr_t raddr);
2452
2453 #if !defined(CONFIG_USER_ONLY)
2454 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2455 {
2456     uintptr_t tlbml = (uintptr_t)tlbm;
2457     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2458
2459     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2460 }
2461
2462 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2463 {
2464     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2465     int r = tlbncfg & TLBnCFG_N_ENTRY;
2466     return r;
2467 }
2468
2469 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2470 {
2471     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2472     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2473     return r;
2474 }
2475
2476 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2477 {
2478     int id = booke206_tlbm_id(env, tlbm);
2479     int end = 0;
2480     int i;
2481
2482     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2483         end += booke206_tlb_size(env, i);
2484         if (id < end) {
2485             return i;
2486         }
2487     }
2488
2489     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2490     return 0;
2491 }
2492
2493 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2494 {
2495     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2496     int tlbid = booke206_tlbm_id(env, tlb);
2497     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2498 }
2499
2500 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2501                                               target_ulong ea, int way)
2502 {
2503     int r;
2504     uint32_t ways = booke206_tlb_ways(env, tlbn);
2505     int ways_bits = ctz32(ways);
2506     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2507     int i;
2508
2509     way &= ways - 1;
2510     ea >>= MAS2_EPN_SHIFT;
2511     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2512     r = (ea << ways_bits) | way;
2513
2514     if (r >= booke206_tlb_size(env, tlbn)) {
2515         return NULL;
2516     }
2517
2518     /* bump up to tlbn index */
2519     for (i = 0; i < tlbn; i++) {
2520         r += booke206_tlb_size(env, i);
2521     }
2522
2523     return &env->tlb.tlbm[r];
2524 }
2525
2526 /* returns bitmap of supported page sizes for a given TLB */
2527 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2528 {
2529     uint32_t ret = 0;
2530
2531     if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2532         /* MAV2 */
2533         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2534     } else {
2535         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2536         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2537         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2538         int i;
2539         for (i = min; i <= max; i++) {
2540             ret |= (1 << (i << 1));
2541         }
2542     }
2543
2544     return ret;
2545 }
2546
2547 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2548                                             ppcmas_tlb_t *tlb)
2549 {
2550     uint8_t i;
2551     int32_t tsize = -1;
2552
2553     for (i = 0; i < 32; i++) {
2554         if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2555             if (tsize == -1) {
2556                 tsize = i;
2557             } else {
2558                 return;
2559             }
2560         }
2561     }
2562
2563     /* TLBnPS unimplemented? Odd.. */
2564     assert(tsize != -1);
2565     tlb->mas1 &= ~MAS1_TSIZE_MASK;
2566     tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2567 }
2568
2569 #endif
2570
2571 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2572 {
2573     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2574         return msr & (1ULL << MSR_CM);
2575     }
2576
2577     return msr & (1ULL << MSR_SF);
2578 }
2579
2580 /**
2581  * Check whether register rx is in the range between start and
2582  * start + nregs (as needed by the LSWX and LSWI instructions)
2583  */
2584 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2585 {
2586     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2587            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2588 }
2589
2590 /* Accessors for FP, VMX and VSX registers */
2591 #if defined(HOST_WORDS_BIGENDIAN)
2592 #define VsrB(i) u8[i]
2593 #define VsrSB(i) s8[i]
2594 #define VsrH(i) u16[i]
2595 #define VsrSH(i) s16[i]
2596 #define VsrW(i) u32[i]
2597 #define VsrSW(i) s32[i]
2598 #define VsrD(i) u64[i]
2599 #define VsrSD(i) s64[i]
2600 #else
2601 #define VsrB(i) u8[15 - (i)]
2602 #define VsrSB(i) s8[15 - (i)]
2603 #define VsrH(i) u16[7 - (i)]
2604 #define VsrSH(i) s16[7 - (i)]
2605 #define VsrW(i) u32[3 - (i)]
2606 #define VsrSW(i) s32[3 - (i)]
2607 #define VsrD(i) u64[1 - (i)]
2608 #define VsrSD(i) s64[1 - (i)]
2609 #endif
2610
2611 static inline int vsr64_offset(int i, bool high)
2612 {
2613     return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2614 }
2615
2616 static inline int vsr_full_offset(int i)
2617 {
2618     return offsetof(CPUPPCState, vsr[i].u64[0]);
2619 }
2620
2621 static inline int fpr_offset(int i)
2622 {
2623     return vsr64_offset(i, true);
2624 }
2625
2626 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2627 {
2628     return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2629 }
2630
2631 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2632 {
2633     return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2634 }
2635
2636 static inline long avr64_offset(int i, bool high)
2637 {
2638     return vsr64_offset(i + 32, high);
2639 }
2640
2641 static inline int avr_full_offset(int i)
2642 {
2643     return vsr_full_offset(i + 32);
2644 }
2645
2646 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2647 {
2648     return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2649 }
2650
2651 void dump_mmu(CPUPPCState *env);
2652
2653 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2654 #endif /* PPC_CPU_H */