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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
[mirror_qemu.git] / target / ppc / cpu_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_common.h"
48 #include "power8-pmu.h"
49
50 /* #define PPC_DEBUG_SPR */
51 /* #define USE_APPLE_GDB */
52
53 static inline void vscr_init(CPUPPCState *env, uint32_t val)
54 {
55 /* Altivec always uses round-to-nearest */
56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
57 ppc_store_vscr(env, val);
58 }
59
60 static void register_745_sprs(CPUPPCState *env)
61 {
62 /* SGPRs */
63 spr_register(env, SPR_SPRG4, "SPRG4",
64 SPR_NOACCESS, SPR_NOACCESS,
65 &spr_read_generic, &spr_write_generic,
66 0x00000000);
67 spr_register(env, SPR_SPRG5, "SPRG5",
68 SPR_NOACCESS, SPR_NOACCESS,
69 &spr_read_generic, &spr_write_generic,
70 0x00000000);
71 spr_register(env, SPR_SPRG6, "SPRG6",
72 SPR_NOACCESS, SPR_NOACCESS,
73 &spr_read_generic, &spr_write_generic,
74 0x00000000);
75 spr_register(env, SPR_SPRG7, "SPRG7",
76 SPR_NOACCESS, SPR_NOACCESS,
77 &spr_read_generic, &spr_write_generic,
78 0x00000000);
79
80 /* Hardware implementation registers */
81 spr_register(env, SPR_HID0, "HID0",
82 SPR_NOACCESS, SPR_NOACCESS,
83 &spr_read_generic, &spr_write_generic,
84 0x00000000);
85
86 spr_register(env, SPR_HID1, "HID1",
87 SPR_NOACCESS, SPR_NOACCESS,
88 &spr_read_generic, &spr_write_generic,
89 0x00000000);
90
91 spr_register(env, SPR_HID2, "HID2",
92 SPR_NOACCESS, SPR_NOACCESS,
93 &spr_read_generic, &spr_write_generic,
94 0x00000000);
95 }
96
97 static void register_755_sprs(CPUPPCState *env)
98 {
99 /* L2 cache control */
100 spr_register(env, SPR_L2CR, "L2CR",
101 SPR_NOACCESS, SPR_NOACCESS,
102 &spr_read_generic, spr_access_nop,
103 0x00000000);
104
105 spr_register(env, SPR_L2PMCR, "L2PMCR",
106 SPR_NOACCESS, SPR_NOACCESS,
107 &spr_read_generic, &spr_write_generic,
108 0x00000000);
109 }
110
111 /* SPR common to all 7xx PowerPC implementations */
112 static void register_7xx_sprs(CPUPPCState *env)
113 {
114 /* Breakpoints */
115 spr_register_kvm(env, SPR_DABR, "DABR",
116 SPR_NOACCESS, SPR_NOACCESS,
117 &spr_read_generic, &spr_write_generic,
118 KVM_REG_PPC_DABR, 0x00000000);
119
120 spr_register(env, SPR_IABR, "IABR",
121 SPR_NOACCESS, SPR_NOACCESS,
122 &spr_read_generic, &spr_write_generic,
123 0x00000000);
124 /* Cache management */
125 spr_register(env, SPR_ICTC, "ICTC",
126 SPR_NOACCESS, SPR_NOACCESS,
127 &spr_read_generic, &spr_write_generic,
128 0x00000000);
129 /* Performance monitors */
130 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
131 SPR_NOACCESS, SPR_NOACCESS,
132 &spr_read_generic, &spr_write_generic,
133 0x00000000);
134
135 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
136 SPR_NOACCESS, SPR_NOACCESS,
137 &spr_read_generic, &spr_write_generic,
138 0x00000000);
139
140 spr_register(env, SPR_7XX_PMC1, "PMC1",
141 SPR_NOACCESS, SPR_NOACCESS,
142 &spr_read_generic, &spr_write_generic,
143 0x00000000);
144
145 spr_register(env, SPR_7XX_PMC2, "PMC2",
146 SPR_NOACCESS, SPR_NOACCESS,
147 &spr_read_generic, &spr_write_generic,
148 0x00000000);
149
150 spr_register(env, SPR_7XX_PMC3, "PMC3",
151 SPR_NOACCESS, SPR_NOACCESS,
152 &spr_read_generic, &spr_write_generic,
153 0x00000000);
154
155 spr_register(env, SPR_7XX_PMC4, "PMC4",
156 SPR_NOACCESS, SPR_NOACCESS,
157 &spr_read_generic, &spr_write_generic,
158 0x00000000);
159
160 spr_register(env, SPR_7XX_SIAR, "SIAR",
161 SPR_NOACCESS, SPR_NOACCESS,
162 &spr_read_generic, SPR_NOACCESS,
163 0x00000000);
164
165 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
166 &spr_read_ureg, SPR_NOACCESS,
167 &spr_read_ureg, SPR_NOACCESS,
168 0x00000000);
169
170 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
171 &spr_read_ureg, SPR_NOACCESS,
172 &spr_read_ureg, SPR_NOACCESS,
173 0x00000000);
174
175 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
176 &spr_read_ureg, SPR_NOACCESS,
177 &spr_read_ureg, SPR_NOACCESS,
178 0x00000000);
179
180 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
181 &spr_read_ureg, SPR_NOACCESS,
182 &spr_read_ureg, SPR_NOACCESS,
183 0x00000000);
184
185 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
186 &spr_read_ureg, SPR_NOACCESS,
187 &spr_read_ureg, SPR_NOACCESS,
188 0x00000000);
189
190 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
191 &spr_read_ureg, SPR_NOACCESS,
192 &spr_read_ureg, SPR_NOACCESS,
193 0x00000000);
194
195 spr_register(env, SPR_7XX_USIAR, "USIAR",
196 &spr_read_ureg, SPR_NOACCESS,
197 &spr_read_ureg, SPR_NOACCESS,
198 0x00000000);
199 /* External access control */
200 spr_register(env, SPR_EAR, "EAR",
201 SPR_NOACCESS, SPR_NOACCESS,
202 &spr_read_generic, &spr_write_generic,
203 0x00000000);
204
205 /* Hardware implementation registers */
206 spr_register(env, SPR_HID0, "HID0",
207 SPR_NOACCESS, SPR_NOACCESS,
208 &spr_read_generic, &spr_write_generic,
209 0x00000000);
210
211 spr_register(env, SPR_HID1, "HID1",
212 SPR_NOACCESS, SPR_NOACCESS,
213 &spr_read_generic, &spr_write_generic,
214 0x00000000);
215 }
216
217 #ifdef TARGET_PPC64
218 static void register_amr_sprs(CPUPPCState *env)
219 {
220 #ifndef CONFIG_USER_ONLY
221 /*
222 * Virtual Page Class Key protection
223 *
224 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
225 * userspace accessible, 29 is privileged. So we only need to set
226 * the kvm ONE_REG id on one of them, we use 29
227 */
228 spr_register(env, SPR_UAMR, "UAMR",
229 &spr_read_generic, &spr_write_amr,
230 &spr_read_generic, &spr_write_amr,
231 0);
232 spr_register_kvm_hv(env, SPR_AMR, "AMR",
233 SPR_NOACCESS, SPR_NOACCESS,
234 &spr_read_generic, &spr_write_amr,
235 &spr_read_generic, &spr_write_generic,
236 KVM_REG_PPC_AMR, 0);
237 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
238 SPR_NOACCESS, SPR_NOACCESS,
239 &spr_read_generic, &spr_write_uamor,
240 &spr_read_generic, &spr_write_generic,
241 KVM_REG_PPC_UAMOR, 0);
242 spr_register_hv(env, SPR_AMOR, "AMOR",
243 SPR_NOACCESS, SPR_NOACCESS,
244 SPR_NOACCESS, SPR_NOACCESS,
245 &spr_read_generic, &spr_write_generic,
246 0);
247 #endif /* !CONFIG_USER_ONLY */
248 }
249
250 static void register_iamr_sprs(CPUPPCState *env)
251 {
252 #ifndef CONFIG_USER_ONLY
253 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
254 SPR_NOACCESS, SPR_NOACCESS,
255 &spr_read_generic, &spr_write_iamr,
256 &spr_read_generic, &spr_write_generic,
257 KVM_REG_PPC_IAMR, 0);
258 #endif /* !CONFIG_USER_ONLY */
259 }
260 #endif /* TARGET_PPC64 */
261
262 /* SPR specific to PowerPC 604 implementation */
263 static void register_604_sprs(CPUPPCState *env)
264 {
265 /* Processor identification */
266 spr_register(env, SPR_PIR, "PIR",
267 SPR_NOACCESS, SPR_NOACCESS,
268 &spr_read_generic, &spr_write_pir,
269 0x00000000);
270 /* Breakpoints */
271 spr_register(env, SPR_IABR, "IABR",
272 SPR_NOACCESS, SPR_NOACCESS,
273 &spr_read_generic, &spr_write_generic,
274 0x00000000);
275
276 spr_register_kvm(env, SPR_DABR, "DABR",
277 SPR_NOACCESS, SPR_NOACCESS,
278 &spr_read_generic, &spr_write_generic,
279 KVM_REG_PPC_DABR, 0x00000000);
280 /* Performance counters */
281 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
282 SPR_NOACCESS, SPR_NOACCESS,
283 &spr_read_generic, &spr_write_generic,
284 0x00000000);
285
286 spr_register(env, SPR_7XX_PMC1, "PMC1",
287 SPR_NOACCESS, SPR_NOACCESS,
288 &spr_read_generic, &spr_write_generic,
289 0x00000000);
290
291 spr_register(env, SPR_7XX_PMC2, "PMC2",
292 SPR_NOACCESS, SPR_NOACCESS,
293 &spr_read_generic, &spr_write_generic,
294 0x00000000);
295
296 spr_register(env, SPR_7XX_SIAR, "SIAR",
297 SPR_NOACCESS, SPR_NOACCESS,
298 &spr_read_generic, SPR_NOACCESS,
299 0x00000000);
300
301 spr_register(env, SPR_SDA, "SDA",
302 SPR_NOACCESS, SPR_NOACCESS,
303 &spr_read_generic, SPR_NOACCESS,
304 0x00000000);
305 /* External access control */
306 spr_register(env, SPR_EAR, "EAR",
307 SPR_NOACCESS, SPR_NOACCESS,
308 &spr_read_generic, &spr_write_generic,
309 0x00000000);
310
311 /* Hardware implementation registers */
312 spr_register(env, SPR_HID0, "HID0",
313 SPR_NOACCESS, SPR_NOACCESS,
314 &spr_read_generic, &spr_write_generic,
315 0x00000000);
316 }
317
318 static void register_604e_sprs(CPUPPCState *env)
319 {
320 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
321 SPR_NOACCESS, SPR_NOACCESS,
322 &spr_read_generic, &spr_write_generic,
323 0x00000000);
324
325 spr_register(env, SPR_7XX_PMC3, "PMC3",
326 SPR_NOACCESS, SPR_NOACCESS,
327 &spr_read_generic, &spr_write_generic,
328 0x00000000);
329
330 spr_register(env, SPR_7XX_PMC4, "PMC4",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_generic, &spr_write_generic,
333 0x00000000);
334 /* Hardware implementation registers */
335 spr_register(env, SPR_HID1, "HID1",
336 SPR_NOACCESS, SPR_NOACCESS,
337 &spr_read_generic, &spr_write_generic,
338 0x00000000);
339 }
340
341 /* SPR specific to PowerPC 603 implementation */
342 static void register_603_sprs(CPUPPCState *env)
343 {
344 /* External access control */
345 spr_register(env, SPR_EAR, "EAR",
346 SPR_NOACCESS, SPR_NOACCESS,
347 &spr_read_generic, &spr_write_generic,
348 0x00000000);
349 /* Breakpoints */
350 spr_register(env, SPR_IABR, "IABR",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_generic, &spr_write_generic,
353 0x00000000);
354
355 spr_register(env, SPR_HID0, "HID0",
356 SPR_NOACCESS, SPR_NOACCESS,
357 &spr_read_generic, &spr_write_generic,
358 0x00000000);
359
360 spr_register(env, SPR_HID1, "HID1",
361 SPR_NOACCESS, SPR_NOACCESS,
362 &spr_read_generic, &spr_write_generic,
363 0x00000000);
364 }
365
366 static void register_e300_sprs(CPUPPCState *env)
367 {
368 /* hardware implementation registers */
369 spr_register(env, SPR_HID2, "HID2",
370 SPR_NOACCESS, SPR_NOACCESS,
371 &spr_read_generic, &spr_write_generic,
372 0x00000000);
373 /* Breakpoints */
374 spr_register(env, SPR_DABR, "DABR",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_generic, &spr_write_generic,
377 0x00000000);
378
379 spr_register(env, SPR_DABR2, "DABR2",
380 SPR_NOACCESS, SPR_NOACCESS,
381 &spr_read_generic, &spr_write_generic,
382 0x00000000);
383
384 spr_register(env, SPR_IABR2, "IABR2",
385 SPR_NOACCESS, SPR_NOACCESS,
386 &spr_read_generic, &spr_write_generic,
387 0x00000000);
388
389 spr_register(env, SPR_IBCR, "IBCR",
390 SPR_NOACCESS, SPR_NOACCESS,
391 &spr_read_generic, &spr_write_generic,
392 0x00000000);
393
394 spr_register(env, SPR_DBCR, "DBCR",
395 SPR_NOACCESS, SPR_NOACCESS,
396 &spr_read_generic, &spr_write_generic,
397 0x00000000);
398 }
399
400 /* SPR specific to PowerPC G2 implementation */
401 static void register_G2_sprs(CPUPPCState *env)
402 {
403 /* Memory base address */
404 /* MBAR */
405 spr_register(env, SPR_MBAR, "MBAR",
406 SPR_NOACCESS, SPR_NOACCESS,
407 &spr_read_generic, &spr_write_generic,
408 0x00000000);
409 /* Exception processing */
410 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
411 SPR_NOACCESS, SPR_NOACCESS,
412 &spr_read_generic, &spr_write_generic,
413 0x00000000);
414 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_generic, &spr_write_generic,
417 0x00000000);
418 /* Breakpoints */
419 spr_register(env, SPR_DABR, "DABR",
420 SPR_NOACCESS, SPR_NOACCESS,
421 &spr_read_generic, &spr_write_generic,
422 0x00000000);
423
424 spr_register(env, SPR_DABR2, "DABR2",
425 SPR_NOACCESS, SPR_NOACCESS,
426 &spr_read_generic, &spr_write_generic,
427 0x00000000);
428
429 spr_register(env, SPR_IABR, "IABR",
430 SPR_NOACCESS, SPR_NOACCESS,
431 &spr_read_generic, &spr_write_generic,
432 0x00000000);
433
434 spr_register(env, SPR_IABR2, "IABR2",
435 SPR_NOACCESS, SPR_NOACCESS,
436 &spr_read_generic, &spr_write_generic,
437 0x00000000);
438
439 spr_register(env, SPR_IBCR, "IBCR",
440 SPR_NOACCESS, SPR_NOACCESS,
441 &spr_read_generic, &spr_write_generic,
442 0x00000000);
443
444 spr_register(env, SPR_DBCR, "DBCR",
445 SPR_NOACCESS, SPR_NOACCESS,
446 &spr_read_generic, &spr_write_generic,
447 0x00000000);
448
449 /* External access control */
450 spr_register(env, SPR_EAR, "EAR",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, &spr_write_generic,
453 0x00000000);
454 /* Hardware implementation register */
455 spr_register(env, SPR_HID0, "HID0",
456 SPR_NOACCESS, SPR_NOACCESS,
457 &spr_read_generic, &spr_write_generic,
458 0x00000000);
459
460 spr_register(env, SPR_HID1, "HID1",
461 SPR_NOACCESS, SPR_NOACCESS,
462 &spr_read_generic, &spr_write_generic,
463 0x00000000);
464
465 spr_register(env, SPR_HID2, "HID2",
466 SPR_NOACCESS, SPR_NOACCESS,
467 &spr_read_generic, &spr_write_generic,
468 0x00000000);
469
470 /* SGPRs */
471 spr_register(env, SPR_SPRG4, "SPRG4",
472 SPR_NOACCESS, SPR_NOACCESS,
473 &spr_read_generic, &spr_write_generic,
474 0x00000000);
475 spr_register(env, SPR_SPRG5, "SPRG5",
476 SPR_NOACCESS, SPR_NOACCESS,
477 &spr_read_generic, &spr_write_generic,
478 0x00000000);
479 spr_register(env, SPR_SPRG6, "SPRG6",
480 SPR_NOACCESS, SPR_NOACCESS,
481 &spr_read_generic, &spr_write_generic,
482 0x00000000);
483 spr_register(env, SPR_SPRG7, "SPRG7",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_generic, &spr_write_generic,
486 0x00000000);
487 }
488
489 static void register_74xx_sprs(CPUPPCState *env)
490 {
491 /* Breakpoints */
492 spr_register_kvm(env, SPR_DABR, "DABR",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
495 KVM_REG_PPC_DABR, 0x00000000);
496
497 spr_register(env, SPR_IABR, "IABR",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, &spr_write_generic,
500 0x00000000);
501 /* Cache management */
502 spr_register(env, SPR_ICTC, "ICTC",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506 /* Performance monitors */
507 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_generic, &spr_write_generic,
510 0x00000000);
511
512 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516
517 spr_register(env, SPR_7XX_PMC1, "PMC1",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, &spr_write_generic,
520 0x00000000);
521
522 spr_register(env, SPR_7XX_PMC2, "PMC2",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_generic, &spr_write_generic,
525 0x00000000);
526
527 spr_register(env, SPR_7XX_PMC3, "PMC3",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_generic, &spr_write_generic,
530 0x00000000);
531
532 spr_register(env, SPR_7XX_PMC4, "PMC4",
533 SPR_NOACCESS, SPR_NOACCESS,
534 &spr_read_generic, &spr_write_generic,
535 0x00000000);
536
537 spr_register(env, SPR_7XX_SIAR, "SIAR",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_generic, SPR_NOACCESS,
540 0x00000000);
541
542 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
543 &spr_read_ureg, SPR_NOACCESS,
544 &spr_read_ureg, SPR_NOACCESS,
545 0x00000000);
546
547 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
548 &spr_read_ureg, SPR_NOACCESS,
549 &spr_read_ureg, SPR_NOACCESS,
550 0x00000000);
551
552 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
553 &spr_read_ureg, SPR_NOACCESS,
554 &spr_read_ureg, SPR_NOACCESS,
555 0x00000000);
556
557 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
558 &spr_read_ureg, SPR_NOACCESS,
559 &spr_read_ureg, SPR_NOACCESS,
560 0x00000000);
561
562 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
563 &spr_read_ureg, SPR_NOACCESS,
564 &spr_read_ureg, SPR_NOACCESS,
565 0x00000000);
566
567 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
568 &spr_read_ureg, SPR_NOACCESS,
569 &spr_read_ureg, SPR_NOACCESS,
570 0x00000000);
571
572 spr_register(env, SPR_7XX_USIAR, "USIAR",
573 &spr_read_ureg, SPR_NOACCESS,
574 &spr_read_ureg, SPR_NOACCESS,
575 0x00000000);
576 /* External access control */
577 spr_register(env, SPR_EAR, "EAR",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_generic, &spr_write_generic,
580 0x00000000);
581
582 /* Processor identification */
583 spr_register(env, SPR_PIR, "PIR",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_generic, &spr_write_pir,
586 0x00000000);
587
588 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
589 SPR_NOACCESS, SPR_NOACCESS,
590 &spr_read_generic, &spr_write_generic,
591 0x00000000);
592
593 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
594 &spr_read_ureg, SPR_NOACCESS,
595 &spr_read_ureg, SPR_NOACCESS,
596 0x00000000);
597
598 spr_register(env, SPR_BAMR, "BAMR",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_generic, &spr_write_generic,
601 0x00000000);
602
603 spr_register(env, SPR_MSSCR0, "MSSCR0",
604 SPR_NOACCESS, SPR_NOACCESS,
605 &spr_read_generic, &spr_write_generic,
606 0x00000000);
607 /* Hardware implementation registers */
608 spr_register(env, SPR_HID0, "HID0",
609 SPR_NOACCESS, SPR_NOACCESS,
610 &spr_read_generic, &spr_write_generic,
611 0x00000000);
612
613 spr_register(env, SPR_HID1, "HID1",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_generic, &spr_write_generic,
616 0x00000000);
617 /* Altivec */
618 spr_register(env, SPR_VRSAVE, "VRSAVE",
619 &spr_read_generic, &spr_write_generic,
620 &spr_read_generic, &spr_write_generic,
621 0x00000000);
622
623 spr_register(env, SPR_L2CR, "L2CR",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_generic, spr_access_nop,
626 0x00000000);
627 }
628
629 static void register_l3_ctrl(CPUPPCState *env)
630 {
631 /* L3CR */
632 spr_register(env, SPR_L3CR, "L3CR",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_generic, &spr_write_generic,
635 0x00000000);
636 /* L3ITCR0 */
637 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 /* L3PM */
642 spr_register(env, SPR_L3PM, "L3PM",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_generic, &spr_write_generic,
645 0x00000000);
646 }
647
648 /* PowerPC BookE SPR */
649 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
650 {
651 const char *ivor_names[64] = {
652 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
653 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
654 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
655 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
656 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
657 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
658 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
659 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
660 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
661 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
662 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
663 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
664 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
665 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
666 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
667 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
668 };
669 #define SPR_BOOKE_IVORxx (-1)
670 int ivor_sprn[64] = {
671 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
672 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
673 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
674 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
675 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
676 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
677 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
678 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
679 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
680 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
681 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
685 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
687 };
688 int i;
689
690 /* Interrupt processing */
691 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, &spr_write_generic,
694 0x00000000);
695 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, &spr_write_generic,
698 0x00000000);
699 /* Debug */
700 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_generic,
703 0x00000000);
704
705 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709
710 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, &spr_write_generic,
713 0x00000000);
714
715 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, &spr_write_generic,
718 0x00000000);
719
720 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_40x_dbcr0,
723 0x00000000);
724
725 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729
730 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_generic,
733 0x00000000);
734 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 0x00000000);
742
743 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_generic, &spr_write_clear,
746 0x00000000);
747 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_generic, &spr_write_generic,
750 0x00000000);
751 spr_register(env, SPR_BOOKE_ESR, "ESR",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 0x00000000);
755 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_excp_prefix,
758 0x00000000);
759 /* Exception vectors */
760 for (i = 0; i < 64; i++) {
761 if (ivor_mask & (1ULL << i)) {
762 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
763 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
764 exit(1);
765 }
766 spr_register(env, ivor_sprn[i], ivor_names[i],
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_generic, &spr_write_excp_vector,
769 0x00000000);
770 }
771 }
772 spr_register(env, SPR_BOOKE_PID, "PID",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_generic, &spr_write_booke_pid,
775 0x00000000);
776 spr_register(env, SPR_BOOKE_TCR, "TCR",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_generic, &spr_write_booke_tcr,
779 0x00000000);
780 spr_register(env, SPR_BOOKE_TSR, "TSR",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_booke_tsr,
783 0x00000000);
784 /* Timer */
785 spr_register(env, SPR_DECR, "DECR",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_decr, &spr_write_decr,
788 0x00000000);
789 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
790 SPR_NOACCESS, SPR_NOACCESS,
791 SPR_NOACCESS, &spr_write_generic,
792 0x00000000);
793 /* SPRGs */
794 spr_register(env, SPR_USPRG0, "USPRG0",
795 &spr_read_generic, &spr_write_generic,
796 &spr_read_generic, &spr_write_generic,
797 0x00000000);
798 spr_register(env, SPR_SPRG4, "SPRG4",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_generic, &spr_write_generic,
801 0x00000000);
802 spr_register(env, SPR_SPRG5, "SPRG5",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806 spr_register(env, SPR_SPRG6, "SPRG6",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 spr_register(env, SPR_SPRG7, "SPRG7",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 0x00000000);
814 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_generic, &spr_write_generic,
817 0x00000000);
818 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_generic, &spr_write_generic,
821 0x00000000);
822 }
823
824 #if !defined(CONFIG_USER_ONLY)
825 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
826 uint32_t maxsize, uint32_t flags,
827 uint32_t nentries)
828 {
829 return (assoc << TLBnCFG_ASSOC_SHIFT) |
830 (minsize << TLBnCFG_MINSIZE_SHIFT) |
831 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
832 flags | nentries;
833 }
834 #endif /* !CONFIG_USER_ONLY */
835
836 /* BookE 2.06 storage control registers */
837 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
838 uint32_t *tlbncfg, uint32_t mmucfg)
839 {
840 #if !defined(CONFIG_USER_ONLY)
841 const char *mas_names[8] = {
842 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
843 };
844 int mas_sprn[8] = {
845 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
846 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
847 };
848 int i;
849
850 /* TLB assist registers */
851 for (i = 0; i < 8; i++) {
852 if (mas_mask & (1 << i)) {
853 spr_register(env, mas_sprn[i], mas_names[i],
854 SPR_NOACCESS, SPR_NOACCESS,
855 &spr_read_generic,
856 (i == 2 && (env->insns_flags & PPC_64B))
857 ? &spr_write_generic : &spr_write_generic32,
858 0x00000000);
859 }
860 }
861 if (env->nb_pids > 1) {
862 spr_register(env, SPR_BOOKE_PID1, "PID1",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_booke_pid,
865 0x00000000);
866 }
867 if (env->nb_pids > 2) {
868 spr_register(env, SPR_BOOKE_PID2, "PID2",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, &spr_write_booke_pid,
871 0x00000000);
872 }
873
874 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, &spr_write_eplc,
877 0x00000000);
878 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_epsc,
881 0x00000000);
882
883 spr_register(env, SPR_MMUCFG, "MMUCFG",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 mmucfg);
887 switch (env->nb_ways) {
888 case 4:
889 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 tlbncfg[3]);
893 /* Fallthru */
894 case 3:
895 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 tlbncfg[2]);
899 /* Fallthru */
900 case 2:
901 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, SPR_NOACCESS,
904 tlbncfg[1]);
905 /* Fallthru */
906 case 1:
907 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, SPR_NOACCESS,
910 tlbncfg[0]);
911 /* Fallthru */
912 case 0:
913 default:
914 break;
915 }
916 #endif
917 }
918
919 /* SPR specific to PowerPC 440 implementation */
920 static void register_440_sprs(CPUPPCState *env)
921 {
922 /* Cache control */
923 spr_register(env, SPR_440_DNV0, "DNV0",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927
928 spr_register(env, SPR_440_DNV1, "DNV1",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932
933 spr_register(env, SPR_440_DNV2, "DNV2",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937
938 spr_register(env, SPR_440_DNV3, "DNV3",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942
943 spr_register(env, SPR_440_DTV0, "DTV0",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947
948 spr_register(env, SPR_440_DTV1, "DTV1",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952
953 spr_register(env, SPR_440_DTV2, "DTV2",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, &spr_write_generic,
956 0x00000000);
957
958 spr_register(env, SPR_440_DTV3, "DTV3",
959 SPR_NOACCESS, SPR_NOACCESS,
960 &spr_read_generic, &spr_write_generic,
961 0x00000000);
962
963 spr_register(env, SPR_440_DVLIM, "DVLIM",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967
968 spr_register(env, SPR_440_INV0, "INV0",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, &spr_write_generic,
971 0x00000000);
972
973 spr_register(env, SPR_440_INV1, "INV1",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, &spr_write_generic,
976 0x00000000);
977
978 spr_register(env, SPR_440_INV2, "INV2",
979 SPR_NOACCESS, SPR_NOACCESS,
980 &spr_read_generic, &spr_write_generic,
981 0x00000000);
982
983 spr_register(env, SPR_440_INV3, "INV3",
984 SPR_NOACCESS, SPR_NOACCESS,
985 &spr_read_generic, &spr_write_generic,
986 0x00000000);
987
988 spr_register(env, SPR_440_ITV0, "ITV0",
989 SPR_NOACCESS, SPR_NOACCESS,
990 &spr_read_generic, &spr_write_generic,
991 0x00000000);
992
993 spr_register(env, SPR_440_ITV1, "ITV1",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
997
998 spr_register(env, SPR_440_ITV2, "ITV2",
999 SPR_NOACCESS, SPR_NOACCESS,
1000 &spr_read_generic, &spr_write_generic,
1001 0x00000000);
1002
1003 spr_register(env, SPR_440_ITV3, "ITV3",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007
1008 spr_register(env, SPR_440_IVLIM, "IVLIM",
1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
1012 /* Cache debug */
1013 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, SPR_NOACCESS,
1016 0x00000000);
1017
1018 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1019 SPR_NOACCESS, SPR_NOACCESS,
1020 &spr_read_generic, SPR_NOACCESS,
1021 0x00000000);
1022
1023 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, SPR_NOACCESS,
1026 0x00000000);
1027
1028 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, SPR_NOACCESS,
1031 0x00000000);
1032
1033 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1034 SPR_NOACCESS, SPR_NOACCESS,
1035 &spr_read_generic, SPR_NOACCESS,
1036 0x00000000);
1037
1038 spr_register(env, SPR_440_DBDR, "DBDR",
1039 SPR_NOACCESS, SPR_NOACCESS,
1040 &spr_read_generic, &spr_write_generic,
1041 0x00000000);
1042 /* Processor control */
1043 spr_register(env, SPR_4xx_CCR0, "CCR0",
1044 SPR_NOACCESS, SPR_NOACCESS,
1045 &spr_read_generic, &spr_write_generic,
1046 0x00000000);
1047 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, SPR_NOACCESS,
1050 0x00000000);
1051 /* Storage control */
1052 spr_register(env, SPR_440_MMUCR, "MMUCR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056
1057 /* Processor identification */
1058 spr_register(env, SPR_BOOKE_PIR, "PIR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_pir,
1061 0x00000000);
1062
1063 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067
1068 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072
1073 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 0x00000000);
1077
1078 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, &spr_write_generic,
1081 0x00000000);
1082 }
1083
1084 /* SPR shared between PowerPC 40x implementations */
1085 static void register_40x_sprs(CPUPPCState *env)
1086 {
1087 /* Cache */
1088 /* not emulated, as QEMU do not emulate caches */
1089 spr_register(env, SPR_40x_DCCR, "DCCR",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093 /* not emulated, as QEMU do not emulate caches */
1094 spr_register(env, SPR_40x_ICCR, "ICCR",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_generic,
1097 0x00000000);
1098 /* not emulated, as QEMU do not emulate caches */
1099 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_generic, SPR_NOACCESS,
1102 0x00000000);
1103 /* Exception */
1104 spr_register(env, SPR_40x_DEAR, "DEAR",
1105 SPR_NOACCESS, SPR_NOACCESS,
1106 &spr_read_generic, &spr_write_generic,
1107 0x00000000);
1108 spr_register(env, SPR_40x_ESR, "ESR",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_generic, &spr_write_generic,
1111 0x00000000);
1112 spr_register(env, SPR_40x_EVPR, "EVPR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_excp_prefix,
1115 0x00000000);
1116 spr_register(env, SPR_40x_SRR2, "SRR2",
1117 &spr_read_generic, &spr_write_generic,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 spr_register(env, SPR_40x_SRR3, "SRR3",
1121 &spr_read_generic, &spr_write_generic,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* Timers */
1125 spr_register(env, SPR_40x_PIT, "PIT",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_40x_pit, &spr_write_40x_pit,
1128 0x00000000);
1129 spr_register(env, SPR_40x_TCR, "TCR",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, &spr_write_40x_tcr,
1132 0x00000000);
1133 spr_register(env, SPR_40x_TSR, "TSR",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_40x_tsr,
1136 0x00000000);
1137 }
1138
1139 /* SPR specific to PowerPC 405 implementation */
1140 static void register_405_sprs(CPUPPCState *env)
1141 {
1142 /* MMU */
1143 spr_register(env, SPR_40x_PID, "PID",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_40x_pid,
1146 0x00000000);
1147 spr_register(env, SPR_4xx_CCR0, "CCR0",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00700000);
1151 /* Debug interface */
1152 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_40x_dbcr0,
1155 0x00000000);
1156
1157 spr_register(env, SPR_405_DBCR1, "DBCR1",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161
1162 spr_register(env, SPR_40x_DBSR, "DBSR",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_clear,
1165 /* Last reset was system reset */
1166 0x00000300);
1167
1168 spr_register(env, SPR_40x_DAC1, "DAC1",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 spr_register(env, SPR_40x_DAC2, "DAC2",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176
1177 spr_register(env, SPR_405_DVC1, "DVC1",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181
1182 spr_register(env, SPR_405_DVC2, "DVC2",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186
1187 spr_register(env, SPR_40x_IAC1, "IAC1",
1188 SPR_NOACCESS, SPR_NOACCESS,
1189 &spr_read_generic, &spr_write_generic,
1190 0x00000000);
1191 spr_register(env, SPR_40x_IAC2, "IAC2",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195
1196 spr_register(env, SPR_405_IAC3, "IAC3",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200
1201 spr_register(env, SPR_405_IAC4, "IAC4",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205 /* Storage control */
1206 spr_register(env, SPR_405_SLER, "SLER",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_40x_sler,
1209 0x00000000);
1210 spr_register(env, SPR_40x_ZPR, "ZPR",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214
1215 spr_register(env, SPR_405_SU0R, "SU0R",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219 /* SPRG */
1220 spr_register(env, SPR_USPRG0, "USPRG0",
1221 &spr_read_ureg, SPR_NOACCESS,
1222 &spr_read_ureg, SPR_NOACCESS,
1223 0x00000000);
1224 spr_register(env, SPR_SPRG4, "SPRG4",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1227 0x00000000);
1228 spr_register(env, SPR_SPRG5, "SPRG5",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 spr_register(env, SPR_SPRG6, "SPRG6",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 spr_register(env, SPR_SPRG7, "SPRG7",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 spr_read_generic, &spr_write_generic,
1239 0x00000000);
1240
1241 /* Bus access control */
1242 /* not emulated, as QEMU never does speculative access */
1243 spr_register(env, SPR_40x_SGR, "SGR",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0xFFFFFFFF);
1247 /* not emulated, as QEMU do not emulate caches */
1248 spr_register(env, SPR_40x_DCWR, "DCWR",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 }
1253
1254
1255 static void register_5xx_8xx_sprs(CPUPPCState *env)
1256 {
1257 /* Exception processing */
1258 spr_register_kvm(env, SPR_DSISR, "DSISR",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 KVM_REG_PPC_DSISR, 0x00000000);
1262 spr_register_kvm(env, SPR_DAR, "DAR",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 KVM_REG_PPC_DAR, 0x00000000);
1266 /* Timer */
1267 spr_register(env, SPR_DECR, "DECR",
1268 SPR_NOACCESS, SPR_NOACCESS,
1269 &spr_read_decr, &spr_write_decr,
1270 0x00000000);
1271
1272 spr_register(env, SPR_MPC_EIE, "EIE",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 &spr_read_generic, &spr_write_generic,
1275 0x00000000);
1276
1277 spr_register(env, SPR_MPC_EID, "EID",
1278 SPR_NOACCESS, SPR_NOACCESS,
1279 &spr_read_generic, &spr_write_generic,
1280 0x00000000);
1281
1282 spr_register(env, SPR_MPC_NRI, "NRI",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_generic,
1285 0x00000000);
1286
1287 spr_register(env, SPR_MPC_CMPA, "CMPA",
1288 SPR_NOACCESS, SPR_NOACCESS,
1289 &spr_read_generic, &spr_write_generic,
1290 0x00000000);
1291
1292 spr_register(env, SPR_MPC_CMPB, "CMPB",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296
1297 spr_register(env, SPR_MPC_CMPC, "CMPC",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301
1302 spr_register(env, SPR_MPC_CMPD, "CMPD",
1303 SPR_NOACCESS, SPR_NOACCESS,
1304 &spr_read_generic, &spr_write_generic,
1305 0x00000000);
1306
1307 spr_register(env, SPR_MPC_ECR, "ECR",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_generic, &spr_write_generic,
1310 0x00000000);
1311
1312 spr_register(env, SPR_MPC_DER, "DER",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_generic,
1315 0x00000000);
1316
1317 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321
1322 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
1326
1327 spr_register(env, SPR_MPC_CMPE, "CMPE",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_generic, &spr_write_generic,
1330 0x00000000);
1331
1332 spr_register(env, SPR_MPC_CMPF, "CMPF",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_generic, &spr_write_generic,
1335 0x00000000);
1336
1337 spr_register(env, SPR_MPC_CMPG, "CMPG",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_generic, &spr_write_generic,
1340 0x00000000);
1341
1342 spr_register(env, SPR_MPC_CMPH, "CMPH",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346
1347 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1348 SPR_NOACCESS, SPR_NOACCESS,
1349 &spr_read_generic, &spr_write_generic,
1350 0x00000000);
1351
1352 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
1356
1357 spr_register(env, SPR_MPC_BAR, "BAR",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 0x00000000);
1361
1362 spr_register(env, SPR_MPC_DPDR, "DPDR",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1365 0x00000000);
1366
1367 spr_register(env, SPR_MPC_IMMR, "IMMR",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 }
1372
1373 static void register_5xx_sprs(CPUPPCState *env)
1374 {
1375 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379
1380 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384
1385 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_generic,
1388 0x00000000);
1389
1390 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1391 SPR_NOACCESS, SPR_NOACCESS,
1392 &spr_read_generic, &spr_write_generic,
1393 0x00000000);
1394
1395 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1396 SPR_NOACCESS, SPR_NOACCESS,
1397 &spr_read_generic, &spr_write_generic,
1398 0x00000000);
1399
1400 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_generic,
1403 0x00000000);
1404
1405 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1406 SPR_NOACCESS, SPR_NOACCESS,
1407 &spr_read_generic, &spr_write_generic,
1408 0x00000000);
1409
1410 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1411 SPR_NOACCESS, SPR_NOACCESS,
1412 &spr_read_generic, &spr_write_generic,
1413 0x00000000);
1414
1415 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419
1420 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1421 SPR_NOACCESS, SPR_NOACCESS,
1422 &spr_read_generic, &spr_write_generic,
1423 0x00000000);
1424
1425 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_generic,
1428 0x00000000);
1429
1430 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_generic, &spr_write_generic,
1433 0x00000000);
1434
1435 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_generic, &spr_write_generic,
1438 0x00000000);
1439
1440 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444
1445 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 &spr_read_generic, &spr_write_generic,
1448 0x00000000);
1449
1450 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1453 0x00000000);
1454
1455 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 &spr_read_generic, &spr_write_generic,
1458 0x00000000);
1459
1460 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1461 SPR_NOACCESS, SPR_NOACCESS,
1462 &spr_read_generic, &spr_write_generic,
1463 0x00000000);
1464
1465 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_generic,
1468 0x00000000);
1469
1470 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474
1475 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_generic,
1478 0x00000000);
1479 }
1480
1481 static void register_8xx_sprs(CPUPPCState *env)
1482 {
1483
1484 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488
1489 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493
1494 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498
1499 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503
1504 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508
1509 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, &spr_write_generic,
1512 0x00000000);
1513
1514 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518
1519 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523
1524 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
1528
1529 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
1533
1534 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538
1539 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 &spr_read_generic, &spr_write_generic,
1542 0x00000000);
1543
1544 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548
1549 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553
1554 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558
1559 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563
1564 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568
1569 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573
1574 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578
1579 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583
1584 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588
1589 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593
1594 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598
1599 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603
1604 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 }
1609
1610 /*
1611 * AMR => SPR 29 (Power 2.04)
1612 * CTRL => SPR 136 (Power 2.04)
1613 * CTRL => SPR 152 (Power 2.04)
1614 * SCOMC => SPR 276 (64 bits ?)
1615 * SCOMD => SPR 277 (64 bits ?)
1616 * TBU40 => SPR 286 (Power 2.04 hypv)
1617 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1618 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1619 * HDSISR => SPR 306 (Power 2.04 hypv)
1620 * HDAR => SPR 307 (Power 2.04 hypv)
1621 * PURR => SPR 309 (Power 2.04 hypv)
1622 * HDEC => SPR 310 (Power 2.04 hypv)
1623 * HIOR => SPR 311 (hypv)
1624 * RMOR => SPR 312 (970)
1625 * HRMOR => SPR 313 (Power 2.04 hypv)
1626 * HSRR0 => SPR 314 (Power 2.04 hypv)
1627 * HSRR1 => SPR 315 (Power 2.04 hypv)
1628 * LPIDR => SPR 317 (970)
1629 * EPR => SPR 702 (Power 2.04 emb)
1630 * perf => 768-783 (Power 2.04)
1631 * perf => 784-799 (Power 2.04)
1632 * PPR => SPR 896 (Power 2.04)
1633 * DABRX => 1015 (Power 2.04 hypv)
1634 * FPECR => SPR 1022 (?)
1635 * ... and more (thermal management, performance counters, ...)
1636 */
1637
1638 /*****************************************************************************/
1639 /* Exception vectors models */
1640 static void init_excp_4xx_softmmu(CPUPPCState *env)
1641 {
1642 #if !defined(CONFIG_USER_ONLY)
1643 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1644 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1645 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1646 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1647 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1648 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1649 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1650 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1651 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1652 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1653 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1654 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1655 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1656 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1657 env->ivor_mask = 0x0000FFF0UL;
1658 env->ivpr_mask = 0xFFFF0000UL;
1659 /* Hardware reset vector */
1660 env->hreset_vector = 0xFFFFFFFCUL;
1661 #endif
1662 }
1663
1664 static void init_excp_MPC5xx(CPUPPCState *env)
1665 {
1666 #if !defined(CONFIG_USER_ONLY)
1667 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1668 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1669 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1670 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1671 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1672 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1673 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1674 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1675 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1676 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1677 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1678 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1679 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1680 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1681 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1682 env->ivor_mask = 0x0000FFF0UL;
1683 env->ivpr_mask = 0xFFFF0000UL;
1684 /* Hardware reset vector */
1685 env->hreset_vector = 0x00000100UL;
1686 #endif
1687 }
1688
1689 static void init_excp_MPC8xx(CPUPPCState *env)
1690 {
1691 #if !defined(CONFIG_USER_ONLY)
1692 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1693 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1694 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1695 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1696 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1697 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1698 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1699 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1700 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1701 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1702 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1703 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1704 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1705 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1706 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1707 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1708 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1709 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1710 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1711 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1712 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1713 env->ivor_mask = 0x0000FFF0UL;
1714 env->ivpr_mask = 0xFFFF0000UL;
1715 /* Hardware reset vector */
1716 env->hreset_vector = 0x00000100UL;
1717 #endif
1718 }
1719
1720 static void init_excp_G2(CPUPPCState *env)
1721 {
1722 #if !defined(CONFIG_USER_ONLY)
1723 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1724 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1725 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1726 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1731 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1732 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1734 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1735 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1736 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1737 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1738 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1739 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1740 /* Hardware reset vector */
1741 env->hreset_vector = 0x00000100UL;
1742 #endif
1743 }
1744
1745 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1746 {
1747 #if !defined(CONFIG_USER_ONLY)
1748 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1749 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1750 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1751 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1752 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1753 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1754 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1755 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1756 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1757 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1758 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1759 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1760 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1761 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1762 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1763 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1764 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1765 /*
1766 * These two are the same IVOR as POWERPC_EXCP_VPU and
1767 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1768 * powerpc_excp().
1769 */
1770 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1771 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1772
1773 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1774 env->ivor_mask = 0x0000FFF7UL;
1775 env->ivpr_mask = ivpr_mask;
1776 /* Hardware reset vector */
1777 env->hreset_vector = 0xFFFFFFFCUL;
1778 #endif
1779 }
1780
1781 static void init_excp_BookE(CPUPPCState *env)
1782 {
1783 #if !defined(CONFIG_USER_ONLY)
1784 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1787 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1788 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1789 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1790 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1791 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1792 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1793 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1794 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1795 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1796 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1797 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1798 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1799 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1800 env->ivor_mask = 0x0000FFF0UL;
1801 env->ivpr_mask = 0xFFFF0000UL;
1802 /* Hardware reset vector */
1803 env->hreset_vector = 0xFFFFFFFCUL;
1804 #endif
1805 }
1806
1807 static void init_excp_603(CPUPPCState *env)
1808 {
1809 #if !defined(CONFIG_USER_ONLY)
1810 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1811 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1812 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1813 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1814 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1815 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1816 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1817 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1818 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1820 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1821 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1822 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1823 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1824 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1825 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1826 /* Hardware reset vector */
1827 env->hreset_vector = 0x00000100UL;
1828 #endif
1829 }
1830
1831 static void init_excp_604(CPUPPCState *env)
1832 {
1833 #if !defined(CONFIG_USER_ONLY)
1834 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1835 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1836 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1837 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1838 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1839 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1840 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1841 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1842 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1844 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1845 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1846 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1847 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1848 /* Hardware reset vector */
1849 env->hreset_vector = 0x00000100UL;
1850 #endif
1851 }
1852
1853 static void init_excp_7x0(CPUPPCState *env)
1854 {
1855 #if !defined(CONFIG_USER_ONLY)
1856 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1857 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1858 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1859 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1860 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1861 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1862 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1863 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1864 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1865 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1866 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1867 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1868 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1869 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1870 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1871 /* Hardware reset vector */
1872 env->hreset_vector = 0x00000100UL;
1873 #endif
1874 }
1875
1876 static void init_excp_750cl(CPUPPCState *env)
1877 {
1878 #if !defined(CONFIG_USER_ONLY)
1879 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1880 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1881 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1882 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1883 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1884 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1885 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1886 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1887 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1888 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1889 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1890 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1891 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1892 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1893 /* Hardware reset vector */
1894 env->hreset_vector = 0x00000100UL;
1895 #endif
1896 }
1897
1898 static void init_excp_750cx(CPUPPCState *env)
1899 {
1900 #if !defined(CONFIG_USER_ONLY)
1901 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1902 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1903 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1904 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1905 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1906 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1907 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1908 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1909 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1910 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1911 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1912 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1913 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1914 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1915 /* Hardware reset vector */
1916 env->hreset_vector = 0x00000100UL;
1917 #endif
1918 }
1919
1920 /* XXX: Check if this is correct */
1921 static void init_excp_7x5(CPUPPCState *env)
1922 {
1923 #if !defined(CONFIG_USER_ONLY)
1924 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1925 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1926 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1927 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1928 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1929 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1930 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1931 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1932 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1933 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1934 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1935 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1936 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1937 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1938 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1939 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1940 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1941 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1942 /* Hardware reset vector */
1943 env->hreset_vector = 0x00000100UL;
1944 #endif
1945 }
1946
1947 static void init_excp_7400(CPUPPCState *env)
1948 {
1949 #if !defined(CONFIG_USER_ONLY)
1950 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1951 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1952 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1953 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1954 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1955 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1956 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1957 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1958 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1959 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1960 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1961 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1962 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1963 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1964 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1965 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1966 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1967 /* Hardware reset vector */
1968 env->hreset_vector = 0x00000100UL;
1969 #endif
1970 }
1971
1972 static void init_excp_7450(CPUPPCState *env)
1973 {
1974 #if !defined(CONFIG_USER_ONLY)
1975 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1976 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1977 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1978 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1979 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1980 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1981 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1982 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1983 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1984 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1985 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1986 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1987 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1988 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1989 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1990 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1991 /* Hardware reset vector */
1992 env->hreset_vector = 0x00000100UL;
1993 #endif
1994 }
1995
1996 #if defined(TARGET_PPC64)
1997 static void init_excp_970(CPUPPCState *env)
1998 {
1999 #if !defined(CONFIG_USER_ONLY)
2000 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2001 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2002 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2003 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2004 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2005 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2006 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2007 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2008 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2009 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2010 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2011 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2012 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2013 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2014 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2015 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2016 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2017 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2018 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2019 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2020 /* Hardware reset vector */
2021 env->hreset_vector = 0x0000000000000100ULL;
2022 #endif
2023 }
2024
2025 static void init_excp_POWER7(CPUPPCState *env)
2026 {
2027 #if !defined(CONFIG_USER_ONLY)
2028 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2029 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2030 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2031 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2032 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2033 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2034 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2035 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2036 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2037 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2038 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2039 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2040 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2041 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2042 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2043 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2044 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2045 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2046 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2047 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2048 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2049 /* Hardware reset vector */
2050 env->hreset_vector = 0x0000000000000100ULL;
2051 #endif
2052 }
2053
2054 static void init_excp_POWER8(CPUPPCState *env)
2055 {
2056 init_excp_POWER7(env);
2057
2058 #if !defined(CONFIG_USER_ONLY)
2059 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2060 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2061 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2062 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2063
2064 /* Userland exceptions without vector value in PowerISA v3.1 */
2065 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2066 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2067 #endif
2068 }
2069
2070 static void init_excp_POWER9(CPUPPCState *env)
2071 {
2072 init_excp_POWER8(env);
2073
2074 #if !defined(CONFIG_USER_ONLY)
2075 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2076 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2077 #endif
2078 }
2079
2080 static void init_excp_POWER10(CPUPPCState *env)
2081 {
2082 init_excp_POWER9(env);
2083 }
2084
2085 #endif
2086
2087 static int check_pow_hid0(CPUPPCState *env)
2088 {
2089 if (env->spr[SPR_HID0] & 0x00E00000) {
2090 return 1;
2091 }
2092
2093 return 0;
2094 }
2095
2096 static int check_pow_hid0_74xx(CPUPPCState *env)
2097 {
2098 if (env->spr[SPR_HID0] & 0x00600000) {
2099 return 1;
2100 }
2101
2102 return 0;
2103 }
2104
2105 static void init_proc_405(CPUPPCState *env)
2106 {
2107 register_40x_sprs(env);
2108 register_405_sprs(env);
2109 register_usprgh_sprs(env);
2110
2111 /* Memory management */
2112 #if !defined(CONFIG_USER_ONLY)
2113 env->nb_tlb = 64;
2114 env->nb_ways = 1;
2115 env->id_tlbs = 0;
2116 env->tlb_type = TLB_EMB;
2117 #endif
2118 init_excp_4xx_softmmu(env);
2119 env->dcache_line_size = 32;
2120 env->icache_line_size = 32;
2121 /* Allocate hardware IRQ controller */
2122 ppc40x_irq_init(env_archcpu(env));
2123
2124 SET_FIT_PERIOD(8, 12, 16, 20);
2125 SET_WDT_PERIOD(16, 20, 24, 28);
2126 }
2127
2128 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2129 {
2130 DeviceClass *dc = DEVICE_CLASS(oc);
2131 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2132
2133 dc->desc = "PowerPC 405";
2134 pcc->init_proc = init_proc_405;
2135 pcc->check_pow = check_pow_nocheck;
2136 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2137 PPC_DCR | PPC_WRTEE |
2138 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2139 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2140 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2141 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2142 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2143 pcc->msr_mask = (1ull << MSR_WE) |
2144 (1ull << MSR_CE) |
2145 (1ull << MSR_EE) |
2146 (1ull << MSR_PR) |
2147 (1ull << MSR_FP) |
2148 (1ull << MSR_ME) |
2149 (1ull << MSR_DWE) |
2150 (1ull << MSR_DE) |
2151 (1ull << MSR_IR) |
2152 (1ull << MSR_DR);
2153 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2154 pcc->excp_model = POWERPC_EXCP_40x;
2155 pcc->bus_model = PPC_FLAGS_INPUT_405;
2156 pcc->bfd_mach = bfd_mach_ppc_403;
2157 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2158 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2159 }
2160
2161 static void init_proc_440EP(CPUPPCState *env)
2162 {
2163 register_BookE_sprs(env, 0x000000000000FFFFULL);
2164 register_440_sprs(env);
2165 register_usprgh_sprs(env);
2166
2167 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, &spr_write_generic,
2170 0x00000000);
2171 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
2179
2180 spr_register(env, SPR_440_CCR1, "CCR1",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
2184 /* Memory management */
2185 #if !defined(CONFIG_USER_ONLY)
2186 env->nb_tlb = 64;
2187 env->nb_ways = 1;
2188 env->id_tlbs = 0;
2189 env->tlb_type = TLB_EMB;
2190 #endif
2191 init_excp_BookE(env);
2192 env->dcache_line_size = 32;
2193 env->icache_line_size = 32;
2194 ppc40x_irq_init(env_archcpu(env));
2195
2196 SET_FIT_PERIOD(12, 16, 20, 24);
2197 SET_WDT_PERIOD(20, 24, 28, 32);
2198 }
2199
2200 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2201 {
2202 DeviceClass *dc = DEVICE_CLASS(oc);
2203 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2204
2205 dc->desc = "PowerPC 440 EP";
2206 pcc->init_proc = init_proc_440EP;
2207 pcc->check_pow = check_pow_nocheck;
2208 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2209 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2210 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2211 PPC_FLOAT_STFIWX |
2212 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2213 PPC_CACHE | PPC_CACHE_ICBI |
2214 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2215 PPC_MEM_TLBSYNC | PPC_MFTB |
2216 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2217 PPC_440_SPEC;
2218 pcc->msr_mask = (1ull << MSR_POW) |
2219 (1ull << MSR_CE) |
2220 (1ull << MSR_EE) |
2221 (1ull << MSR_PR) |
2222 (1ull << MSR_FP) |
2223 (1ull << MSR_ME) |
2224 (1ull << MSR_FE0) |
2225 (1ull << MSR_DWE) |
2226 (1ull << MSR_DE) |
2227 (1ull << MSR_FE1) |
2228 (1ull << MSR_IR) |
2229 (1ull << MSR_DR);
2230 pcc->mmu_model = POWERPC_MMU_BOOKE;
2231 pcc->excp_model = POWERPC_EXCP_BOOKE;
2232 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2233 pcc->bfd_mach = bfd_mach_ppc_403;
2234 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2235 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2236 }
2237
2238 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2239 {
2240 DeviceClass *dc = DEVICE_CLASS(oc);
2241 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2242
2243 dc->desc = "PowerPC 460 EX";
2244 pcc->init_proc = init_proc_440EP;
2245 pcc->check_pow = check_pow_nocheck;
2246 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2247 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2248 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2249 PPC_FLOAT_STFIWX |
2250 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2251 PPC_CACHE | PPC_CACHE_ICBI |
2252 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2253 PPC_MEM_TLBSYNC | PPC_MFTB |
2254 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2255 PPC_440_SPEC;
2256 pcc->msr_mask = (1ull << MSR_POW) |
2257 (1ull << MSR_CE) |
2258 (1ull << MSR_EE) |
2259 (1ull << MSR_PR) |
2260 (1ull << MSR_FP) |
2261 (1ull << MSR_ME) |
2262 (1ull << MSR_FE0) |
2263 (1ull << MSR_DWE) |
2264 (1ull << MSR_DE) |
2265 (1ull << MSR_FE1) |
2266 (1ull << MSR_IR) |
2267 (1ull << MSR_DR);
2268 pcc->mmu_model = POWERPC_MMU_BOOKE;
2269 pcc->excp_model = POWERPC_EXCP_BOOKE;
2270 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2271 pcc->bfd_mach = bfd_mach_ppc_403;
2272 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2273 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2274 }
2275
2276 static void init_proc_440GP(CPUPPCState *env)
2277 {
2278 register_BookE_sprs(env, 0x000000000000FFFFULL);
2279 register_440_sprs(env);
2280 register_usprgh_sprs(env);
2281
2282 /* Memory management */
2283 #if !defined(CONFIG_USER_ONLY)
2284 env->nb_tlb = 64;
2285 env->nb_ways = 1;
2286 env->id_tlbs = 0;
2287 env->tlb_type = TLB_EMB;
2288 #endif
2289 init_excp_BookE(env);
2290 env->dcache_line_size = 32;
2291 env->icache_line_size = 32;
2292 /* XXX: TODO: allocate internal IRQ controller */
2293
2294 SET_FIT_PERIOD(12, 16, 20, 24);
2295 SET_WDT_PERIOD(20, 24, 28, 32);
2296 }
2297
2298 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2299 {
2300 DeviceClass *dc = DEVICE_CLASS(oc);
2301 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2302
2303 dc->desc = "PowerPC 440 GP";
2304 pcc->init_proc = init_proc_440GP;
2305 pcc->check_pow = check_pow_nocheck;
2306 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2307 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2308 PPC_CACHE | PPC_CACHE_ICBI |
2309 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2310 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2311 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2312 PPC_440_SPEC;
2313 pcc->msr_mask = (1ull << MSR_POW) |
2314 (1ull << MSR_CE) |
2315 (1ull << MSR_EE) |
2316 (1ull << MSR_PR) |
2317 (1ull << MSR_FP) |
2318 (1ull << MSR_ME) |
2319 (1ull << MSR_FE0) |
2320 (1ull << MSR_DWE) |
2321 (1ull << MSR_DE) |
2322 (1ull << MSR_FE1) |
2323 (1ull << MSR_IR) |
2324 (1ull << MSR_DR);
2325 pcc->mmu_model = POWERPC_MMU_BOOKE;
2326 pcc->excp_model = POWERPC_EXCP_BOOKE;
2327 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2328 pcc->bfd_mach = bfd_mach_ppc_403;
2329 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2330 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2331 }
2332
2333 static void init_proc_440x5(CPUPPCState *env)
2334 {
2335 register_BookE_sprs(env, 0x000000000000FFFFULL);
2336 register_440_sprs(env);
2337 register_usprgh_sprs(env);
2338
2339 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351
2352 spr_register(env, SPR_440_CCR1, "CCR1",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* Memory management */
2357 #if !defined(CONFIG_USER_ONLY)
2358 env->nb_tlb = 64;
2359 env->nb_ways = 1;
2360 env->id_tlbs = 0;
2361 env->tlb_type = TLB_EMB;
2362 #endif
2363 init_excp_BookE(env);
2364 env->dcache_line_size = 32;
2365 env->icache_line_size = 32;
2366 ppc40x_irq_init(env_archcpu(env));
2367
2368 SET_FIT_PERIOD(12, 16, 20, 24);
2369 SET_WDT_PERIOD(20, 24, 28, 32);
2370 }
2371
2372 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2373 {
2374 DeviceClass *dc = DEVICE_CLASS(oc);
2375 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2376
2377 dc->desc = "PowerPC 440x5";
2378 pcc->init_proc = init_proc_440x5;
2379 pcc->check_pow = check_pow_nocheck;
2380 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2381 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2382 PPC_CACHE | PPC_CACHE_ICBI |
2383 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2384 PPC_MEM_TLBSYNC | PPC_MFTB |
2385 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2386 PPC_440_SPEC;
2387 pcc->msr_mask = (1ull << MSR_POW) |
2388 (1ull << MSR_CE) |
2389 (1ull << MSR_EE) |
2390 (1ull << MSR_PR) |
2391 (1ull << MSR_FP) |
2392 (1ull << MSR_ME) |
2393 (1ull << MSR_FE0) |
2394 (1ull << MSR_DWE) |
2395 (1ull << MSR_DE) |
2396 (1ull << MSR_FE1) |
2397 (1ull << MSR_IR) |
2398 (1ull << MSR_DR);
2399 pcc->mmu_model = POWERPC_MMU_BOOKE;
2400 pcc->excp_model = POWERPC_EXCP_BOOKE;
2401 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2402 pcc->bfd_mach = bfd_mach_ppc_403;
2403 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2404 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2405 }
2406
2407 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2408 {
2409 DeviceClass *dc = DEVICE_CLASS(oc);
2410 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2411
2412 dc->desc = "PowerPC 440x5 with double precision FPU";
2413 pcc->init_proc = init_proc_440x5;
2414 pcc->check_pow = check_pow_nocheck;
2415 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2416 PPC_FLOAT | PPC_FLOAT_FSQRT |
2417 PPC_FLOAT_STFIWX |
2418 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2419 PPC_CACHE | PPC_CACHE_ICBI |
2420 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2421 PPC_MEM_TLBSYNC | PPC_MFTB |
2422 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2423 PPC_440_SPEC;
2424 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2425 pcc->msr_mask = (1ull << MSR_POW) |
2426 (1ull << MSR_CE) |
2427 (1ull << MSR_EE) |
2428 (1ull << MSR_PR) |
2429 (1ull << MSR_FP) |
2430 (1ull << MSR_ME) |
2431 (1ull << MSR_FE0) |
2432 (1ull << MSR_DWE) |
2433 (1ull << MSR_DE) |
2434 (1ull << MSR_FE1) |
2435 (1ull << MSR_IR) |
2436 (1ull << MSR_DR);
2437 pcc->mmu_model = POWERPC_MMU_BOOKE;
2438 pcc->excp_model = POWERPC_EXCP_BOOKE;
2439 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2440 pcc->bfd_mach = bfd_mach_ppc_403;
2441 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2442 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2443 }
2444
2445 static void init_proc_MPC5xx(CPUPPCState *env)
2446 {
2447 register_5xx_8xx_sprs(env);
2448 register_5xx_sprs(env);
2449 init_excp_MPC5xx(env);
2450 env->dcache_line_size = 32;
2451 env->icache_line_size = 32;
2452 /* XXX: TODO: allocate internal IRQ controller */
2453 }
2454
2455 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2456 {
2457 DeviceClass *dc = DEVICE_CLASS(oc);
2458 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2459
2460 dc->desc = "Freescale 5xx cores (aka RCPU)";
2461 pcc->init_proc = init_proc_MPC5xx;
2462 pcc->check_pow = check_pow_none;
2463 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2464 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2465 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2466 PPC_MFTB;
2467 pcc->msr_mask = (1ull << MSR_ILE) |
2468 (1ull << MSR_EE) |
2469 (1ull << MSR_PR) |
2470 (1ull << MSR_FP) |
2471 (1ull << MSR_ME) |
2472 (1ull << MSR_FE0) |
2473 (1ull << MSR_SE) |
2474 (1ull << MSR_DE) |
2475 (1ull << MSR_FE1) |
2476 (1ull << MSR_EP) |
2477 (1ull << MSR_RI) |
2478 (1ull << MSR_LE);
2479 pcc->mmu_model = POWERPC_MMU_REAL;
2480 pcc->excp_model = POWERPC_EXCP_6xx;
2481 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2482 pcc->bfd_mach = bfd_mach_ppc_505;
2483 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2484 POWERPC_FLAG_BUS_CLK;
2485 }
2486
2487 static void init_proc_MPC8xx(CPUPPCState *env)
2488 {
2489 register_5xx_8xx_sprs(env);
2490 register_8xx_sprs(env);
2491 init_excp_MPC8xx(env);
2492 env->dcache_line_size = 32;
2493 env->icache_line_size = 32;
2494 /* XXX: TODO: allocate internal IRQ controller */
2495 }
2496
2497 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2498 {
2499 DeviceClass *dc = DEVICE_CLASS(oc);
2500 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2501
2502 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2503 pcc->init_proc = init_proc_MPC8xx;
2504 pcc->check_pow = check_pow_none;
2505 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2506 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2507 PPC_CACHE_ICBI | PPC_MFTB;
2508 pcc->msr_mask = (1ull << MSR_ILE) |
2509 (1ull << MSR_EE) |
2510 (1ull << MSR_PR) |
2511 (1ull << MSR_FP) |
2512 (1ull << MSR_ME) |
2513 (1ull << MSR_SE) |
2514 (1ull << MSR_DE) |
2515 (1ull << MSR_EP) |
2516 (1ull << MSR_IR) |
2517 (1ull << MSR_DR) |
2518 (1ull << MSR_RI) |
2519 (1ull << MSR_LE);
2520 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2521 pcc->excp_model = POWERPC_EXCP_6xx;
2522 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2523 pcc->bfd_mach = bfd_mach_ppc_860;
2524 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2525 POWERPC_FLAG_BUS_CLK;
2526 }
2527
2528 /* Freescale 82xx cores (aka PowerQUICC-II) */
2529
2530 static void init_proc_G2(CPUPPCState *env)
2531 {
2532 register_non_embedded_sprs(env);
2533 register_sdr1_sprs(env);
2534 register_G2_sprs(env);
2535
2536 /* Memory management */
2537 register_low_BATs(env);
2538 register_high_BATs(env);
2539 register_6xx_7xx_soft_tlb(env, 64, 2);
2540 init_excp_G2(env);
2541 env->dcache_line_size = 32;
2542 env->icache_line_size = 32;
2543 /* Allocate hardware IRQ controller */
2544 ppc6xx_irq_init(env_archcpu(env));
2545 }
2546
2547 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2548 {
2549 DeviceClass *dc = DEVICE_CLASS(oc);
2550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2551
2552 dc->desc = "PowerPC G2";
2553 pcc->init_proc = init_proc_G2;
2554 pcc->check_pow = check_pow_hid0;
2555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2556 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2557 PPC_FLOAT_STFIWX |
2558 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2559 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2560 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2561 PPC_SEGMENT | PPC_EXTERN;
2562 pcc->msr_mask = (1ull << MSR_POW) |
2563 (1ull << MSR_TGPR) |
2564 (1ull << MSR_EE) |
2565 (1ull << MSR_PR) |
2566 (1ull << MSR_FP) |
2567 (1ull << MSR_ME) |
2568 (1ull << MSR_FE0) |
2569 (1ull << MSR_SE) |
2570 (1ull << MSR_DE) |
2571 (1ull << MSR_FE1) |
2572 (1ull << MSR_AL) |
2573 (1ull << MSR_EP) |
2574 (1ull << MSR_IR) |
2575 (1ull << MSR_DR) |
2576 (1ull << MSR_RI);
2577 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2578 pcc->excp_model = POWERPC_EXCP_6xx;
2579 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2580 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2581 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2582 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2583 }
2584
2585 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2586 {
2587 DeviceClass *dc = DEVICE_CLASS(oc);
2588 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2589
2590 dc->desc = "PowerPC G2LE";
2591 pcc->init_proc = init_proc_G2;
2592 pcc->check_pow = check_pow_hid0;
2593 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2594 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2595 PPC_FLOAT_STFIWX |
2596 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2597 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2598 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2599 PPC_SEGMENT | PPC_EXTERN;
2600 pcc->msr_mask = (1ull << MSR_POW) |
2601 (1ull << MSR_TGPR) |
2602 (1ull << MSR_ILE) |
2603 (1ull << MSR_EE) |
2604 (1ull << MSR_PR) |
2605 (1ull << MSR_FP) |
2606 (1ull << MSR_ME) |
2607 (1ull << MSR_FE0) |
2608 (1ull << MSR_SE) |
2609 (1ull << MSR_DE) |
2610 (1ull << MSR_FE1) |
2611 (1ull << MSR_AL) |
2612 (1ull << MSR_EP) |
2613 (1ull << MSR_IR) |
2614 (1ull << MSR_DR) |
2615 (1ull << MSR_RI) |
2616 (1ull << MSR_LE);
2617 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2618 pcc->excp_model = POWERPC_EXCP_6xx;
2619 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2620 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2621 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2622 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2623 }
2624
2625 static void init_proc_e200(CPUPPCState *env)
2626 {
2627 register_BookE_sprs(env, 0x000000070000FFFFULL);
2628
2629 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2630 &spr_read_spefscr, &spr_write_spefscr,
2631 &spr_read_spefscr, &spr_write_spefscr,
2632 0x00000000);
2633 /* Memory management */
2634 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2635 register_usprgh_sprs(env);
2636
2637 spr_register(env, SPR_HID0, "HID0",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641
2642 spr_register(env, SPR_HID1, "HID1",
2643 SPR_NOACCESS, SPR_NOACCESS,
2644 &spr_read_generic, &spr_write_generic,
2645 0x00000000);
2646
2647 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2648 SPR_NOACCESS, SPR_NOACCESS,
2649 &spr_read_generic, &spr_write_generic,
2650 0x00000000);
2651
2652 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2653 SPR_NOACCESS, SPR_NOACCESS,
2654 &spr_read_generic, &spr_write_generic,
2655 0x00000000);
2656
2657 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2658 SPR_NOACCESS, SPR_NOACCESS,
2659 &spr_read_generic, &spr_write_generic,
2660 0x00000000);
2661
2662 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2663 SPR_NOACCESS, SPR_NOACCESS,
2664 &spr_read_generic, &spr_write_generic,
2665 0x00000000);
2666
2667 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2668 SPR_NOACCESS, SPR_NOACCESS,
2669 &spr_read_generic, &spr_write_generic,
2670 0x00000000);
2671
2672 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2673 &spr_read_generic, SPR_NOACCESS,
2674 &spr_read_generic, SPR_NOACCESS,
2675 0x00000000);
2676
2677 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2678 SPR_NOACCESS, SPR_NOACCESS,
2679 &spr_read_generic, &spr_write_generic,
2680 0x00000000);
2681
2682 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2683 SPR_NOACCESS, SPR_NOACCESS,
2684 &spr_read_generic, &spr_write_generic,
2685 0x00000000);
2686
2687 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2688 SPR_NOACCESS, SPR_NOACCESS,
2689 &spr_read_generic, &spr_write_generic,
2690 0x00000000);
2691
2692 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2693 SPR_NOACCESS, SPR_NOACCESS,
2694 &spr_read_generic, &spr_write_generic,
2695 0x00000000);
2696
2697 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2698 SPR_NOACCESS, SPR_NOACCESS,
2699 &spr_read_generic, &spr_write_generic,
2700 0x00000000);
2701
2702 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2703 SPR_NOACCESS, SPR_NOACCESS,
2704 &spr_read_generic, &spr_write_generic,
2705 0x00000000);
2706
2707 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2708 SPR_NOACCESS, SPR_NOACCESS,
2709 &spr_read_generic, &spr_write_generic,
2710 0x00000000); /* TOFIX */
2711 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
2712 SPR_NOACCESS, SPR_NOACCESS,
2713 &spr_read_generic, &spr_write_generic,
2714 0x00000000);
2715 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
2716 SPR_NOACCESS, SPR_NOACCESS,
2717 &spr_read_generic, &spr_write_generic,
2718 0x00000000);
2719 #if !defined(CONFIG_USER_ONLY)
2720 env->nb_tlb = 64;
2721 env->nb_ways = 1;
2722 env->id_tlbs = 0;
2723 env->tlb_type = TLB_EMB;
2724 #endif
2725 init_excp_e200(env, 0xFFFF0000UL);
2726 env->dcache_line_size = 32;
2727 env->icache_line_size = 32;
2728 /* XXX: TODO: allocate internal IRQ controller */
2729 }
2730
2731 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
2732 {
2733 DeviceClass *dc = DEVICE_CLASS(oc);
2734 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2735
2736 dc->desc = "e200 core";
2737 pcc->init_proc = init_proc_e200;
2738 pcc->check_pow = check_pow_hid0;
2739 /*
2740 * XXX: unimplemented instructions:
2741 * dcblc
2742 * dcbtlst
2743 * dcbtstls
2744 * icblc
2745 * icbtls
2746 * tlbivax
2747 * all SPE multiply-accumulate instructions
2748 */
2749 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2750 PPC_SPE | PPC_SPE_SINGLE |
2751 PPC_WRTEE | PPC_RFDI |
2752 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2753 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2754 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2755 PPC_BOOKE;
2756 pcc->msr_mask = (1ull << MSR_UCLE) |
2757 (1ull << MSR_SPE) |
2758 (1ull << MSR_POW) |
2759 (1ull << MSR_CE) |
2760 (1ull << MSR_EE) |
2761 (1ull << MSR_PR) |
2762 (1ull << MSR_FP) |
2763 (1ull << MSR_ME) |
2764 (1ull << MSR_FE0) |
2765 (1ull << MSR_DWE) |
2766 (1ull << MSR_DE) |
2767 (1ull << MSR_FE1) |
2768 (1ull << MSR_IR) |
2769 (1ull << MSR_DR);
2770 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2771 pcc->excp_model = POWERPC_EXCP_BOOKE;
2772 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2773 pcc->bfd_mach = bfd_mach_ppc_860;
2774 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2775 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2776 POWERPC_FLAG_BUS_CLK;
2777 }
2778
2779 enum fsl_e500_version {
2780 fsl_e500v1,
2781 fsl_e500v2,
2782 fsl_e500mc,
2783 fsl_e5500,
2784 fsl_e6500,
2785 };
2786
2787 static void init_proc_e500(CPUPPCState *env, int version)
2788 {
2789 uint32_t tlbncfg[2];
2790 uint64_t ivor_mask;
2791 uint64_t ivpr_mask = 0xFFFF0000ULL;
2792 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2793 | 0x0020; /* 32 kb */
2794 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2795 | 0x0020; /* 32 kb */
2796 uint32_t mmucfg = 0;
2797 #if !defined(CONFIG_USER_ONLY)
2798 int i;
2799 #endif
2800
2801 /*
2802 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2803 * complain when accessing them.
2804 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2805 */
2806 switch (version) {
2807 case fsl_e500v1:
2808 case fsl_e500v2:
2809 default:
2810 ivor_mask = 0x0000000F0000FFFFULL;
2811 break;
2812 case fsl_e500mc:
2813 case fsl_e5500:
2814 ivor_mask = 0x000003FE0000FFFFULL;
2815 break;
2816 case fsl_e6500:
2817 ivor_mask = 0x000003FF0000FFFFULL;
2818 break;
2819 }
2820 register_BookE_sprs(env, ivor_mask);
2821
2822 spr_register(env, SPR_USPRG3, "USPRG3",
2823 &spr_read_ureg, SPR_NOACCESS,
2824 &spr_read_ureg, SPR_NOACCESS,
2825 0x00000000);
2826
2827 /* Processor identification */
2828 spr_register(env, SPR_BOOKE_PIR, "PIR",
2829 SPR_NOACCESS, SPR_NOACCESS,
2830 &spr_read_generic, &spr_write_pir,
2831 0x00000000);
2832
2833 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2834 &spr_read_spefscr, &spr_write_spefscr,
2835 &spr_read_spefscr, &spr_write_spefscr,
2836 0x00000000);
2837 #if !defined(CONFIG_USER_ONLY)
2838 /* Memory management */
2839 env->nb_pids = 3;
2840 env->nb_ways = 2;
2841 env->id_tlbs = 0;
2842 switch (version) {
2843 case fsl_e500v1:
2844 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2845 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2846 break;
2847 case fsl_e500v2:
2848 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2849 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2850 break;
2851 case fsl_e500mc:
2852 case fsl_e5500:
2853 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2854 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2855 break;
2856 case fsl_e6500:
2857 mmucfg = 0x6510B45;
2858 env->nb_pids = 1;
2859 tlbncfg[0] = 0x08052400;
2860 tlbncfg[1] = 0x40028040;
2861 break;
2862 default:
2863 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2864 env->spr[SPR_PVR]);
2865 }
2866 #endif
2867 /* Cache sizes */
2868 switch (version) {
2869 case fsl_e500v1:
2870 case fsl_e500v2:
2871 env->dcache_line_size = 32;
2872 env->icache_line_size = 32;
2873 break;
2874 case fsl_e500mc:
2875 case fsl_e5500:
2876 env->dcache_line_size = 64;
2877 env->icache_line_size = 64;
2878 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2879 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2880 break;
2881 case fsl_e6500:
2882 env->dcache_line_size = 32;
2883 env->icache_line_size = 32;
2884 l1cfg0 |= 0x0F83820;
2885 l1cfg1 |= 0x0B83820;
2886 break;
2887 default:
2888 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2889 env->spr[SPR_PVR]);
2890 }
2891 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2892 register_usprgh_sprs(env);
2893
2894 spr_register(env, SPR_HID0, "HID0",
2895 SPR_NOACCESS, SPR_NOACCESS,
2896 &spr_read_generic, &spr_write_generic,
2897 0x00000000);
2898
2899 spr_register(env, SPR_HID1, "HID1",
2900 SPR_NOACCESS, SPR_NOACCESS,
2901 &spr_read_generic, &spr_write_generic,
2902 0x00000000);
2903
2904 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2905 SPR_NOACCESS, SPR_NOACCESS,
2906 &spr_read_generic, &spr_write_generic,
2907 0x00000000);
2908
2909 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2910 SPR_NOACCESS, SPR_NOACCESS,
2911 &spr_read_generic, &spr_write_generic,
2912 0x00000000);
2913
2914 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2915 SPR_NOACCESS, SPR_NOACCESS,
2916 &spr_read_generic, &spr_write_generic,
2917 0x00000000);
2918
2919 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2920 SPR_NOACCESS, SPR_NOACCESS,
2921 &spr_read_generic, &spr_write_generic,
2922 0x00000000);
2923
2924 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2925 SPR_NOACCESS, SPR_NOACCESS,
2926 &spr_read_generic, &spr_write_generic,
2927 0x00000000);
2928
2929 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2930 SPR_NOACCESS, SPR_NOACCESS,
2931 &spr_read_generic, &spr_write_generic,
2932 0x00000000);
2933
2934 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2935 &spr_read_generic, SPR_NOACCESS,
2936 &spr_read_generic, SPR_NOACCESS,
2937 l1cfg0);
2938 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2939 &spr_read_generic, SPR_NOACCESS,
2940 &spr_read_generic, SPR_NOACCESS,
2941 l1cfg1);
2942 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2943 SPR_NOACCESS, SPR_NOACCESS,
2944 &spr_read_generic, &spr_write_e500_l1csr0,
2945 0x00000000);
2946 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2947 SPR_NOACCESS, SPR_NOACCESS,
2948 &spr_read_generic, &spr_write_e500_l1csr1,
2949 0x00000000);
2950 if (version != fsl_e500v1 && version != fsl_e500v2) {
2951 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2952 SPR_NOACCESS, SPR_NOACCESS,
2953 &spr_read_generic, &spr_write_e500_l2csr0,
2954 0x00000000);
2955 }
2956 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2957 SPR_NOACCESS, SPR_NOACCESS,
2958 &spr_read_generic, &spr_write_generic,
2959 0x00000000);
2960 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2961 SPR_NOACCESS, SPR_NOACCESS,
2962 &spr_read_generic, &spr_write_generic,
2963 0x00000000);
2964 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2965 SPR_NOACCESS, SPR_NOACCESS,
2966 &spr_read_generic, &spr_write_booke206_mmucsr0,
2967 0x00000000);
2968 spr_register(env, SPR_BOOKE_EPR, "EPR",
2969 SPR_NOACCESS, SPR_NOACCESS,
2970 &spr_read_generic, SPR_NOACCESS,
2971 0x00000000);
2972 /* XXX better abstract into Emb.xxx features */
2973 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2974 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2975 SPR_NOACCESS, SPR_NOACCESS,
2976 &spr_read_generic, &spr_write_generic,
2977 0x00000000);
2978 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2979 SPR_NOACCESS, SPR_NOACCESS,
2980 &spr_read_mas73, &spr_write_mas73,
2981 0x00000000);
2982 ivpr_mask = (target_ulong)~0xFFFFULL;
2983 }
2984
2985 if (version == fsl_e6500) {
2986 /* Thread identification */
2987 spr_register(env, SPR_TIR, "TIR",
2988 SPR_NOACCESS, SPR_NOACCESS,
2989 &spr_read_generic, SPR_NOACCESS,
2990 0x00000000);
2991 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
2992 SPR_NOACCESS, SPR_NOACCESS,
2993 &spr_read_generic, SPR_NOACCESS,
2994 0x00000004);
2995 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
2996 SPR_NOACCESS, SPR_NOACCESS,
2997 &spr_read_generic, SPR_NOACCESS,
2998 0x7FFFFFFC);
2999 }
3000
3001 #if !defined(CONFIG_USER_ONLY)
3002 env->nb_tlb = 0;
3003 env->tlb_type = TLB_MAS;
3004 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3005 env->nb_tlb += booke206_tlb_size(env, i);
3006 }
3007 #endif
3008
3009 init_excp_e200(env, ivpr_mask);
3010 /* Allocate hardware IRQ controller */
3011 ppce500_irq_init(env_archcpu(env));
3012 }
3013
3014 static void init_proc_e500v1(CPUPPCState *env)
3015 {
3016 init_proc_e500(env, fsl_e500v1);
3017 }
3018
3019 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3020 {
3021 DeviceClass *dc = DEVICE_CLASS(oc);
3022 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3023
3024 dc->desc = "e500v1 core";
3025 pcc->init_proc = init_proc_e500v1;
3026 pcc->check_pow = check_pow_hid0;
3027 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3028 PPC_SPE | PPC_SPE_SINGLE |
3029 PPC_WRTEE | PPC_RFDI |
3030 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3031 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3032 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3033 pcc->insns_flags2 = PPC2_BOOKE206;
3034 pcc->msr_mask = (1ull << MSR_UCLE) |
3035 (1ull << MSR_SPE) |
3036 (1ull << MSR_POW) |
3037 (1ull << MSR_CE) |
3038 (1ull << MSR_EE) |
3039 (1ull << MSR_PR) |
3040 (1ull << MSR_FP) |
3041 (1ull << MSR_ME) |
3042 (1ull << MSR_FE0) |
3043 (1ull << MSR_DWE) |
3044 (1ull << MSR_DE) |
3045 (1ull << MSR_FE1) |
3046 (1ull << MSR_IR) |
3047 (1ull << MSR_DR);
3048 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3049 pcc->excp_model = POWERPC_EXCP_BOOKE;
3050 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3051 pcc->bfd_mach = bfd_mach_ppc_860;
3052 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3053 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3054 POWERPC_FLAG_BUS_CLK;
3055 }
3056
3057 static void init_proc_e500v2(CPUPPCState *env)
3058 {
3059 init_proc_e500(env, fsl_e500v2);
3060 }
3061
3062 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3063 {
3064 DeviceClass *dc = DEVICE_CLASS(oc);
3065 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3066
3067 dc->desc = "e500v2 core";
3068 pcc->init_proc = init_proc_e500v2;
3069 pcc->check_pow = check_pow_hid0;
3070 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3071 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3072 PPC_WRTEE | PPC_RFDI |
3073 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3074 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3075 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3076 pcc->insns_flags2 = PPC2_BOOKE206;
3077 pcc->msr_mask = (1ull << MSR_UCLE) |
3078 (1ull << MSR_SPE) |
3079 (1ull << MSR_POW) |
3080 (1ull << MSR_CE) |
3081 (1ull << MSR_EE) |
3082 (1ull << MSR_PR) |
3083 (1ull << MSR_FP) |
3084 (1ull << MSR_ME) |
3085 (1ull << MSR_FE0) |
3086 (1ull << MSR_DWE) |
3087 (1ull << MSR_DE) |
3088 (1ull << MSR_FE1) |
3089 (1ull << MSR_IR) |
3090 (1ull << MSR_DR);
3091 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3092 pcc->excp_model = POWERPC_EXCP_BOOKE;
3093 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3094 pcc->bfd_mach = bfd_mach_ppc_860;
3095 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3096 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3097 POWERPC_FLAG_BUS_CLK;
3098 }
3099
3100 static void init_proc_e500mc(CPUPPCState *env)
3101 {
3102 init_proc_e500(env, fsl_e500mc);
3103 }
3104
3105 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3106 {
3107 DeviceClass *dc = DEVICE_CLASS(oc);
3108 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3109
3110 dc->desc = "e500mc core";
3111 pcc->init_proc = init_proc_e500mc;
3112 pcc->check_pow = check_pow_none;
3113 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3114 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3115 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3116 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3117 PPC_FLOAT | PPC_FLOAT_FRES |
3118 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3119 PPC_FLOAT_STFIWX | PPC_WAIT |
3120 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3121 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3122 pcc->msr_mask = (1ull << MSR_GS) |
3123 (1ull << MSR_UCLE) |
3124 (1ull << MSR_CE) |
3125 (1ull << MSR_EE) |
3126 (1ull << MSR_PR) |
3127 (1ull << MSR_FP) |
3128 (1ull << MSR_ME) |
3129 (1ull << MSR_FE0) |
3130 (1ull << MSR_DE) |
3131 (1ull << MSR_FE1) |
3132 (1ull << MSR_IR) |
3133 (1ull << MSR_DR) |
3134 (1ull << MSR_PX) |
3135 (1ull << MSR_RI);
3136 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3137 pcc->excp_model = POWERPC_EXCP_BOOKE;
3138 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3139 /* FIXME: figure out the correct flag for e500mc */
3140 pcc->bfd_mach = bfd_mach_ppc_e500;
3141 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3142 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3143 }
3144
3145 #ifdef TARGET_PPC64
3146 static void init_proc_e5500(CPUPPCState *env)
3147 {
3148 init_proc_e500(env, fsl_e5500);
3149 }
3150
3151 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3152 {
3153 DeviceClass *dc = DEVICE_CLASS(oc);
3154 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3155
3156 dc->desc = "e5500 core";
3157 pcc->init_proc = init_proc_e5500;
3158 pcc->check_pow = check_pow_none;
3159 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3160 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3161 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3162 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3163 PPC_FLOAT | PPC_FLOAT_FRES |
3164 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3165 PPC_FLOAT_STFIWX | PPC_WAIT |
3166 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3167 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3168 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3169 PPC2_FP_CVT_S64;
3170 pcc->msr_mask = (1ull << MSR_CM) |
3171 (1ull << MSR_GS) |
3172 (1ull << MSR_UCLE) |
3173 (1ull << MSR_CE) |
3174 (1ull << MSR_EE) |
3175 (1ull << MSR_PR) |
3176 (1ull << MSR_FP) |
3177 (1ull << MSR_ME) |
3178 (1ull << MSR_FE0) |
3179 (1ull << MSR_DE) |
3180 (1ull << MSR_FE1) |
3181 (1ull << MSR_IR) |
3182 (1ull << MSR_DR) |
3183 (1ull << MSR_PX) |
3184 (1ull << MSR_RI);
3185 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3186 pcc->excp_model = POWERPC_EXCP_BOOKE;
3187 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3188 /* FIXME: figure out the correct flag for e5500 */
3189 pcc->bfd_mach = bfd_mach_ppc_e500;
3190 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3191 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3192 }
3193
3194 static void init_proc_e6500(CPUPPCState *env)
3195 {
3196 init_proc_e500(env, fsl_e6500);
3197 }
3198
3199 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3200 {
3201 DeviceClass *dc = DEVICE_CLASS(oc);
3202 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3203
3204 dc->desc = "e6500 core";
3205 pcc->init_proc = init_proc_e6500;
3206 pcc->check_pow = check_pow_none;
3207 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3208 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3209 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3210 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3211 PPC_FLOAT | PPC_FLOAT_FRES |
3212 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3213 PPC_FLOAT_STFIWX | PPC_WAIT |
3214 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3215 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3216 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3217 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3218 pcc->msr_mask = (1ull << MSR_CM) |
3219 (1ull << MSR_GS) |
3220 (1ull << MSR_UCLE) |
3221 (1ull << MSR_CE) |
3222 (1ull << MSR_EE) |
3223 (1ull << MSR_PR) |
3224 (1ull << MSR_FP) |
3225 (1ull << MSR_ME) |
3226 (1ull << MSR_FE0) |
3227 (1ull << MSR_DE) |
3228 (1ull << MSR_FE1) |
3229 (1ull << MSR_IS) |
3230 (1ull << MSR_DS) |
3231 (1ull << MSR_PX) |
3232 (1ull << MSR_RI) |
3233 (1ull << MSR_VR);
3234 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3235 pcc->excp_model = POWERPC_EXCP_BOOKE;
3236 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3237 pcc->bfd_mach = bfd_mach_ppc_e500;
3238 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3239 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3240 }
3241
3242 #endif
3243
3244 /* Non-embedded PowerPC */
3245 static void init_proc_603(CPUPPCState *env)
3246 {
3247 register_non_embedded_sprs(env);
3248 register_sdr1_sprs(env);
3249 register_603_sprs(env);
3250
3251 /* Memory management */
3252 register_low_BATs(env);
3253 register_6xx_7xx_soft_tlb(env, 64, 2);
3254 init_excp_603(env);
3255 env->dcache_line_size = 32;
3256 env->icache_line_size = 32;
3257 /* Allocate hardware IRQ controller */
3258 ppc6xx_irq_init(env_archcpu(env));
3259 }
3260
3261 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3262 {
3263 DeviceClass *dc = DEVICE_CLASS(oc);
3264 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3265
3266 dc->desc = "PowerPC 603";
3267 pcc->init_proc = init_proc_603;
3268 pcc->check_pow = check_pow_hid0;
3269 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3270 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3271 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3272 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3273 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3274 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3275 PPC_SEGMENT | PPC_EXTERN;
3276 pcc->msr_mask = (1ull << MSR_POW) |
3277 (1ull << MSR_TGPR) |
3278 (1ull << MSR_ILE) |
3279 (1ull << MSR_EE) |
3280 (1ull << MSR_PR) |
3281 (1ull << MSR_FP) |
3282 (1ull << MSR_ME) |
3283 (1ull << MSR_FE0) |
3284 (1ull << MSR_SE) |
3285 (1ull << MSR_DE) |
3286 (1ull << MSR_FE1) |
3287 (1ull << MSR_EP) |
3288 (1ull << MSR_IR) |
3289 (1ull << MSR_DR) |
3290 (1ull << MSR_RI) |
3291 (1ull << MSR_LE);
3292 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3293 pcc->excp_model = POWERPC_EXCP_6xx;
3294 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3295 pcc->bfd_mach = bfd_mach_ppc_603;
3296 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3297 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3298 }
3299
3300 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3301 {
3302 DeviceClass *dc = DEVICE_CLASS(oc);
3303 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3304
3305 dc->desc = "PowerPC 603e";
3306 pcc->init_proc = init_proc_603;
3307 pcc->check_pow = check_pow_hid0;
3308 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3309 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3310 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3311 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3312 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3313 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3314 PPC_SEGMENT | PPC_EXTERN;
3315 pcc->msr_mask = (1ull << MSR_POW) |
3316 (1ull << MSR_TGPR) |
3317 (1ull << MSR_ILE) |
3318 (1ull << MSR_EE) |
3319 (1ull << MSR_PR) |
3320 (1ull << MSR_FP) |
3321 (1ull << MSR_ME) |
3322 (1ull << MSR_FE0) |
3323 (1ull << MSR_SE) |
3324 (1ull << MSR_DE) |
3325 (1ull << MSR_FE1) |
3326 (1ull << MSR_EP) |
3327 (1ull << MSR_IR) |
3328 (1ull << MSR_DR) |
3329 (1ull << MSR_RI) |
3330 (1ull << MSR_LE);
3331 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3332 pcc->excp_model = POWERPC_EXCP_6xx;
3333 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3334 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3335 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3336 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3337 }
3338
3339 static void init_proc_e300(CPUPPCState *env)
3340 {
3341 init_proc_603(env);
3342 register_e300_sprs(env);
3343 }
3344
3345 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3346 {
3347 DeviceClass *dc = DEVICE_CLASS(oc);
3348 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3349
3350 dc->desc = "e300 core";
3351 pcc->init_proc = init_proc_e300;
3352 pcc->check_pow = check_pow_hid0;
3353 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3354 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3355 PPC_FLOAT_STFIWX |
3356 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3357 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3358 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3359 PPC_SEGMENT | PPC_EXTERN;
3360 pcc->msr_mask = (1ull << MSR_POW) |
3361 (1ull << MSR_TGPR) |
3362 (1ull << MSR_ILE) |
3363 (1ull << MSR_EE) |
3364 (1ull << MSR_PR) |
3365 (1ull << MSR_FP) |
3366 (1ull << MSR_ME) |
3367 (1ull << MSR_FE0) |
3368 (1ull << MSR_SE) |
3369 (1ull << MSR_DE) |
3370 (1ull << MSR_FE1) |
3371 (1ull << MSR_AL) |
3372 (1ull << MSR_EP) |
3373 (1ull << MSR_IR) |
3374 (1ull << MSR_DR) |
3375 (1ull << MSR_RI) |
3376 (1ull << MSR_LE);
3377 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3378 pcc->excp_model = POWERPC_EXCP_6xx;
3379 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3380 pcc->bfd_mach = bfd_mach_ppc_603;
3381 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3382 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3383 }
3384
3385 static void init_proc_604(CPUPPCState *env)
3386 {
3387 register_non_embedded_sprs(env);
3388 register_sdr1_sprs(env);
3389 register_604_sprs(env);
3390
3391 /* Memory management */
3392 register_low_BATs(env);
3393 init_excp_604(env);
3394 env->dcache_line_size = 32;
3395 env->icache_line_size = 32;
3396 /* Allocate hardware IRQ controller */
3397 ppc6xx_irq_init(env_archcpu(env));
3398 }
3399
3400 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3401 {
3402 DeviceClass *dc = DEVICE_CLASS(oc);
3403 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3404
3405 dc->desc = "PowerPC 604";
3406 pcc->init_proc = init_proc_604;
3407 pcc->check_pow = check_pow_nocheck;
3408 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3409 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3410 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3411 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3412 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3413 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3414 PPC_SEGMENT | PPC_EXTERN;
3415 pcc->msr_mask = (1ull << MSR_POW) |
3416 (1ull << MSR_ILE) |
3417 (1ull << MSR_EE) |
3418 (1ull << MSR_PR) |
3419 (1ull << MSR_FP) |
3420 (1ull << MSR_ME) |
3421 (1ull << MSR_FE0) |
3422 (1ull << MSR_SE) |
3423 (1ull << MSR_DE) |
3424 (1ull << MSR_FE1) |
3425 (1ull << MSR_EP) |
3426 (1ull << MSR_IR) |
3427 (1ull << MSR_DR) |
3428 (1ull << MSR_PMM) |
3429 (1ull << MSR_RI) |
3430 (1ull << MSR_LE);
3431 pcc->mmu_model = POWERPC_MMU_32B;
3432 pcc->excp_model = POWERPC_EXCP_6xx;
3433 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3434 pcc->bfd_mach = bfd_mach_ppc_604;
3435 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3436 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3437 }
3438
3439 static void init_proc_604E(CPUPPCState *env)
3440 {
3441 init_proc_604(env);
3442 register_604e_sprs(env);
3443 }
3444
3445 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3446 {
3447 DeviceClass *dc = DEVICE_CLASS(oc);
3448 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3449
3450 dc->desc = "PowerPC 604E";
3451 pcc->init_proc = init_proc_604E;
3452 pcc->check_pow = check_pow_nocheck;
3453 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3454 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3455 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3456 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3457 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3458 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3459 PPC_SEGMENT | PPC_EXTERN;
3460 pcc->msr_mask = (1ull << MSR_POW) |
3461 (1ull << MSR_ILE) |
3462 (1ull << MSR_EE) |
3463 (1ull << MSR_PR) |
3464 (1ull << MSR_FP) |
3465 (1ull << MSR_ME) |
3466 (1ull << MSR_FE0) |
3467 (1ull << MSR_SE) |
3468 (1ull << MSR_DE) |
3469 (1ull << MSR_FE1) |
3470 (1ull << MSR_EP) |
3471 (1ull << MSR_IR) |
3472 (1ull << MSR_DR) |
3473 (1ull << MSR_PMM) |
3474 (1ull << MSR_RI) |
3475 (1ull << MSR_LE);
3476 pcc->mmu_model = POWERPC_MMU_32B;
3477 pcc->excp_model = POWERPC_EXCP_6xx;
3478 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3479 pcc->bfd_mach = bfd_mach_ppc_604;
3480 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3481 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3482 }
3483
3484 static void init_proc_740(CPUPPCState *env)
3485 {
3486 register_non_embedded_sprs(env);
3487 register_sdr1_sprs(env);
3488 register_7xx_sprs(env);
3489 /* Thermal management */
3490 register_thrm_sprs(env);
3491
3492 /* Memory management */
3493 register_low_BATs(env);
3494 init_excp_7x0(env);
3495 env->dcache_line_size = 32;
3496 env->icache_line_size = 32;
3497 /* Allocate hardware IRQ controller */
3498 ppc6xx_irq_init(env_archcpu(env));
3499 }
3500
3501 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3502 {
3503 DeviceClass *dc = DEVICE_CLASS(oc);
3504 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3505
3506 dc->desc = "PowerPC 740";
3507 pcc->init_proc = init_proc_740;
3508 pcc->check_pow = check_pow_hid0;
3509 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3510 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3511 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3512 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3513 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3514 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3515 PPC_SEGMENT | PPC_EXTERN;
3516 pcc->msr_mask = (1ull << MSR_POW) |
3517 (1ull << MSR_ILE) |
3518 (1ull << MSR_EE) |
3519 (1ull << MSR_PR) |
3520 (1ull << MSR_FP) |
3521 (1ull << MSR_ME) |
3522 (1ull << MSR_FE0) |
3523 (1ull << MSR_SE) |
3524 (1ull << MSR_DE) |
3525 (1ull << MSR_FE1) |
3526 (1ull << MSR_EP) |
3527 (1ull << MSR_IR) |
3528 (1ull << MSR_DR) |
3529 (1ull << MSR_PMM) |
3530 (1ull << MSR_RI) |
3531 (1ull << MSR_LE);
3532 pcc->mmu_model = POWERPC_MMU_32B;
3533 pcc->excp_model = POWERPC_EXCP_7xx;
3534 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3535 pcc->bfd_mach = bfd_mach_ppc_750;
3536 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3537 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3538 }
3539
3540 static void init_proc_750(CPUPPCState *env)
3541 {
3542 register_non_embedded_sprs(env);
3543 register_sdr1_sprs(env);
3544 register_7xx_sprs(env);
3545
3546 spr_register(env, SPR_L2CR, "L2CR",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, spr_access_nop,
3549 0x00000000);
3550 /* Thermal management */
3551 register_thrm_sprs(env);
3552
3553 /* Memory management */
3554 register_low_BATs(env);
3555 /*
3556 * XXX: high BATs are also present but are known to be bugged on
3557 * die version 1.x
3558 */
3559 init_excp_7x0(env);
3560 env->dcache_line_size = 32;
3561 env->icache_line_size = 32;
3562 /* Allocate hardware IRQ controller */
3563 ppc6xx_irq_init(env_archcpu(env));
3564 }
3565
3566 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
3567 {
3568 DeviceClass *dc = DEVICE_CLASS(oc);
3569 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3570
3571 dc->desc = "PowerPC 750";
3572 pcc->init_proc = init_proc_750;
3573 pcc->check_pow = check_pow_hid0;
3574 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3575 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3576 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3577 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3578 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3579 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3580 PPC_SEGMENT | PPC_EXTERN;
3581 pcc->msr_mask = (1ull << MSR_POW) |
3582 (1ull << MSR_ILE) |
3583 (1ull << MSR_EE) |
3584 (1ull << MSR_PR) |
3585 (1ull << MSR_FP) |
3586 (1ull << MSR_ME) |
3587 (1ull << MSR_FE0) |
3588 (1ull << MSR_SE) |
3589 (1ull << MSR_DE) |
3590 (1ull << MSR_FE1) |
3591 (1ull << MSR_EP) |
3592 (1ull << MSR_IR) |
3593 (1ull << MSR_DR) |
3594 (1ull << MSR_PMM) |
3595 (1ull << MSR_RI) |
3596 (1ull << MSR_LE);
3597 pcc->mmu_model = POWERPC_MMU_32B;
3598 pcc->excp_model = POWERPC_EXCP_7xx;
3599 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3600 pcc->bfd_mach = bfd_mach_ppc_750;
3601 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3602 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3603 }
3604
3605 static void init_proc_750cl(CPUPPCState *env)
3606 {
3607 register_non_embedded_sprs(env);
3608 register_sdr1_sprs(env);
3609 register_7xx_sprs(env);
3610
3611 spr_register(env, SPR_L2CR, "L2CR",
3612 SPR_NOACCESS, SPR_NOACCESS,
3613 &spr_read_generic, spr_access_nop,
3614 0x00000000);
3615 /* Thermal management */
3616 /* Those registers are fake on 750CL */
3617 spr_register(env, SPR_THRM1, "THRM1",
3618 SPR_NOACCESS, SPR_NOACCESS,
3619 &spr_read_generic, &spr_write_generic,
3620 0x00000000);
3621 spr_register(env, SPR_THRM2, "THRM2",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 spr_register(env, SPR_THRM3, "THRM3",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629
3630 spr_register(env, SPR_750_TDCL, "TDCL",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_generic,
3633 0x00000000);
3634 spr_register(env, SPR_750_TDCH, "TDCH",
3635 SPR_NOACCESS, SPR_NOACCESS,
3636 &spr_read_generic, &spr_write_generic,
3637 0x00000000);
3638 /* DMA */
3639 spr_register(env, SPR_750_WPAR, "WPAR",
3640 SPR_NOACCESS, SPR_NOACCESS,
3641 &spr_read_generic, &spr_write_generic,
3642 0x00000000);
3643 spr_register(env, SPR_750_DMAL, "DMAL",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 spr_register(env, SPR_750_DMAU, "DMAU",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* Hardware implementation registers */
3652 spr_register(env, SPR_750CL_HID2, "HID2",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656
3657 spr_register(env, SPR_750CL_HID4, "HID4",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661 /* Quantization registers */
3662 spr_register(env, SPR_750_GQR0, "GQR0",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666
3667 spr_register(env, SPR_750_GQR1, "GQR1",
3668 SPR_NOACCESS, SPR_NOACCESS,
3669 &spr_read_generic, &spr_write_generic,
3670 0x00000000);
3671
3672 spr_register(env, SPR_750_GQR2, "GQR2",
3673 SPR_NOACCESS, SPR_NOACCESS,
3674 &spr_read_generic, &spr_write_generic,
3675 0x00000000);
3676
3677 spr_register(env, SPR_750_GQR3, "GQR3",
3678 SPR_NOACCESS, SPR_NOACCESS,
3679 &spr_read_generic, &spr_write_generic,
3680 0x00000000);
3681
3682 spr_register(env, SPR_750_GQR4, "GQR4",
3683 SPR_NOACCESS, SPR_NOACCESS,
3684 &spr_read_generic, &spr_write_generic,
3685 0x00000000);
3686
3687 spr_register(env, SPR_750_GQR5, "GQR5",
3688 SPR_NOACCESS, SPR_NOACCESS,
3689 &spr_read_generic, &spr_write_generic,
3690 0x00000000);
3691
3692 spr_register(env, SPR_750_GQR6, "GQR6",
3693 SPR_NOACCESS, SPR_NOACCESS,
3694 &spr_read_generic, &spr_write_generic,
3695 0x00000000);
3696
3697 spr_register(env, SPR_750_GQR7, "GQR7",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0x00000000);
3701 /* Memory management */
3702 register_low_BATs(env);
3703 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3704 register_high_BATs(env);
3705 init_excp_750cl(env);
3706 env->dcache_line_size = 32;
3707 env->icache_line_size = 32;
3708 /* Allocate hardware IRQ controller */
3709 ppc6xx_irq_init(env_archcpu(env));
3710 }
3711
3712 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
3713 {
3714 DeviceClass *dc = DEVICE_CLASS(oc);
3715 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3716
3717 dc->desc = "PowerPC 750 CL";
3718 pcc->init_proc = init_proc_750cl;
3719 pcc->check_pow = check_pow_hid0;
3720 /*
3721 * XXX: not implemented:
3722 * cache lock instructions:
3723 * dcbz_l
3724 * floating point paired instructions
3725 * psq_lux
3726 * psq_lx
3727 * psq_stux
3728 * psq_stx
3729 * ps_abs
3730 * ps_add
3731 * ps_cmpo0
3732 * ps_cmpo1
3733 * ps_cmpu0
3734 * ps_cmpu1
3735 * ps_div
3736 * ps_madd
3737 * ps_madds0
3738 * ps_madds1
3739 * ps_merge00
3740 * ps_merge01
3741 * ps_merge10
3742 * ps_merge11
3743 * ps_mr
3744 * ps_msub
3745 * ps_mul
3746 * ps_muls0
3747 * ps_muls1
3748 * ps_nabs
3749 * ps_neg
3750 * ps_nmadd
3751 * ps_nmsub
3752 * ps_res
3753 * ps_rsqrte
3754 * ps_sel
3755 * ps_sub
3756 * ps_sum0
3757 * ps_sum1
3758 */
3759 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3760 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3761 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3762 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3763 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3764 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3765 PPC_SEGMENT | PPC_EXTERN;
3766 pcc->msr_mask = (1ull << MSR_POW) |
3767 (1ull << MSR_ILE) |
3768 (1ull << MSR_EE) |
3769 (1ull << MSR_PR) |
3770 (1ull << MSR_FP) |
3771 (1ull << MSR_ME) |
3772 (1ull << MSR_FE0) |
3773 (1ull << MSR_SE) |
3774 (1ull << MSR_DE) |
3775 (1ull << MSR_FE1) |
3776 (1ull << MSR_EP) |
3777 (1ull << MSR_IR) |
3778 (1ull << MSR_DR) |
3779 (1ull << MSR_PMM) |
3780 (1ull << MSR_RI) |
3781 (1ull << MSR_LE);
3782 pcc->mmu_model = POWERPC_MMU_32B;
3783 pcc->excp_model = POWERPC_EXCP_7xx;
3784 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3785 pcc->bfd_mach = bfd_mach_ppc_750;
3786 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3787 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3788 }
3789
3790 static void init_proc_750cx(CPUPPCState *env)
3791 {
3792 register_non_embedded_sprs(env);
3793 register_sdr1_sprs(env);
3794 register_7xx_sprs(env);
3795
3796 spr_register(env, SPR_L2CR, "L2CR",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, spr_access_nop,
3799 0x00000000);
3800 /* Thermal management */
3801 register_thrm_sprs(env);
3802
3803 spr_register(env, SPR_SDA, "SDA",
3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_generic,
3806 0x00000000);
3807
3808 /* Memory management */
3809 register_low_BATs(env);
3810 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3811 register_high_BATs(env);
3812 init_excp_750cx(env);
3813 env->dcache_line_size = 32;
3814 env->icache_line_size = 32;
3815 /* Allocate hardware IRQ controller */
3816 ppc6xx_irq_init(env_archcpu(env));
3817 }
3818
3819 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
3820 {
3821 DeviceClass *dc = DEVICE_CLASS(oc);
3822 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3823
3824 dc->desc = "PowerPC 750CX";
3825 pcc->init_proc = init_proc_750cx;
3826 pcc->check_pow = check_pow_hid0;
3827 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3828 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3829 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3830 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3831 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3832 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3833 PPC_SEGMENT | PPC_EXTERN;
3834 pcc->msr_mask = (1ull << MSR_POW) |
3835 (1ull << MSR_ILE) |
3836 (1ull << MSR_EE) |
3837 (1ull << MSR_PR) |
3838 (1ull << MSR_FP) |
3839 (1ull << MSR_ME) |
3840 (1ull << MSR_FE0) |
3841 (1ull << MSR_SE) |
3842 (1ull << MSR_DE) |
3843 (1ull << MSR_FE1) |
3844 (1ull << MSR_EP) |
3845 (1ull << MSR_IR) |
3846 (1ull << MSR_DR) |
3847 (1ull << MSR_PMM) |
3848 (1ull << MSR_RI) |
3849 (1ull << MSR_LE);
3850 pcc->mmu_model = POWERPC_MMU_32B;
3851 pcc->excp_model = POWERPC_EXCP_7xx;
3852 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3853 pcc->bfd_mach = bfd_mach_ppc_750;
3854 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3855 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3856 }
3857
3858 static void init_proc_750fx(CPUPPCState *env)
3859 {
3860 register_non_embedded_sprs(env);
3861 register_sdr1_sprs(env);
3862 register_7xx_sprs(env);
3863
3864 spr_register(env, SPR_L2CR, "L2CR",
3865 SPR_NOACCESS, SPR_NOACCESS,
3866 &spr_read_generic, spr_access_nop,
3867 0x00000000);
3868 /* Thermal management */
3869 register_thrm_sprs(env);
3870
3871 spr_register(env, SPR_750_THRM4, "THRM4",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 /* Hardware implementation registers */
3876 spr_register(env, SPR_750FX_HID2, "HID2",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 /* Memory management */
3881 register_low_BATs(env);
3882 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3883 register_high_BATs(env);
3884 init_excp_7x0(env);
3885 env->dcache_line_size = 32;
3886 env->icache_line_size = 32;
3887 /* Allocate hardware IRQ controller */
3888 ppc6xx_irq_init(env_archcpu(env));
3889 }
3890
3891 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
3892 {
3893 DeviceClass *dc = DEVICE_CLASS(oc);
3894 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3895
3896 dc->desc = "PowerPC 750FX";
3897 pcc->init_proc = init_proc_750fx;
3898 pcc->check_pow = check_pow_hid0;
3899 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3900 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3901 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3902 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3903 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3904 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3905 PPC_SEGMENT | PPC_EXTERN;
3906 pcc->msr_mask = (1ull << MSR_POW) |
3907 (1ull << MSR_ILE) |
3908 (1ull << MSR_EE) |
3909 (1ull << MSR_PR) |
3910 (1ull << MSR_FP) |
3911 (1ull << MSR_ME) |
3912 (1ull << MSR_FE0) |
3913 (1ull << MSR_SE) |
3914 (1ull << MSR_DE) |
3915 (1ull << MSR_FE1) |
3916 (1ull << MSR_EP) |
3917 (1ull << MSR_IR) |
3918 (1ull << MSR_DR) |
3919 (1ull << MSR_PMM) |
3920 (1ull << MSR_RI) |
3921 (1ull << MSR_LE);
3922 pcc->mmu_model = POWERPC_MMU_32B;
3923 pcc->excp_model = POWERPC_EXCP_7xx;
3924 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3925 pcc->bfd_mach = bfd_mach_ppc_750;
3926 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3927 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3928 }
3929
3930 static void init_proc_750gx(CPUPPCState *env)
3931 {
3932 register_non_embedded_sprs(env);
3933 register_sdr1_sprs(env);
3934 register_7xx_sprs(env);
3935
3936 spr_register(env, SPR_L2CR, "L2CR",
3937 SPR_NOACCESS, SPR_NOACCESS,
3938 &spr_read_generic, spr_access_nop,
3939 0x00000000);
3940 /* Thermal management */
3941 register_thrm_sprs(env);
3942
3943 spr_register(env, SPR_750_THRM4, "THRM4",
3944 SPR_NOACCESS, SPR_NOACCESS,
3945 &spr_read_generic, &spr_write_generic,
3946 0x00000000);
3947 /* Hardware implementation registers */
3948 spr_register(env, SPR_750FX_HID2, "HID2",
3949 SPR_NOACCESS, SPR_NOACCESS,
3950 &spr_read_generic, &spr_write_generic,
3951 0x00000000);
3952 /* Memory management */
3953 register_low_BATs(env);
3954 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3955 register_high_BATs(env);
3956 init_excp_7x0(env);
3957 env->dcache_line_size = 32;
3958 env->icache_line_size = 32;
3959 /* Allocate hardware IRQ controller */
3960 ppc6xx_irq_init(env_archcpu(env));
3961 }
3962
3963 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
3964 {
3965 DeviceClass *dc = DEVICE_CLASS(oc);
3966 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3967
3968 dc->desc = "PowerPC 750GX";
3969 pcc->init_proc = init_proc_750gx;
3970 pcc->check_pow = check_pow_hid0;
3971 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3972 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3973 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3974 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3975 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3976 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3977 PPC_SEGMENT | PPC_EXTERN;
3978 pcc->msr_mask = (1ull << MSR_POW) |
3979 (1ull << MSR_ILE) |
3980 (1ull << MSR_EE) |
3981 (1ull << MSR_PR) |
3982 (1ull << MSR_FP) |
3983 (1ull << MSR_ME) |
3984 (1ull << MSR_FE0) |
3985 (1ull << MSR_SE) |
3986 (1ull << MSR_DE) |
3987 (1ull << MSR_FE1) |
3988 (1ull << MSR_EP) |
3989 (1ull << MSR_IR) |
3990 (1ull << MSR_DR) |
3991 (1ull << MSR_PMM) |
3992 (1ull << MSR_RI) |
3993 (1ull << MSR_LE);
3994 pcc->mmu_model = POWERPC_MMU_32B;
3995 pcc->excp_model = POWERPC_EXCP_7xx;
3996 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3997 pcc->bfd_mach = bfd_mach_ppc_750;
3998 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3999 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4000 }
4001
4002 static void init_proc_745(CPUPPCState *env)
4003 {
4004 register_non_embedded_sprs(env);
4005 register_sdr1_sprs(env);
4006 register_7xx_sprs(env);
4007 register_745_sprs(env);
4008 /* Thermal management */
4009 register_thrm_sprs(env);
4010
4011 /* Memory management */
4012 register_low_BATs(env);
4013 register_high_BATs(env);
4014 register_6xx_7xx_soft_tlb(env, 64, 2);
4015 init_excp_7x5(env);
4016 env->dcache_line_size = 32;
4017 env->icache_line_size = 32;
4018 /* Allocate hardware IRQ controller */
4019 ppc6xx_irq_init(env_archcpu(env));
4020 }
4021
4022 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4023 {
4024 DeviceClass *dc = DEVICE_CLASS(oc);
4025 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4026
4027 dc->desc = "PowerPC 745";
4028 pcc->init_proc = init_proc_745;
4029 pcc->check_pow = check_pow_hid0;
4030 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4031 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4032 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4033 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4034 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4035 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4036 PPC_SEGMENT | PPC_EXTERN;
4037 pcc->msr_mask = (1ull << MSR_POW) |
4038 (1ull << MSR_ILE) |
4039 (1ull << MSR_EE) |
4040 (1ull << MSR_PR) |
4041 (1ull << MSR_FP) |
4042 (1ull << MSR_ME) |
4043 (1ull << MSR_FE0) |
4044 (1ull << MSR_SE) |
4045 (1ull << MSR_DE) |
4046 (1ull << MSR_FE1) |
4047 (1ull << MSR_EP) |
4048 (1ull << MSR_IR) |
4049 (1ull << MSR_DR) |
4050 (1ull << MSR_PMM) |
4051 (1ull << MSR_RI) |
4052 (1ull << MSR_LE);
4053 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4054 pcc->excp_model = POWERPC_EXCP_7xx;
4055 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4056 pcc->bfd_mach = bfd_mach_ppc_750;
4057 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4058 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4059 }
4060
4061 static void init_proc_755(CPUPPCState *env)
4062 {
4063 init_proc_745(env);
4064 register_755_sprs(env);
4065 }
4066
4067 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4068 {
4069 DeviceClass *dc = DEVICE_CLASS(oc);
4070 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4071
4072 dc->desc = "PowerPC 755";
4073 pcc->init_proc = init_proc_755;
4074 pcc->check_pow = check_pow_hid0;
4075 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4077 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4078 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4079 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4080 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4081 PPC_SEGMENT | PPC_EXTERN;
4082 pcc->msr_mask = (1ull << MSR_POW) |
4083 (1ull << MSR_ILE) |
4084 (1ull << MSR_EE) |
4085 (1ull << MSR_PR) |
4086 (1ull << MSR_FP) |
4087 (1ull << MSR_ME) |
4088 (1ull << MSR_FE0) |
4089 (1ull << MSR_SE) |
4090 (1ull << MSR_DE) |
4091 (1ull << MSR_FE1) |
4092 (1ull << MSR_EP) |
4093 (1ull << MSR_IR) |
4094 (1ull << MSR_DR) |
4095 (1ull << MSR_PMM) |
4096 (1ull << MSR_RI) |
4097 (1ull << MSR_LE);
4098 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4099 pcc->excp_model = POWERPC_EXCP_7xx;
4100 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4101 pcc->bfd_mach = bfd_mach_ppc_750;
4102 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4103 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4104 }
4105
4106 static void init_proc_7400(CPUPPCState *env)
4107 {
4108 register_non_embedded_sprs(env);
4109 register_sdr1_sprs(env);
4110 register_74xx_sprs(env);
4111 vscr_init(env, 0x00010000);
4112
4113 spr_register(env, SPR_UBAMR, "UBAMR",
4114 &spr_read_ureg, SPR_NOACCESS,
4115 &spr_read_ureg, SPR_NOACCESS,
4116 0x00000000);
4117
4118 spr_register(env, SPR_MSSCR1, "MSSCR1",
4119 SPR_NOACCESS, SPR_NOACCESS,
4120 &spr_read_generic, &spr_write_generic,
4121 0x00000000);
4122 /* Thermal management */
4123 register_thrm_sprs(env);
4124 /* Memory management */
4125 register_low_BATs(env);
4126 init_excp_7400(env);
4127 env->dcache_line_size = 32;
4128 env->icache_line_size = 32;
4129 /* Allocate hardware IRQ controller */
4130 ppc6xx_irq_init(env_archcpu(env));
4131 }
4132
4133 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4134 {
4135 DeviceClass *dc = DEVICE_CLASS(oc);
4136 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4137
4138 dc->desc = "PowerPC 7400 (aka G4)";
4139 pcc->init_proc = init_proc_7400;
4140 pcc->check_pow = check_pow_hid0;
4141 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4142 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4143 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4144 PPC_FLOAT_STFIWX |
4145 PPC_CACHE | PPC_CACHE_ICBI |
4146 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4147 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4148 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4149 PPC_MEM_TLBIA |
4150 PPC_SEGMENT | PPC_EXTERN |
4151 PPC_ALTIVEC;
4152 pcc->msr_mask = (1ull << MSR_VR) |
4153 (1ull << MSR_POW) |
4154 (1ull << MSR_ILE) |
4155 (1ull << MSR_EE) |
4156 (1ull << MSR_PR) |
4157 (1ull << MSR_FP) |
4158 (1ull << MSR_ME) |
4159 (1ull << MSR_FE0) |
4160 (1ull << MSR_SE) |
4161 (1ull << MSR_DE) |
4162 (1ull << MSR_FE1) |
4163 (1ull << MSR_EP) |
4164 (1ull << MSR_IR) |
4165 (1ull << MSR_DR) |
4166 (1ull << MSR_PMM) |
4167 (1ull << MSR_RI) |
4168 (1ull << MSR_LE);
4169 pcc->mmu_model = POWERPC_MMU_32B;
4170 pcc->excp_model = POWERPC_EXCP_74xx;
4171 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4172 pcc->bfd_mach = bfd_mach_ppc_7400;
4173 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4174 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4175 POWERPC_FLAG_BUS_CLK;
4176 }
4177
4178 static void init_proc_7410(CPUPPCState *env)
4179 {
4180 register_non_embedded_sprs(env);
4181 register_sdr1_sprs(env);
4182 register_74xx_sprs(env);
4183 vscr_init(env, 0x00010000);
4184
4185 spr_register(env, SPR_UBAMR, "UBAMR",
4186 &spr_read_ureg, SPR_NOACCESS,
4187 &spr_read_ureg, SPR_NOACCESS,
4188 0x00000000);
4189 /* Thermal management */
4190 register_thrm_sprs(env);
4191 /* L2PMCR */
4192
4193 spr_register(env, SPR_L2PMCR, "L2PMCR",
4194 SPR_NOACCESS, SPR_NOACCESS,
4195 &spr_read_generic, &spr_write_generic,
4196 0x00000000);
4197 /* LDSTDB */
4198
4199 spr_register(env, SPR_LDSTDB, "LDSTDB",
4200 SPR_NOACCESS, SPR_NOACCESS,
4201 &spr_read_generic, &spr_write_generic,
4202 0x00000000);
4203 /* Memory management */
4204 register_low_BATs(env);
4205 init_excp_7400(env);
4206 env->dcache_line_size = 32;
4207 env->icache_line_size = 32;
4208 /* Allocate hardware IRQ controller */
4209 ppc6xx_irq_init(env_archcpu(env));
4210 }
4211
4212 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4213 {
4214 DeviceClass *dc = DEVICE_CLASS(oc);
4215 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4216
4217 dc->desc = "PowerPC 7410 (aka G4)";
4218 pcc->init_proc = init_proc_7410;
4219 pcc->check_pow = check_pow_hid0;
4220 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4221 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4222 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4223 PPC_FLOAT_STFIWX |
4224 PPC_CACHE | PPC_CACHE_ICBI |
4225 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4226 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4227 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4228 PPC_MEM_TLBIA |
4229 PPC_SEGMENT | PPC_EXTERN |
4230 PPC_ALTIVEC;
4231 pcc->msr_mask = (1ull << MSR_VR) |
4232 (1ull << MSR_POW) |
4233 (1ull << MSR_ILE) |
4234 (1ull << MSR_EE) |
4235 (1ull << MSR_PR) |
4236 (1ull << MSR_FP) |
4237 (1ull << MSR_ME) |
4238 (1ull << MSR_FE0) |
4239 (1ull << MSR_SE) |
4240 (1ull << MSR_DE) |
4241 (1ull << MSR_FE1) |
4242 (1ull << MSR_EP) |
4243 (1ull << MSR_IR) |
4244 (1ull << MSR_DR) |
4245 (1ull << MSR_PMM) |
4246 (1ull << MSR_RI) |
4247 (1ull << MSR_LE);
4248 pcc->mmu_model = POWERPC_MMU_32B;
4249 pcc->excp_model = POWERPC_EXCP_74xx;
4250 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4251 pcc->bfd_mach = bfd_mach_ppc_7400;
4252 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4253 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4254 POWERPC_FLAG_BUS_CLK;
4255 }
4256
4257 static void init_proc_7440(CPUPPCState *env)
4258 {
4259 register_non_embedded_sprs(env);
4260 register_sdr1_sprs(env);
4261 register_74xx_sprs(env);
4262 vscr_init(env, 0x00010000);
4263
4264 spr_register(env, SPR_UBAMR, "UBAMR",
4265 &spr_read_ureg, SPR_NOACCESS,
4266 &spr_read_ureg, SPR_NOACCESS,
4267 0x00000000);
4268 /* LDSTCR */
4269 spr_register(env, SPR_LDSTCR, "LDSTCR",
4270 SPR_NOACCESS, SPR_NOACCESS,
4271 &spr_read_generic, &spr_write_generic,
4272 0x00000000);
4273 /* ICTRL */
4274 spr_register(env, SPR_ICTRL, "ICTRL",
4275 SPR_NOACCESS, SPR_NOACCESS,
4276 &spr_read_generic, &spr_write_generic,
4277 0x00000000);
4278 /* MSSSR0 */
4279 spr_register(env, SPR_MSSSR0, "MSSSR0",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000);
4283 /* PMC */
4284 spr_register(env, SPR_7XX_PMC5, "PMC5",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288
4289 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4290 &spr_read_ureg, SPR_NOACCESS,
4291 &spr_read_ureg, SPR_NOACCESS,
4292 0x00000000);
4293
4294 spr_register(env, SPR_7XX_PMC6, "PMC6",
4295 SPR_NOACCESS, SPR_NOACCESS,
4296 &spr_read_generic, &spr_write_generic,
4297 0x00000000);
4298
4299 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4300 &spr_read_ureg, SPR_NOACCESS,
4301 &spr_read_ureg, SPR_NOACCESS,
4302 0x00000000);
4303 /* Memory management */
4304 register_low_BATs(env);
4305 init_excp_7450(env);
4306 env->dcache_line_size = 32;
4307 env->icache_line_size = 32;
4308 /* Allocate hardware IRQ controller */
4309 ppc6xx_irq_init(env_archcpu(env));
4310 }
4311
4312 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4313 {
4314 DeviceClass *dc = DEVICE_CLASS(oc);
4315 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4316
4317 dc->desc = "PowerPC 7440 (aka G4)";
4318 pcc->init_proc = init_proc_7440;
4319 pcc->check_pow = check_pow_hid0_74xx;
4320 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4321 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4322 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4323 PPC_FLOAT_STFIWX |
4324 PPC_CACHE | PPC_CACHE_ICBI |
4325 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4326 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4327 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4328 PPC_MEM_TLBIA |
4329 PPC_SEGMENT | PPC_EXTERN |
4330 PPC_ALTIVEC;
4331 pcc->msr_mask = (1ull << MSR_VR) |
4332 (1ull << MSR_POW) |
4333 (1ull << MSR_ILE) |
4334 (1ull << MSR_EE) |
4335 (1ull << MSR_PR) |
4336 (1ull << MSR_FP) |
4337 (1ull << MSR_ME) |
4338 (1ull << MSR_FE0) |
4339 (1ull << MSR_SE) |
4340 (1ull << MSR_DE) |
4341 (1ull << MSR_FE1) |
4342 (1ull << MSR_EP) |
4343 (1ull << MSR_IR) |
4344 (1ull << MSR_DR) |
4345 (1ull << MSR_PMM) |
4346 (1ull << MSR_RI) |
4347 (1ull << MSR_LE);
4348 pcc->mmu_model = POWERPC_MMU_32B;
4349 pcc->excp_model = POWERPC_EXCP_74xx;
4350 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4351 pcc->bfd_mach = bfd_mach_ppc_7400;
4352 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4353 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4354 POWERPC_FLAG_BUS_CLK;
4355 }
4356
4357 static void init_proc_7450(CPUPPCState *env)
4358 {
4359 register_non_embedded_sprs(env);
4360 register_sdr1_sprs(env);
4361 register_74xx_sprs(env);
4362 vscr_init(env, 0x00010000);
4363 /* Level 3 cache control */
4364 register_l3_ctrl(env);
4365 /* L3ITCR1 */
4366 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4367 SPR_NOACCESS, SPR_NOACCESS,
4368 &spr_read_generic, &spr_write_generic,
4369 0x00000000);
4370 /* L3ITCR2 */
4371 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4372 SPR_NOACCESS, SPR_NOACCESS,
4373 &spr_read_generic, &spr_write_generic,
4374 0x00000000);
4375 /* L3ITCR3 */
4376 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4377 SPR_NOACCESS, SPR_NOACCESS,
4378 &spr_read_generic, &spr_write_generic,
4379 0x00000000);
4380 /* L3OHCR */
4381 spr_register(env, SPR_L3OHCR, "L3OHCR",
4382 SPR_NOACCESS, SPR_NOACCESS,
4383 &spr_read_generic, &spr_write_generic,
4384 0x00000000);
4385
4386 spr_register(env, SPR_UBAMR, "UBAMR",
4387 &spr_read_ureg, SPR_NOACCESS,
4388 &spr_read_ureg, SPR_NOACCESS,
4389 0x00000000);
4390 /* LDSTCR */
4391 spr_register(env, SPR_LDSTCR, "LDSTCR",
4392 SPR_NOACCESS, SPR_NOACCESS,
4393 &spr_read_generic, &spr_write_generic,
4394 0x00000000);
4395 /* ICTRL */
4396 spr_register(env, SPR_ICTRL, "ICTRL",
4397 SPR_NOACCESS, SPR_NOACCESS,
4398 &spr_read_generic, &spr_write_generic,
4399 0x00000000);
4400 /* MSSSR0 */
4401 spr_register(env, SPR_MSSSR0, "MSSSR0",
4402 SPR_NOACCESS, SPR_NOACCESS,
4403 &spr_read_generic, &spr_write_generic,
4404 0x00000000);
4405 /* PMC */
4406 spr_register(env, SPR_7XX_PMC5, "PMC5",
4407 SPR_NOACCESS, SPR_NOACCESS,
4408 &spr_read_generic, &spr_write_generic,
4409 0x00000000);
4410
4411 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4412 &spr_read_ureg, SPR_NOACCESS,
4413 &spr_read_ureg, SPR_NOACCESS,
4414 0x00000000);
4415
4416 spr_register(env, SPR_7XX_PMC6, "PMC6",
4417 SPR_NOACCESS, SPR_NOACCESS,
4418 &spr_read_generic, &spr_write_generic,
4419 0x00000000);
4420
4421 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4422 &spr_read_ureg, SPR_NOACCESS,
4423 &spr_read_ureg, SPR_NOACCESS,
4424 0x00000000);
4425 /* Memory management */
4426 register_low_BATs(env);
4427 init_excp_7450(env);
4428 env->dcache_line_size = 32;
4429 env->icache_line_size = 32;
4430 /* Allocate hardware IRQ controller */
4431 ppc6xx_irq_init(env_archcpu(env));
4432 }
4433
4434 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4435 {
4436 DeviceClass *dc = DEVICE_CLASS(oc);
4437 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4438
4439 dc->desc = "PowerPC 7450 (aka G4)";
4440 pcc->init_proc = init_proc_7450;
4441 pcc->check_pow = check_pow_hid0_74xx;
4442 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4443 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4444 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4445 PPC_FLOAT_STFIWX |
4446 PPC_CACHE | PPC_CACHE_ICBI |
4447 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4448 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4449 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4450 PPC_MEM_TLBIA |
4451 PPC_SEGMENT | PPC_EXTERN |
4452 PPC_ALTIVEC;
4453 pcc->msr_mask = (1ull << MSR_VR) |
4454 (1ull << MSR_POW) |
4455 (1ull << MSR_ILE) |
4456 (1ull << MSR_EE) |
4457 (1ull << MSR_PR) |
4458 (1ull << MSR_FP) |
4459 (1ull << MSR_ME) |
4460 (1ull << MSR_FE0) |
4461 (1ull << MSR_SE) |
4462 (1ull << MSR_DE) |
4463 (1ull << MSR_FE1) |
4464 (1ull << MSR_EP) |
4465 (1ull << MSR_IR) |
4466 (1ull << MSR_DR) |
4467 (1ull << MSR_PMM) |
4468 (1ull << MSR_RI) |
4469 (1ull << MSR_LE);
4470 pcc->mmu_model = POWERPC_MMU_32B;
4471 pcc->excp_model = POWERPC_EXCP_74xx;
4472 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4473 pcc->bfd_mach = bfd_mach_ppc_7400;
4474 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4475 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4476 POWERPC_FLAG_BUS_CLK;
4477 }
4478
4479 static void init_proc_7445(CPUPPCState *env)
4480 {
4481 register_non_embedded_sprs(env);
4482 register_sdr1_sprs(env);
4483 register_74xx_sprs(env);
4484 vscr_init(env, 0x00010000);
4485 /* LDSTCR */
4486 spr_register(env, SPR_LDSTCR, "LDSTCR",
4487 SPR_NOACCESS, SPR_NOACCESS,
4488 &spr_read_generic, &spr_write_generic,
4489 0x00000000);
4490 /* ICTRL */
4491 spr_register(env, SPR_ICTRL, "ICTRL",
4492 SPR_NOACCESS, SPR_NOACCESS,
4493 &spr_read_generic, &spr_write_generic,
4494 0x00000000);
4495 /* MSSSR0 */
4496 spr_register(env, SPR_MSSSR0, "MSSSR0",
4497 SPR_NOACCESS, SPR_NOACCESS,
4498 &spr_read_generic, &spr_write_generic,
4499 0x00000000);
4500 /* PMC */
4501 spr_register(env, SPR_7XX_PMC5, "PMC5",
4502 SPR_NOACCESS, SPR_NOACCESS,
4503 &spr_read_generic, &spr_write_generic,
4504 0x00000000);
4505
4506 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4507 &spr_read_ureg, SPR_NOACCESS,
4508 &spr_read_ureg, SPR_NOACCESS,
4509 0x00000000);
4510
4511 spr_register(env, SPR_7XX_PMC6, "PMC6",
4512 SPR_NOACCESS, SPR_NOACCESS,
4513 &spr_read_generic, &spr_write_generic,
4514 0x00000000);
4515
4516 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4517 &spr_read_ureg, SPR_NOACCESS,
4518 &spr_read_ureg, SPR_NOACCESS,
4519 0x00000000);
4520 /* SPRGs */
4521 spr_register(env, SPR_SPRG4, "SPRG4",
4522 SPR_NOACCESS, SPR_NOACCESS,
4523 &spr_read_generic, &spr_write_generic,
4524 0x00000000);
4525 spr_register(env, SPR_USPRG4, "USPRG4",
4526 &spr_read_ureg, SPR_NOACCESS,
4527 &spr_read_ureg, SPR_NOACCESS,
4528 0x00000000);
4529 spr_register(env, SPR_SPRG5, "SPRG5",
4530 SPR_NOACCESS, SPR_NOACCESS,
4531 &spr_read_generic, &spr_write_generic,
4532 0x00000000);
4533 spr_register(env, SPR_USPRG5, "USPRG5",
4534 &spr_read_ureg, SPR_NOACCESS,
4535 &spr_read_ureg, SPR_NOACCESS,
4536 0x00000000);
4537 spr_register(env, SPR_SPRG6, "SPRG6",
4538 SPR_NOACCESS, SPR_NOACCESS,
4539 &spr_read_generic, &spr_write_generic,
4540 0x00000000);
4541 spr_register(env, SPR_USPRG6, "USPRG6",
4542 &spr_read_ureg, SPR_NOACCESS,
4543 &spr_read_ureg, SPR_NOACCESS,
4544 0x00000000);
4545 spr_register(env, SPR_SPRG7, "SPRG7",
4546 SPR_NOACCESS, SPR_NOACCESS,
4547 &spr_read_generic, &spr_write_generic,
4548 0x00000000);
4549 spr_register(env, SPR_USPRG7, "USPRG7",
4550 &spr_read_ureg, SPR_NOACCESS,
4551 &spr_read_ureg, SPR_NOACCESS,
4552 0x00000000);
4553 /* Memory management */
4554 register_low_BATs(env);
4555 register_high_BATs(env);
4556 init_excp_7450(env);
4557 env->dcache_line_size = 32;
4558 env->icache_line_size = 32;
4559 /* Allocate hardware IRQ controller */
4560 ppc6xx_irq_init(env_archcpu(env));
4561 }
4562
4563 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
4564 {
4565 DeviceClass *dc = DEVICE_CLASS(oc);
4566 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4567
4568 dc->desc = "PowerPC 7445 (aka G4)";
4569 pcc->init_proc = init_proc_7445;
4570 pcc->check_pow = check_pow_hid0_74xx;
4571 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4572 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4573 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4574 PPC_FLOAT_STFIWX |
4575 PPC_CACHE | PPC_CACHE_ICBI |
4576 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4577 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4578 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4579 PPC_MEM_TLBIA |
4580 PPC_SEGMENT | PPC_EXTERN |
4581 PPC_ALTIVEC;
4582 pcc->msr_mask = (1ull << MSR_VR) |
4583 (1ull << MSR_POW) |
4584 (1ull << MSR_ILE) |
4585 (1ull << MSR_EE) |
4586 (1ull << MSR_PR) |
4587 (1ull << MSR_FP) |
4588 (1ull << MSR_ME) |
4589 (1ull << MSR_FE0) |
4590 (1ull << MSR_SE) |
4591 (1ull << MSR_DE) |
4592 (1ull << MSR_FE1) |
4593 (1ull << MSR_EP) |
4594 (1ull << MSR_IR) |
4595 (1ull << MSR_DR) |
4596 (1ull << MSR_PMM) |
4597 (1ull << MSR_RI) |
4598 (1ull << MSR_LE);
4599 pcc->mmu_model = POWERPC_MMU_32B;
4600 pcc->excp_model = POWERPC_EXCP_74xx;
4601 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4602 pcc->bfd_mach = bfd_mach_ppc_7400;
4603 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4604 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4605 POWERPC_FLAG_BUS_CLK;
4606 }
4607
4608 static void init_proc_7455(CPUPPCState *env)
4609 {
4610 register_non_embedded_sprs(env);
4611 register_sdr1_sprs(env);
4612 register_74xx_sprs(env);
4613 vscr_init(env, 0x00010000);
4614 /* Level 3 cache control */
4615 register_l3_ctrl(env);
4616 /* LDSTCR */
4617 spr_register(env, SPR_LDSTCR, "LDSTCR",
4618 SPR_NOACCESS, SPR_NOACCESS,
4619 &spr_read_generic, &spr_write_generic,
4620 0x00000000);
4621 /* ICTRL */
4622 spr_register(env, SPR_ICTRL, "ICTRL",
4623 SPR_NOACCESS, SPR_NOACCESS,
4624 &spr_read_generic, &spr_write_generic,
4625 0x00000000);
4626 /* MSSSR0 */
4627 spr_register(env, SPR_MSSSR0, "MSSSR0",
4628 SPR_NOACCESS, SPR_NOACCESS,
4629 &spr_read_generic, &spr_write_generic,
4630 0x00000000);
4631 /* PMC */
4632 spr_register(env, SPR_7XX_PMC5, "PMC5",
4633 SPR_NOACCESS, SPR_NOACCESS,
4634 &spr_read_generic, &spr_write_generic,
4635 0x00000000);
4636
4637 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4638 &spr_read_ureg, SPR_NOACCESS,
4639 &spr_read_ureg, SPR_NOACCESS,
4640 0x00000000);
4641
4642 spr_register(env, SPR_7XX_PMC6, "PMC6",
4643 SPR_NOACCESS, SPR_NOACCESS,
4644 &spr_read_generic, &spr_write_generic,
4645 0x00000000);
4646
4647 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4648 &spr_read_ureg, SPR_NOACCESS,
4649 &spr_read_ureg, SPR_NOACCESS,
4650 0x00000000);
4651 /* SPRGs */
4652 spr_register(env, SPR_SPRG4, "SPRG4",
4653 SPR_NOACCESS, SPR_NOACCESS,
4654 &spr_read_generic, &spr_write_generic,
4655 0x00000000);
4656 spr_register(env, SPR_USPRG4, "USPRG4",
4657 &spr_read_ureg, SPR_NOACCESS,
4658 &spr_read_ureg, SPR_NOACCESS,
4659 0x00000000);
4660 spr_register(env, SPR_SPRG5, "SPRG5",
4661 SPR_NOACCESS, SPR_NOACCESS,
4662 &spr_read_generic, &spr_write_generic,
4663 0x00000000);
4664 spr_register(env, SPR_USPRG5, "USPRG5",
4665 &spr_read_ureg, SPR_NOACCESS,
4666 &spr_read_ureg, SPR_NOACCESS,
4667 0x00000000);
4668 spr_register(env, SPR_SPRG6, "SPRG6",
4669 SPR_NOACCESS, SPR_NOACCESS,
4670 &spr_read_generic, &spr_write_generic,
4671 0x00000000);
4672 spr_register(env, SPR_USPRG6, "USPRG6",
4673 &spr_read_ureg, SPR_NOACCESS,
4674 &spr_read_ureg, SPR_NOACCESS,
4675 0x00000000);
4676 spr_register(env, SPR_SPRG7, "SPRG7",
4677 SPR_NOACCESS, SPR_NOACCESS,
4678 &spr_read_generic, &spr_write_generic,
4679 0x00000000);
4680 spr_register(env, SPR_USPRG7, "USPRG7",
4681 &spr_read_ureg, SPR_NOACCESS,
4682 &spr_read_ureg, SPR_NOACCESS,
4683 0x00000000);
4684 /* Memory management */
4685 register_low_BATs(env);
4686 register_high_BATs(env);
4687 init_excp_7450(env);
4688 env->dcache_line_size = 32;
4689 env->icache_line_size = 32;
4690 /* Allocate hardware IRQ controller */
4691 ppc6xx_irq_init(env_archcpu(env));
4692 }
4693
4694 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
4695 {
4696 DeviceClass *dc = DEVICE_CLASS(oc);
4697 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4698
4699 dc->desc = "PowerPC 7455 (aka G4)";
4700 pcc->init_proc = init_proc_7455;
4701 pcc->check_pow = check_pow_hid0_74xx;
4702 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4703 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4704 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4705 PPC_FLOAT_STFIWX |
4706 PPC_CACHE | PPC_CACHE_ICBI |
4707 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4708 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4709 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4710 PPC_MEM_TLBIA |
4711 PPC_SEGMENT | PPC_EXTERN |
4712 PPC_ALTIVEC;
4713 pcc->msr_mask = (1ull << MSR_VR) |
4714 (1ull << MSR_POW) |
4715 (1ull << MSR_ILE) |
4716 (1ull << MSR_EE) |
4717 (1ull << MSR_PR) |
4718 (1ull << MSR_FP) |
4719 (1ull << MSR_ME) |
4720 (1ull << MSR_FE0) |
4721 (1ull << MSR_SE) |
4722 (1ull << MSR_DE) |
4723 (1ull << MSR_FE1) |
4724 (1ull << MSR_EP) |
4725 (1ull << MSR_IR) |
4726 (1ull << MSR_DR) |
4727 (1ull << MSR_PMM) |
4728 (1ull << MSR_RI) |
4729 (1ull << MSR_LE);
4730 pcc->mmu_model = POWERPC_MMU_32B;
4731 pcc->excp_model = POWERPC_EXCP_74xx;
4732 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4733 pcc->bfd_mach = bfd_mach_ppc_7400;
4734 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4735 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4736 POWERPC_FLAG_BUS_CLK;
4737 }
4738
4739 static void init_proc_7457(CPUPPCState *env)
4740 {
4741 register_non_embedded_sprs(env);
4742 register_sdr1_sprs(env);
4743 register_74xx_sprs(env);
4744 vscr_init(env, 0x00010000);
4745 /* Level 3 cache control */
4746 register_l3_ctrl(env);
4747 /* L3ITCR1 */
4748 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4749 SPR_NOACCESS, SPR_NOACCESS,
4750 &spr_read_generic, &spr_write_generic,
4751 0x00000000);
4752 /* L3ITCR2 */
4753 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4754 SPR_NOACCESS, SPR_NOACCESS,
4755 &spr_read_generic, &spr_write_generic,
4756 0x00000000);
4757 /* L3ITCR3 */
4758 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4759 SPR_NOACCESS, SPR_NOACCESS,
4760 &spr_read_generic, &spr_write_generic,
4761 0x00000000);
4762 /* L3OHCR */
4763 spr_register(env, SPR_L3OHCR, "L3OHCR",
4764 SPR_NOACCESS, SPR_NOACCESS,
4765 &spr_read_generic, &spr_write_generic,
4766 0x00000000);
4767 /* LDSTCR */
4768 spr_register(env, SPR_LDSTCR, "LDSTCR",
4769 SPR_NOACCESS, SPR_NOACCESS,
4770 &spr_read_generic, &spr_write_generic,
4771 0x00000000);
4772 /* ICTRL */
4773 spr_register(env, SPR_ICTRL, "ICTRL",
4774 SPR_NOACCESS, SPR_NOACCESS,
4775 &spr_read_generic, &spr_write_generic,
4776 0x00000000);
4777 /* MSSSR0 */
4778 spr_register(env, SPR_MSSSR0, "MSSSR0",
4779 SPR_NOACCESS, SPR_NOACCESS,
4780 &spr_read_generic, &spr_write_generic,
4781 0x00000000);
4782 /* PMC */
4783 spr_register(env, SPR_7XX_PMC5, "PMC5",
4784 SPR_NOACCESS, SPR_NOACCESS,
4785 &spr_read_generic, &spr_write_generic,
4786 0x00000000);
4787
4788 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4789 &spr_read_ureg, SPR_NOACCESS,
4790 &spr_read_ureg, SPR_NOACCESS,
4791 0x00000000);
4792
4793 spr_register(env, SPR_7XX_PMC6, "PMC6",
4794 SPR_NOACCESS, SPR_NOACCESS,
4795 &spr_read_generic, &spr_write_generic,
4796 0x00000000);
4797
4798 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4799 &spr_read_ureg, SPR_NOACCESS,
4800 &spr_read_ureg, SPR_NOACCESS,
4801 0x00000000);
4802 /* SPRGs */
4803 spr_register(env, SPR_SPRG4, "SPRG4",
4804 SPR_NOACCESS, SPR_NOACCESS,
4805 &spr_read_generic, &spr_write_generic,
4806 0x00000000);
4807 spr_register(env, SPR_USPRG4, "USPRG4",
4808 &spr_read_ureg, SPR_NOACCESS,
4809 &spr_read_ureg, SPR_NOACCESS,
4810 0x00000000);
4811 spr_register(env, SPR_SPRG5, "SPRG5",
4812 SPR_NOACCESS, SPR_NOACCESS,
4813 &spr_read_generic, &spr_write_generic,
4814 0x00000000);
4815 spr_register(env, SPR_USPRG5, "USPRG5",
4816 &spr_read_ureg, SPR_NOACCESS,
4817 &spr_read_ureg, SPR_NOACCESS,
4818 0x00000000);
4819 spr_register(env, SPR_SPRG6, "SPRG6",
4820 SPR_NOACCESS, SPR_NOACCESS,
4821 &spr_read_generic, &spr_write_generic,
4822 0x00000000);
4823 spr_register(env, SPR_USPRG6, "USPRG6",
4824 &spr_read_ureg, SPR_NOACCESS,
4825 &spr_read_ureg, SPR_NOACCESS,
4826 0x00000000);
4827 spr_register(env, SPR_SPRG7, "SPRG7",
4828 SPR_NOACCESS, SPR_NOACCESS,
4829 &spr_read_generic, &spr_write_generic,
4830 0x00000000);
4831 spr_register(env, SPR_USPRG7, "USPRG7",
4832 &spr_read_ureg, SPR_NOACCESS,
4833 &spr_read_ureg, SPR_NOACCESS,
4834 0x00000000);
4835 /* Memory management */
4836 register_low_BATs(env);
4837 register_high_BATs(env);
4838 init_excp_7450(env);
4839 env->dcache_line_size = 32;
4840 env->icache_line_size = 32;
4841 /* Allocate hardware IRQ controller */
4842 ppc6xx_irq_init(env_archcpu(env));
4843 }
4844
4845 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
4846 {
4847 DeviceClass *dc = DEVICE_CLASS(oc);
4848 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4849
4850 dc->desc = "PowerPC 7457 (aka G4)";
4851 pcc->init_proc = init_proc_7457;
4852 pcc->check_pow = check_pow_hid0_74xx;
4853 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4854 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4855 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4856 PPC_FLOAT_STFIWX |
4857 PPC_CACHE | PPC_CACHE_ICBI |
4858 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4859 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4860 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4861 PPC_MEM_TLBIA |
4862 PPC_SEGMENT | PPC_EXTERN |
4863 PPC_ALTIVEC;
4864 pcc->msr_mask = (1ull << MSR_VR) |
4865 (1ull << MSR_POW) |
4866 (1ull << MSR_ILE) |
4867 (1ull << MSR_EE) |
4868 (1ull << MSR_PR) |
4869 (1ull << MSR_FP) |
4870 (1ull << MSR_ME) |
4871 (1ull << MSR_FE0) |
4872 (1ull << MSR_SE) |
4873 (1ull << MSR_DE) |
4874 (1ull << MSR_FE1) |
4875 (1ull << MSR_EP) |
4876 (1ull << MSR_IR) |
4877 (1ull << MSR_DR) |
4878 (1ull << MSR_PMM) |
4879 (1ull << MSR_RI) |
4880 (1ull << MSR_LE);
4881 pcc->mmu_model = POWERPC_MMU_32B;
4882 pcc->excp_model = POWERPC_EXCP_74xx;
4883 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4884 pcc->bfd_mach = bfd_mach_ppc_7400;
4885 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4886 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4887 POWERPC_FLAG_BUS_CLK;
4888 }
4889
4890 static void init_proc_e600(CPUPPCState *env)
4891 {
4892 register_non_embedded_sprs(env);
4893 register_sdr1_sprs(env);
4894 register_74xx_sprs(env);
4895 vscr_init(env, 0x00010000);
4896
4897 spr_register(env, SPR_UBAMR, "UBAMR",
4898 &spr_read_ureg, SPR_NOACCESS,
4899 &spr_read_ureg, SPR_NOACCESS,
4900 0x00000000);
4901
4902 spr_register(env, SPR_LDSTCR, "LDSTCR",
4903 SPR_NOACCESS, SPR_NOACCESS,
4904 &spr_read_generic, &spr_write_generic,
4905 0x00000000);
4906
4907 spr_register(env, SPR_ICTRL, "ICTRL",
4908 SPR_NOACCESS, SPR_NOACCESS,
4909 &spr_read_generic, &spr_write_generic,
4910 0x00000000);
4911
4912 spr_register(env, SPR_MSSSR0, "MSSSR0",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916
4917 spr_register(env, SPR_7XX_PMC5, "PMC5",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921
4922 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4923 &spr_read_ureg, SPR_NOACCESS,
4924 &spr_read_ureg, SPR_NOACCESS,
4925 0x00000000);
4926
4927 spr_register(env, SPR_7XX_PMC6, "PMC6",
4928 SPR_NOACCESS, SPR_NOACCESS,
4929 &spr_read_generic, &spr_write_generic,
4930 0x00000000);
4931
4932 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4933 &spr_read_ureg, SPR_NOACCESS,
4934 &spr_read_ureg, SPR_NOACCESS,
4935 0x00000000);
4936 /* SPRGs */
4937 spr_register(env, SPR_SPRG4, "SPRG4",
4938 SPR_NOACCESS, SPR_NOACCESS,
4939 &spr_read_generic, &spr_write_generic,
4940 0x00000000);
4941 spr_register(env, SPR_USPRG4, "USPRG4",
4942 &spr_read_ureg, SPR_NOACCESS,
4943 &spr_read_ureg, SPR_NOACCESS,
4944 0x00000000);
4945 spr_register(env, SPR_SPRG5, "SPRG5",
4946 SPR_NOACCESS, SPR_NOACCESS,
4947 &spr_read_generic, &spr_write_generic,
4948 0x00000000);
4949 spr_register(env, SPR_USPRG5, "USPRG5",
4950 &spr_read_ureg, SPR_NOACCESS,
4951 &spr_read_ureg, SPR_NOACCESS,
4952 0x00000000);
4953 spr_register(env, SPR_SPRG6, "SPRG6",
4954 SPR_NOACCESS, SPR_NOACCESS,
4955 &spr_read_generic, &spr_write_generic,
4956 0x00000000);
4957 spr_register(env, SPR_USPRG6, "USPRG6",
4958 &spr_read_ureg, SPR_NOACCESS,
4959 &spr_read_ureg, SPR_NOACCESS,
4960 0x00000000);
4961 spr_register(env, SPR_SPRG7, "SPRG7",
4962 SPR_NOACCESS, SPR_NOACCESS,
4963 &spr_read_generic, &spr_write_generic,
4964 0x00000000);
4965 spr_register(env, SPR_USPRG7, "USPRG7",
4966 &spr_read_ureg, SPR_NOACCESS,
4967 &spr_read_ureg, SPR_NOACCESS,
4968 0x00000000);
4969 /* Memory management */
4970 register_low_BATs(env);
4971 register_high_BATs(env);
4972 init_excp_7450(env);
4973 env->dcache_line_size = 32;
4974 env->icache_line_size = 32;
4975 /* Allocate hardware IRQ controller */
4976 ppc6xx_irq_init(env_archcpu(env));
4977 }
4978
4979 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
4980 {
4981 DeviceClass *dc = DEVICE_CLASS(oc);
4982 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4983
4984 dc->desc = "PowerPC e600";
4985 pcc->init_proc = init_proc_e600;
4986 pcc->check_pow = check_pow_hid0_74xx;
4987 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4988 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4989 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4990 PPC_FLOAT_STFIWX |
4991 PPC_CACHE | PPC_CACHE_ICBI |
4992 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4993 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4995 PPC_MEM_TLBIA |
4996 PPC_SEGMENT | PPC_EXTERN |
4997 PPC_ALTIVEC;
4998 pcc->insns_flags2 = PPC_NONE;
4999 pcc->msr_mask = (1ull << MSR_VR) |
5000 (1ull << MSR_POW) |
5001 (1ull << MSR_ILE) |
5002 (1ull << MSR_EE) |
5003 (1ull << MSR_PR) |
5004 (1ull << MSR_FP) |
5005 (1ull << MSR_ME) |
5006 (1ull << MSR_FE0) |
5007 (1ull << MSR_SE) |
5008 (1ull << MSR_DE) |
5009 (1ull << MSR_FE1) |
5010 (1ull << MSR_EP) |
5011 (1ull << MSR_IR) |
5012 (1ull << MSR_DR) |
5013 (1ull << MSR_PMM) |
5014 (1ull << MSR_RI) |
5015 (1ull << MSR_LE);
5016 pcc->mmu_model = POWERPC_MMU_32B;
5017 pcc->excp_model = POWERPC_EXCP_74xx;
5018 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5019 pcc->bfd_mach = bfd_mach_ppc_7400;
5020 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5021 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5022 POWERPC_FLAG_BUS_CLK;
5023 }
5024
5025 #if defined(TARGET_PPC64)
5026 #if defined(CONFIG_USER_ONLY)
5027 #define POWERPC970_HID5_INIT 0x00000080
5028 #else
5029 #define POWERPC970_HID5_INIT 0x00000000
5030 #endif
5031
5032 static int check_pow_970(CPUPPCState *env)
5033 {
5034 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5035 return 1;
5036 }
5037
5038 return 0;
5039 }
5040
5041 static void register_970_hid_sprs(CPUPPCState *env)
5042 {
5043 /* Hardware implementation registers */
5044 spr_register(env, SPR_HID0, "HID0",
5045 SPR_NOACCESS, SPR_NOACCESS,
5046 &spr_read_generic, &spr_write_clear,
5047 0x60000000);
5048 spr_register(env, SPR_HID1, "HID1",
5049 SPR_NOACCESS, SPR_NOACCESS,
5050 &spr_read_generic, &spr_write_generic,
5051 0x00000000);
5052 spr_register(env, SPR_970_HID5, "HID5",
5053 SPR_NOACCESS, SPR_NOACCESS,
5054 &spr_read_generic, &spr_write_generic,
5055 POWERPC970_HID5_INIT);
5056 }
5057
5058 static void register_970_hior_sprs(CPUPPCState *env)
5059 {
5060 spr_register(env, SPR_HIOR, "SPR_HIOR",
5061 SPR_NOACCESS, SPR_NOACCESS,
5062 &spr_read_hior, &spr_write_hior,
5063 0x00000000);
5064 }
5065
5066 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5067 {
5068 spr_register(env, SPR_CTRL, "SPR_CTRL",
5069 SPR_NOACCESS, SPR_NOACCESS,
5070 SPR_NOACCESS, &spr_write_CTRL,
5071 0x00000000);
5072 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5073 &spr_read_ureg, SPR_NOACCESS,
5074 &spr_read_ureg, SPR_NOACCESS,
5075 0x00000000);
5076 }
5077
5078 static void register_book3s_altivec_sprs(CPUPPCState *env)
5079 {
5080 if (!(env->insns_flags & PPC_ALTIVEC)) {
5081 return;
5082 }
5083
5084 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5085 &spr_read_generic, &spr_write_generic,
5086 &spr_read_generic, &spr_write_generic,
5087 KVM_REG_PPC_VRSAVE, 0x00000000);
5088
5089 }
5090
5091 static void register_book3s_dbg_sprs(CPUPPCState *env)
5092 {
5093 /*
5094 * TODO: different specs define different scopes for these,
5095 * will have to address this:
5096 * 970: super/write and super/read
5097 * powerisa 2.03..2.04: hypv/write and super/read.
5098 * powerisa 2.05 and newer: hypv/write and hypv/read.
5099 */
5100 spr_register_kvm(env, SPR_DABR, "DABR",
5101 SPR_NOACCESS, SPR_NOACCESS,
5102 &spr_read_generic, &spr_write_generic,
5103 KVM_REG_PPC_DABR, 0x00000000);
5104 spr_register_kvm(env, SPR_DABRX, "DABRX",
5105 SPR_NOACCESS, SPR_NOACCESS,
5106 &spr_read_generic, &spr_write_generic,
5107 KVM_REG_PPC_DABRX, 0x00000000);
5108 }
5109
5110 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5111 {
5112 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 SPR_NOACCESS, SPR_NOACCESS,
5115 &spr_read_generic, &spr_write_generic,
5116 KVM_REG_PPC_DAWR, 0x00000000);
5117 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 SPR_NOACCESS, SPR_NOACCESS,
5120 &spr_read_generic, &spr_write_generic,
5121 KVM_REG_PPC_DAWRX, 0x00000000);
5122 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 SPR_NOACCESS, SPR_NOACCESS,
5125 &spr_read_generic, &spr_write_generic,
5126 KVM_REG_PPC_CIABR, 0x00000000);
5127 }
5128
5129 static void register_970_dbg_sprs(CPUPPCState *env)
5130 {
5131 /* Breakpoints */
5132 spr_register(env, SPR_IABR, "IABR",
5133 SPR_NOACCESS, SPR_NOACCESS,
5134 &spr_read_generic, &spr_write_generic,
5135 0x00000000);
5136 }
5137
5138 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5139 {
5140 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5141 SPR_NOACCESS, SPR_NOACCESS,
5142 &spr_read_generic, &spr_write_MMCR0,
5143 KVM_REG_PPC_MMCR0, 0x80000000);
5144 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5145 SPR_NOACCESS, SPR_NOACCESS,
5146 &spr_read_generic, &spr_write_MMCR1,
5147 KVM_REG_PPC_MMCR1, 0x00000000);
5148 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5149 SPR_NOACCESS, SPR_NOACCESS,
5150 &spr_read_generic, &spr_write_generic,
5151 KVM_REG_PPC_MMCRA, 0x00000000);
5152 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_PMC, &spr_write_PMC,
5155 KVM_REG_PPC_PMC1, 0x00000000);
5156 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5157 SPR_NOACCESS, SPR_NOACCESS,
5158 &spr_read_PMC, &spr_write_PMC,
5159 KVM_REG_PPC_PMC2, 0x00000000);
5160 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5161 SPR_NOACCESS, SPR_NOACCESS,
5162 &spr_read_PMC, &spr_write_PMC,
5163 KVM_REG_PPC_PMC3, 0x00000000);
5164 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_PMC, &spr_write_PMC,
5167 KVM_REG_PPC_PMC4, 0x00000000);
5168 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5169 SPR_NOACCESS, SPR_NOACCESS,
5170 &spr_read_PMC, &spr_write_PMC,
5171 KVM_REG_PPC_PMC5, 0x00000000);
5172 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_PMC, &spr_write_PMC,
5175 KVM_REG_PPC_PMC6, 0x00000000);
5176 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5177 SPR_NOACCESS, SPR_NOACCESS,
5178 &spr_read_generic, &spr_write_generic,
5179 KVM_REG_PPC_SIAR, 0x00000000);
5180 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5181 SPR_NOACCESS, SPR_NOACCESS,
5182 &spr_read_generic, &spr_write_generic,
5183 KVM_REG_PPC_SDAR, 0x00000000);
5184 }
5185
5186 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5187 {
5188 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5189 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5190 &spr_read_ureg, &spr_write_ureg,
5191 0x80000000);
5192 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5193 &spr_read_ureg, SPR_NOACCESS,
5194 &spr_read_ureg, &spr_write_ureg,
5195 0x00000000);
5196 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5197 &spr_read_ureg, SPR_NOACCESS,
5198 &spr_read_ureg, &spr_write_ureg,
5199 0x00000000);
5200 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5201 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5202 &spr_read_ureg, &spr_write_ureg,
5203 0x00000000);
5204 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5205 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5206 &spr_read_ureg, &spr_write_ureg,
5207 0x00000000);
5208 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5209 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5210 &spr_read_ureg, &spr_write_ureg,
5211 0x00000000);
5212 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5213 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5214 &spr_read_ureg, &spr_write_ureg,
5215 0x00000000);
5216 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5217 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5218 &spr_read_ureg, &spr_write_ureg,
5219 0x00000000);
5220 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5221 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5222 &spr_read_ureg, &spr_write_ureg,
5223 0x00000000);
5224 spr_register(env, SPR_POWER_USIAR, "USIAR",
5225 &spr_read_ureg, SPR_NOACCESS,
5226 &spr_read_ureg, &spr_write_ureg,
5227 0x00000000);
5228 spr_register(env, SPR_POWER_USDAR, "USDAR",
5229 &spr_read_ureg, SPR_NOACCESS,
5230 &spr_read_ureg, &spr_write_ureg,
5231 0x00000000);
5232 }
5233
5234 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5235 {
5236 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5237 SPR_NOACCESS, SPR_NOACCESS,
5238 &spr_read_generic, &spr_write_generic,
5239 KVM_REG_PPC_PMC7, 0x00000000);
5240 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 KVM_REG_PPC_PMC8, 0x00000000);
5244 }
5245
5246 static void register_970_pmu_user_sprs(CPUPPCState *env)
5247 {
5248 spr_register(env, SPR_970_UPMC7, "UPMC7",
5249 &spr_read_ureg, SPR_NOACCESS,
5250 &spr_read_ureg, &spr_write_ureg,
5251 0x00000000);
5252 spr_register(env, SPR_970_UPMC8, "UPMC8",
5253 &spr_read_ureg, SPR_NOACCESS,
5254 &spr_read_ureg, &spr_write_ureg,
5255 0x00000000);
5256 }
5257
5258 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5259 {
5260 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5261 SPR_NOACCESS, SPR_NOACCESS,
5262 &spr_read_generic, &spr_write_generic,
5263 KVM_REG_PPC_MMCR2, 0x00000000);
5264 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5265 SPR_NOACCESS, SPR_NOACCESS,
5266 &spr_read_generic, &spr_write_generic,
5267 KVM_REG_PPC_MMCRS, 0x00000000);
5268 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 KVM_REG_PPC_SIER, 0x00000000);
5272 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5273 SPR_NOACCESS, SPR_NOACCESS,
5274 &spr_read_generic, &spr_write_generic,
5275 KVM_REG_PPC_SPMC1, 0x00000000);
5276 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 KVM_REG_PPC_SPMC2, 0x00000000);
5280 spr_register_kvm(env, SPR_TACR, "TACR",
5281 SPR_NOACCESS, SPR_NOACCESS,
5282 &spr_read_generic, &spr_write_generic,
5283 KVM_REG_PPC_TACR, 0x00000000);
5284 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5285 SPR_NOACCESS, SPR_NOACCESS,
5286 &spr_read_generic, &spr_write_generic,
5287 KVM_REG_PPC_TCSCR, 0x00000000);
5288 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 KVM_REG_PPC_CSIGR, 0x00000000);
5292 }
5293
5294 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5295 {
5296 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5297 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5298 &spr_read_ureg, &spr_write_ureg,
5299 0x00000000);
5300 spr_register(env, SPR_POWER_USIER, "USIER",
5301 &spr_read_generic, SPR_NOACCESS,
5302 &spr_read_generic, &spr_write_generic,
5303 0x00000000);
5304 }
5305
5306 static void register_power5p_ear_sprs(CPUPPCState *env)
5307 {
5308 /* External access control */
5309 spr_register(env, SPR_EAR, "EAR",
5310 SPR_NOACCESS, SPR_NOACCESS,
5311 &spr_read_generic, &spr_write_generic,
5312 0x00000000);
5313 }
5314
5315 static void register_power5p_tb_sprs(CPUPPCState *env)
5316 {
5317 /* TBU40 (High 40 bits of the Timebase register */
5318 spr_register_hv(env, SPR_TBU40, "TBU40",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 SPR_NOACCESS, SPR_NOACCESS,
5321 SPR_NOACCESS, &spr_write_tbu40,
5322 0x00000000);
5323 }
5324
5325 static void register_970_lpar_sprs(CPUPPCState *env)
5326 {
5327 #if !defined(CONFIG_USER_ONLY)
5328 /*
5329 * PPC970: HID4 covers things later controlled by the LPCR and
5330 * RMOR in later CPUs, but with a different encoding. We only
5331 * support the 970 in "Apple mode" which has all hypervisor
5332 * facilities disabled by strapping, so we can basically just
5333 * ignore it
5334 */
5335 spr_register(env, SPR_970_HID4, "HID4",
5336 SPR_NOACCESS, SPR_NOACCESS,
5337 &spr_read_generic, &spr_write_generic,
5338 0x00000000);
5339 #endif
5340 }
5341
5342 static void register_power5p_lpar_sprs(CPUPPCState *env)
5343 {
5344 #if !defined(CONFIG_USER_ONLY)
5345 /* Logical partitionning */
5346 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5347 SPR_NOACCESS, SPR_NOACCESS,
5348 SPR_NOACCESS, SPR_NOACCESS,
5349 &spr_read_generic, &spr_write_lpcr,
5350 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5351 spr_register_hv(env, SPR_HDEC, "HDEC",
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 SPR_NOACCESS, SPR_NOACCESS,
5354 &spr_read_hdecr, &spr_write_hdecr, 0);
5355 #endif
5356 }
5357
5358 static void register_book3s_ids_sprs(CPUPPCState *env)
5359 {
5360 /* FIXME: Will need to deal with thread vs core only SPRs */
5361
5362 /* Processor identification */
5363 spr_register_hv(env, SPR_PIR, "PIR",
5364 SPR_NOACCESS, SPR_NOACCESS,
5365 &spr_read_generic, SPR_NOACCESS,
5366 &spr_read_generic, NULL,
5367 0x00000000);
5368 spr_register_hv(env, SPR_HID0, "HID0",
5369 SPR_NOACCESS, SPR_NOACCESS,
5370 SPR_NOACCESS, SPR_NOACCESS,
5371 &spr_read_generic, &spr_write_generic,
5372 0x00000000);
5373 spr_register_hv(env, SPR_TSCR, "TSCR",
5374 SPR_NOACCESS, SPR_NOACCESS,
5375 SPR_NOACCESS, SPR_NOACCESS,
5376 &spr_read_generic, &spr_write_generic,
5377 0x00000000);
5378 spr_register_hv(env, SPR_HMER, "HMER",
5379 SPR_NOACCESS, SPR_NOACCESS,
5380 SPR_NOACCESS, SPR_NOACCESS,
5381 &spr_read_generic, &spr_write_hmer,
5382 0x00000000);
5383 spr_register_hv(env, SPR_HMEER, "HMEER",
5384 SPR_NOACCESS, SPR_NOACCESS,
5385 SPR_NOACCESS, SPR_NOACCESS,
5386 &spr_read_generic, &spr_write_generic,
5387 0x00000000);
5388 spr_register_hv(env, SPR_TFMR, "TFMR",
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 SPR_NOACCESS, SPR_NOACCESS,
5391 &spr_read_generic, &spr_write_generic,
5392 0x00000000);
5393 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5394 SPR_NOACCESS, SPR_NOACCESS,
5395 SPR_NOACCESS, SPR_NOACCESS,
5396 &spr_read_generic, &spr_write_lpidr,
5397 0x00000000);
5398 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5399 SPR_NOACCESS, SPR_NOACCESS,
5400 SPR_NOACCESS, SPR_NOACCESS,
5401 &spr_read_generic, &spr_write_generic,
5402 0x00000000);
5403 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 SPR_NOACCESS, SPR_NOACCESS,
5406 &spr_read_generic, &spr_write_generic,
5407 0x00000000);
5408 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5409 SPR_NOACCESS, SPR_NOACCESS,
5410 SPR_NOACCESS, SPR_NOACCESS,
5411 &spr_read_generic, &spr_write_generic,
5412 0x00000000);
5413 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5414 SPR_NOACCESS, SPR_NOACCESS,
5415 SPR_NOACCESS, SPR_NOACCESS,
5416 &spr_read_generic, &spr_write_generic,
5417 0x00000000);
5418 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5419 SPR_NOACCESS, SPR_NOACCESS,
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5424 SPR_NOACCESS, SPR_NOACCESS,
5425 SPR_NOACCESS, SPR_NOACCESS,
5426 &spr_read_generic, &spr_write_generic,
5427 0x00000000);
5428 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5429 SPR_NOACCESS, SPR_NOACCESS,
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 &spr_read_generic, &spr_write_generic,
5432 0x00000000);
5433 spr_register_hv(env, SPR_HDAR, "HDAR",
5434 SPR_NOACCESS, SPR_NOACCESS,
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_generic,
5437 0x00000000);
5438 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5439 SPR_NOACCESS, SPR_NOACCESS,
5440 SPR_NOACCESS, SPR_NOACCESS,
5441 &spr_read_generic, &spr_write_generic,
5442 0x00000000);
5443 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5444 SPR_NOACCESS, SPR_NOACCESS,
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448 }
5449
5450 static void register_rmor_sprs(CPUPPCState *env)
5451 {
5452 spr_register_hv(env, SPR_RMOR, "RMOR",
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 }
5458
5459 static void register_power8_ids_sprs(CPUPPCState *env)
5460 {
5461 /* Thread identification */
5462 spr_register(env, SPR_TIR, "TIR",
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, SPR_NOACCESS,
5465 0x00000000);
5466 }
5467
5468 static void register_book3s_purr_sprs(CPUPPCState *env)
5469 {
5470 #if !defined(CONFIG_USER_ONLY)
5471 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5472 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5473 &spr_read_purr, SPR_NOACCESS,
5474 &spr_read_purr, SPR_NOACCESS,
5475 &spr_read_purr, &spr_write_purr,
5476 KVM_REG_PPC_PURR, 0x00000000);
5477 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5478 &spr_read_purr, SPR_NOACCESS,
5479 &spr_read_purr, SPR_NOACCESS,
5480 &spr_read_purr, &spr_write_purr,
5481 KVM_REG_PPC_SPURR, 0x00000000);
5482 #endif
5483 }
5484
5485 static void register_power6_dbg_sprs(CPUPPCState *env)
5486 {
5487 #if !defined(CONFIG_USER_ONLY)
5488 spr_register(env, SPR_CFAR, "SPR_CFAR",
5489 SPR_NOACCESS, SPR_NOACCESS,
5490 &spr_read_cfar, &spr_write_cfar,
5491 0x00000000);
5492 #endif
5493 }
5494
5495 static void register_power5p_common_sprs(CPUPPCState *env)
5496 {
5497 spr_register_kvm(env, SPR_PPR, "PPR",
5498 &spr_read_generic, &spr_write_generic,
5499 &spr_read_generic, &spr_write_generic,
5500 KVM_REG_PPC_PPR, 0x00000000);
5501 }
5502
5503 static void register_power6_common_sprs(CPUPPCState *env)
5504 {
5505 #if !defined(CONFIG_USER_ONLY)
5506 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_write_generic,
5509 KVM_REG_PPC_DSCR, 0x00000000);
5510 #endif
5511 /*
5512 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5513 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5514 */
5515 spr_register_hv(env, SPR_PCR, "PCR",
5516 SPR_NOACCESS, SPR_NOACCESS,
5517 SPR_NOACCESS, SPR_NOACCESS,
5518 &spr_read_generic, &spr_write_pcr,
5519 0x00000000);
5520 }
5521
5522 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5523 {
5524 spr_register_kvm(env, SPR_TAR, "TAR",
5525 &spr_read_tar, &spr_write_tar,
5526 &spr_read_generic, &spr_write_generic,
5527 KVM_REG_PPC_TAR, 0x00000000);
5528 }
5529
5530 static void register_power8_tm_sprs(CPUPPCState *env)
5531 {
5532 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5533 &spr_read_tm, &spr_write_tm,
5534 &spr_read_tm, &spr_write_tm,
5535 KVM_REG_PPC_TFHAR, 0x00000000);
5536 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5537 &spr_read_tm, &spr_write_tm,
5538 &spr_read_tm, &spr_write_tm,
5539 KVM_REG_PPC_TFIAR, 0x00000000);
5540 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5541 &spr_read_tm, &spr_write_tm,
5542 &spr_read_tm, &spr_write_tm,
5543 KVM_REG_PPC_TEXASR, 0x00000000);
5544 spr_register(env, SPR_TEXASRU, "TEXASRU",
5545 &spr_read_tm_upper32, &spr_write_tm_upper32,
5546 &spr_read_tm_upper32, &spr_write_tm_upper32,
5547 0x00000000);
5548 }
5549
5550 static void register_power8_ebb_sprs(CPUPPCState *env)
5551 {
5552 spr_register(env, SPR_BESCRS, "BESCRS",
5553 &spr_read_ebb, &spr_write_ebb,
5554 &spr_read_generic, &spr_write_generic,
5555 0x00000000);
5556 spr_register(env, SPR_BESCRSU, "BESCRSU",
5557 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5558 &spr_read_prev_upper32, &spr_write_prev_upper32,
5559 0x00000000);
5560 spr_register(env, SPR_BESCRR, "BESCRR",
5561 &spr_read_ebb, &spr_write_ebb,
5562 &spr_read_generic, &spr_write_generic,
5563 0x00000000);
5564 spr_register(env, SPR_BESCRRU, "BESCRRU",
5565 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5566 &spr_read_prev_upper32, &spr_write_prev_upper32,
5567 0x00000000);
5568 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5569 &spr_read_ebb, &spr_write_ebb,
5570 &spr_read_generic, &spr_write_generic,
5571 KVM_REG_PPC_EBBHR, 0x00000000);
5572 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5573 &spr_read_ebb, &spr_write_ebb,
5574 &spr_read_generic, &spr_write_generic,
5575 KVM_REG_PPC_EBBRR, 0x00000000);
5576 spr_register_kvm(env, SPR_BESCR, "BESCR",
5577 &spr_read_ebb, &spr_write_ebb,
5578 &spr_read_generic, &spr_write_generic,
5579 KVM_REG_PPC_BESCR, 0x00000000);
5580 }
5581
5582 /* Virtual Time Base */
5583 static void register_vtb_sprs(CPUPPCState *env)
5584 {
5585 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5586 SPR_NOACCESS, SPR_NOACCESS,
5587 &spr_read_vtb, SPR_NOACCESS,
5588 &spr_read_vtb, &spr_write_vtb,
5589 KVM_REG_PPC_VTB, 0x00000000);
5590 }
5591
5592 static void register_power8_fscr_sprs(CPUPPCState *env)
5593 {
5594 #if defined(CONFIG_USER_ONLY)
5595 target_ulong initval = 1ULL << FSCR_TAR;
5596 #else
5597 target_ulong initval = 0;
5598 #endif
5599 spr_register_kvm(env, SPR_FSCR, "FSCR",
5600 SPR_NOACCESS, SPR_NOACCESS,
5601 &spr_read_generic, &spr_write_generic,
5602 KVM_REG_PPC_FSCR, initval);
5603 }
5604
5605 static void register_power8_pspb_sprs(CPUPPCState *env)
5606 {
5607 spr_register_kvm(env, SPR_PSPB, "PSPB",
5608 SPR_NOACCESS, SPR_NOACCESS,
5609 &spr_read_generic, &spr_write_generic32,
5610 KVM_REG_PPC_PSPB, 0);
5611 }
5612
5613 static void register_power8_dpdes_sprs(CPUPPCState *env)
5614 {
5615 #if !defined(CONFIG_USER_ONLY)
5616 /* Directed Privileged Door-bell Exception State, used for IPI */
5617 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5618 SPR_NOACCESS, SPR_NOACCESS,
5619 &spr_read_dpdes, SPR_NOACCESS,
5620 &spr_read_dpdes, &spr_write_dpdes,
5621 KVM_REG_PPC_DPDES, 0x00000000);
5622 #endif
5623 }
5624
5625 static void register_power8_ic_sprs(CPUPPCState *env)
5626 {
5627 #if !defined(CONFIG_USER_ONLY)
5628 spr_register_hv(env, SPR_IC, "IC",
5629 SPR_NOACCESS, SPR_NOACCESS,
5630 &spr_read_generic, SPR_NOACCESS,
5631 &spr_read_generic, &spr_write_generic,
5632 0);
5633 #endif
5634 }
5635
5636 static void register_power8_book4_sprs(CPUPPCState *env)
5637 {
5638 /* Add a number of P8 book4 registers */
5639 #if !defined(CONFIG_USER_ONLY)
5640 spr_register_kvm(env, SPR_ACOP, "ACOP",
5641 SPR_NOACCESS, SPR_NOACCESS,
5642 &spr_read_generic, &spr_write_generic,
5643 KVM_REG_PPC_ACOP, 0);
5644 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5645 SPR_NOACCESS, SPR_NOACCESS,
5646 &spr_read_generic, &spr_write_pidr,
5647 KVM_REG_PPC_PID, 0);
5648 spr_register_kvm(env, SPR_WORT, "WORT",
5649 SPR_NOACCESS, SPR_NOACCESS,
5650 &spr_read_generic, &spr_write_generic,
5651 KVM_REG_PPC_WORT, 0);
5652 #endif
5653 }
5654
5655 static void register_power7_book4_sprs(CPUPPCState *env)
5656 {
5657 /* Add a number of P7 book4 registers */
5658 #if !defined(CONFIG_USER_ONLY)
5659 spr_register_kvm(env, SPR_ACOP, "ACOP",
5660 SPR_NOACCESS, SPR_NOACCESS,
5661 &spr_read_generic, &spr_write_generic,
5662 KVM_REG_PPC_ACOP, 0);
5663 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5664 SPR_NOACCESS, SPR_NOACCESS,
5665 &spr_read_generic, &spr_write_generic,
5666 KVM_REG_PPC_PID, 0);
5667 #endif
5668 }
5669
5670 static void register_power8_rpr_sprs(CPUPPCState *env)
5671 {
5672 #if !defined(CONFIG_USER_ONLY)
5673 spr_register_hv(env, SPR_RPR, "RPR",
5674 SPR_NOACCESS, SPR_NOACCESS,
5675 SPR_NOACCESS, SPR_NOACCESS,
5676 &spr_read_generic, &spr_write_generic,
5677 0x00000103070F1F3F);
5678 #endif
5679 }
5680
5681 static void register_power9_mmu_sprs(CPUPPCState *env)
5682 {
5683 #if !defined(CONFIG_USER_ONLY)
5684 /* Partition Table Control */
5685 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5686 SPR_NOACCESS, SPR_NOACCESS,
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_ptcr,
5689 KVM_REG_PPC_PTCR, 0x00000000);
5690 /* Address Segment Descriptor Register */
5691 spr_register_hv(env, SPR_ASDR, "ASDR",
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 SPR_NOACCESS, SPR_NOACCESS,
5694 &spr_read_generic, &spr_write_generic,
5695 0x0000000000000000);
5696 #endif
5697 }
5698
5699 /*
5700 * Initialize PMU counter overflow timers for Power8 and
5701 * newer Power chips when using TCG.
5702 */
5703 static void init_tcg_pmu_power8(CPUPPCState *env)
5704 {
5705 /* Init PMU overflow timers */
5706 if (tcg_enabled()) {
5707 cpu_ppc_pmu_init(env);
5708 }
5709 }
5710
5711 static void init_proc_book3s_common(CPUPPCState *env)
5712 {
5713 register_non_embedded_sprs(env);
5714 register_book3s_altivec_sprs(env);
5715 register_book3s_pmu_sup_sprs(env);
5716 register_book3s_pmu_user_sprs(env);
5717 register_book3s_ctrl_sprs(env);
5718 /*
5719 * Can't find information on what this should be on reset. This
5720 * value is the one used by 74xx processors.
5721 */
5722 vscr_init(env, 0x00010000);
5723
5724 spr_register(env, SPR_USPRG3, "USPRG3",
5725 &spr_read_ureg, SPR_NOACCESS,
5726 &spr_read_ureg, SPR_NOACCESS,
5727 0x00000000);
5728 }
5729
5730 static void init_proc_970(CPUPPCState *env)
5731 {
5732 /* Common Registers */
5733 init_proc_book3s_common(env);
5734 register_sdr1_sprs(env);
5735 register_book3s_dbg_sprs(env);
5736
5737 /* 970 Specific Registers */
5738 register_970_hid_sprs(env);
5739 register_970_hior_sprs(env);
5740 register_low_BATs(env);
5741 register_970_pmu_sup_sprs(env);
5742 register_970_pmu_user_sprs(env);
5743 register_970_lpar_sprs(env);
5744 register_970_dbg_sprs(env);
5745
5746 /* env variables */
5747 env->dcache_line_size = 128;
5748 env->icache_line_size = 128;
5749
5750 /* Allocate hardware IRQ controller */
5751 init_excp_970(env);
5752 ppc970_irq_init(env_archcpu(env));
5753 }
5754
5755 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
5756 {
5757 DeviceClass *dc = DEVICE_CLASS(oc);
5758 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5759
5760 dc->desc = "PowerPC 970";
5761 pcc->init_proc = init_proc_970;
5762 pcc->check_pow = check_pow_970;
5763 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5765 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5766 PPC_FLOAT_STFIWX |
5767 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5768 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5769 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5770 PPC_64B | PPC_ALTIVEC |
5771 PPC_SEGMENT_64B | PPC_SLBI;
5772 pcc->insns_flags2 = PPC2_FP_CVT_S64;
5773 pcc->msr_mask = (1ull << MSR_SF) |
5774 (1ull << MSR_VR) |
5775 (1ull << MSR_POW) |
5776 (1ull << MSR_EE) |
5777 (1ull << MSR_PR) |
5778 (1ull << MSR_FP) |
5779 (1ull << MSR_ME) |
5780 (1ull << MSR_FE0) |
5781 (1ull << MSR_SE) |
5782 (1ull << MSR_DE) |
5783 (1ull << MSR_FE1) |
5784 (1ull << MSR_IR) |
5785 (1ull << MSR_DR) |
5786 (1ull << MSR_PMM) |
5787 (1ull << MSR_RI);
5788 pcc->mmu_model = POWERPC_MMU_64B;
5789 #if defined(CONFIG_SOFTMMU)
5790 pcc->hash64_opts = &ppc_hash64_opts_basic;
5791 #endif
5792 pcc->excp_model = POWERPC_EXCP_970;
5793 pcc->bus_model = PPC_FLAGS_INPUT_970;
5794 pcc->bfd_mach = bfd_mach_ppc64;
5795 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5796 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5797 POWERPC_FLAG_BUS_CLK;
5798 pcc->l1_dcache_size = 0x8000;
5799 pcc->l1_icache_size = 0x10000;
5800 }
5801
5802 static void init_proc_power5plus(CPUPPCState *env)
5803 {
5804 /* Common Registers */
5805 init_proc_book3s_common(env);
5806 register_sdr1_sprs(env);
5807 register_book3s_dbg_sprs(env);
5808
5809 /* POWER5+ Specific Registers */
5810 register_970_hid_sprs(env);
5811 register_970_hior_sprs(env);
5812 register_low_BATs(env);
5813 register_970_pmu_sup_sprs(env);
5814 register_970_pmu_user_sprs(env);
5815 register_power5p_common_sprs(env);
5816 register_power5p_lpar_sprs(env);
5817 register_power5p_ear_sprs(env);
5818 register_power5p_tb_sprs(env);
5819
5820 /* env variables */
5821 env->dcache_line_size = 128;
5822 env->icache_line_size = 128;
5823
5824 /* Allocate hardware IRQ controller */
5825 init_excp_970(env);
5826 ppc970_irq_init(env_archcpu(env));
5827 }
5828
5829 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
5830 {
5831 DeviceClass *dc = DEVICE_CLASS(oc);
5832 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5833
5834 dc->fw_name = "PowerPC,POWER5";
5835 dc->desc = "POWER5+";
5836 pcc->init_proc = init_proc_power5plus;
5837 pcc->check_pow = check_pow_970;
5838 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5839 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5840 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5841 PPC_FLOAT_STFIWX |
5842 PPC_FLOAT_EXT |
5843 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5844 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5845 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5846 PPC_64B |
5847 PPC_POPCNTB |
5848 PPC_SEGMENT_64B | PPC_SLBI;
5849 pcc->insns_flags2 = PPC2_FP_CVT_S64;
5850 pcc->msr_mask = (1ull << MSR_SF) |
5851 (1ull << MSR_VR) |
5852 (1ull << MSR_POW) |
5853 (1ull << MSR_EE) |
5854 (1ull << MSR_PR) |
5855 (1ull << MSR_FP) |
5856 (1ull << MSR_ME) |
5857 (1ull << MSR_FE0) |
5858 (1ull << MSR_SE) |
5859 (1ull << MSR_DE) |
5860 (1ull << MSR_FE1) |
5861 (1ull << MSR_IR) |
5862 (1ull << MSR_DR) |
5863 (1ull << MSR_PMM) |
5864 (1ull << MSR_RI);
5865 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
5866 LPCR_RMI | LPCR_HDICE;
5867 pcc->mmu_model = POWERPC_MMU_2_03;
5868 #if defined(CONFIG_SOFTMMU)
5869 pcc->hash64_opts = &ppc_hash64_opts_basic;
5870 pcc->lrg_decr_bits = 32;
5871 #endif
5872 pcc->excp_model = POWERPC_EXCP_970;
5873 pcc->bus_model = PPC_FLAGS_INPUT_970;
5874 pcc->bfd_mach = bfd_mach_ppc64;
5875 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5876 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5877 POWERPC_FLAG_BUS_CLK;
5878 pcc->l1_dcache_size = 0x8000;
5879 pcc->l1_icache_size = 0x10000;
5880 }
5881
5882 static void init_proc_POWER7(CPUPPCState *env)
5883 {
5884 /* Common Registers */
5885 init_proc_book3s_common(env);
5886 register_sdr1_sprs(env);
5887 register_book3s_dbg_sprs(env);
5888
5889 /* POWER7 Specific Registers */
5890 register_book3s_ids_sprs(env);
5891 register_rmor_sprs(env);
5892 register_amr_sprs(env);
5893 register_book3s_purr_sprs(env);
5894 register_power5p_common_sprs(env);
5895 register_power5p_lpar_sprs(env);
5896 register_power5p_ear_sprs(env);
5897 register_power5p_tb_sprs(env);
5898 register_power6_common_sprs(env);
5899 register_power6_dbg_sprs(env);
5900 register_power7_book4_sprs(env);
5901
5902 /* env variables */
5903 env->dcache_line_size = 128;
5904 env->icache_line_size = 128;
5905
5906 /* Allocate hardware IRQ controller */
5907 init_excp_POWER7(env);
5908 ppcPOWER7_irq_init(env_archcpu(env));
5909 }
5910
5911 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
5912 {
5913 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
5914 return true;
5915 }
5916 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
5917 return true;
5918 }
5919 return false;
5920 }
5921
5922 static bool cpu_has_work_POWER7(CPUState *cs)
5923 {
5924 PowerPCCPU *cpu = POWERPC_CPU(cs);
5925 CPUPPCState *env = &cpu->env;
5926
5927 if (cs->halted) {
5928 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
5929 return false;
5930 }
5931 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
5932 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
5933 return true;
5934 }
5935 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
5936 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
5937 return true;
5938 }
5939 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
5940 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
5941 return true;
5942 }
5943 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
5944 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
5945 return true;
5946 }
5947 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
5948 return true;
5949 }
5950 return false;
5951 } else {
5952 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
5953 }
5954 }
5955
5956 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
5957 {
5958 DeviceClass *dc = DEVICE_CLASS(oc);
5959 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5960 CPUClass *cc = CPU_CLASS(oc);
5961
5962 dc->fw_name = "PowerPC,POWER7";
5963 dc->desc = "POWER7";
5964 pcc->pvr_match = ppc_pvr_match_power7;
5965 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
5966 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
5967 pcc->init_proc = init_proc_POWER7;
5968 pcc->check_pow = check_pow_nocheck;
5969 cc->has_work = cpu_has_work_POWER7;
5970 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
5971 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5972 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5973 PPC_FLOAT_FRSQRTES |
5974 PPC_FLOAT_STFIWX |
5975 PPC_FLOAT_EXT |
5976 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5977 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5978 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5979 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
5980 PPC_SEGMENT_64B | PPC_SLBI |
5981 PPC_POPCNTB | PPC_POPCNTWD |
5982 PPC_CILDST;
5983 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
5984 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
5985 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
5986 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
5987 PPC2_PM_ISA206;
5988 pcc->msr_mask = (1ull << MSR_SF) |
5989 (1ull << MSR_VR) |
5990 (1ull << MSR_VSX) |
5991 (1ull << MSR_EE) |
5992 (1ull << MSR_PR) |
5993 (1ull << MSR_FP) |
5994 (1ull << MSR_ME) |
5995 (1ull << MSR_FE0) |
5996 (1ull << MSR_SE) |
5997 (1ull << MSR_DE) |
5998 (1ull << MSR_FE1) |
5999 (1ull << MSR_IR) |
6000 (1ull << MSR_DR) |
6001 (1ull << MSR_PMM) |
6002 (1ull << MSR_RI) |
6003 (1ull << MSR_LE);
6004 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6005 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6006 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6007 LPCR_MER | LPCR_TC |
6008 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6009 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6010 pcc->mmu_model = POWERPC_MMU_2_06;
6011 #if defined(CONFIG_SOFTMMU)
6012 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6013 pcc->lrg_decr_bits = 32;
6014 #endif
6015 pcc->excp_model = POWERPC_EXCP_POWER7;
6016 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6017 pcc->bfd_mach = bfd_mach_ppc64;
6018 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6019 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6020 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6021 POWERPC_FLAG_VSX;
6022 pcc->l1_dcache_size = 0x8000;
6023 pcc->l1_icache_size = 0x8000;
6024 }
6025
6026 static void init_proc_POWER8(CPUPPCState *env)
6027 {
6028 /* Common Registers */
6029 init_proc_book3s_common(env);
6030 register_sdr1_sprs(env);
6031 register_book3s_207_dbg_sprs(env);
6032
6033 /* Common TCG PMU */
6034 init_tcg_pmu_power8(env);
6035
6036 /* POWER8 Specific Registers */
6037 register_book3s_ids_sprs(env);
6038 register_rmor_sprs(env);
6039 register_amr_sprs(env);
6040 register_iamr_sprs(env);
6041 register_book3s_purr_sprs(env);
6042 register_power5p_common_sprs(env);
6043 register_power5p_lpar_sprs(env);
6044 register_power5p_ear_sprs(env);
6045 register_power5p_tb_sprs(env);
6046 register_power6_common_sprs(env);
6047 register_power6_dbg_sprs(env);
6048 register_power8_tce_address_control_sprs(env);
6049 register_power8_ids_sprs(env);
6050 register_power8_ebb_sprs(env);
6051 register_power8_fscr_sprs(env);
6052 register_power8_pmu_sup_sprs(env);
6053 register_power8_pmu_user_sprs(env);
6054 register_power8_tm_sprs(env);
6055 register_power8_pspb_sprs(env);
6056 register_power8_dpdes_sprs(env);
6057 register_vtb_sprs(env);
6058 register_power8_ic_sprs(env);
6059 register_power8_book4_sprs(env);
6060 register_power8_rpr_sprs(env);
6061
6062 /* env variables */
6063 env->dcache_line_size = 128;
6064 env->icache_line_size = 128;
6065
6066 /* Allocate hardware IRQ controller */
6067 init_excp_POWER8(env);
6068 ppcPOWER7_irq_init(env_archcpu(env));
6069 }
6070
6071 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
6072 {
6073 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
6074 return true;
6075 }
6076 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
6077 return true;
6078 }
6079 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
6080 return true;
6081 }
6082 return false;
6083 }
6084
6085 static bool cpu_has_work_POWER8(CPUState *cs)
6086 {
6087 PowerPCCPU *cpu = POWERPC_CPU(cs);
6088 CPUPPCState *env = &cpu->env;
6089
6090 if (cs->halted) {
6091 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6092 return false;
6093 }
6094 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6095 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6096 return true;
6097 }
6098 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6099 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6100 return true;
6101 }
6102 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6103 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6104 return true;
6105 }
6106 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6107 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6108 return true;
6109 }
6110 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6111 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6112 return true;
6113 }
6114 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6115 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6116 return true;
6117 }
6118 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6119 return true;
6120 }
6121 return false;
6122 } else {
6123 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6124 }
6125 }
6126
6127 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6128 {
6129 DeviceClass *dc = DEVICE_CLASS(oc);
6130 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6131 CPUClass *cc = CPU_CLASS(oc);
6132
6133 dc->fw_name = "PowerPC,POWER8";
6134 dc->desc = "POWER8";
6135 pcc->pvr_match = ppc_pvr_match_power8;
6136 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6137 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6138 pcc->init_proc = init_proc_POWER8;
6139 pcc->check_pow = check_pow_nocheck;
6140 cc->has_work = cpu_has_work_POWER8;
6141 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6142 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6143 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6144 PPC_FLOAT_FRSQRTES |
6145 PPC_FLOAT_STFIWX |
6146 PPC_FLOAT_EXT |
6147 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6148 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6149 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6150 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6151 PPC_SEGMENT_64B | PPC_SLBI |
6152 PPC_POPCNTB | PPC_POPCNTWD |
6153 PPC_CILDST;
6154 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6155 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6156 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6157 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6158 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6159 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6160 PPC2_TM | PPC2_PM_ISA206;
6161 pcc->msr_mask = (1ull << MSR_SF) |
6162 (1ull << MSR_HV) |
6163 (1ull << MSR_TM) |
6164 (1ull << MSR_VR) |
6165 (1ull << MSR_VSX) |
6166 (1ull << MSR_EE) |
6167 (1ull << MSR_PR) |
6168 (1ull << MSR_FP) |
6169 (1ull << MSR_ME) |
6170 (1ull << MSR_FE0) |
6171 (1ull << MSR_SE) |
6172 (1ull << MSR_DE) |
6173 (1ull << MSR_FE1) |
6174 (1ull << MSR_IR) |
6175 (1ull << MSR_DR) |
6176 (1ull << MSR_PMM) |
6177 (1ull << MSR_RI) |
6178 (1ull << MSR_TS0) |
6179 (1ull << MSR_TS1) |
6180 (1ull << MSR_LE);
6181 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6182 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6183 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6184 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6185 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6186 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6187 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6188 pcc->mmu_model = POWERPC_MMU_2_07;
6189 #if defined(CONFIG_SOFTMMU)
6190 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6191 pcc->lrg_decr_bits = 32;
6192 pcc->n_host_threads = 8;
6193 #endif
6194 pcc->excp_model = POWERPC_EXCP_POWER8;
6195 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6196 pcc->bfd_mach = bfd_mach_ppc64;
6197 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6198 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6199 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6200 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6201 pcc->l1_dcache_size = 0x8000;
6202 pcc->l1_icache_size = 0x8000;
6203 }
6204
6205 #ifdef CONFIG_SOFTMMU
6206 /*
6207 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6208 * Encoded as array of int_32s in the form:
6209 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6210 * x -> AP encoding
6211 * y -> radix mode supported page size (encoded as a shift)
6212 */
6213 static struct ppc_radix_page_info POWER9_radix_page_info = {
6214 .count = 4,
6215 .entries = {
6216 0x0000000c, /* 4K - enc: 0x0 */
6217 0xa0000010, /* 64K - enc: 0x5 */
6218 0x20000015, /* 2M - enc: 0x1 */
6219 0x4000001e /* 1G - enc: 0x2 */
6220 }
6221 };
6222 #endif /* CONFIG_SOFTMMU */
6223
6224 static void init_proc_POWER9(CPUPPCState *env)
6225 {
6226 /* Common Registers */
6227 init_proc_book3s_common(env);
6228 register_book3s_207_dbg_sprs(env);
6229
6230 /* Common TCG PMU */
6231 init_tcg_pmu_power8(env);
6232
6233 /* POWER8 Specific Registers */
6234 register_book3s_ids_sprs(env);
6235 register_amr_sprs(env);
6236 register_iamr_sprs(env);
6237 register_book3s_purr_sprs(env);
6238 register_power5p_common_sprs(env);
6239 register_power5p_lpar_sprs(env);
6240 register_power5p_ear_sprs(env);
6241 register_power5p_tb_sprs(env);
6242 register_power6_common_sprs(env);
6243 register_power6_dbg_sprs(env);
6244 register_power8_tce_address_control_sprs(env);
6245 register_power8_ids_sprs(env);
6246 register_power8_ebb_sprs(env);
6247 register_power8_fscr_sprs(env);
6248 register_power8_pmu_sup_sprs(env);
6249 register_power8_pmu_user_sprs(env);
6250 register_power8_tm_sprs(env);
6251 register_power8_pspb_sprs(env);
6252 register_power8_dpdes_sprs(env);
6253 register_vtb_sprs(env);
6254 register_power8_ic_sprs(env);
6255 register_power8_book4_sprs(env);
6256 register_power8_rpr_sprs(env);
6257 register_power9_mmu_sprs(env);
6258
6259 /* POWER9 Specific registers */
6260 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6261 spr_read_generic, spr_write_generic,
6262 KVM_REG_PPC_TIDR, 0);
6263
6264 /* FIXME: Filter fields properly based on privilege level */
6265 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6266 spr_read_generic, spr_write_generic,
6267 KVM_REG_PPC_PSSCR, 0);
6268
6269 /* env variables */
6270 env->dcache_line_size = 128;
6271 env->icache_line_size = 128;
6272
6273 /* Allocate hardware IRQ controller */
6274 init_excp_POWER9(env);
6275 ppcPOWER9_irq_init(env_archcpu(env));
6276 }
6277
6278 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
6279 {
6280 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
6281 return true;
6282 }
6283 return false;
6284 }
6285
6286 static bool cpu_has_work_POWER9(CPUState *cs)
6287 {
6288 PowerPCCPU *cpu = POWERPC_CPU(cs);
6289 CPUPPCState *env = &cpu->env;
6290
6291 if (cs->halted) {
6292 uint64_t psscr = env->spr[SPR_PSSCR];
6293
6294 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6295 return false;
6296 }
6297
6298 /* If EC is clear, just return true on any pending interrupt */
6299 if (!(psscr & PSSCR_EC)) {
6300 return true;
6301 }
6302 /* External Exception */
6303 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6304 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6305 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6306 if (heic == 0 || !msr_hv || msr_pr) {
6307 return true;
6308 }
6309 }
6310 /* Decrementer Exception */
6311 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6312 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6313 return true;
6314 }
6315 /* Machine Check or Hypervisor Maintenance Exception */
6316 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6317 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6318 return true;
6319 }
6320 /* Privileged Doorbell Exception */
6321 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6322 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6323 return true;
6324 }
6325 /* Hypervisor Doorbell Exception */
6326 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6327 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6328 return true;
6329 }
6330 /* Hypervisor virtualization exception */
6331 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6332 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6333 return true;
6334 }
6335 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6336 return true;
6337 }
6338 return false;
6339 } else {
6340 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6341 }
6342 }
6343
6344 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6345 {
6346 DeviceClass *dc = DEVICE_CLASS(oc);
6347 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6348 CPUClass *cc = CPU_CLASS(oc);
6349
6350 dc->fw_name = "PowerPC,POWER9";
6351 dc->desc = "POWER9";
6352 pcc->pvr_match = ppc_pvr_match_power9;
6353 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6354 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6355 PCR_COMPAT_2_05;
6356 pcc->init_proc = init_proc_POWER9;
6357 pcc->check_pow = check_pow_nocheck;
6358 cc->has_work = cpu_has_work_POWER9;
6359 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6360 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6361 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6362 PPC_FLOAT_FRSQRTES |
6363 PPC_FLOAT_STFIWX |
6364 PPC_FLOAT_EXT |
6365 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6366 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6367 PPC_MEM_TLBSYNC |
6368 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6369 PPC_SEGMENT_64B | PPC_SLBI |
6370 PPC_POPCNTB | PPC_POPCNTWD |
6371 PPC_CILDST;
6372 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6373 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6374 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6375 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6376 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6377 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6378 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
6379 pcc->msr_mask = (1ull << MSR_SF) |
6380 (1ull << MSR_HV) |
6381 (1ull << MSR_TM) |
6382 (1ull << MSR_VR) |
6383 (1ull << MSR_VSX) |
6384 (1ull << MSR_EE) |
6385 (1ull << MSR_PR) |
6386 (1ull << MSR_FP) |
6387 (1ull << MSR_ME) |
6388 (1ull << MSR_FE0) |
6389 (1ull << MSR_SE) |
6390 (1ull << MSR_DE) |
6391 (1ull << MSR_FE1) |
6392 (1ull << MSR_IR) |
6393 (1ull << MSR_DR) |
6394 (1ull << MSR_PMM) |
6395 (1ull << MSR_RI) |
6396 (1ull << MSR_LE);
6397 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6398 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6399 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6400 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6401 LPCR_DEE | LPCR_OEE))
6402 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6403 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6404 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6405 pcc->mmu_model = POWERPC_MMU_3_00;
6406 #if defined(CONFIG_SOFTMMU)
6407 /* segment page size remain the same */
6408 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6409 pcc->radix_page_info = &POWER9_radix_page_info;
6410 pcc->lrg_decr_bits = 56;
6411 pcc->n_host_threads = 4;
6412 #endif
6413 pcc->excp_model = POWERPC_EXCP_POWER9;
6414 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6415 pcc->bfd_mach = bfd_mach_ppc64;
6416 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6417 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6418 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6419 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6420 pcc->l1_dcache_size = 0x8000;
6421 pcc->l1_icache_size = 0x8000;
6422 }
6423
6424 #ifdef CONFIG_SOFTMMU
6425 /*
6426 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6427 * Encoded as array of int_32s in the form:
6428 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6429 * x -> AP encoding
6430 * y -> radix mode supported page size (encoded as a shift)
6431 */
6432 static struct ppc_radix_page_info POWER10_radix_page_info = {
6433 .count = 4,
6434 .entries = {
6435 0x0000000c, /* 4K - enc: 0x0 */
6436 0xa0000010, /* 64K - enc: 0x5 */
6437 0x20000015, /* 2M - enc: 0x1 */
6438 0x4000001e /* 1G - enc: 0x2 */
6439 }
6440 };
6441 #endif /* CONFIG_SOFTMMU */
6442
6443 static void init_proc_POWER10(CPUPPCState *env)
6444 {
6445 /* Common Registers */
6446 init_proc_book3s_common(env);
6447 register_book3s_207_dbg_sprs(env);
6448
6449 /* Common TCG PMU */
6450 init_tcg_pmu_power8(env);
6451
6452 /* POWER8 Specific Registers */
6453 register_book3s_ids_sprs(env);
6454 register_amr_sprs(env);
6455 register_iamr_sprs(env);
6456 register_book3s_purr_sprs(env);
6457 register_power5p_common_sprs(env);
6458 register_power5p_lpar_sprs(env);
6459 register_power5p_ear_sprs(env);
6460 register_power6_common_sprs(env);
6461 register_power6_dbg_sprs(env);
6462 register_power8_tce_address_control_sprs(env);
6463 register_power8_ids_sprs(env);
6464 register_power8_ebb_sprs(env);
6465 register_power8_fscr_sprs(env);
6466 register_power8_pmu_sup_sprs(env);
6467 register_power8_pmu_user_sprs(env);
6468 register_power8_tm_sprs(env);
6469 register_power8_pspb_sprs(env);
6470 register_vtb_sprs(env);
6471 register_power8_ic_sprs(env);
6472 register_power8_book4_sprs(env);
6473 register_power8_rpr_sprs(env);
6474 register_power9_mmu_sprs(env);
6475
6476 /* FIXME: Filter fields properly based on privilege level */
6477 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6478 spr_read_generic, spr_write_generic,
6479 KVM_REG_PPC_PSSCR, 0);
6480
6481 /* env variables */
6482 env->dcache_line_size = 128;
6483 env->icache_line_size = 128;
6484
6485 /* Allocate hardware IRQ controller */
6486 init_excp_POWER10(env);
6487 ppcPOWER9_irq_init(env_archcpu(env));
6488 }
6489
6490 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
6491 {
6492 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
6493 return true;
6494 }
6495 return false;
6496 }
6497
6498 static bool cpu_has_work_POWER10(CPUState *cs)
6499 {
6500 PowerPCCPU *cpu = POWERPC_CPU(cs);
6501 CPUPPCState *env = &cpu->env;
6502
6503 if (cs->halted) {
6504 uint64_t psscr = env->spr[SPR_PSSCR];
6505
6506 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6507 return false;
6508 }
6509
6510 /* If EC is clear, just return true on any pending interrupt */
6511 if (!(psscr & PSSCR_EC)) {
6512 return true;
6513 }
6514 /* External Exception */
6515 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6516 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6517 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6518 if (heic == 0 || !msr_hv || msr_pr) {
6519 return true;
6520 }
6521 }
6522 /* Decrementer Exception */
6523 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6524 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6525 return true;
6526 }
6527 /* Machine Check or Hypervisor Maintenance Exception */
6528 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6529 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6530 return true;
6531 }
6532 /* Privileged Doorbell Exception */
6533 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6534 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6535 return true;
6536 }
6537 /* Hypervisor Doorbell Exception */
6538 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6539 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6540 return true;
6541 }
6542 /* Hypervisor virtualization exception */
6543 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6544 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6545 return true;
6546 }
6547 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6548 return true;
6549 }
6550 return false;
6551 } else {
6552 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6553 }
6554 }
6555
6556 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
6557 {
6558 DeviceClass *dc = DEVICE_CLASS(oc);
6559 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6560 CPUClass *cc = CPU_CLASS(oc);
6561
6562 dc->fw_name = "PowerPC,POWER10";
6563 dc->desc = "POWER10";
6564 pcc->pvr_match = ppc_pvr_match_power10;
6565 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
6566 PCR_COMPAT_3_00;
6567 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
6568 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6569 pcc->init_proc = init_proc_POWER10;
6570 pcc->check_pow = check_pow_nocheck;
6571 cc->has_work = cpu_has_work_POWER10;
6572 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6573 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6574 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6575 PPC_FLOAT_FRSQRTES |
6576 PPC_FLOAT_STFIWX |
6577 PPC_FLOAT_EXT |
6578 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6579 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6580 PPC_MEM_TLBSYNC |
6581 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6582 PPC_SEGMENT_64B | PPC_SLBI |
6583 PPC_POPCNTB | PPC_POPCNTWD |
6584 PPC_CILDST;
6585 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6586 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6587 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6588 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6589 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6590 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6591 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
6592 pcc->msr_mask = (1ull << MSR_SF) |
6593 (1ull << MSR_HV) |
6594 (1ull << MSR_TM) |
6595 (1ull << MSR_VR) |
6596 (1ull << MSR_VSX) |
6597 (1ull << MSR_EE) |
6598 (1ull << MSR_PR) |
6599 (1ull << MSR_FP) |
6600 (1ull << MSR_ME) |
6601 (1ull << MSR_FE0) |
6602 (1ull << MSR_SE) |
6603 (1ull << MSR_DE) |
6604 (1ull << MSR_FE1) |
6605 (1ull << MSR_IR) |
6606 (1ull << MSR_DR) |
6607 (1ull << MSR_PMM) |
6608 (1ull << MSR_RI) |
6609 (1ull << MSR_LE);
6610 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6611 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6612 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6613 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6614 LPCR_DEE | LPCR_OEE))
6615 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6616 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6617 /* DD2 adds an extra HAIL bit */
6618 pcc->lpcr_mask |= LPCR_HAIL;
6619
6620 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6621 pcc->mmu_model = POWERPC_MMU_3_00;
6622 #if defined(CONFIG_SOFTMMU)
6623 /* segment page size remain the same */
6624 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6625 pcc->radix_page_info = &POWER10_radix_page_info;
6626 pcc->lrg_decr_bits = 56;
6627 #endif
6628 pcc->excp_model = POWERPC_EXCP_POWER10;
6629 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6630 pcc->bfd_mach = bfd_mach_ppc64;
6631 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6632 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6633 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6634 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6635 pcc->l1_dcache_size = 0x8000;
6636 pcc->l1_icache_size = 0x8000;
6637 }
6638
6639 #if !defined(CONFIG_USER_ONLY)
6640 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6641 {
6642 CPUPPCState *env = &cpu->env;
6643
6644 cpu->vhyp = vhyp;
6645
6646 /*
6647 * With a virtual hypervisor mode we never allow the CPU to go
6648 * hypervisor mode itself
6649 */
6650 env->msr_mask &= ~MSR_HVB;
6651 }
6652
6653 #endif /* !defined(CONFIG_USER_ONLY) */
6654
6655 #endif /* defined(TARGET_PPC64) */
6656
6657 /*****************************************************************************/
6658 /* Generic CPU instantiation routine */
6659 static void init_ppc_proc(PowerPCCPU *cpu)
6660 {
6661 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6662 CPUPPCState *env = &cpu->env;
6663 #if !defined(CONFIG_USER_ONLY)
6664 int i;
6665
6666 env->irq_inputs = NULL;
6667 /* Set all exception vectors to an invalid address */
6668 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6669 env->excp_vectors[i] = (target_ulong)(-1ULL);
6670 }
6671 env->ivor_mask = 0x00000000;
6672 env->ivpr_mask = 0x00000000;
6673 /* Default MMU definitions */
6674 env->nb_BATs = 0;
6675 env->nb_tlb = 0;
6676 env->nb_ways = 0;
6677 env->tlb_type = TLB_NONE;
6678 #endif
6679 /* Register SPR common to all PowerPC implementations */
6680 register_generic_sprs(cpu);
6681
6682 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6683 (*pcc->init_proc)(env);
6684
6685 #if !defined(CONFIG_USER_ONLY)
6686 ppc_gdb_gen_spr_xml(cpu);
6687 #endif
6688
6689 /* MSR bits & flags consistency checks */
6690 if (env->msr_mask & (1 << 25)) {
6691 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6692 case POWERPC_FLAG_SPE:
6693 case POWERPC_FLAG_VRE:
6694 break;
6695 default:
6696 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6697 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6698 exit(1);
6699 }
6700 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6701 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6702 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6703 exit(1);
6704 }
6705 if (env->msr_mask & (1 << 17)) {
6706 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6707 case POWERPC_FLAG_TGPR:
6708 case POWERPC_FLAG_CE:
6709 break;
6710 default:
6711 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6712 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6713 exit(1);
6714 }
6715 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6716 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6717 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6718 exit(1);
6719 }
6720 if (env->msr_mask & (1 << 10)) {
6721 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6722 POWERPC_FLAG_UBLE)) {
6723 case POWERPC_FLAG_SE:
6724 case POWERPC_FLAG_DWE:
6725 case POWERPC_FLAG_UBLE:
6726 break;
6727 default:
6728 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6729 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6730 "POWERPC_FLAG_UBLE\n");
6731 exit(1);
6732 }
6733 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6734 POWERPC_FLAG_UBLE)) {
6735 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6736 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6737 "POWERPC_FLAG_UBLE\n");
6738 exit(1);
6739 }
6740 if (env->msr_mask & (1 << 9)) {
6741 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6742 case POWERPC_FLAG_BE:
6743 case POWERPC_FLAG_DE:
6744 break;
6745 default:
6746 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6747 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6748 exit(1);
6749 }
6750 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6751 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6752 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6753 exit(1);
6754 }
6755 if (env->msr_mask & (1 << 2)) {
6756 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6757 case POWERPC_FLAG_PX:
6758 case POWERPC_FLAG_PMM:
6759 break;
6760 default:
6761 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6762 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6763 exit(1);
6764 }
6765 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6766 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6767 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6768 exit(1);
6769 }
6770 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6771 fprintf(stderr, "PowerPC flags inconsistency\n"
6772 "Should define the time-base and decrementer clock source\n");
6773 exit(1);
6774 }
6775 /* Allocate TLBs buffer when needed */
6776 #if !defined(CONFIG_USER_ONLY)
6777 if (env->nb_tlb != 0) {
6778 int nb_tlb = env->nb_tlb;
6779 if (env->id_tlbs != 0) {
6780 nb_tlb *= 2;
6781 }
6782 switch (env->tlb_type) {
6783 case TLB_6XX:
6784 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
6785 break;
6786 case TLB_EMB:
6787 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
6788 break;
6789 case TLB_MAS:
6790 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
6791 break;
6792 }
6793 /* Pre-compute some useful values */
6794 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6795 }
6796 if (env->irq_inputs == NULL) {
6797 warn_report("no internal IRQ controller registered."
6798 " Attempt QEMU to crash very soon !");
6799 }
6800 #endif
6801 if (env->check_pow == NULL) {
6802 warn_report("no power management check handler registered."
6803 " Attempt QEMU to crash very soon !");
6804 }
6805 }
6806
6807
6808 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6809 {
6810 CPUState *cs = CPU(dev);
6811 PowerPCCPU *cpu = POWERPC_CPU(dev);
6812 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6813 Error *local_err = NULL;
6814
6815 cpu_exec_realizefn(cs, &local_err);
6816 if (local_err != NULL) {
6817 error_propagate(errp, local_err);
6818 return;
6819 }
6820 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6821 cpu->vcpu_id = cs->cpu_index;
6822 }
6823
6824 if (tcg_enabled()) {
6825 if (ppc_fixup_cpu(cpu) != 0) {
6826 error_setg(errp, "Unable to emulate selected CPU with TCG");
6827 goto unrealize;
6828 }
6829 }
6830
6831 create_ppc_opcodes(cpu, &local_err);
6832 if (local_err != NULL) {
6833 error_propagate(errp, local_err);
6834 goto unrealize;
6835 }
6836 init_ppc_proc(cpu);
6837
6838 ppc_gdb_init(cs, pcc);
6839 qemu_init_vcpu(cs);
6840
6841 pcc->parent_realize(dev, errp);
6842
6843 return;
6844
6845 unrealize:
6846 cpu_exec_unrealizefn(cs);
6847 }
6848
6849 static void ppc_cpu_unrealize(DeviceState *dev)
6850 {
6851 PowerPCCPU *cpu = POWERPC_CPU(dev);
6852 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6853
6854 pcc->parent_unrealize(dev);
6855
6856 cpu_remove_sync(CPU(cpu));
6857
6858 destroy_ppc_opcodes(cpu);
6859 }
6860
6861 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6862 {
6863 ObjectClass *oc = (ObjectClass *)a;
6864 uint32_t pvr = *(uint32_t *)b;
6865 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6866
6867 /* -cpu host does a PVR lookup during construction */
6868 if (unlikely(strcmp(object_class_get_name(oc),
6869 TYPE_HOST_POWERPC_CPU) == 0)) {
6870 return -1;
6871 }
6872
6873 return pcc->pvr == pvr ? 0 : -1;
6874 }
6875
6876 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6877 {
6878 GSList *list, *item;
6879 PowerPCCPUClass *pcc = NULL;
6880
6881 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6882 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
6883 if (item != NULL) {
6884 pcc = POWERPC_CPU_CLASS(item->data);
6885 }
6886 g_slist_free(list);
6887
6888 return pcc;
6889 }
6890
6891 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
6892 {
6893 ObjectClass *oc = (ObjectClass *)a;
6894 uint32_t pvr = *(uint32_t *)b;
6895 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6896
6897 /* -cpu host does a PVR lookup during construction */
6898 if (unlikely(strcmp(object_class_get_name(oc),
6899 TYPE_HOST_POWERPC_CPU) == 0)) {
6900 return -1;
6901 }
6902
6903 if (pcc->pvr_match(pcc, pvr)) {
6904 return 0;
6905 }
6906
6907 return -1;
6908 }
6909
6910 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
6911 {
6912 GSList *list, *item;
6913 PowerPCCPUClass *pcc = NULL;
6914
6915 list = object_class_get_list(TYPE_POWERPC_CPU, true);
6916 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
6917 if (item != NULL) {
6918 pcc = POWERPC_CPU_CLASS(item->data);
6919 }
6920 g_slist_free(list);
6921
6922 return pcc;
6923 }
6924
6925 static const char *ppc_cpu_lookup_alias(const char *alias)
6926 {
6927 int ai;
6928
6929 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
6930 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
6931 return ppc_cpu_aliases[ai].model;
6932 }
6933 }
6934
6935 return NULL;
6936 }
6937
6938 static ObjectClass *ppc_cpu_class_by_name(const char *name)
6939 {
6940 char *cpu_model, *typename;
6941 ObjectClass *oc;
6942 const char *p;
6943 unsigned long pvr;
6944
6945 /*
6946 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
6947 * 0x prefix if present)
6948 */
6949 if (!qemu_strtoul(name, &p, 16, &pvr)) {
6950 int len = p - name;
6951 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
6952 if ((len == 8) && (*p == '\0')) {
6953 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
6954 }
6955 }
6956
6957 cpu_model = g_ascii_strdown(name, -1);
6958 p = ppc_cpu_lookup_alias(cpu_model);
6959 if (p) {
6960 g_free(cpu_model);
6961 cpu_model = g_strdup(p);
6962 }
6963
6964 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
6965 oc = object_class_by_name(typename);
6966 g_free(typename);
6967 g_free(cpu_model);
6968
6969 return oc;
6970 }
6971
6972 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
6973 {
6974 ObjectClass *oc = OBJECT_CLASS(pcc);
6975
6976 while (oc && !object_class_is_abstract(oc)) {
6977 oc = object_class_get_parent(oc);
6978 }
6979 assert(oc);
6980
6981 return POWERPC_CPU_CLASS(oc);
6982 }
6983
6984 /* Sort by PVR, ordering special case "host" last. */
6985 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
6986 {
6987 ObjectClass *oc_a = (ObjectClass *)a;
6988 ObjectClass *oc_b = (ObjectClass *)b;
6989 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
6990 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
6991 const char *name_a = object_class_get_name(oc_a);
6992 const char *name_b = object_class_get_name(oc_b);
6993
6994 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
6995 return 1;
6996 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
6997 return -1;
6998 } else {
6999 /* Avoid an integer overflow during subtraction */
7000 if (pcc_a->pvr < pcc_b->pvr) {
7001 return -1;
7002 } else if (pcc_a->pvr > pcc_b->pvr) {
7003 return 1;
7004 } else {
7005 return 0;
7006 }
7007 }
7008 }
7009
7010 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7011 {
7012 ObjectClass *oc = data;
7013 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7014 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7015 const char *typename = object_class_get_name(oc);
7016 char *name;
7017 int i;
7018
7019 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7020 return;
7021 }
7022
7023 name = g_strndup(typename,
7024 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7025 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7026 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7027 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7028 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7029
7030 if (alias_oc != oc) {
7031 continue;
7032 }
7033 /*
7034 * If running with KVM, we might update the family alias later, so
7035 * avoid printing the wrong alias here and use "preferred" instead
7036 */
7037 if (strcmp(alias->alias, family->desc) == 0) {
7038 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7039 alias->alias, family->desc);
7040 } else {
7041 qemu_printf("PowerPC %-16s (alias for %s)\n",
7042 alias->alias, name);
7043 }
7044 }
7045 g_free(name);
7046 }
7047
7048 void ppc_cpu_list(void)
7049 {
7050 GSList *list;
7051
7052 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7053 list = g_slist_sort(list, ppc_cpu_list_compare);
7054 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7055 g_slist_free(list);
7056
7057 #ifdef CONFIG_KVM
7058 qemu_printf("\n");
7059 qemu_printf("PowerPC %s\n", "host");
7060 #endif
7061 }
7062
7063 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7064 {
7065 ObjectClass *oc = data;
7066 CpuDefinitionInfoList **first = user_data;
7067 const char *typename;
7068 CpuDefinitionInfo *info;
7069
7070 typename = object_class_get_name(oc);
7071 info = g_malloc0(sizeof(*info));
7072 info->name = g_strndup(typename,
7073 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7074
7075 QAPI_LIST_PREPEND(*first, info);
7076 }
7077
7078 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7079 {
7080 CpuDefinitionInfoList *cpu_list = NULL;
7081 GSList *list;
7082 int i;
7083
7084 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7085 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7086 g_slist_free(list);
7087
7088 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7089 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7090 ObjectClass *oc;
7091 CpuDefinitionInfo *info;
7092
7093 oc = ppc_cpu_class_by_name(alias->model);
7094 if (oc == NULL) {
7095 continue;
7096 }
7097
7098 info = g_malloc0(sizeof(*info));
7099 info->name = g_strdup(alias->alias);
7100 info->q_typename = g_strdup(object_class_get_name(oc));
7101
7102 QAPI_LIST_PREPEND(cpu_list, info);
7103 }
7104
7105 return cpu_list;
7106 }
7107
7108 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7109 {
7110 PowerPCCPU *cpu = POWERPC_CPU(cs);
7111
7112 cpu->env.nip = value;
7113 }
7114
7115 static bool ppc_cpu_has_work(CPUState *cs)
7116 {
7117 PowerPCCPU *cpu = POWERPC_CPU(cs);
7118 CPUPPCState *env = &cpu->env;
7119
7120 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7121 }
7122
7123 static void ppc_cpu_reset(DeviceState *dev)
7124 {
7125 CPUState *s = CPU(dev);
7126 PowerPCCPU *cpu = POWERPC_CPU(s);
7127 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7128 CPUPPCState *env = &cpu->env;
7129 target_ulong msr;
7130 int i;
7131
7132 pcc->parent_reset(dev);
7133
7134 msr = (target_ulong)0;
7135 msr |= (target_ulong)MSR_HVB;
7136 msr |= (target_ulong)1 << MSR_EP;
7137 #if defined(DO_SINGLE_STEP) && 0
7138 /* Single step trace mode */
7139 msr |= (target_ulong)1 << MSR_SE;
7140 msr |= (target_ulong)1 << MSR_BE;
7141 #endif
7142 #if defined(CONFIG_USER_ONLY)
7143 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7144 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7145 msr |= (target_ulong)1 << MSR_FE1;
7146 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7147 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7148 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7149 msr |= (target_ulong)1 << MSR_PR;
7150 #if defined(TARGET_PPC64)
7151 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7152 #endif
7153 #if !TARGET_BIG_ENDIAN
7154 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7155 if (!((env->msr_mask >> MSR_LE) & 1)) {
7156 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7157 exit(1);
7158 }
7159 #endif
7160 #endif
7161
7162 #if defined(TARGET_PPC64)
7163 if (mmu_is_64bit(env->mmu_model)) {
7164 msr |= (1ULL << MSR_SF);
7165 }
7166 #endif
7167
7168 hreg_store_msr(env, msr, 1);
7169
7170 #if !defined(CONFIG_USER_ONLY)
7171 env->nip = env->hreset_vector | env->excp_prefix;
7172
7173 if (tcg_enabled()) {
7174 if (env->mmu_model != POWERPC_MMU_REAL) {
7175 ppc_tlb_invalidate_all(env);
7176 }
7177 pmu_update_summaries(env);
7178 }
7179 #endif
7180 hreg_compute_hflags(env);
7181 env->reserve_addr = (target_ulong)-1ULL;
7182 /* Be sure no exception or interrupt is pending */
7183 env->pending_interrupts = 0;
7184 s->exception_index = POWERPC_EXCP_NONE;
7185 env->error_code = 0;
7186 ppc_irq_reset(cpu);
7187
7188 /* tininess for underflow is detected before rounding */
7189 set_float_detect_tininess(float_tininess_before_rounding,
7190 &env->fp_status);
7191
7192 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7193 ppc_spr_t *spr = &env->spr_cb[i];
7194
7195 if (!spr->name) {
7196 continue;
7197 }
7198 env->spr[i] = spr->default_value;
7199 }
7200 }
7201
7202 #ifndef CONFIG_USER_ONLY
7203
7204 static bool ppc_cpu_is_big_endian(CPUState *cs)
7205 {
7206 PowerPCCPU *cpu = POWERPC_CPU(cs);
7207 CPUPPCState *env = &cpu->env;
7208
7209 cpu_synchronize_state(cs);
7210
7211 return !msr_le;
7212 }
7213
7214 #ifdef CONFIG_TCG
7215 static void ppc_cpu_exec_enter(CPUState *cs)
7216 {
7217 PowerPCCPU *cpu = POWERPC_CPU(cs);
7218
7219 if (cpu->vhyp) {
7220 PPCVirtualHypervisorClass *vhc =
7221 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7222 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7223 }
7224 }
7225
7226 static void ppc_cpu_exec_exit(CPUState *cs)
7227 {
7228 PowerPCCPU *cpu = POWERPC_CPU(cs);
7229
7230 if (cpu->vhyp) {
7231 PPCVirtualHypervisorClass *vhc =
7232 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7233 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7234 }
7235 }
7236 #endif /* CONFIG_TCG */
7237
7238 #endif /* !CONFIG_USER_ONLY */
7239
7240 static void ppc_cpu_instance_init(Object *obj)
7241 {
7242 PowerPCCPU *cpu = POWERPC_CPU(obj);
7243 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7244 CPUPPCState *env = &cpu->env;
7245
7246 cpu_set_cpustate_pointers(cpu);
7247 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7248
7249 env->msr_mask = pcc->msr_mask;
7250 env->mmu_model = pcc->mmu_model;
7251 env->excp_model = pcc->excp_model;
7252 env->bus_model = pcc->bus_model;
7253 env->insns_flags = pcc->insns_flags;
7254 env->insns_flags2 = pcc->insns_flags2;
7255 env->flags = pcc->flags;
7256 env->bfd_mach = pcc->bfd_mach;
7257 env->check_pow = pcc->check_pow;
7258
7259 /*
7260 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7261 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7262 * mode support will remain, thus enforcing that we cannot use
7263 * priv. instructions in guest in PAPR mode. For 970 we currently
7264 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7265 * 970. If we ever want to support 970 HV mode, we'll have to add
7266 * a processor attribute of some sort.
7267 */
7268 #if !defined(CONFIG_USER_ONLY)
7269 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7270 #endif
7271
7272 ppc_hash64_init(cpu);
7273 }
7274
7275 static void ppc_cpu_instance_finalize(Object *obj)
7276 {
7277 PowerPCCPU *cpu = POWERPC_CPU(obj);
7278
7279 ppc_hash64_finalize(cpu);
7280 }
7281
7282 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
7283 {
7284 return pcc->pvr == pvr;
7285 }
7286
7287 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7288 {
7289 PowerPCCPU *cpu = POWERPC_CPU(cs);
7290 CPUPPCState *env = &cpu->env;
7291
7292 if ((env->hflags >> MSR_LE) & 1) {
7293 info->endian = BFD_ENDIAN_LITTLE;
7294 }
7295 info->mach = env->bfd_mach;
7296 if (!env->bfd_mach) {
7297 #ifdef TARGET_PPC64
7298 info->mach = bfd_mach_ppc64;
7299 #else
7300 info->mach = bfd_mach_ppc;
7301 #endif
7302 }
7303 info->disassembler_options = (char *)"any";
7304 info->print_insn = print_insn_ppc;
7305
7306 info->cap_arch = CS_ARCH_PPC;
7307 #ifdef TARGET_PPC64
7308 info->cap_mode = CS_MODE_64;
7309 #endif
7310 }
7311
7312 static Property ppc_cpu_properties[] = {
7313 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7314 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7315 false),
7316 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7317 false),
7318 DEFINE_PROP_END_OF_LIST(),
7319 };
7320
7321 #ifndef CONFIG_USER_ONLY
7322 #include "hw/core/sysemu-cpu-ops.h"
7323
7324 static const struct SysemuCPUOps ppc_sysemu_ops = {
7325 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7326 .write_elf32_note = ppc32_cpu_write_elf32_note,
7327 .write_elf64_note = ppc64_cpu_write_elf64_note,
7328 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7329 .legacy_vmsd = &vmstate_ppc_cpu,
7330 };
7331 #endif
7332
7333 #ifdef CONFIG_TCG
7334 #include "hw/core/tcg-cpu-ops.h"
7335
7336 static const struct TCGCPUOps ppc_tcg_ops = {
7337 .initialize = ppc_translate_init,
7338
7339 #ifdef CONFIG_USER_ONLY
7340 .record_sigsegv = ppc_cpu_record_sigsegv,
7341 #else
7342 .tlb_fill = ppc_cpu_tlb_fill,
7343 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7344 .do_interrupt = ppc_cpu_do_interrupt,
7345 .cpu_exec_enter = ppc_cpu_exec_enter,
7346 .cpu_exec_exit = ppc_cpu_exec_exit,
7347 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7348 #endif /* !CONFIG_USER_ONLY */
7349 };
7350 #endif /* CONFIG_TCG */
7351
7352 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7353 {
7354 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7355 CPUClass *cc = CPU_CLASS(oc);
7356 DeviceClass *dc = DEVICE_CLASS(oc);
7357
7358 device_class_set_parent_realize(dc, ppc_cpu_realize,
7359 &pcc->parent_realize);
7360 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7361 &pcc->parent_unrealize);
7362 pcc->pvr_match = ppc_pvr_match_default;
7363 device_class_set_props(dc, ppc_cpu_properties);
7364
7365 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
7366
7367 cc->class_by_name = ppc_cpu_class_by_name;
7368 cc->has_work = ppc_cpu_has_work;
7369 cc->dump_state = ppc_cpu_dump_state;
7370 cc->set_pc = ppc_cpu_set_pc;
7371 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7372 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7373 #ifndef CONFIG_USER_ONLY
7374 cc->sysemu_ops = &ppc_sysemu_ops;
7375 #endif
7376
7377 cc->gdb_num_core_regs = 71;
7378 #ifndef CONFIG_USER_ONLY
7379 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7380 #endif
7381 #ifdef USE_APPLE_GDB
7382 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7383 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7384 cc->gdb_num_core_regs = 71 + 32;
7385 #endif
7386
7387 cc->gdb_arch_name = ppc_gdb_arch_name;
7388 #if defined(TARGET_PPC64)
7389 cc->gdb_core_xml_file = "power64-core.xml";
7390 #else
7391 cc->gdb_core_xml_file = "power-core.xml";
7392 #endif
7393 cc->disas_set_info = ppc_disas_set_info;
7394
7395 dc->fw_name = "PowerPC,UNKNOWN";
7396
7397 #ifdef CONFIG_TCG
7398 cc->tcg_ops = &ppc_tcg_ops;
7399 #endif /* CONFIG_TCG */
7400 }
7401
7402 static const TypeInfo ppc_cpu_type_info = {
7403 .name = TYPE_POWERPC_CPU,
7404 .parent = TYPE_CPU,
7405 .instance_size = sizeof(PowerPCCPU),
7406 .instance_align = __alignof__(PowerPCCPU),
7407 .instance_init = ppc_cpu_instance_init,
7408 .instance_finalize = ppc_cpu_instance_finalize,
7409 .abstract = true,
7410 .class_size = sizeof(PowerPCCPUClass),
7411 .class_init = ppc_cpu_class_init,
7412 };
7413
7414 #ifndef CONFIG_USER_ONLY
7415 static const TypeInfo ppc_vhyp_type_info = {
7416 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7417 .parent = TYPE_INTERFACE,
7418 .class_size = sizeof(PPCVirtualHypervisorClass),
7419 };
7420 #endif
7421
7422 static void ppc_cpu_register_types(void)
7423 {
7424 type_register_static(&ppc_cpu_type_info);
7425 #ifndef CONFIG_USER_ONLY
7426 type_register_static(&ppc_vhyp_type_info);
7427 #endif
7428 }
7429
7430 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7431 {
7432 #define RGPL 4
7433 #define RFPL 4
7434
7435 PowerPCCPU *cpu = POWERPC_CPU(cs);
7436 CPUPPCState *env = &cpu->env;
7437 int i;
7438
7439 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7440 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7441 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7442 cs->cpu_index);
7443 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7444 "%08x iidx %d didx %d\n",
7445 env->msr, env->spr[SPR_HID0], env->hflags,
7446 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
7447 #if !defined(NO_TIMER_DUMP)
7448 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7449 #if !defined(CONFIG_USER_ONLY)
7450 " DECR " TARGET_FMT_lu
7451 #endif
7452 "\n",
7453 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7454 #if !defined(CONFIG_USER_ONLY)
7455 , cpu_ppc_load_decr(env)
7456 #endif
7457 );
7458 #endif
7459 for (i = 0; i < 32; i++) {
7460 if ((i & (RGPL - 1)) == 0) {
7461 qemu_fprintf(f, "GPR%02d", i);
7462 }
7463 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7464 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7465 qemu_fprintf(f, "\n");
7466 }
7467 }
7468 qemu_fprintf(f, "CR ");
7469 for (i = 0; i < 8; i++)
7470 qemu_fprintf(f, "%01x", env->crf[i]);
7471 qemu_fprintf(f, " [");
7472 for (i = 0; i < 8; i++) {
7473 char a = '-';
7474 if (env->crf[i] & 0x08) {
7475 a = 'L';
7476 } else if (env->crf[i] & 0x04) {
7477 a = 'G';
7478 } else if (env->crf[i] & 0x02) {
7479 a = 'E';
7480 }
7481 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7482 }
7483 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7484 env->reserve_addr);
7485
7486 if (flags & CPU_DUMP_FPU) {
7487 for (i = 0; i < 32; i++) {
7488 if ((i & (RFPL - 1)) == 0) {
7489 qemu_fprintf(f, "FPR%02d", i);
7490 }
7491 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7492 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7493 qemu_fprintf(f, "\n");
7494 }
7495 }
7496 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7497 }
7498
7499 #if !defined(CONFIG_USER_ONLY)
7500 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7501 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7502 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7503 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7504
7505 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7506 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7507 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7508 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7509
7510 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7511 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7512 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7513 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7514
7515 switch (env->excp_model) {
7516 #if defined(TARGET_PPC64)
7517 case POWERPC_EXCP_POWER7:
7518 case POWERPC_EXCP_POWER8:
7519 case POWERPC_EXCP_POWER9:
7520 case POWERPC_EXCP_POWER10:
7521 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7522 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7523 break;
7524 #endif
7525 case POWERPC_EXCP_BOOKE:
7526 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7527 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7528 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7529 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7530
7531 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7532 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7533 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7534 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7535
7536 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7537 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7538 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7539 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7540
7541 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7542 " EPR " TARGET_FMT_lx "\n",
7543 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7544 env->spr[SPR_BOOKE_EPR]);
7545
7546 /* FSL-specific */
7547 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7548 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7549 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7550 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7551
7552 /*
7553 * IVORs are left out as they are large and do not change often --
7554 * they can be read with "p $ivor0", "p $ivor1", etc.
7555 */
7556 break;
7557 case POWERPC_EXCP_40x:
7558 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7559 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7560 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7561 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7562
7563 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7564 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7565 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7566 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7567 break;
7568 default:
7569 break;
7570 }
7571
7572 #if defined(TARGET_PPC64)
7573 if (env->flags & POWERPC_FLAG_CFAR) {
7574 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7575 }
7576 #endif
7577
7578 if (env->spr_cb[SPR_LPCR].name) {
7579 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7580 }
7581
7582 switch (env->mmu_model) {
7583 case POWERPC_MMU_32B:
7584 case POWERPC_MMU_SOFT_6xx:
7585 #if defined(TARGET_PPC64)
7586 case POWERPC_MMU_64B:
7587 case POWERPC_MMU_2_03:
7588 case POWERPC_MMU_2_06:
7589 case POWERPC_MMU_2_07:
7590 case POWERPC_MMU_3_00:
7591 #endif
7592 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7593 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7594 }
7595 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7596 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7597 }
7598 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7599 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7600 break;
7601 case POWERPC_MMU_BOOKE206:
7602 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7603 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7604 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7605 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7606
7607 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7608 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7609 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7610 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7611
7612 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7613 " TLB1CFG " TARGET_FMT_lx "\n",
7614 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7615 env->spr[SPR_BOOKE_TLB1CFG]);
7616 break;
7617 default:
7618 break;
7619 }
7620 #endif
7621
7622 #undef RGPL
7623 #undef RFPL
7624 }
7625 type_init(ppc_cpu_register_types)
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