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Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request...
[mirror_qemu.git] / target / ppc / cpu_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_tcg.h"
48
49 /* #define PPC_DEBUG_SPR */
50 /* #define USE_APPLE_GDB */
51
52 static inline void vscr_init(CPUPPCState *env, uint32_t val)
53 {
54 /* Altivec always uses round-to-nearest */
55 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
56 ppc_store_vscr(env, val);
57 }
58
59 /**
60 * _spr_register
61 *
62 * Register an SPR with all the callbacks required for tcg,
63 * and the ID number for KVM.
64 *
65 * The reason for the conditional compilation is that the tcg functions
66 * may be compiled out, and the system kvm header may not be available
67 * for supplying the ID numbers. This is ugly, but the best we can do.
68 */
69
70 #ifdef CONFIG_TCG
71 # define USR_ARG(X) X,
72 # ifdef CONFIG_USER_ONLY
73 # define SYS_ARG(X)
74 # else
75 # define SYS_ARG(X) X,
76 # endif
77 #else
78 # define USR_ARG(X)
79 # define SYS_ARG(X)
80 #endif
81 #ifdef CONFIG_KVM
82 # define KVM_ARG(X) X,
83 #else
84 # define KVM_ARG(X)
85 #endif
86
87 typedef void spr_callback(DisasContext *, int, int);
88
89 static void _spr_register(CPUPPCState *env, int num, const char *name,
90 USR_ARG(spr_callback *uea_read)
91 USR_ARG(spr_callback *uea_write)
92 SYS_ARG(spr_callback *oea_read)
93 SYS_ARG(spr_callback *oea_write)
94 SYS_ARG(spr_callback *hea_read)
95 SYS_ARG(spr_callback *hea_write)
96 KVM_ARG(uint64_t one_reg_id)
97 target_ulong initial_value)
98 {
99 ppc_spr_t *spr = &env->spr_cb[num];
100
101 /* No SPR should be registered twice. */
102 assert(spr->name == NULL);
103 assert(name != NULL);
104
105 spr->name = name;
106 spr->default_value = initial_value;
107 env->spr[num] = initial_value;
108
109 #ifdef CONFIG_TCG
110 spr->uea_read = uea_read;
111 spr->uea_write = uea_write;
112 # ifndef CONFIG_USER_ONLY
113 spr->oea_read = oea_read;
114 spr->oea_write = oea_write;
115 spr->hea_read = hea_read;
116 spr->hea_write = hea_write;
117 # endif
118 #endif
119 #ifdef CONFIG_KVM
120 spr->one_reg_id = one_reg_id;
121 #endif
122 }
123
124 /* spr_register_kvm_hv passes all required arguments. */
125 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
126 oea_read, oea_write, hea_read, hea_write, \
127 one_reg_id, initial_value) \
128 _spr_register(env, num, name, \
129 USR_ARG(uea_read) USR_ARG(uea_write) \
130 SYS_ARG(oea_read) SYS_ARG(oea_write) \
131 SYS_ARG(hea_read) SYS_ARG(hea_write) \
132 KVM_ARG(one_reg_id) initial_value)
133
134 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
135 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
136 oea_read, oea_write, one_reg_id, ival) \
137 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
138 oea_write, oea_read, oea_write, one_reg_id, ival)
139
140 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
141 #define spr_register_hv(env, num, name, uea_read, uea_write, \
142 oea_read, oea_write, hea_read, hea_write, ival) \
143 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
144 oea_write, hea_read, hea_write, 0, ival)
145
146 #define spr_register(env, num, name, uea_read, uea_write, \
147 oea_read, oea_write, ival) \
148 spr_register_kvm(env, num, name, uea_read, uea_write, \
149 oea_read, oea_write, 0, ival)
150
151 /* Generic PowerPC SPRs */
152 static void register_generic_sprs(CPUPPCState *env)
153 {
154 /* Integer processing */
155 spr_register(env, SPR_XER, "XER",
156 &spr_read_xer, &spr_write_xer,
157 &spr_read_xer, &spr_write_xer,
158 0x00000000);
159 /* Branch control */
160 spr_register(env, SPR_LR, "LR",
161 &spr_read_lr, &spr_write_lr,
162 &spr_read_lr, &spr_write_lr,
163 0x00000000);
164 spr_register(env, SPR_CTR, "CTR",
165 &spr_read_ctr, &spr_write_ctr,
166 &spr_read_ctr, &spr_write_ctr,
167 0x00000000);
168 /* Interrupt processing */
169 spr_register(env, SPR_SRR0, "SRR0",
170 SPR_NOACCESS, SPR_NOACCESS,
171 &spr_read_generic, &spr_write_generic,
172 0x00000000);
173 spr_register(env, SPR_SRR1, "SRR1",
174 SPR_NOACCESS, SPR_NOACCESS,
175 &spr_read_generic, &spr_write_generic,
176 0x00000000);
177 /* Processor control */
178 spr_register(env, SPR_SPRG0, "SPRG0",
179 SPR_NOACCESS, SPR_NOACCESS,
180 &spr_read_generic, &spr_write_generic,
181 0x00000000);
182 spr_register(env, SPR_SPRG1, "SPRG1",
183 SPR_NOACCESS, SPR_NOACCESS,
184 &spr_read_generic, &spr_write_generic,
185 0x00000000);
186 spr_register(env, SPR_SPRG2, "SPRG2",
187 SPR_NOACCESS, SPR_NOACCESS,
188 &spr_read_generic, &spr_write_generic,
189 0x00000000);
190 spr_register(env, SPR_SPRG3, "SPRG3",
191 SPR_NOACCESS, SPR_NOACCESS,
192 &spr_read_generic, &spr_write_generic,
193 0x00000000);
194 }
195
196 /* SPR common to all non-embedded PowerPC, including 601 */
197 static void register_ne_601_sprs(CPUPPCState *env)
198 {
199 /* Exception processing */
200 spr_register_kvm(env, SPR_DSISR, "DSISR",
201 SPR_NOACCESS, SPR_NOACCESS,
202 &spr_read_generic, &spr_write_generic,
203 KVM_REG_PPC_DSISR, 0x00000000);
204 spr_register_kvm(env, SPR_DAR, "DAR",
205 SPR_NOACCESS, SPR_NOACCESS,
206 &spr_read_generic, &spr_write_generic,
207 KVM_REG_PPC_DAR, 0x00000000);
208 /* Timer */
209 spr_register(env, SPR_DECR, "DECR",
210 SPR_NOACCESS, SPR_NOACCESS,
211 &spr_read_decr, &spr_write_decr,
212 0x00000000);
213 }
214
215 /* Storage Description Register 1 */
216 static void register_sdr1_sprs(CPUPPCState *env)
217 {
218 #ifndef CONFIG_USER_ONLY
219 if (env->has_hv_mode) {
220 /*
221 * SDR1 is a hypervisor resource on CPUs which have a
222 * hypervisor mode
223 */
224 spr_register_hv(env, SPR_SDR1, "SDR1",
225 SPR_NOACCESS, SPR_NOACCESS,
226 SPR_NOACCESS, SPR_NOACCESS,
227 &spr_read_generic, &spr_write_sdr1,
228 0x00000000);
229 } else {
230 spr_register(env, SPR_SDR1, "SDR1",
231 SPR_NOACCESS, SPR_NOACCESS,
232 &spr_read_generic, &spr_write_sdr1,
233 0x00000000);
234 }
235 #endif
236 }
237
238 /* BATs 0-3 */
239 static void register_low_BATs(CPUPPCState *env)
240 {
241 #if !defined(CONFIG_USER_ONLY)
242 spr_register(env, SPR_IBAT0U, "IBAT0U",
243 SPR_NOACCESS, SPR_NOACCESS,
244 &spr_read_ibat, &spr_write_ibatu,
245 0x00000000);
246 spr_register(env, SPR_IBAT0L, "IBAT0L",
247 SPR_NOACCESS, SPR_NOACCESS,
248 &spr_read_ibat, &spr_write_ibatl,
249 0x00000000);
250 spr_register(env, SPR_IBAT1U, "IBAT1U",
251 SPR_NOACCESS, SPR_NOACCESS,
252 &spr_read_ibat, &spr_write_ibatu,
253 0x00000000);
254 spr_register(env, SPR_IBAT1L, "IBAT1L",
255 SPR_NOACCESS, SPR_NOACCESS,
256 &spr_read_ibat, &spr_write_ibatl,
257 0x00000000);
258 spr_register(env, SPR_IBAT2U, "IBAT2U",
259 SPR_NOACCESS, SPR_NOACCESS,
260 &spr_read_ibat, &spr_write_ibatu,
261 0x00000000);
262 spr_register(env, SPR_IBAT2L, "IBAT2L",
263 SPR_NOACCESS, SPR_NOACCESS,
264 &spr_read_ibat, &spr_write_ibatl,
265 0x00000000);
266 spr_register(env, SPR_IBAT3U, "IBAT3U",
267 SPR_NOACCESS, SPR_NOACCESS,
268 &spr_read_ibat, &spr_write_ibatu,
269 0x00000000);
270 spr_register(env, SPR_IBAT3L, "IBAT3L",
271 SPR_NOACCESS, SPR_NOACCESS,
272 &spr_read_ibat, &spr_write_ibatl,
273 0x00000000);
274 spr_register(env, SPR_DBAT0U, "DBAT0U",
275 SPR_NOACCESS, SPR_NOACCESS,
276 &spr_read_dbat, &spr_write_dbatu,
277 0x00000000);
278 spr_register(env, SPR_DBAT0L, "DBAT0L",
279 SPR_NOACCESS, SPR_NOACCESS,
280 &spr_read_dbat, &spr_write_dbatl,
281 0x00000000);
282 spr_register(env, SPR_DBAT1U, "DBAT1U",
283 SPR_NOACCESS, SPR_NOACCESS,
284 &spr_read_dbat, &spr_write_dbatu,
285 0x00000000);
286 spr_register(env, SPR_DBAT1L, "DBAT1L",
287 SPR_NOACCESS, SPR_NOACCESS,
288 &spr_read_dbat, &spr_write_dbatl,
289 0x00000000);
290 spr_register(env, SPR_DBAT2U, "DBAT2U",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_dbat, &spr_write_dbatu,
293 0x00000000);
294 spr_register(env, SPR_DBAT2L, "DBAT2L",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_dbat, &spr_write_dbatl,
297 0x00000000);
298 spr_register(env, SPR_DBAT3U, "DBAT3U",
299 SPR_NOACCESS, SPR_NOACCESS,
300 &spr_read_dbat, &spr_write_dbatu,
301 0x00000000);
302 spr_register(env, SPR_DBAT3L, "DBAT3L",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_dbat, &spr_write_dbatl,
305 0x00000000);
306 env->nb_BATs += 4;
307 #endif
308 }
309
310 /* BATs 4-7 */
311 static void register_high_BATs(CPUPPCState *env)
312 {
313 #if !defined(CONFIG_USER_ONLY)
314 spr_register(env, SPR_IBAT4U, "IBAT4U",
315 SPR_NOACCESS, SPR_NOACCESS,
316 &spr_read_ibat_h, &spr_write_ibatu_h,
317 0x00000000);
318 spr_register(env, SPR_IBAT4L, "IBAT4L",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_ibat_h, &spr_write_ibatl_h,
321 0x00000000);
322 spr_register(env, SPR_IBAT5U, "IBAT5U",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_ibat_h, &spr_write_ibatu_h,
325 0x00000000);
326 spr_register(env, SPR_IBAT5L, "IBAT5L",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_ibat_h, &spr_write_ibatl_h,
329 0x00000000);
330 spr_register(env, SPR_IBAT6U, "IBAT6U",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_ibat_h, &spr_write_ibatu_h,
333 0x00000000);
334 spr_register(env, SPR_IBAT6L, "IBAT6L",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_ibat_h, &spr_write_ibatl_h,
337 0x00000000);
338 spr_register(env, SPR_IBAT7U, "IBAT7U",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_ibat_h, &spr_write_ibatu_h,
341 0x00000000);
342 spr_register(env, SPR_IBAT7L, "IBAT7L",
343 SPR_NOACCESS, SPR_NOACCESS,
344 &spr_read_ibat_h, &spr_write_ibatl_h,
345 0x00000000);
346 spr_register(env, SPR_DBAT4U, "DBAT4U",
347 SPR_NOACCESS, SPR_NOACCESS,
348 &spr_read_dbat_h, &spr_write_dbatu_h,
349 0x00000000);
350 spr_register(env, SPR_DBAT4L, "DBAT4L",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_dbat_h, &spr_write_dbatl_h,
353 0x00000000);
354 spr_register(env, SPR_DBAT5U, "DBAT5U",
355 SPR_NOACCESS, SPR_NOACCESS,
356 &spr_read_dbat_h, &spr_write_dbatu_h,
357 0x00000000);
358 spr_register(env, SPR_DBAT5L, "DBAT5L",
359 SPR_NOACCESS, SPR_NOACCESS,
360 &spr_read_dbat_h, &spr_write_dbatl_h,
361 0x00000000);
362 spr_register(env, SPR_DBAT6U, "DBAT6U",
363 SPR_NOACCESS, SPR_NOACCESS,
364 &spr_read_dbat_h, &spr_write_dbatu_h,
365 0x00000000);
366 spr_register(env, SPR_DBAT6L, "DBAT6L",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_dbat_h, &spr_write_dbatl_h,
369 0x00000000);
370 spr_register(env, SPR_DBAT7U, "DBAT7U",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_dbat_h, &spr_write_dbatu_h,
373 0x00000000);
374 spr_register(env, SPR_DBAT7L, "DBAT7L",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_dbat_h, &spr_write_dbatl_h,
377 0x00000000);
378 env->nb_BATs += 4;
379 #endif
380 }
381
382 /* Generic PowerPC time base */
383 static void register_tbl(CPUPPCState *env)
384 {
385 spr_register(env, SPR_VTBL, "TBL",
386 &spr_read_tbl, SPR_NOACCESS,
387 &spr_read_tbl, SPR_NOACCESS,
388 0x00000000);
389 spr_register(env, SPR_TBL, "TBL",
390 &spr_read_tbl, SPR_NOACCESS,
391 &spr_read_tbl, &spr_write_tbl,
392 0x00000000);
393 spr_register(env, SPR_VTBU, "TBU",
394 &spr_read_tbu, SPR_NOACCESS,
395 &spr_read_tbu, SPR_NOACCESS,
396 0x00000000);
397 spr_register(env, SPR_TBU, "TBU",
398 &spr_read_tbu, SPR_NOACCESS,
399 &spr_read_tbu, &spr_write_tbu,
400 0x00000000);
401 }
402
403 /* Softare table search registers */
404 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
405 {
406 #if !defined(CONFIG_USER_ONLY)
407 env->nb_tlb = nb_tlbs;
408 env->nb_ways = nb_ways;
409 env->id_tlbs = 1;
410 env->tlb_type = TLB_6XX;
411 spr_register(env, SPR_DMISS, "DMISS",
412 SPR_NOACCESS, SPR_NOACCESS,
413 &spr_read_generic, SPR_NOACCESS,
414 0x00000000);
415 spr_register(env, SPR_DCMP, "DCMP",
416 SPR_NOACCESS, SPR_NOACCESS,
417 &spr_read_generic, SPR_NOACCESS,
418 0x00000000);
419 spr_register(env, SPR_HASH1, "HASH1",
420 SPR_NOACCESS, SPR_NOACCESS,
421 &spr_read_generic, SPR_NOACCESS,
422 0x00000000);
423 spr_register(env, SPR_HASH2, "HASH2",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, SPR_NOACCESS,
426 0x00000000);
427 spr_register(env, SPR_IMISS, "IMISS",
428 SPR_NOACCESS, SPR_NOACCESS,
429 &spr_read_generic, SPR_NOACCESS,
430 0x00000000);
431 spr_register(env, SPR_ICMP, "ICMP",
432 SPR_NOACCESS, SPR_NOACCESS,
433 &spr_read_generic, SPR_NOACCESS,
434 0x00000000);
435 spr_register(env, SPR_RPA, "RPA",
436 SPR_NOACCESS, SPR_NOACCESS,
437 &spr_read_generic, &spr_write_generic,
438 0x00000000);
439 #endif
440 }
441
442 /* SPR common to MPC755 and G2 */
443 static void register_G2_755_sprs(CPUPPCState *env)
444 {
445 /* SGPRs */
446 spr_register(env, SPR_SPRG4, "SPRG4",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, &spr_write_generic,
449 0x00000000);
450 spr_register(env, SPR_SPRG5, "SPRG5",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, &spr_write_generic,
453 0x00000000);
454 spr_register(env, SPR_SPRG6, "SPRG6",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, &spr_write_generic,
457 0x00000000);
458 spr_register(env, SPR_SPRG7, "SPRG7",
459 SPR_NOACCESS, SPR_NOACCESS,
460 &spr_read_generic, &spr_write_generic,
461 0x00000000);
462 }
463
464 /* SPR common to all 7xx PowerPC implementations */
465 static void register_7xx_sprs(CPUPPCState *env)
466 {
467 /* Breakpoints */
468 /* XXX : not implemented */
469 spr_register_kvm(env, SPR_DABR, "DABR",
470 SPR_NOACCESS, SPR_NOACCESS,
471 &spr_read_generic, &spr_write_generic,
472 KVM_REG_PPC_DABR, 0x00000000);
473 /* XXX : not implemented */
474 spr_register(env, SPR_IABR, "IABR",
475 SPR_NOACCESS, SPR_NOACCESS,
476 &spr_read_generic, &spr_write_generic,
477 0x00000000);
478 /* Cache management */
479 /* XXX : not implemented */
480 spr_register(env, SPR_ICTC, "ICTC",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 /* Performance monitors */
485 /* XXX : not implemented */
486 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 /* XXX : not implemented */
491 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_generic, &spr_write_generic,
494 0x00000000);
495 /* XXX : not implemented */
496 spr_register(env, SPR_7XX_PMC1, "PMC1",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 0x00000000);
500 /* XXX : not implemented */
501 spr_register(env, SPR_7XX_PMC2, "PMC2",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 0x00000000);
505 /* XXX : not implemented */
506 spr_register(env, SPR_7XX_PMC3, "PMC3",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510 /* XXX : not implemented */
511 spr_register(env, SPR_7XX_PMC4, "PMC4",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_generic, &spr_write_generic,
514 0x00000000);
515 /* XXX : not implemented */
516 spr_register(env, SPR_7XX_SIAR, "SIAR",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, SPR_NOACCESS,
519 0x00000000);
520 /* XXX : not implemented */
521 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
522 &spr_read_ureg, SPR_NOACCESS,
523 &spr_read_ureg, SPR_NOACCESS,
524 0x00000000);
525 /* XXX : not implemented */
526 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
527 &spr_read_ureg, SPR_NOACCESS,
528 &spr_read_ureg, SPR_NOACCESS,
529 0x00000000);
530 /* XXX : not implemented */
531 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
532 &spr_read_ureg, SPR_NOACCESS,
533 &spr_read_ureg, SPR_NOACCESS,
534 0x00000000);
535 /* XXX : not implemented */
536 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
537 &spr_read_ureg, SPR_NOACCESS,
538 &spr_read_ureg, SPR_NOACCESS,
539 0x00000000);
540 /* XXX : not implemented */
541 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
542 &spr_read_ureg, SPR_NOACCESS,
543 &spr_read_ureg, SPR_NOACCESS,
544 0x00000000);
545 /* XXX : not implemented */
546 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
547 &spr_read_ureg, SPR_NOACCESS,
548 &spr_read_ureg, SPR_NOACCESS,
549 0x00000000);
550 /* XXX : not implemented */
551 spr_register(env, SPR_7XX_USIAR, "USIAR",
552 &spr_read_ureg, SPR_NOACCESS,
553 &spr_read_ureg, SPR_NOACCESS,
554 0x00000000);
555 /* External access control */
556 /* XXX : not implemented */
557 spr_register(env, SPR_EAR, "EAR",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_generic, &spr_write_generic,
560 0x00000000);
561 }
562
563 #ifdef TARGET_PPC64
564 static void register_amr_sprs(CPUPPCState *env)
565 {
566 #ifndef CONFIG_USER_ONLY
567 /*
568 * Virtual Page Class Key protection
569 *
570 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
571 * userspace accessible, 29 is privileged. So we only need to set
572 * the kvm ONE_REG id on one of them, we use 29
573 */
574 spr_register(env, SPR_UAMR, "UAMR",
575 &spr_read_generic, &spr_write_amr,
576 &spr_read_generic, &spr_write_amr,
577 0);
578 spr_register_kvm_hv(env, SPR_AMR, "AMR",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_generic, &spr_write_amr,
581 &spr_read_generic, &spr_write_generic,
582 KVM_REG_PPC_AMR, 0);
583 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_generic, &spr_write_uamor,
586 &spr_read_generic, &spr_write_generic,
587 KVM_REG_PPC_UAMOR, 0);
588 spr_register_hv(env, SPR_AMOR, "AMOR",
589 SPR_NOACCESS, SPR_NOACCESS,
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_generic, &spr_write_generic,
592 0);
593 #endif /* !CONFIG_USER_ONLY */
594 }
595
596 static void register_iamr_sprs(CPUPPCState *env)
597 {
598 #ifndef CONFIG_USER_ONLY
599 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
600 SPR_NOACCESS, SPR_NOACCESS,
601 &spr_read_generic, &spr_write_iamr,
602 &spr_read_generic, &spr_write_generic,
603 KVM_REG_PPC_IAMR, 0);
604 #endif /* !CONFIG_USER_ONLY */
605 }
606 #endif /* TARGET_PPC64 */
607
608 static void register_thrm_sprs(CPUPPCState *env)
609 {
610 /* Thermal management */
611 /* XXX : not implemented */
612 spr_register(env, SPR_THRM1, "THRM1",
613 SPR_NOACCESS, SPR_NOACCESS,
614 &spr_read_thrm, &spr_write_generic,
615 0x00000000);
616 /* XXX : not implemented */
617 spr_register(env, SPR_THRM2, "THRM2",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_thrm, &spr_write_generic,
620 0x00000000);
621 /* XXX : not implemented */
622 spr_register(env, SPR_THRM3, "THRM3",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_thrm, &spr_write_generic,
625 0x00000000);
626 }
627
628 /* SPR specific to PowerPC 604 implementation */
629 static void register_604_sprs(CPUPPCState *env)
630 {
631 /* Processor identification */
632 spr_register(env, SPR_PIR, "PIR",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_generic, &spr_write_pir,
635 0x00000000);
636 /* Breakpoints */
637 /* XXX : not implemented */
638 spr_register(env, SPR_IABR, "IABR",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_generic, &spr_write_generic,
641 0x00000000);
642 /* XXX : not implemented */
643 spr_register_kvm(env, SPR_DABR, "DABR",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_generic, &spr_write_generic,
646 KVM_REG_PPC_DABR, 0x00000000);
647 /* Performance counters */
648 /* XXX : not implemented */
649 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_generic, &spr_write_generic,
652 0x00000000);
653 /* XXX : not implemented */
654 spr_register(env, SPR_7XX_PMC1, "PMC1",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_generic, &spr_write_generic,
657 0x00000000);
658 /* XXX : not implemented */
659 spr_register(env, SPR_7XX_PMC2, "PMC2",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* XXX : not implemented */
664 spr_register(env, SPR_7XX_SIAR, "SIAR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, SPR_NOACCESS,
667 0x00000000);
668 /* XXX : not implemented */
669 spr_register(env, SPR_SDA, "SDA",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, SPR_NOACCESS,
672 0x00000000);
673 /* External access control */
674 /* XXX : not implemented */
675 spr_register(env, SPR_EAR, "EAR",
676 SPR_NOACCESS, SPR_NOACCESS,
677 &spr_read_generic, &spr_write_generic,
678 0x00000000);
679 }
680
681 /* SPR specific to PowerPC 603 implementation */
682 static void register_603_sprs(CPUPPCState *env)
683 {
684 /* External access control */
685 /* XXX : not implemented */
686 spr_register(env, SPR_EAR, "EAR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 0x00000000);
690 /* Breakpoints */
691 /* XXX : not implemented */
692 spr_register(env, SPR_IABR, "IABR",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_generic, &spr_write_generic,
695 0x00000000);
696
697 }
698
699 /* SPR specific to PowerPC G2 implementation */
700 static void register_G2_sprs(CPUPPCState *env)
701 {
702 /* Memory base address */
703 /* MBAR */
704 /* XXX : not implemented */
705 spr_register(env, SPR_MBAR, "MBAR",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709 /* Exception processing */
710 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, &spr_write_generic,
713 0x00000000);
714 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718 /* Breakpoints */
719 /* XXX : not implemented */
720 spr_register(env, SPR_DABR, "DABR",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724 /* XXX : not implemented */
725 spr_register(env, SPR_DABR2, "DABR2",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729 /* XXX : not implemented */
730 spr_register(env, SPR_IABR, "IABR",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_generic,
733 0x00000000);
734 /* XXX : not implemented */
735 spr_register(env, SPR_IABR2, "IABR2",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_generic, &spr_write_generic,
738 0x00000000);
739 /* XXX : not implemented */
740 spr_register(env, SPR_IBCR, "IBCR",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 /* XXX : not implemented */
745 spr_register(env, SPR_DBCR, "DBCR",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_generic, &spr_write_generic,
748 0x00000000);
749 }
750
751 /* SPR specific to PowerPC 602 implementation */
752 static void register_602_sprs(CPUPPCState *env)
753 {
754 /* ESA registers */
755 /* XXX : not implemented */
756 spr_register(env, SPR_SER, "SER",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_generic, &spr_write_generic,
759 0x00000000);
760 /* XXX : not implemented */
761 spr_register(env, SPR_SEBR, "SEBR",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_generic,
764 0x00000000);
765 /* XXX : not implemented */
766 spr_register(env, SPR_ESASRR, "ESASRR",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_generic, &spr_write_generic,
769 0x00000000);
770 /* Floating point status */
771 /* XXX : not implemented */
772 spr_register(env, SPR_SP, "SP",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_generic, &spr_write_generic,
775 0x00000000);
776 /* XXX : not implemented */
777 spr_register(env, SPR_LT, "LT",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_generic, &spr_write_generic,
780 0x00000000);
781 /* Watchdog timer */
782 /* XXX : not implemented */
783 spr_register(env, SPR_TCR, "TCR",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, &spr_write_generic,
786 0x00000000);
787 /* Interrupt base */
788 spr_register(env, SPR_IBR, "IBR",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_generic, &spr_write_generic,
791 0x00000000);
792 /* XXX : not implemented */
793 spr_register(env, SPR_IABR, "IABR",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_generic, &spr_write_generic,
796 0x00000000);
797 }
798
799 /* SPR specific to PowerPC 601 implementation */
800 static void register_601_sprs(CPUPPCState *env)
801 {
802 /* Multiplication/division register */
803 /* MQ */
804 spr_register(env, SPR_MQ, "MQ",
805 &spr_read_generic, &spr_write_generic,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 /* RTC registers */
809 spr_register(env, SPR_601_RTCU, "RTCU",
810 SPR_NOACCESS, SPR_NOACCESS,
811 SPR_NOACCESS, &spr_write_601_rtcu,
812 0x00000000);
813 spr_register(env, SPR_601_VRTCU, "RTCU",
814 &spr_read_601_rtcu, SPR_NOACCESS,
815 &spr_read_601_rtcu, SPR_NOACCESS,
816 0x00000000);
817 spr_register(env, SPR_601_RTCL, "RTCL",
818 SPR_NOACCESS, SPR_NOACCESS,
819 SPR_NOACCESS, &spr_write_601_rtcl,
820 0x00000000);
821 spr_register(env, SPR_601_VRTCL, "RTCL",
822 &spr_read_601_rtcl, SPR_NOACCESS,
823 &spr_read_601_rtcl, SPR_NOACCESS,
824 0x00000000);
825 /* Timer */
826 #if 0 /* ? */
827 spr_register(env, SPR_601_UDECR, "UDECR",
828 &spr_read_decr, SPR_NOACCESS,
829 &spr_read_decr, SPR_NOACCESS,
830 0x00000000);
831 #endif
832 /* External access control */
833 /* XXX : not implemented */
834 spr_register(env, SPR_EAR, "EAR",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, &spr_write_generic,
837 0x00000000);
838 /* Memory management */
839 #if !defined(CONFIG_USER_ONLY)
840 spr_register(env, SPR_IBAT0U, "IBAT0U",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_601_ubat, &spr_write_601_ubatu,
843 0x00000000);
844 spr_register(env, SPR_IBAT0L, "IBAT0L",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_601_ubat, &spr_write_601_ubatl,
847 0x00000000);
848 spr_register(env, SPR_IBAT1U, "IBAT1U",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_601_ubat, &spr_write_601_ubatu,
851 0x00000000);
852 spr_register(env, SPR_IBAT1L, "IBAT1L",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_601_ubat, &spr_write_601_ubatl,
855 0x00000000);
856 spr_register(env, SPR_IBAT2U, "IBAT2U",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_601_ubat, &spr_write_601_ubatu,
859 0x00000000);
860 spr_register(env, SPR_IBAT2L, "IBAT2L",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_601_ubat, &spr_write_601_ubatl,
863 0x00000000);
864 spr_register(env, SPR_IBAT3U, "IBAT3U",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_601_ubat, &spr_write_601_ubatu,
867 0x00000000);
868 spr_register(env, SPR_IBAT3L, "IBAT3L",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_601_ubat, &spr_write_601_ubatl,
871 0x00000000);
872 env->nb_BATs = 4;
873 #endif
874 }
875
876 static void register_74xx_sprs(CPUPPCState *env)
877 {
878 /* Processor identification */
879 spr_register(env, SPR_PIR, "PIR",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, &spr_write_pir,
882 0x00000000);
883 /* XXX : not implemented */
884 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_generic,
887 0x00000000);
888 /* XXX : not implemented */
889 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
890 &spr_read_ureg, SPR_NOACCESS,
891 &spr_read_ureg, SPR_NOACCESS,
892 0x00000000);
893 /* XXX: not implemented */
894 spr_register(env, SPR_BAMR, "BAMR",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 /* XXX : not implemented */
899 spr_register(env, SPR_MSSCR0, "MSSCR0",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, &spr_write_generic,
902 0x00000000);
903 /* Hardware implementation registers */
904 /* XXX : not implemented */
905 spr_register(env, SPR_HID0, "HID0",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 /* XXX : not implemented */
910 spr_register(env, SPR_HID1, "HID1",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* Altivec */
915 spr_register(env, SPR_VRSAVE, "VRSAVE",
916 &spr_read_generic, &spr_write_generic,
917 &spr_read_generic, &spr_write_generic,
918 0x00000000);
919 /* XXX : not implemented */
920 spr_register(env, SPR_L2CR, "L2CR",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, spr_access_nop,
923 0x00000000);
924 }
925
926 static void register_l3_ctrl(CPUPPCState *env)
927 {
928 /* L3CR */
929 /* XXX : not implemented */
930 spr_register(env, SPR_L3CR, "L3CR",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* L3ITCR0 */
935 /* XXX : not implemented */
936 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940 /* L3PM */
941 /* XXX : not implemented */
942 spr_register(env, SPR_L3PM, "L3PM",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 }
947
948 static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
949 {
950 #if !defined(CONFIG_USER_ONLY)
951 env->nb_tlb = nb_tlbs;
952 env->nb_ways = nb_ways;
953 env->id_tlbs = 1;
954 env->tlb_type = TLB_6XX;
955 /* XXX : not implemented */
956 spr_register(env, SPR_PTEHI, "PTEHI",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960 /* XXX : not implemented */
961 spr_register(env, SPR_PTELO, "PTELO",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 /* XXX : not implemented */
966 spr_register(env, SPR_TLBMISS, "TLBMISS",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970 #endif
971 }
972
973 static void register_usprg3_sprs(CPUPPCState *env)
974 {
975 spr_register(env, SPR_USPRG3, "USPRG3",
976 &spr_read_ureg, SPR_NOACCESS,
977 &spr_read_ureg, SPR_NOACCESS,
978 0x00000000);
979 }
980
981 static void register_usprgh_sprs(CPUPPCState *env)
982 {
983 spr_register(env, SPR_USPRG4, "USPRG4",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 spr_register(env, SPR_USPRG5, "USPRG5",
988 &spr_read_ureg, SPR_NOACCESS,
989 &spr_read_ureg, SPR_NOACCESS,
990 0x00000000);
991 spr_register(env, SPR_USPRG6, "USPRG6",
992 &spr_read_ureg, SPR_NOACCESS,
993 &spr_read_ureg, SPR_NOACCESS,
994 0x00000000);
995 spr_register(env, SPR_USPRG7, "USPRG7",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999 }
1000
1001 /* PowerPC BookE SPR */
1002 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
1003 {
1004 const char *ivor_names[64] = {
1005 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1006 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1007 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1008 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1009 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1010 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1011 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1012 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1013 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1014 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1015 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1016 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1017 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1018 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1019 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1020 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1021 };
1022 #define SPR_BOOKE_IVORxx (-1)
1023 int ivor_sprn[64] = {
1024 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1025 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1026 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1027 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1028 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1029 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1030 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1031 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1032 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1033 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1034 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1035 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1036 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1037 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1038 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1039 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1040 };
1041 int i;
1042
1043 /* Interrupt processing */
1044 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1049 SPR_NOACCESS, SPR_NOACCESS,
1050 &spr_read_generic, &spr_write_generic,
1051 0x00000000);
1052 /* Debug */
1053 /* XXX : not implemented */
1054 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1055 SPR_NOACCESS, SPR_NOACCESS,
1056 &spr_read_generic, &spr_write_generic,
1057 0x00000000);
1058 /* XXX : not implemented */
1059 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063 /* XXX : not implemented */
1064 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_40x_dbcr0,
1077 0x00000000);
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 /* XXX : not implemented */
1084 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
1096 /* XXX : not implemented */
1097 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_clear,
1100 0x00000000);
1101 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1102 SPR_NOACCESS, SPR_NOACCESS,
1103 &spr_read_generic, &spr_write_generic,
1104 0x00000000);
1105 spr_register(env, SPR_BOOKE_ESR, "ESR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_excp_prefix,
1112 0x00000000);
1113 /* Exception vectors */
1114 for (i = 0; i < 64; i++) {
1115 if (ivor_mask & (1ULL << i)) {
1116 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1117 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1118 exit(1);
1119 }
1120 spr_register(env, ivor_sprn[i], ivor_names[i],
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_excp_vector,
1123 0x00000000);
1124 }
1125 }
1126 spr_register(env, SPR_BOOKE_PID, "PID",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_booke_pid,
1129 0x00000000);
1130 spr_register(env, SPR_BOOKE_TCR, "TCR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_booke_tcr,
1133 0x00000000);
1134 spr_register(env, SPR_BOOKE_TSR, "TSR",
1135 SPR_NOACCESS, SPR_NOACCESS,
1136 &spr_read_generic, &spr_write_booke_tsr,
1137 0x00000000);
1138 /* Timer */
1139 spr_register(env, SPR_DECR, "DECR",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_decr, &spr_write_decr,
1142 0x00000000);
1143 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 SPR_NOACCESS, &spr_write_generic,
1146 0x00000000);
1147 /* SPRGs */
1148 spr_register(env, SPR_USPRG0, "USPRG0",
1149 &spr_read_generic, &spr_write_generic,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 spr_register(env, SPR_SPRG4, "SPRG4",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 spr_register(env, SPR_SPRG5, "SPRG5",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 spr_register(env, SPR_SPRG6, "SPRG6",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164 spr_register(env, SPR_SPRG7, "SPRG7",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00000000);
1168 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 }
1177
1178 #if !defined(CONFIG_USER_ONLY)
1179 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1180 uint32_t maxsize, uint32_t flags,
1181 uint32_t nentries)
1182 {
1183 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1184 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1185 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1186 flags | nentries;
1187 }
1188 #endif /* !CONFIG_USER_ONLY */
1189
1190 /* BookE 2.06 storage control registers */
1191 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1192 uint32_t *tlbncfg, uint32_t mmucfg)
1193 {
1194 #if !defined(CONFIG_USER_ONLY)
1195 const char *mas_names[8] = {
1196 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1197 };
1198 int mas_sprn[8] = {
1199 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1200 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1201 };
1202 int i;
1203
1204 /* TLB assist registers */
1205 /* XXX : not implemented */
1206 for (i = 0; i < 8; i++) {
1207 if (mas_mask & (1 << i)) {
1208 spr_register(env, mas_sprn[i], mas_names[i],
1209 SPR_NOACCESS, SPR_NOACCESS,
1210 &spr_read_generic,
1211 (i == 2 && (env->insns_flags & PPC_64B))
1212 ? &spr_write_generic : &spr_write_generic32,
1213 0x00000000);
1214 }
1215 }
1216 if (env->nb_pids > 1) {
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_BOOKE_PID1, "PID1",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_booke_pid,
1221 0x00000000);
1222 }
1223 if (env->nb_pids > 2) {
1224 /* XXX : not implemented */
1225 spr_register(env, SPR_BOOKE_PID2, "PID2",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_generic, &spr_write_booke_pid,
1228 0x00000000);
1229 }
1230
1231 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, &spr_write_eplc,
1234 0x00000000);
1235 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_epsc,
1238 0x00000000);
1239
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_MMUCFG, "MMUCFG",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, SPR_NOACCESS,
1244 mmucfg);
1245 switch (env->nb_ways) {
1246 case 4:
1247 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, SPR_NOACCESS,
1250 tlbncfg[3]);
1251 /* Fallthru */
1252 case 3:
1253 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_generic, SPR_NOACCESS,
1256 tlbncfg[2]);
1257 /* Fallthru */
1258 case 2:
1259 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, SPR_NOACCESS,
1262 tlbncfg[1]);
1263 /* Fallthru */
1264 case 1:
1265 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, SPR_NOACCESS,
1268 tlbncfg[0]);
1269 /* Fallthru */
1270 case 0:
1271 default:
1272 break;
1273 }
1274 #endif
1275
1276 register_usprgh_sprs(env);
1277 }
1278
1279 /* SPR specific to PowerPC 440 implementation */
1280 static void register_440_sprs(CPUPPCState *env)
1281 {
1282 /* Cache control */
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_440_DNV0, "DNV0",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_440_DNV1, "DNV1",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_440_DNV2, "DNV2",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_440_DNV3, "DNV3",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_440_DTV0, "DTV0",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* XXX : not implemented */
1309 spr_register(env, SPR_440_DTV1, "DTV1",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_440_DTV2, "DTV2",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_440_DTV3, "DTV3",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_440_DVLIM, "DVLIM",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_440_INV0, "INV0",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 /* XXX : not implemented */
1334 spr_register(env, SPR_440_INV1, "INV1",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_440_INV2, "INV2",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_440_INV3, "INV3",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* XXX : not implemented */
1349 spr_register(env, SPR_440_ITV0, "ITV0",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_440_ITV1, "ITV1",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 /* XXX : not implemented */
1359 spr_register(env, SPR_440_ITV2, "ITV2",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 /* XXX : not implemented */
1364 spr_register(env, SPR_440_ITV3, "ITV3",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 /* XXX : not implemented */
1369 spr_register(env, SPR_440_IVLIM, "IVLIM",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373 /* Cache debug */
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, SPR_NOACCESS,
1378 0x00000000);
1379 /* XXX : not implemented */
1380 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, SPR_NOACCESS,
1383 0x00000000);
1384 /* XXX : not implemented */
1385 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, SPR_NOACCESS,
1388 0x00000000);
1389 /* XXX : not implemented */
1390 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1391 SPR_NOACCESS, SPR_NOACCESS,
1392 &spr_read_generic, SPR_NOACCESS,
1393 0x00000000);
1394 /* XXX : not implemented */
1395 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1396 SPR_NOACCESS, SPR_NOACCESS,
1397 &spr_read_generic, SPR_NOACCESS,
1398 0x00000000);
1399 /* XXX : not implemented */
1400 spr_register(env, SPR_440_DBDR, "DBDR",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_generic,
1403 0x00000000);
1404 /* Processor control */
1405 spr_register(env, SPR_4xx_CCR0, "CCR0",
1406 SPR_NOACCESS, SPR_NOACCESS,
1407 &spr_read_generic, &spr_write_generic,
1408 0x00000000);
1409 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, SPR_NOACCESS,
1412 0x00000000);
1413 /* Storage control */
1414 spr_register(env, SPR_440_MMUCR, "MMUCR",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418 }
1419
1420 /* SPR shared between PowerPC 40x implementations */
1421 static void register_40x_sprs(CPUPPCState *env)
1422 {
1423 /* Cache */
1424 /* not emulated, as QEMU do not emulate caches */
1425 spr_register(env, SPR_40x_DCCR, "DCCR",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_generic,
1428 0x00000000);
1429 /* not emulated, as QEMU do not emulate caches */
1430 spr_register(env, SPR_40x_ICCR, "ICCR",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_generic, &spr_write_generic,
1433 0x00000000);
1434 /* not emulated, as QEMU do not emulate caches */
1435 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_generic, SPR_NOACCESS,
1438 0x00000000);
1439 /* Exception */
1440 spr_register(env, SPR_40x_DEAR, "DEAR",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444 spr_register(env, SPR_40x_ESR, "ESR",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448 spr_register(env, SPR_40x_EVPR, "EVPR",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_excp_prefix,
1451 0x00000000);
1452 spr_register(env, SPR_40x_SRR2, "SRR2",
1453 &spr_read_generic, &spr_write_generic,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456 spr_register(env, SPR_40x_SRR3, "SRR3",
1457 &spr_read_generic, &spr_write_generic,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460 /* Timers */
1461 spr_register(env, SPR_40x_PIT, "PIT",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_40x_pit, &spr_write_40x_pit,
1464 0x00000000);
1465 spr_register(env, SPR_40x_TCR, "TCR",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_generic, &spr_write_booke_tcr,
1468 0x00000000);
1469 spr_register(env, SPR_40x_TSR, "TSR",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_booke_tsr,
1472 0x00000000);
1473 }
1474
1475 /* SPR specific to PowerPC 405 implementation */
1476 static void register_405_sprs(CPUPPCState *env)
1477 {
1478 /* MMU */
1479 spr_register(env, SPR_40x_PID, "PID",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 spr_register(env, SPR_4xx_CCR0, "CCR0",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00700000);
1487 /* Debug interface */
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_40x_dbcr0,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_405_DBCR1, "DBCR1",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* XXX : not implemented */
1499 spr_register(env, SPR_40x_DBSR, "DBSR",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_clear,
1502 /* Last reset was system reset */
1503 0x00000300);
1504 /* XXX : not implemented */
1505 spr_register(env, SPR_40x_DAC1, "DAC1",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 spr_register(env, SPR_40x_DAC2, "DAC2",
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, &spr_write_generic,
1512 0x00000000);
1513 /* XXX : not implemented */
1514 spr_register(env, SPR_405_DVC1, "DVC1",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518 /* XXX : not implemented */
1519 spr_register(env, SPR_405_DVC2, "DVC2",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523 /* XXX : not implemented */
1524 spr_register(env, SPR_40x_IAC1, "IAC1",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
1528 spr_register(env, SPR_40x_IAC2, "IAC2",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* XXX : not implemented */
1533 spr_register(env, SPR_405_IAC3, "IAC3",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537 /* XXX : not implemented */
1538 spr_register(env, SPR_405_IAC4, "IAC4",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* Storage control */
1543 /* XXX: TODO: not implemented */
1544 spr_register(env, SPR_405_SLER, "SLER",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_40x_sler,
1547 0x00000000);
1548 spr_register(env, SPR_40x_ZPR, "ZPR",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_405_SU0R, "SU0R",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* SPRG */
1558 spr_register(env, SPR_USPRG0, "USPRG0",
1559 &spr_read_ureg, SPR_NOACCESS,
1560 &spr_read_ureg, SPR_NOACCESS,
1561 0x00000000);
1562 spr_register(env, SPR_SPRG4, "SPRG4",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, &spr_write_generic,
1565 0x00000000);
1566 spr_register(env, SPR_SPRG5, "SPRG5",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 spr_register(env, SPR_SPRG6, "SPRG6",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 spr_register(env, SPR_SPRG7, "SPRG7",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 register_usprgh_sprs(env);
1579 }
1580
1581 /* SPR shared between PowerPC 401 & 403 implementations */
1582 static void register_401_403_sprs(CPUPPCState *env)
1583 {
1584 /* Time base */
1585 spr_register(env, SPR_403_VTBL, "TBL",
1586 &spr_read_tbl, SPR_NOACCESS,
1587 &spr_read_tbl, SPR_NOACCESS,
1588 0x00000000);
1589 spr_register(env, SPR_403_TBL, "TBL",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 SPR_NOACCESS, &spr_write_tbl,
1592 0x00000000);
1593 spr_register(env, SPR_403_VTBU, "TBU",
1594 &spr_read_tbu, SPR_NOACCESS,
1595 &spr_read_tbu, SPR_NOACCESS,
1596 0x00000000);
1597 spr_register(env, SPR_403_TBU, "TBU",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 SPR_NOACCESS, &spr_write_tbu,
1600 0x00000000);
1601 /* Debug */
1602 /* not emulated, as QEMU do not emulate caches */
1603 spr_register(env, SPR_403_CDBCR, "CDBCR",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00000000);
1607 }
1608
1609 /* SPR specific to PowerPC 401 implementation */
1610 static void register_401_sprs(CPUPPCState *env)
1611 {
1612 /* Debug interface */
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_40x_DBCR0, "DBCR",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_40x_dbcr0,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_40x_DBSR, "DBSR",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_clear,
1622 /* Last reset was system reset */
1623 0x00000300);
1624 /* XXX : not implemented */
1625 spr_register(env, SPR_40x_DAC1, "DAC",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_generic,
1628 0x00000000);
1629 /* XXX : not implemented */
1630 spr_register(env, SPR_40x_IAC1, "IAC",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 /* Storage control */
1635 /* XXX: TODO: not implemented */
1636 spr_register(env, SPR_405_SLER, "SLER",
1637 SPR_NOACCESS, SPR_NOACCESS,
1638 &spr_read_generic, &spr_write_40x_sler,
1639 0x00000000);
1640 /* not emulated, as QEMU never does speculative access */
1641 spr_register(env, SPR_40x_SGR, "SGR",
1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, &spr_write_generic,
1644 0xFFFFFFFF);
1645 /* not emulated, as QEMU do not emulate caches */
1646 spr_register(env, SPR_40x_DCWR, "DCWR",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650 }
1651
1652 static void register_401x2_sprs(CPUPPCState *env)
1653 {
1654 register_401_sprs(env);
1655 spr_register(env, SPR_40x_PID, "PID",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 spr_register(env, SPR_40x_ZPR, "ZPR",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 }
1664
1665 /* SPR specific to PowerPC 403 implementation */
1666 static void register_403_sprs(CPUPPCState *env)
1667 {
1668 /* Debug interface */
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_40x_dbcr0,
1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_40x_DBSR, "DBSR",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, &spr_write_clear,
1678 /* Last reset was system reset */
1679 0x00000300);
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_40x_DAC1, "DAC1",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 /* XXX : not implemented */
1686 spr_register(env, SPR_40x_DAC2, "DAC2",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
1690 /* XXX : not implemented */
1691 spr_register(env, SPR_40x_IAC1, "IAC1",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_40x_IAC2, "IAC2",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 }
1701
1702 static void register_403_real_sprs(CPUPPCState *env)
1703 {
1704 spr_register(env, SPR_403_PBL1, "PBL1",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_403_pbr, &spr_write_403_pbr,
1707 0x00000000);
1708 spr_register(env, SPR_403_PBU1, "PBU1",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_403_pbr, &spr_write_403_pbr,
1711 0x00000000);
1712 spr_register(env, SPR_403_PBL2, "PBL2",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_403_pbr, &spr_write_403_pbr,
1715 0x00000000);
1716 spr_register(env, SPR_403_PBU2, "PBU2",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_403_pbr, &spr_write_403_pbr,
1719 0x00000000);
1720 }
1721
1722 static void register_403_mmu_sprs(CPUPPCState *env)
1723 {
1724 /* MMU */
1725 spr_register(env, SPR_40x_PID, "PID",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, &spr_write_generic,
1728 0x00000000);
1729 spr_register(env, SPR_40x_ZPR, "ZPR",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 }
1734
1735 /* SPR specific to PowerPC compression coprocessor extension */
1736 static void register_compress_sprs(CPUPPCState *env)
1737 {
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_401_SKR, "SKR",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 }
1744
1745 static void register_5xx_8xx_sprs(CPUPPCState *env)
1746 {
1747 /* Exception processing */
1748 spr_register_kvm(env, SPR_DSISR, "DSISR",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 KVM_REG_PPC_DSISR, 0x00000000);
1752 spr_register_kvm(env, SPR_DAR, "DAR",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, &spr_write_generic,
1755 KVM_REG_PPC_DAR, 0x00000000);
1756 /* Timer */
1757 spr_register(env, SPR_DECR, "DECR",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_decr, &spr_write_decr,
1760 0x00000000);
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_MPC_EIE, "EIE",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, &spr_write_generic,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_MPC_EID, "EID",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_MPC_NRI, "NRI",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_MPC_CMPA, "CMPA",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 /* XXX : not implemented */
1782 spr_register(env, SPR_MPC_CMPB, "CMPB",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_MPC_CMPC, "CMPC",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* XXX : not implemented */
1792 spr_register(env, SPR_MPC_CMPD, "CMPD",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 /* XXX : not implemented */
1797 spr_register(env, SPR_MPC_ECR, "ECR",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_MPC_DER, "DER",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* XXX : not implemented */
1807 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* XXX : not implemented */
1817 spr_register(env, SPR_MPC_CMPE, "CMPE",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* XXX : not implemented */
1822 spr_register(env, SPR_MPC_CMPF, "CMPF",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 /* XXX : not implemented */
1827 spr_register(env, SPR_MPC_CMPG, "CMPG",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 /* XXX : not implemented */
1832 spr_register(env, SPR_MPC_CMPH, "CMPH",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_generic,
1835 0x00000000);
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 /* XXX : not implemented */
1847 spr_register(env, SPR_MPC_BAR, "BAR",
1848 SPR_NOACCESS, SPR_NOACCESS,
1849 &spr_read_generic, &spr_write_generic,
1850 0x00000000);
1851 /* XXX : not implemented */
1852 spr_register(env, SPR_MPC_DPDR, "DPDR",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 /* XXX : not implemented */
1857 spr_register(env, SPR_MPC_IMMR, "IMMR",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00000000);
1861 }
1862
1863 static void register_5xx_sprs(CPUPPCState *env)
1864 {
1865 /* XXX : not implemented */
1866 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 /* XXX : not implemented */
1871 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 /* XXX : not implemented */
1891 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* XXX : not implemented */
1896 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* XXX : not implemented */
1901 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905 /* XXX : not implemented */
1906 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910 /* XXX : not implemented */
1911 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915 /* XXX : not implemented */
1916 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1917 SPR_NOACCESS, SPR_NOACCESS,
1918 &spr_read_generic, &spr_write_generic,
1919 0x00000000);
1920 /* XXX : not implemented */
1921 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 /* XXX : not implemented */
1926 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_generic,
1929 0x00000000);
1930 /* XXX : not implemented */
1931 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_generic,
1934 0x00000000);
1935 /* XXX : not implemented */
1936 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1937 SPR_NOACCESS, SPR_NOACCESS,
1938 &spr_read_generic, &spr_write_generic,
1939 0x00000000);
1940 /* XXX : not implemented */
1941 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 &spr_read_generic, &spr_write_generic,
1944 0x00000000);
1945 /* XXX : not implemented */
1946 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1947 SPR_NOACCESS, SPR_NOACCESS,
1948 &spr_read_generic, &spr_write_generic,
1949 0x00000000);
1950 /* XXX : not implemented */
1951 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1952 SPR_NOACCESS, SPR_NOACCESS,
1953 &spr_read_generic, &spr_write_generic,
1954 0x00000000);
1955 /* XXX : not implemented */
1956 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1957 SPR_NOACCESS, SPR_NOACCESS,
1958 &spr_read_generic, &spr_write_generic,
1959 0x00000000);
1960 /* XXX : not implemented */
1961 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 &spr_read_generic, &spr_write_generic,
1964 0x00000000);
1965 /* XXX : not implemented */
1966 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 &spr_read_generic, &spr_write_generic,
1969 0x00000000);
1970 }
1971
1972 static void register_8xx_sprs(CPUPPCState *env)
1973 {
1974 /* XXX : not implemented */
1975 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 /* XXX : not implemented */
1980 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, &spr_write_generic,
1983 0x00000000);
1984 /* XXX : not implemented */
1985 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989 /* XXX : not implemented */
1990 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994 /* XXX : not implemented */
1995 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999 /* XXX : not implemented */
2000 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* XXX : not implemented */
2010 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014 /* XXX : not implemented */
2015 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0x00000000);
2019 /* XXX : not implemented */
2020 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024 /* XXX : not implemented */
2025 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029 /* XXX : not implemented */
2030 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 /* XXX : not implemented */
2035 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039 /* XXX : not implemented */
2040 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0x00000000);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 /* XXX : not implemented */
2060 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 /* XXX : not implemented */
2065 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2066 SPR_NOACCESS, SPR_NOACCESS,
2067 &spr_read_generic, &spr_write_generic,
2068 0x00000000);
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
2074 /* XXX : not implemented */
2075 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_generic,
2078 0x00000000);
2079 /* XXX : not implemented */
2080 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 /* XXX : not implemented */
2085 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089 /* XXX : not implemented */
2090 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
2094 /* XXX : not implemented */
2095 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
2099 }
2100
2101 /*
2102 * AMR => SPR 29 (Power 2.04)
2103 * CTRL => SPR 136 (Power 2.04)
2104 * CTRL => SPR 152 (Power 2.04)
2105 * SCOMC => SPR 276 (64 bits ?)
2106 * SCOMD => SPR 277 (64 bits ?)
2107 * TBU40 => SPR 286 (Power 2.04 hypv)
2108 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2109 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2110 * HDSISR => SPR 306 (Power 2.04 hypv)
2111 * HDAR => SPR 307 (Power 2.04 hypv)
2112 * PURR => SPR 309 (Power 2.04 hypv)
2113 * HDEC => SPR 310 (Power 2.04 hypv)
2114 * HIOR => SPR 311 (hypv)
2115 * RMOR => SPR 312 (970)
2116 * HRMOR => SPR 313 (Power 2.04 hypv)
2117 * HSRR0 => SPR 314 (Power 2.04 hypv)
2118 * HSRR1 => SPR 315 (Power 2.04 hypv)
2119 * LPIDR => SPR 317 (970)
2120 * EPR => SPR 702 (Power 2.04 emb)
2121 * perf => 768-783 (Power 2.04)
2122 * perf => 784-799 (Power 2.04)
2123 * PPR => SPR 896 (Power 2.04)
2124 * DABRX => 1015 (Power 2.04 hypv)
2125 * FPECR => SPR 1022 (?)
2126 * ... and more (thermal management, performance counters, ...)
2127 */
2128
2129 /*****************************************************************************/
2130 /* Exception vectors models */
2131 static void init_excp_4xx_real(CPUPPCState *env)
2132 {
2133 #if !defined(CONFIG_USER_ONLY)
2134 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2135 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2136 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2137 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2138 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2139 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2140 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2141 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2142 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2143 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2144 env->ivor_mask = 0x0000FFF0UL;
2145 env->ivpr_mask = 0xFFFF0000UL;
2146 /* Hardware reset vector */
2147 env->hreset_vector = 0xFFFFFFFCUL;
2148 #endif
2149 }
2150
2151 static void init_excp_4xx_softmmu(CPUPPCState *env)
2152 {
2153 #if !defined(CONFIG_USER_ONLY)
2154 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2155 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2156 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2157 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2158 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2159 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2160 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2161 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2162 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2163 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2164 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2165 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2166 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2167 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2168 env->ivor_mask = 0x0000FFF0UL;
2169 env->ivpr_mask = 0xFFFF0000UL;
2170 /* Hardware reset vector */
2171 env->hreset_vector = 0xFFFFFFFCUL;
2172 #endif
2173 }
2174
2175 static void init_excp_MPC5xx(CPUPPCState *env)
2176 {
2177 #if !defined(CONFIG_USER_ONLY)
2178 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2179 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2180 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2181 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2182 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2183 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2184 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2185 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2186 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2187 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2188 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2189 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2190 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2191 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2192 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2193 env->ivor_mask = 0x0000FFF0UL;
2194 env->ivpr_mask = 0xFFFF0000UL;
2195 /* Hardware reset vector */
2196 env->hreset_vector = 0x00000100UL;
2197 #endif
2198 }
2199
2200 static void init_excp_MPC8xx(CPUPPCState *env)
2201 {
2202 #if !defined(CONFIG_USER_ONLY)
2203 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2204 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2205 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2206 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2207 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2208 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2209 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2210 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2211 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2212 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2213 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2214 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2215 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2216 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2217 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2218 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2219 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2220 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2221 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2222 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2223 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2224 env->ivor_mask = 0x0000FFF0UL;
2225 env->ivpr_mask = 0xFFFF0000UL;
2226 /* Hardware reset vector */
2227 env->hreset_vector = 0x00000100UL;
2228 #endif
2229 }
2230
2231 static void init_excp_G2(CPUPPCState *env)
2232 {
2233 #if !defined(CONFIG_USER_ONLY)
2234 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2235 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2236 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2237 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2238 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2239 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2240 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2241 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2242 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2243 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2244 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2245 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2246 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2247 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2248 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2249 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2250 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2251 /* Hardware reset vector */
2252 env->hreset_vector = 0x00000100UL;
2253 #endif
2254 }
2255
2256 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2257 {
2258 #if !defined(CONFIG_USER_ONLY)
2259 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2260 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2261 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2262 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2263 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2264 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2265 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2266 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2267 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2268 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2269 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2270 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2271 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2272 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2273 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2274 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2275 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2276 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2277 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2278 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2279 env->ivor_mask = 0x0000FFF7UL;
2280 env->ivpr_mask = ivpr_mask;
2281 /* Hardware reset vector */
2282 env->hreset_vector = 0xFFFFFFFCUL;
2283 #endif
2284 }
2285
2286 static void init_excp_BookE(CPUPPCState *env)
2287 {
2288 #if !defined(CONFIG_USER_ONLY)
2289 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2290 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2291 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2292 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2293 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2300 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2301 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2302 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2303 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2304 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2305 env->ivor_mask = 0x0000FFF0UL;
2306 env->ivpr_mask = 0xFFFF0000UL;
2307 /* Hardware reset vector */
2308 env->hreset_vector = 0xFFFFFFFCUL;
2309 #endif
2310 }
2311
2312 static void init_excp_601(CPUPPCState *env)
2313 {
2314 #if !defined(CONFIG_USER_ONLY)
2315 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2316 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2317 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2318 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2319 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2320 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2321 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2322 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2323 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2324 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2325 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2326 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2327 /* Hardware reset vector */
2328 env->hreset_vector = 0x00000100UL;
2329 #endif
2330 }
2331
2332 static void init_excp_602(CPUPPCState *env)
2333 {
2334 #if !defined(CONFIG_USER_ONLY)
2335 /* XXX: exception prefix has a special behavior on 602 */
2336 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2337 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2338 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2339 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2340 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2341 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2342 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2343 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2344 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2345 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2346 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2347 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2348 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2349 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2350 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2351 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2352 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2353 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2354 /* Hardware reset vector */
2355 env->hreset_vector = 0x00000100UL;
2356 #endif
2357 }
2358
2359 static void init_excp_603(CPUPPCState *env)
2360 {
2361 #if !defined(CONFIG_USER_ONLY)
2362 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2363 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2364 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2365 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2366 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2367 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2368 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2369 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2370 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2371 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2372 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2373 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2374 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2375 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2376 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2377 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2378 /* Hardware reset vector */
2379 env->hreset_vector = 0x00000100UL;
2380 #endif
2381 }
2382
2383 static void init_excp_604(CPUPPCState *env)
2384 {
2385 #if !defined(CONFIG_USER_ONLY)
2386 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2387 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2388 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2389 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2390 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2391 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2392 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2393 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2394 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2395 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2396 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2397 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2398 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2399 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2400 /* Hardware reset vector */
2401 env->hreset_vector = 0x00000100UL;
2402 #endif
2403 }
2404
2405 static void init_excp_7x0(CPUPPCState *env)
2406 {
2407 #if !defined(CONFIG_USER_ONLY)
2408 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2409 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2410 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2411 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2412 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2413 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2414 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2415 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2416 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2417 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2418 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2419 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2420 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2421 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2422 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2423 /* Hardware reset vector */
2424 env->hreset_vector = 0x00000100UL;
2425 #endif
2426 }
2427
2428 static void init_excp_750cl(CPUPPCState *env)
2429 {
2430 #if !defined(CONFIG_USER_ONLY)
2431 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2432 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2433 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2434 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2435 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2436 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2437 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2438 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2439 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2440 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2441 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2442 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2443 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2444 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2445 /* Hardware reset vector */
2446 env->hreset_vector = 0x00000100UL;
2447 #endif
2448 }
2449
2450 static void init_excp_750cx(CPUPPCState *env)
2451 {
2452 #if !defined(CONFIG_USER_ONLY)
2453 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2454 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2455 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2456 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2457 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2458 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2459 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2460 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2461 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2462 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2463 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2464 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2465 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2466 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2467 /* Hardware reset vector */
2468 env->hreset_vector = 0x00000100UL;
2469 #endif
2470 }
2471
2472 /* XXX: Check if this is correct */
2473 static void init_excp_7x5(CPUPPCState *env)
2474 {
2475 #if !defined(CONFIG_USER_ONLY)
2476 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2477 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2478 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2479 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2480 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2481 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2482 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2483 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2484 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2485 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2486 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2487 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2488 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2489 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2490 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2491 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2492 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2493 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2494 /* Hardware reset vector */
2495 env->hreset_vector = 0x00000100UL;
2496 #endif
2497 }
2498
2499 static void init_excp_7400(CPUPPCState *env)
2500 {
2501 #if !defined(CONFIG_USER_ONLY)
2502 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2503 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2504 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2505 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2506 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2507 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2508 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2509 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2510 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2511 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2512 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2513 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2514 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2515 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2516 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2517 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2518 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2519 /* Hardware reset vector */
2520 env->hreset_vector = 0x00000100UL;
2521 #endif
2522 }
2523
2524 static void init_excp_7450(CPUPPCState *env)
2525 {
2526 #if !defined(CONFIG_USER_ONLY)
2527 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2528 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2529 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2530 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2531 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2532 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2533 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2534 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2535 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2536 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2537 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2538 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2539 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2540 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2541 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2542 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2543 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2544 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2545 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2546 /* Hardware reset vector */
2547 env->hreset_vector = 0x00000100UL;
2548 #endif
2549 }
2550
2551 #if defined(TARGET_PPC64)
2552 static void init_excp_970(CPUPPCState *env)
2553 {
2554 #if !defined(CONFIG_USER_ONLY)
2555 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2556 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2557 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2558 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2559 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2560 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2561 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2562 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2563 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2564 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2565 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2566 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2567 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2568 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2569 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2570 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2571 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2572 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2573 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2574 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2575 /* Hardware reset vector */
2576 env->hreset_vector = 0x0000000000000100ULL;
2577 #endif
2578 }
2579
2580 static void init_excp_POWER7(CPUPPCState *env)
2581 {
2582 #if !defined(CONFIG_USER_ONLY)
2583 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2584 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2585 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2586 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2587 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2588 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2589 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2590 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2591 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2592 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2593 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2594 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2595 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2596 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2597 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2598 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2599 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2600 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2601 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2602 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2603 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2604 /* Hardware reset vector */
2605 env->hreset_vector = 0x0000000000000100ULL;
2606 #endif
2607 }
2608
2609 static void init_excp_POWER8(CPUPPCState *env)
2610 {
2611 init_excp_POWER7(env);
2612
2613 #if !defined(CONFIG_USER_ONLY)
2614 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2615 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2616 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2617 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2618 #endif
2619 }
2620
2621 static void init_excp_POWER9(CPUPPCState *env)
2622 {
2623 init_excp_POWER8(env);
2624
2625 #if !defined(CONFIG_USER_ONLY)
2626 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2627 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2628 #endif
2629 }
2630
2631 static void init_excp_POWER10(CPUPPCState *env)
2632 {
2633 init_excp_POWER9(env);
2634 }
2635
2636 #endif
2637
2638 /*****************************************************************************/
2639 /* Power management enable checks */
2640 static int check_pow_none(CPUPPCState *env)
2641 {
2642 return 0;
2643 }
2644
2645 static int check_pow_nocheck(CPUPPCState *env)
2646 {
2647 return 1;
2648 }
2649
2650 static int check_pow_hid0(CPUPPCState *env)
2651 {
2652 if (env->spr[SPR_HID0] & 0x00E00000) {
2653 return 1;
2654 }
2655
2656 return 0;
2657 }
2658
2659 static int check_pow_hid0_74xx(CPUPPCState *env)
2660 {
2661 if (env->spr[SPR_HID0] & 0x00600000) {
2662 return 1;
2663 }
2664
2665 return 0;
2666 }
2667
2668 /*****************************************************************************/
2669 /* PowerPC implementations definitions */
2670
2671 #define POWERPC_FAMILY(_name) \
2672 static void \
2673 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2674 \
2675 static const TypeInfo \
2676 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2677 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2678 .parent = TYPE_POWERPC_CPU, \
2679 .abstract = true, \
2680 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2681 }; \
2682 \
2683 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2684 { \
2685 type_register_static( \
2686 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2687 } \
2688 \
2689 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2690 \
2691 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2692
2693 static void init_proc_401(CPUPPCState *env)
2694 {
2695 register_40x_sprs(env);
2696 register_401_403_sprs(env);
2697 register_401_sprs(env);
2698 init_excp_4xx_real(env);
2699 env->dcache_line_size = 32;
2700 env->icache_line_size = 32;
2701 /* Allocate hardware IRQ controller */
2702 ppc40x_irq_init(env_archcpu(env));
2703
2704 SET_FIT_PERIOD(12, 16, 20, 24);
2705 SET_WDT_PERIOD(16, 20, 24, 28);
2706 }
2707
2708 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
2709 {
2710 DeviceClass *dc = DEVICE_CLASS(oc);
2711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2712
2713 dc->desc = "PowerPC 401";
2714 pcc->init_proc = init_proc_401;
2715 pcc->check_pow = check_pow_nocheck;
2716 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2717 PPC_WRTEE | PPC_DCR |
2718 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2719 PPC_CACHE_DCBZ |
2720 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2721 PPC_4xx_COMMON | PPC_40x_EXCP;
2722 pcc->msr_mask = (1ull << MSR_KEY) |
2723 (1ull << MSR_POW) |
2724 (1ull << MSR_CE) |
2725 (1ull << MSR_ILE) |
2726 (1ull << MSR_EE) |
2727 (1ull << MSR_PR) |
2728 (1ull << MSR_ME) |
2729 (1ull << MSR_DE) |
2730 (1ull << MSR_LE);
2731 pcc->mmu_model = POWERPC_MMU_REAL;
2732 pcc->excp_model = POWERPC_EXCP_40x;
2733 pcc->bus_model = PPC_FLAGS_INPUT_401;
2734 pcc->bfd_mach = bfd_mach_ppc_403;
2735 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2736 POWERPC_FLAG_BUS_CLK;
2737 }
2738
2739 static void init_proc_401x2(CPUPPCState *env)
2740 {
2741 register_40x_sprs(env);
2742 register_401_403_sprs(env);
2743 register_401x2_sprs(env);
2744 register_compress_sprs(env);
2745 /* Memory management */
2746 #if !defined(CONFIG_USER_ONLY)
2747 env->nb_tlb = 64;
2748 env->nb_ways = 1;
2749 env->id_tlbs = 0;
2750 env->tlb_type = TLB_EMB;
2751 #endif
2752 init_excp_4xx_softmmu(env);
2753 env->dcache_line_size = 32;
2754 env->icache_line_size = 32;
2755 /* Allocate hardware IRQ controller */
2756 ppc40x_irq_init(env_archcpu(env));
2757
2758 SET_FIT_PERIOD(12, 16, 20, 24);
2759 SET_WDT_PERIOD(16, 20, 24, 28);
2760 }
2761
2762 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
2763 {
2764 DeviceClass *dc = DEVICE_CLASS(oc);
2765 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2766
2767 dc->desc = "PowerPC 401x2";
2768 pcc->init_proc = init_proc_401x2;
2769 pcc->check_pow = check_pow_nocheck;
2770 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2771 PPC_DCR | PPC_WRTEE |
2772 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2773 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2774 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2775 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2776 PPC_4xx_COMMON | PPC_40x_EXCP;
2777 pcc->msr_mask = (1ull << 20) |
2778 (1ull << MSR_KEY) |
2779 (1ull << MSR_POW) |
2780 (1ull << MSR_CE) |
2781 (1ull << MSR_ILE) |
2782 (1ull << MSR_EE) |
2783 (1ull << MSR_PR) |
2784 (1ull << MSR_ME) |
2785 (1ull << MSR_DE) |
2786 (1ull << MSR_IR) |
2787 (1ull << MSR_DR) |
2788 (1ull << MSR_LE);
2789 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2790 pcc->excp_model = POWERPC_EXCP_40x;
2791 pcc->bus_model = PPC_FLAGS_INPUT_401;
2792 pcc->bfd_mach = bfd_mach_ppc_403;
2793 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2794 POWERPC_FLAG_BUS_CLK;
2795 }
2796
2797 static void init_proc_401x3(CPUPPCState *env)
2798 {
2799 register_40x_sprs(env);
2800 register_401_403_sprs(env);
2801 register_401_sprs(env);
2802 register_401x2_sprs(env);
2803 register_compress_sprs(env);
2804 init_excp_4xx_softmmu(env);
2805 env->dcache_line_size = 32;
2806 env->icache_line_size = 32;
2807 /* Allocate hardware IRQ controller */
2808 ppc40x_irq_init(env_archcpu(env));
2809
2810 SET_FIT_PERIOD(12, 16, 20, 24);
2811 SET_WDT_PERIOD(16, 20, 24, 28);
2812 }
2813
2814 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
2815 {
2816 DeviceClass *dc = DEVICE_CLASS(oc);
2817 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2818
2819 dc->desc = "PowerPC 401x3";
2820 pcc->init_proc = init_proc_401x3;
2821 pcc->check_pow = check_pow_nocheck;
2822 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2823 PPC_DCR | PPC_WRTEE |
2824 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2825 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2826 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2827 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2828 PPC_4xx_COMMON | PPC_40x_EXCP;
2829 pcc->msr_mask = (1ull << 20) |
2830 (1ull << MSR_KEY) |
2831 (1ull << MSR_POW) |
2832 (1ull << MSR_CE) |
2833 (1ull << MSR_ILE) |
2834 (1ull << MSR_EE) |
2835 (1ull << MSR_PR) |
2836 (1ull << MSR_ME) |
2837 (1ull << MSR_DWE) |
2838 (1ull << MSR_DE) |
2839 (1ull << MSR_IR) |
2840 (1ull << MSR_DR) |
2841 (1ull << MSR_LE);
2842 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2843 pcc->excp_model = POWERPC_EXCP_40x;
2844 pcc->bus_model = PPC_FLAGS_INPUT_401;
2845 pcc->bfd_mach = bfd_mach_ppc_403;
2846 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2847 POWERPC_FLAG_BUS_CLK;
2848 }
2849
2850 static void init_proc_IOP480(CPUPPCState *env)
2851 {
2852 register_40x_sprs(env);
2853 register_401_403_sprs(env);
2854 register_401x2_sprs(env);
2855 register_compress_sprs(env);
2856 /* Memory management */
2857 #if !defined(CONFIG_USER_ONLY)
2858 env->nb_tlb = 64;
2859 env->nb_ways = 1;
2860 env->id_tlbs = 0;
2861 env->tlb_type = TLB_EMB;
2862 #endif
2863 init_excp_4xx_softmmu(env);
2864 env->dcache_line_size = 32;
2865 env->icache_line_size = 32;
2866 /* Allocate hardware IRQ controller */
2867 ppc40x_irq_init(env_archcpu(env));
2868
2869 SET_FIT_PERIOD(8, 12, 16, 20);
2870 SET_WDT_PERIOD(16, 20, 24, 28);
2871 }
2872
2873 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
2874 {
2875 DeviceClass *dc = DEVICE_CLASS(oc);
2876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2877
2878 dc->desc = "IOP480";
2879 pcc->init_proc = init_proc_IOP480;
2880 pcc->check_pow = check_pow_nocheck;
2881 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2882 PPC_DCR | PPC_WRTEE |
2883 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2884 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2885 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2886 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2887 PPC_4xx_COMMON | PPC_40x_EXCP;
2888 pcc->msr_mask = (1ull << 20) |
2889 (1ull << MSR_KEY) |
2890 (1ull << MSR_POW) |
2891 (1ull << MSR_CE) |
2892 (1ull << MSR_ILE) |
2893 (1ull << MSR_EE) |
2894 (1ull << MSR_PR) |
2895 (1ull << MSR_ME) |
2896 (1ull << MSR_DE) |
2897 (1ull << MSR_IR) |
2898 (1ull << MSR_DR) |
2899 (1ull << MSR_LE);
2900 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2901 pcc->excp_model = POWERPC_EXCP_40x;
2902 pcc->bus_model = PPC_FLAGS_INPUT_401;
2903 pcc->bfd_mach = bfd_mach_ppc_403;
2904 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2905 POWERPC_FLAG_BUS_CLK;
2906 }
2907
2908 static void init_proc_403(CPUPPCState *env)
2909 {
2910 register_40x_sprs(env);
2911 register_401_403_sprs(env);
2912 register_403_sprs(env);
2913 register_403_real_sprs(env);
2914 init_excp_4xx_real(env);
2915 env->dcache_line_size = 32;
2916 env->icache_line_size = 32;
2917 /* Allocate hardware IRQ controller */
2918 ppc40x_irq_init(env_archcpu(env));
2919
2920 SET_FIT_PERIOD(8, 12, 16, 20);
2921 SET_WDT_PERIOD(16, 20, 24, 28);
2922 }
2923
2924 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
2925 {
2926 DeviceClass *dc = DEVICE_CLASS(oc);
2927 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2928
2929 dc->desc = "PowerPC 403";
2930 pcc->init_proc = init_proc_403;
2931 pcc->check_pow = check_pow_nocheck;
2932 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2933 PPC_DCR | PPC_WRTEE |
2934 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2935 PPC_CACHE_DCBZ |
2936 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2937 PPC_4xx_COMMON | PPC_40x_EXCP;
2938 pcc->msr_mask = (1ull << MSR_POW) |
2939 (1ull << MSR_CE) |
2940 (1ull << MSR_ILE) |
2941 (1ull << MSR_EE) |
2942 (1ull << MSR_PR) |
2943 (1ull << MSR_ME) |
2944 (1ull << MSR_PE) |
2945 (1ull << MSR_PX) |
2946 (1ull << MSR_LE);
2947 pcc->mmu_model = POWERPC_MMU_REAL;
2948 pcc->excp_model = POWERPC_EXCP_40x;
2949 pcc->bus_model = PPC_FLAGS_INPUT_401;
2950 pcc->bfd_mach = bfd_mach_ppc_403;
2951 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
2952 POWERPC_FLAG_BUS_CLK;
2953 }
2954
2955 static void init_proc_403GCX(CPUPPCState *env)
2956 {
2957 register_40x_sprs(env);
2958 register_401_403_sprs(env);
2959 register_403_sprs(env);
2960 register_403_real_sprs(env);
2961 register_403_mmu_sprs(env);
2962 /* Bus access control */
2963 /* not emulated, as QEMU never does speculative access */
2964 spr_register(env, SPR_40x_SGR, "SGR",
2965 SPR_NOACCESS, SPR_NOACCESS,
2966 &spr_read_generic, &spr_write_generic,
2967 0xFFFFFFFF);
2968 /* not emulated, as QEMU do not emulate caches */
2969 spr_register(env, SPR_40x_DCWR, "DCWR",
2970 SPR_NOACCESS, SPR_NOACCESS,
2971 &spr_read_generic, &spr_write_generic,
2972 0x00000000);
2973 /* Memory management */
2974 #if !defined(CONFIG_USER_ONLY)
2975 env->nb_tlb = 64;
2976 env->nb_ways = 1;
2977 env->id_tlbs = 0;
2978 env->tlb_type = TLB_EMB;
2979 #endif
2980 init_excp_4xx_softmmu(env);
2981 env->dcache_line_size = 32;
2982 env->icache_line_size = 32;
2983 /* Allocate hardware IRQ controller */
2984 ppc40x_irq_init(env_archcpu(env));
2985
2986 SET_FIT_PERIOD(8, 12, 16, 20);
2987 SET_WDT_PERIOD(16, 20, 24, 28);
2988 }
2989
2990 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
2991 {
2992 DeviceClass *dc = DEVICE_CLASS(oc);
2993 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2994
2995 dc->desc = "PowerPC 403 GCX";
2996 pcc->init_proc = init_proc_403GCX;
2997 pcc->check_pow = check_pow_nocheck;
2998 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2999 PPC_DCR | PPC_WRTEE |
3000 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3001 PPC_CACHE_DCBZ |
3002 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3003 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3004 PPC_4xx_COMMON | PPC_40x_EXCP;
3005 pcc->msr_mask = (1ull << MSR_POW) |
3006 (1ull << MSR_CE) |
3007 (1ull << MSR_ILE) |
3008 (1ull << MSR_EE) |
3009 (1ull << MSR_PR) |
3010 (1ull << MSR_ME) |
3011 (1ull << MSR_PE) |
3012 (1ull << MSR_PX) |
3013 (1ull << MSR_LE);
3014 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3015 pcc->excp_model = POWERPC_EXCP_40x;
3016 pcc->bus_model = PPC_FLAGS_INPUT_401;
3017 pcc->bfd_mach = bfd_mach_ppc_403;
3018 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3019 POWERPC_FLAG_BUS_CLK;
3020 }
3021
3022 static void init_proc_405(CPUPPCState *env)
3023 {
3024 /* Time base */
3025 register_tbl(env);
3026 register_40x_sprs(env);
3027 register_405_sprs(env);
3028 /* Bus access control */
3029 /* not emulated, as QEMU never does speculative access */
3030 spr_register(env, SPR_40x_SGR, "SGR",
3031 SPR_NOACCESS, SPR_NOACCESS,
3032 &spr_read_generic, &spr_write_generic,
3033 0xFFFFFFFF);
3034 /* not emulated, as QEMU do not emulate caches */
3035 spr_register(env, SPR_40x_DCWR, "DCWR",
3036 SPR_NOACCESS, SPR_NOACCESS,
3037 &spr_read_generic, &spr_write_generic,
3038 0x00000000);
3039 /* Memory management */
3040 #if !defined(CONFIG_USER_ONLY)
3041 env->nb_tlb = 64;
3042 env->nb_ways = 1;
3043 env->id_tlbs = 0;
3044 env->tlb_type = TLB_EMB;
3045 #endif
3046 init_excp_4xx_softmmu(env);
3047 env->dcache_line_size = 32;
3048 env->icache_line_size = 32;
3049 /* Allocate hardware IRQ controller */
3050 ppc40x_irq_init(env_archcpu(env));
3051
3052 SET_FIT_PERIOD(8, 12, 16, 20);
3053 SET_WDT_PERIOD(16, 20, 24, 28);
3054 }
3055
3056 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3057 {
3058 DeviceClass *dc = DEVICE_CLASS(oc);
3059 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3060
3061 dc->desc = "PowerPC 405";
3062 pcc->init_proc = init_proc_405;
3063 pcc->check_pow = check_pow_nocheck;
3064 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3065 PPC_DCR | PPC_WRTEE |
3066 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3067 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3068 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3069 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3070 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3071 pcc->msr_mask = (1ull << MSR_POW) |
3072 (1ull << MSR_CE) |
3073 (1ull << MSR_EE) |
3074 (1ull << MSR_PR) |
3075 (1ull << MSR_FP) |
3076 (1ull << MSR_DWE) |
3077 (1ull << MSR_DE) |
3078 (1ull << MSR_IR) |
3079 (1ull << MSR_DR);
3080 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3081 pcc->excp_model = POWERPC_EXCP_40x;
3082 pcc->bus_model = PPC_FLAGS_INPUT_405;
3083 pcc->bfd_mach = bfd_mach_ppc_403;
3084 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3085 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3086 }
3087
3088 static void init_proc_440EP(CPUPPCState *env)
3089 {
3090 /* Time base */
3091 register_tbl(env);
3092 register_BookE_sprs(env, 0x000000000000FFFFULL);
3093 register_440_sprs(env);
3094 register_usprgh_sprs(env);
3095 /* Processor identification */
3096 spr_register(env, SPR_BOOKE_PIR, "PIR",
3097 SPR_NOACCESS, SPR_NOACCESS,
3098 &spr_read_generic, &spr_write_pir,
3099 0x00000000);
3100 /* XXX : not implemented */
3101 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3102 SPR_NOACCESS, SPR_NOACCESS,
3103 &spr_read_generic, &spr_write_generic,
3104 0x00000000);
3105 /* XXX : not implemented */
3106 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3107 SPR_NOACCESS, SPR_NOACCESS,
3108 &spr_read_generic, &spr_write_generic,
3109 0x00000000);
3110 /* XXX : not implemented */
3111 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3112 SPR_NOACCESS, SPR_NOACCESS,
3113 &spr_read_generic, &spr_write_generic,
3114 0x00000000);
3115 /* XXX : not implemented */
3116 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3117 SPR_NOACCESS, SPR_NOACCESS,
3118 &spr_read_generic, &spr_write_generic,
3119 0x00000000);
3120 /* XXX : not implemented */
3121 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3122 SPR_NOACCESS, SPR_NOACCESS,
3123 &spr_read_generic, &spr_write_generic,
3124 0x00000000);
3125 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3126 SPR_NOACCESS, SPR_NOACCESS,
3127 &spr_read_generic, &spr_write_generic,
3128 0x00000000);
3129 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3130 SPR_NOACCESS, SPR_NOACCESS,
3131 &spr_read_generic, &spr_write_generic,
3132 0x00000000);
3133 /* XXX : not implemented */
3134 spr_register(env, SPR_440_CCR1, "CCR1",
3135 SPR_NOACCESS, SPR_NOACCESS,
3136 &spr_read_generic, &spr_write_generic,
3137 0x00000000);
3138 /* Memory management */
3139 #if !defined(CONFIG_USER_ONLY)
3140 env->nb_tlb = 64;
3141 env->nb_ways = 1;
3142 env->id_tlbs = 0;
3143 env->tlb_type = TLB_EMB;
3144 #endif
3145 init_excp_BookE(env);
3146 env->dcache_line_size = 32;
3147 env->icache_line_size = 32;
3148 ppc40x_irq_init(env_archcpu(env));
3149
3150 SET_FIT_PERIOD(12, 16, 20, 24);
3151 SET_WDT_PERIOD(20, 24, 28, 32);
3152 }
3153
3154 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3155 {
3156 DeviceClass *dc = DEVICE_CLASS(oc);
3157 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3158
3159 dc->desc = "PowerPC 440 EP";
3160 pcc->init_proc = init_proc_440EP;
3161 pcc->check_pow = check_pow_nocheck;
3162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3163 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3164 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3165 PPC_FLOAT_STFIWX |
3166 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3167 PPC_CACHE | PPC_CACHE_ICBI |
3168 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3169 PPC_MEM_TLBSYNC | PPC_MFTB |
3170 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3171 PPC_440_SPEC;
3172 pcc->msr_mask = (1ull << MSR_POW) |
3173 (1ull << MSR_CE) |
3174 (1ull << MSR_EE) |
3175 (1ull << MSR_PR) |
3176 (1ull << MSR_FP) |
3177 (1ull << MSR_ME) |
3178 (1ull << MSR_FE0) |
3179 (1ull << MSR_DWE) |
3180 (1ull << MSR_DE) |
3181 (1ull << MSR_FE1) |
3182 (1ull << MSR_IR) |
3183 (1ull << MSR_DR);
3184 pcc->mmu_model = POWERPC_MMU_BOOKE;
3185 pcc->excp_model = POWERPC_EXCP_BOOKE;
3186 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3187 pcc->bfd_mach = bfd_mach_ppc_403;
3188 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3189 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3190 }
3191
3192 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3193 {
3194 DeviceClass *dc = DEVICE_CLASS(oc);
3195 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3196
3197 dc->desc = "PowerPC 460 EX";
3198 pcc->init_proc = init_proc_440EP;
3199 pcc->check_pow = check_pow_nocheck;
3200 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3201 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3202 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3203 PPC_FLOAT_STFIWX |
3204 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3205 PPC_CACHE | PPC_CACHE_ICBI |
3206 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3207 PPC_MEM_TLBSYNC | PPC_MFTB |
3208 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3209 PPC_440_SPEC;
3210 pcc->msr_mask = (1ull << MSR_POW) |
3211 (1ull << MSR_CE) |
3212 (1ull << MSR_EE) |
3213 (1ull << MSR_PR) |
3214 (1ull << MSR_FP) |
3215 (1ull << MSR_ME) |
3216 (1ull << MSR_FE0) |
3217 (1ull << MSR_DWE) |
3218 (1ull << MSR_DE) |
3219 (1ull << MSR_FE1) |
3220 (1ull << MSR_IR) |
3221 (1ull << MSR_DR);
3222 pcc->mmu_model = POWERPC_MMU_BOOKE;
3223 pcc->excp_model = POWERPC_EXCP_BOOKE;
3224 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3225 pcc->bfd_mach = bfd_mach_ppc_403;
3226 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3227 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3228 }
3229
3230 static void init_proc_440GP(CPUPPCState *env)
3231 {
3232 /* Time base */
3233 register_tbl(env);
3234 register_BookE_sprs(env, 0x000000000000FFFFULL);
3235 register_440_sprs(env);
3236 register_usprgh_sprs(env);
3237 /* Processor identification */
3238 spr_register(env, SPR_BOOKE_PIR, "PIR",
3239 SPR_NOACCESS, SPR_NOACCESS,
3240 &spr_read_generic, &spr_write_pir,
3241 0x00000000);
3242 /* XXX : not implemented */
3243 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3244 SPR_NOACCESS, SPR_NOACCESS,
3245 &spr_read_generic, &spr_write_generic,
3246 0x00000000);
3247 /* XXX : not implemented */
3248 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3249 SPR_NOACCESS, SPR_NOACCESS,
3250 &spr_read_generic, &spr_write_generic,
3251 0x00000000);
3252 /* XXX : not implemented */
3253 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3254 SPR_NOACCESS, SPR_NOACCESS,
3255 &spr_read_generic, &spr_write_generic,
3256 0x00000000);
3257 /* XXX : not implemented */
3258 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3259 SPR_NOACCESS, SPR_NOACCESS,
3260 &spr_read_generic, &spr_write_generic,
3261 0x00000000);
3262 /* Memory management */
3263 #if !defined(CONFIG_USER_ONLY)
3264 env->nb_tlb = 64;
3265 env->nb_ways = 1;
3266 env->id_tlbs = 0;
3267 env->tlb_type = TLB_EMB;
3268 #endif
3269 init_excp_BookE(env);
3270 env->dcache_line_size = 32;
3271 env->icache_line_size = 32;
3272 /* XXX: TODO: allocate internal IRQ controller */
3273
3274 SET_FIT_PERIOD(12, 16, 20, 24);
3275 SET_WDT_PERIOD(20, 24, 28, 32);
3276 }
3277
3278 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3279 {
3280 DeviceClass *dc = DEVICE_CLASS(oc);
3281 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3282
3283 dc->desc = "PowerPC 440 GP";
3284 pcc->init_proc = init_proc_440GP;
3285 pcc->check_pow = check_pow_nocheck;
3286 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3287 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3288 PPC_CACHE | PPC_CACHE_ICBI |
3289 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3290 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3291 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3292 PPC_440_SPEC;
3293 pcc->msr_mask = (1ull << MSR_POW) |
3294 (1ull << MSR_CE) |
3295 (1ull << MSR_EE) |
3296 (1ull << MSR_PR) |
3297 (1ull << MSR_FP) |
3298 (1ull << MSR_ME) |
3299 (1ull << MSR_FE0) |
3300 (1ull << MSR_DWE) |
3301 (1ull << MSR_DE) |
3302 (1ull << MSR_FE1) |
3303 (1ull << MSR_IR) |
3304 (1ull << MSR_DR);
3305 pcc->mmu_model = POWERPC_MMU_BOOKE;
3306 pcc->excp_model = POWERPC_EXCP_BOOKE;
3307 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3308 pcc->bfd_mach = bfd_mach_ppc_403;
3309 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3310 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3311 }
3312
3313 static void init_proc_440x4(CPUPPCState *env)
3314 {
3315 /* Time base */
3316 register_tbl(env);
3317 register_BookE_sprs(env, 0x000000000000FFFFULL);
3318 register_440_sprs(env);
3319 register_usprgh_sprs(env);
3320 /* Processor identification */
3321 spr_register(env, SPR_BOOKE_PIR, "PIR",
3322 SPR_NOACCESS, SPR_NOACCESS,
3323 &spr_read_generic, &spr_write_pir,
3324 0x00000000);
3325 /* XXX : not implemented */
3326 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3327 SPR_NOACCESS, SPR_NOACCESS,
3328 &spr_read_generic, &spr_write_generic,
3329 0x00000000);
3330 /* XXX : not implemented */
3331 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3332 SPR_NOACCESS, SPR_NOACCESS,
3333 &spr_read_generic, &spr_write_generic,
3334 0x00000000);
3335 /* XXX : not implemented */
3336 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3337 SPR_NOACCESS, SPR_NOACCESS,
3338 &spr_read_generic, &spr_write_generic,
3339 0x00000000);
3340 /* XXX : not implemented */
3341 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3342 SPR_NOACCESS, SPR_NOACCESS,
3343 &spr_read_generic, &spr_write_generic,
3344 0x00000000);
3345 /* Memory management */
3346 #if !defined(CONFIG_USER_ONLY)
3347 env->nb_tlb = 64;
3348 env->nb_ways = 1;
3349 env->id_tlbs = 0;
3350 env->tlb_type = TLB_EMB;
3351 #endif
3352 init_excp_BookE(env);
3353 env->dcache_line_size = 32;
3354 env->icache_line_size = 32;
3355 /* XXX: TODO: allocate internal IRQ controller */
3356
3357 SET_FIT_PERIOD(12, 16, 20, 24);
3358 SET_WDT_PERIOD(20, 24, 28, 32);
3359 }
3360
3361 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3362 {
3363 DeviceClass *dc = DEVICE_CLASS(oc);
3364 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3365
3366 dc->desc = "PowerPC 440x4";
3367 pcc->init_proc = init_proc_440x4;
3368 pcc->check_pow = check_pow_nocheck;
3369 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3370 PPC_DCR | PPC_WRTEE |
3371 PPC_CACHE | PPC_CACHE_ICBI |
3372 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3373 PPC_MEM_TLBSYNC | PPC_MFTB |
3374 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3375 PPC_440_SPEC;
3376 pcc->msr_mask = (1ull << MSR_POW) |
3377 (1ull << MSR_CE) |
3378 (1ull << MSR_EE) |
3379 (1ull << MSR_PR) |
3380 (1ull << MSR_FP) |
3381 (1ull << MSR_ME) |
3382 (1ull << MSR_FE0) |
3383 (1ull << MSR_DWE) |
3384 (1ull << MSR_DE) |
3385 (1ull << MSR_FE1) |
3386 (1ull << MSR_IR) |
3387 (1ull << MSR_DR);
3388 pcc->mmu_model = POWERPC_MMU_BOOKE;
3389 pcc->excp_model = POWERPC_EXCP_BOOKE;
3390 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3391 pcc->bfd_mach = bfd_mach_ppc_403;
3392 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3393 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3394 }
3395
3396 static void init_proc_440x5(CPUPPCState *env)
3397 {
3398 /* Time base */
3399 register_tbl(env);
3400 register_BookE_sprs(env, 0x000000000000FFFFULL);
3401 register_440_sprs(env);
3402 register_usprgh_sprs(env);
3403 /* Processor identification */
3404 spr_register(env, SPR_BOOKE_PIR, "PIR",
3405 SPR_NOACCESS, SPR_NOACCESS,
3406 &spr_read_generic, &spr_write_pir,
3407 0x00000000);
3408 /* XXX : not implemented */
3409 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3410 SPR_NOACCESS, SPR_NOACCESS,
3411 &spr_read_generic, &spr_write_generic,
3412 0x00000000);
3413 /* XXX : not implemented */
3414 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3415 SPR_NOACCESS, SPR_NOACCESS,
3416 &spr_read_generic, &spr_write_generic,
3417 0x00000000);
3418 /* XXX : not implemented */
3419 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3420 SPR_NOACCESS, SPR_NOACCESS,
3421 &spr_read_generic, &spr_write_generic,
3422 0x00000000);
3423 /* XXX : not implemented */
3424 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3425 SPR_NOACCESS, SPR_NOACCESS,
3426 &spr_read_generic, &spr_write_generic,
3427 0x00000000);
3428 /* XXX : not implemented */
3429 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3430 SPR_NOACCESS, SPR_NOACCESS,
3431 &spr_read_generic, &spr_write_generic,
3432 0x00000000);
3433 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3434 SPR_NOACCESS, SPR_NOACCESS,
3435 &spr_read_generic, &spr_write_generic,
3436 0x00000000);
3437 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3438 SPR_NOACCESS, SPR_NOACCESS,
3439 &spr_read_generic, &spr_write_generic,
3440 0x00000000);
3441 /* XXX : not implemented */
3442 spr_register(env, SPR_440_CCR1, "CCR1",
3443 SPR_NOACCESS, SPR_NOACCESS,
3444 &spr_read_generic, &spr_write_generic,
3445 0x00000000);
3446 /* Memory management */
3447 #if !defined(CONFIG_USER_ONLY)
3448 env->nb_tlb = 64;
3449 env->nb_ways = 1;
3450 env->id_tlbs = 0;
3451 env->tlb_type = TLB_EMB;
3452 #endif
3453 init_excp_BookE(env);
3454 env->dcache_line_size = 32;
3455 env->icache_line_size = 32;
3456 ppc40x_irq_init(env_archcpu(env));
3457
3458 SET_FIT_PERIOD(12, 16, 20, 24);
3459 SET_WDT_PERIOD(20, 24, 28, 32);
3460 }
3461
3462 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3463 {
3464 DeviceClass *dc = DEVICE_CLASS(oc);
3465 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3466
3467 dc->desc = "PowerPC 440x5";
3468 pcc->init_proc = init_proc_440x5;
3469 pcc->check_pow = check_pow_nocheck;
3470 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3471 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3472 PPC_CACHE | PPC_CACHE_ICBI |
3473 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3474 PPC_MEM_TLBSYNC | PPC_MFTB |
3475 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3476 PPC_440_SPEC;
3477 pcc->msr_mask = (1ull << MSR_POW) |
3478 (1ull << MSR_CE) |
3479 (1ull << MSR_EE) |
3480 (1ull << MSR_PR) |
3481 (1ull << MSR_FP) |
3482 (1ull << MSR_ME) |
3483 (1ull << MSR_FE0) |
3484 (1ull << MSR_DWE) |
3485 (1ull << MSR_DE) |
3486 (1ull << MSR_FE1) |
3487 (1ull << MSR_IR) |
3488 (1ull << MSR_DR);
3489 pcc->mmu_model = POWERPC_MMU_BOOKE;
3490 pcc->excp_model = POWERPC_EXCP_BOOKE;
3491 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3492 pcc->bfd_mach = bfd_mach_ppc_403;
3493 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3494 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3495 }
3496
3497 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
3498 {
3499 DeviceClass *dc = DEVICE_CLASS(oc);
3500 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3501
3502 dc->desc = "PowerPC 440x5 with double precision FPU";
3503 pcc->init_proc = init_proc_440x5;
3504 pcc->check_pow = check_pow_nocheck;
3505 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3506 PPC_FLOAT | PPC_FLOAT_FSQRT |
3507 PPC_FLOAT_STFIWX |
3508 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3509 PPC_CACHE | PPC_CACHE_ICBI |
3510 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3511 PPC_MEM_TLBSYNC | PPC_MFTB |
3512 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3513 PPC_440_SPEC;
3514 pcc->insns_flags2 = PPC2_FP_CVT_S64;
3515 pcc->msr_mask = (1ull << MSR_POW) |
3516 (1ull << MSR_CE) |
3517 (1ull << MSR_EE) |
3518 (1ull << MSR_PR) |
3519 (1ull << MSR_FP) |
3520 (1ull << MSR_ME) |
3521 (1ull << MSR_FE0) |
3522 (1ull << MSR_DWE) |
3523 (1ull << MSR_DE) |
3524 (1ull << MSR_FE1) |
3525 (1ull << MSR_IR) |
3526 (1ull << MSR_DR);
3527 pcc->mmu_model = POWERPC_MMU_BOOKE;
3528 pcc->excp_model = POWERPC_EXCP_BOOKE;
3529 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3530 pcc->bfd_mach = bfd_mach_ppc_403;
3531 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3532 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3533 }
3534
3535 static void init_proc_MPC5xx(CPUPPCState *env)
3536 {
3537 /* Time base */
3538 register_tbl(env);
3539 register_5xx_8xx_sprs(env);
3540 register_5xx_sprs(env);
3541 init_excp_MPC5xx(env);
3542 env->dcache_line_size = 32;
3543 env->icache_line_size = 32;
3544 /* XXX: TODO: allocate internal IRQ controller */
3545 }
3546
3547 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3548 {
3549 DeviceClass *dc = DEVICE_CLASS(oc);
3550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3551
3552 dc->desc = "Freescale 5xx cores (aka RCPU)";
3553 pcc->init_proc = init_proc_MPC5xx;
3554 pcc->check_pow = check_pow_none;
3555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3556 PPC_MEM_EIEIO | PPC_MEM_SYNC |
3557 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
3558 PPC_MFTB;
3559 pcc->msr_mask = (1ull << MSR_ILE) |
3560 (1ull << MSR_EE) |
3561 (1ull << MSR_PR) |
3562 (1ull << MSR_FP) |
3563 (1ull << MSR_ME) |
3564 (1ull << MSR_FE0) |
3565 (1ull << MSR_SE) |
3566 (1ull << MSR_DE) |
3567 (1ull << MSR_FE1) |
3568 (1ull << MSR_EP) |
3569 (1ull << MSR_RI) |
3570 (1ull << MSR_LE);
3571 pcc->mmu_model = POWERPC_MMU_REAL;
3572 pcc->excp_model = POWERPC_EXCP_603;
3573 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3574 pcc->bfd_mach = bfd_mach_ppc_505;
3575 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3576 POWERPC_FLAG_BUS_CLK;
3577 }
3578
3579 static void init_proc_MPC8xx(CPUPPCState *env)
3580 {
3581 /* Time base */
3582 register_tbl(env);
3583 register_5xx_8xx_sprs(env);
3584 register_8xx_sprs(env);
3585 init_excp_MPC8xx(env);
3586 env->dcache_line_size = 32;
3587 env->icache_line_size = 32;
3588 /* XXX: TODO: allocate internal IRQ controller */
3589 }
3590
3591 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
3592 {
3593 DeviceClass *dc = DEVICE_CLASS(oc);
3594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3595
3596 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
3597 pcc->init_proc = init_proc_MPC8xx;
3598 pcc->check_pow = check_pow_none;
3599 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3600 PPC_MEM_EIEIO | PPC_MEM_SYNC |
3601 PPC_CACHE_ICBI | PPC_MFTB;
3602 pcc->msr_mask = (1ull << MSR_ILE) |
3603 (1ull << MSR_EE) |
3604 (1ull << MSR_PR) |
3605 (1ull << MSR_FP) |
3606 (1ull << MSR_ME) |
3607 (1ull << MSR_SE) |
3608 (1ull << MSR_DE) |
3609 (1ull << MSR_EP) |
3610 (1ull << MSR_IR) |
3611 (1ull << MSR_DR) |
3612 (1ull << MSR_RI) |
3613 (1ull << MSR_LE);
3614 pcc->mmu_model = POWERPC_MMU_MPC8xx;
3615 pcc->excp_model = POWERPC_EXCP_603;
3616 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3617 pcc->bfd_mach = bfd_mach_ppc_860;
3618 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3619 POWERPC_FLAG_BUS_CLK;
3620 }
3621
3622 /* Freescale 82xx cores (aka PowerQUICC-II) */
3623
3624 static void init_proc_G2(CPUPPCState *env)
3625 {
3626 register_ne_601_sprs(env);
3627 register_sdr1_sprs(env);
3628 register_G2_755_sprs(env);
3629 register_G2_sprs(env);
3630 /* Time base */
3631 register_tbl(env);
3632 /* External access control */
3633 /* XXX : not implemented */
3634 spr_register(env, SPR_EAR, "EAR",
3635 SPR_NOACCESS, SPR_NOACCESS,
3636 &spr_read_generic, &spr_write_generic,
3637 0x00000000);
3638 /* Hardware implementation register */
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_HID0, "HID0",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 /* XXX : not implemented */
3645 spr_register(env, SPR_HID1, "HID1",
3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 /* XXX : not implemented */
3650 spr_register(env, SPR_HID2, "HID2",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 /* Memory management */
3655 register_low_BATs(env);
3656 register_high_BATs(env);
3657 register_6xx_7xx_soft_tlb(env, 64, 2);
3658 init_excp_G2(env);
3659 env->dcache_line_size = 32;
3660 env->icache_line_size = 32;
3661 /* Allocate hardware IRQ controller */
3662 ppc6xx_irq_init(env_archcpu(env));
3663 }
3664
3665 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3666 {
3667 DeviceClass *dc = DEVICE_CLASS(oc);
3668 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3669
3670 dc->desc = "PowerPC G2";
3671 pcc->init_proc = init_proc_G2;
3672 pcc->check_pow = check_pow_hid0;
3673 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3674 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3675 PPC_FLOAT_STFIWX |
3676 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3677 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3678 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3679 PPC_SEGMENT | PPC_EXTERN;
3680 pcc->msr_mask = (1ull << MSR_POW) |
3681 (1ull << MSR_TGPR) |
3682 (1ull << MSR_EE) |
3683 (1ull << MSR_PR) |
3684 (1ull << MSR_FP) |
3685 (1ull << MSR_ME) |
3686 (1ull << MSR_FE0) |
3687 (1ull << MSR_SE) |
3688 (1ull << MSR_DE) |
3689 (1ull << MSR_FE1) |
3690 (1ull << MSR_AL) |
3691 (1ull << MSR_EP) |
3692 (1ull << MSR_IR) |
3693 (1ull << MSR_DR) |
3694 (1ull << MSR_RI);
3695 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3696 pcc->excp_model = POWERPC_EXCP_G2;
3697 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3698 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3699 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3700 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3701 }
3702
3703 static void init_proc_G2LE(CPUPPCState *env)
3704 {
3705 register_ne_601_sprs(env);
3706 register_sdr1_sprs(env);
3707 register_G2_755_sprs(env);
3708 register_G2_sprs(env);
3709 /* Time base */
3710 register_tbl(env);
3711 /* External access control */
3712 /* XXX : not implemented */
3713 spr_register(env, SPR_EAR, "EAR",
3714 SPR_NOACCESS, SPR_NOACCESS,
3715 &spr_read_generic, &spr_write_generic,
3716 0x00000000);
3717 /* Hardware implementation register */
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_HID0, "HID0",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* XXX : not implemented */
3724 spr_register(env, SPR_HID1, "HID1",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_HID2, "HID2",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733
3734 /* Memory management */
3735 register_low_BATs(env);
3736 register_high_BATs(env);
3737 register_6xx_7xx_soft_tlb(env, 64, 2);
3738 init_excp_G2(env);
3739 env->dcache_line_size = 32;
3740 env->icache_line_size = 32;
3741 /* Allocate hardware IRQ controller */
3742 ppc6xx_irq_init(env_archcpu(env));
3743 }
3744
3745 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3746 {
3747 DeviceClass *dc = DEVICE_CLASS(oc);
3748 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3749
3750 dc->desc = "PowerPC G2LE";
3751 pcc->init_proc = init_proc_G2LE;
3752 pcc->check_pow = check_pow_hid0;
3753 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3754 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3755 PPC_FLOAT_STFIWX |
3756 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3757 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3758 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3759 PPC_SEGMENT | PPC_EXTERN;
3760 pcc->msr_mask = (1ull << MSR_POW) |
3761 (1ull << MSR_TGPR) |
3762 (1ull << MSR_ILE) |
3763 (1ull << MSR_EE) |
3764 (1ull << MSR_PR) |
3765 (1ull << MSR_FP) |
3766 (1ull << MSR_ME) |
3767 (1ull << MSR_FE0) |
3768 (1ull << MSR_SE) |
3769 (1ull << MSR_DE) |
3770 (1ull << MSR_FE1) |
3771 (1ull << MSR_AL) |
3772 (1ull << MSR_EP) |
3773 (1ull << MSR_IR) |
3774 (1ull << MSR_DR) |
3775 (1ull << MSR_RI) |
3776 (1ull << MSR_LE);
3777 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3778 pcc->excp_model = POWERPC_EXCP_G2;
3779 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3780 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3781 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3782 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3783 }
3784
3785 static void init_proc_e200(CPUPPCState *env)
3786 {
3787 /* Time base */
3788 register_tbl(env);
3789 register_BookE_sprs(env, 0x000000070000FFFFULL);
3790 /* XXX : not implemented */
3791 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3792 &spr_read_spefscr, &spr_write_spefscr,
3793 &spr_read_spefscr, &spr_write_spefscr,
3794 0x00000000);
3795 /* Memory management */
3796 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3797 /* XXX : not implemented */
3798 spr_register(env, SPR_HID0, "HID0",
3799 SPR_NOACCESS, SPR_NOACCESS,
3800 &spr_read_generic, &spr_write_generic,
3801 0x00000000);
3802 /* XXX : not implemented */
3803 spr_register(env, SPR_HID1, "HID1",
3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_generic,
3806 0x00000000);
3807 /* XXX : not implemented */
3808 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3809 SPR_NOACCESS, SPR_NOACCESS,
3810 &spr_read_generic, &spr_write_generic,
3811 0x00000000);
3812 /* XXX : not implemented */
3813 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3814 SPR_NOACCESS, SPR_NOACCESS,
3815 &spr_read_generic, &spr_write_generic,
3816 0x00000000);
3817 /* XXX : not implemented */
3818 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
3822 /* XXX : not implemented */
3823 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3824 SPR_NOACCESS, SPR_NOACCESS,
3825 &spr_read_generic, &spr_write_generic,
3826 0x00000000);
3827 /* XXX : not implemented */
3828 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_generic,
3831 0x00000000);
3832 /* XXX : not implemented */
3833 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3834 &spr_read_generic, SPR_NOACCESS,
3835 &spr_read_generic, SPR_NOACCESS,
3836 0x00000000);
3837 /* XXX : not implemented */
3838 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3839 SPR_NOACCESS, SPR_NOACCESS,
3840 &spr_read_generic, &spr_write_generic,
3841 0x00000000);
3842 /* XXX : not implemented */
3843 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3844 SPR_NOACCESS, SPR_NOACCESS,
3845 &spr_read_generic, &spr_write_generic,
3846 0x00000000);
3847 /* XXX : not implemented */
3848 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3849 SPR_NOACCESS, SPR_NOACCESS,
3850 &spr_read_generic, &spr_write_generic,
3851 0x00000000);
3852 /* XXX : not implemented */
3853 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
3857 /* XXX : not implemented */
3858 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3859 SPR_NOACCESS, SPR_NOACCESS,
3860 &spr_read_generic, &spr_write_generic,
3861 0x00000000);
3862 /* XXX : not implemented */
3863 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3864 SPR_NOACCESS, SPR_NOACCESS,
3865 &spr_read_generic, &spr_write_generic,
3866 0x00000000);
3867 /* XXX : not implemented */
3868 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3869 SPR_NOACCESS, SPR_NOACCESS,
3870 &spr_read_generic, &spr_write_generic,
3871 0x00000000); /* TOFIX */
3872 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3873 SPR_NOACCESS, SPR_NOACCESS,
3874 &spr_read_generic, &spr_write_generic,
3875 0x00000000);
3876 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 #if !defined(CONFIG_USER_ONLY)
3881 env->nb_tlb = 64;
3882 env->nb_ways = 1;
3883 env->id_tlbs = 0;
3884 env->tlb_type = TLB_EMB;
3885 #endif
3886 init_excp_e200(env, 0xFFFF0000UL);
3887 env->dcache_line_size = 32;
3888 env->icache_line_size = 32;
3889 /* XXX: TODO: allocate internal IRQ controller */
3890 }
3891
3892 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3893 {
3894 DeviceClass *dc = DEVICE_CLASS(oc);
3895 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3896
3897 dc->desc = "e200 core";
3898 pcc->init_proc = init_proc_e200;
3899 pcc->check_pow = check_pow_hid0;
3900 /*
3901 * XXX: unimplemented instructions:
3902 * dcblc
3903 * dcbtlst
3904 * dcbtstls
3905 * icblc
3906 * icbtls
3907 * tlbivax
3908 * all SPE multiply-accumulate instructions
3909 */
3910 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3911 PPC_SPE | PPC_SPE_SINGLE |
3912 PPC_WRTEE | PPC_RFDI |
3913 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3914 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3915 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3916 PPC_BOOKE;
3917 pcc->msr_mask = (1ull << MSR_UCLE) |
3918 (1ull << MSR_SPE) |
3919 (1ull << MSR_POW) |
3920 (1ull << MSR_CE) |
3921 (1ull << MSR_EE) |
3922 (1ull << MSR_PR) |
3923 (1ull << MSR_FP) |
3924 (1ull << MSR_ME) |
3925 (1ull << MSR_FE0) |
3926 (1ull << MSR_DWE) |
3927 (1ull << MSR_DE) |
3928 (1ull << MSR_FE1) |
3929 (1ull << MSR_IR) |
3930 (1ull << MSR_DR);
3931 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3932 pcc->excp_model = POWERPC_EXCP_BOOKE;
3933 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3934 pcc->bfd_mach = bfd_mach_ppc_860;
3935 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3936 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3937 POWERPC_FLAG_BUS_CLK;
3938 }
3939
3940 static void init_proc_e300(CPUPPCState *env)
3941 {
3942 register_ne_601_sprs(env);
3943 register_sdr1_sprs(env);
3944 register_603_sprs(env);
3945 /* Time base */
3946 register_tbl(env);
3947 /* hardware implementation registers */
3948 /* XXX : not implemented */
3949 spr_register(env, SPR_HID0, "HID0",
3950 SPR_NOACCESS, SPR_NOACCESS,
3951 &spr_read_generic, &spr_write_generic,
3952 0x00000000);
3953 /* XXX : not implemented */
3954 spr_register(env, SPR_HID1, "HID1",
3955 SPR_NOACCESS, SPR_NOACCESS,
3956 &spr_read_generic, &spr_write_generic,
3957 0x00000000);
3958 /* XXX : not implemented */
3959 spr_register(env, SPR_HID2, "HID2",
3960 SPR_NOACCESS, SPR_NOACCESS,
3961 &spr_read_generic, &spr_write_generic,
3962 0x00000000);
3963 /* Breakpoints */
3964 /* XXX : not implemented */
3965 spr_register(env, SPR_DABR, "DABR",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_generic,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_DABR2, "DABR2",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 /* XXX : not implemented */
3975 spr_register(env, SPR_IABR2, "IABR2",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* XXX : not implemented */
3980 spr_register(env, SPR_IBCR, "IBCR",
3981 SPR_NOACCESS, SPR_NOACCESS,
3982 &spr_read_generic, &spr_write_generic,
3983 0x00000000);
3984 /* XXX : not implemented */
3985 spr_register(env, SPR_DBCR, "DBCR",
3986 SPR_NOACCESS, SPR_NOACCESS,
3987 &spr_read_generic, &spr_write_generic,
3988 0x00000000);
3989 /* Memory management */
3990 register_low_BATs(env);
3991 register_high_BATs(env);
3992 register_6xx_7xx_soft_tlb(env, 64, 2);
3993 init_excp_603(env);
3994 env->dcache_line_size = 32;
3995 env->icache_line_size = 32;
3996 /* Allocate hardware IRQ controller */
3997 ppc6xx_irq_init(env_archcpu(env));
3998 }
3999
4000 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4001 {
4002 DeviceClass *dc = DEVICE_CLASS(oc);
4003 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4004
4005 dc->desc = "e300 core";
4006 pcc->init_proc = init_proc_e300;
4007 pcc->check_pow = check_pow_hid0;
4008 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4009 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4010 PPC_FLOAT_STFIWX |
4011 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4012 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4013 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4014 PPC_SEGMENT | PPC_EXTERN;
4015 pcc->msr_mask = (1ull << MSR_POW) |
4016 (1ull << MSR_TGPR) |
4017 (1ull << MSR_ILE) |
4018 (1ull << MSR_EE) |
4019 (1ull << MSR_PR) |
4020 (1ull << MSR_FP) |
4021 (1ull << MSR_ME) |
4022 (1ull << MSR_FE0) |
4023 (1ull << MSR_SE) |
4024 (1ull << MSR_DE) |
4025 (1ull << MSR_FE1) |
4026 (1ull << MSR_AL) |
4027 (1ull << MSR_EP) |
4028 (1ull << MSR_IR) |
4029 (1ull << MSR_DR) |
4030 (1ull << MSR_RI) |
4031 (1ull << MSR_LE);
4032 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4033 pcc->excp_model = POWERPC_EXCP_603;
4034 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4035 pcc->bfd_mach = bfd_mach_ppc_603;
4036 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4037 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4038 }
4039
4040 enum fsl_e500_version {
4041 fsl_e500v1,
4042 fsl_e500v2,
4043 fsl_e500mc,
4044 fsl_e5500,
4045 fsl_e6500,
4046 };
4047
4048 static void init_proc_e500(CPUPPCState *env, int version)
4049 {
4050 uint32_t tlbncfg[2];
4051 uint64_t ivor_mask;
4052 uint64_t ivpr_mask = 0xFFFF0000ULL;
4053 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4054 | 0x0020; /* 32 kb */
4055 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4056 | 0x0020; /* 32 kb */
4057 uint32_t mmucfg = 0;
4058 #if !defined(CONFIG_USER_ONLY)
4059 int i;
4060 #endif
4061
4062 /* Time base */
4063 register_tbl(env);
4064 /*
4065 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4066 * complain when accessing them.
4067 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
4068 */
4069 switch (version) {
4070 case fsl_e500v1:
4071 case fsl_e500v2:
4072 default:
4073 ivor_mask = 0x0000000F0000FFFFULL;
4074 break;
4075 case fsl_e500mc:
4076 case fsl_e5500:
4077 ivor_mask = 0x000003FE0000FFFFULL;
4078 break;
4079 case fsl_e6500:
4080 ivor_mask = 0x000003FF0000FFFFULL;
4081 break;
4082 }
4083 register_BookE_sprs(env, ivor_mask);
4084 register_usprg3_sprs(env);
4085 /* Processor identification */
4086 spr_register(env, SPR_BOOKE_PIR, "PIR",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_pir,
4089 0x00000000);
4090 /* XXX : not implemented */
4091 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4092 &spr_read_spefscr, &spr_write_spefscr,
4093 &spr_read_spefscr, &spr_write_spefscr,
4094 0x00000000);
4095 #if !defined(CONFIG_USER_ONLY)
4096 /* Memory management */
4097 env->nb_pids = 3;
4098 env->nb_ways = 2;
4099 env->id_tlbs = 0;
4100 switch (version) {
4101 case fsl_e500v1:
4102 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
4103 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4104 break;
4105 case fsl_e500v2:
4106 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4107 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4108 break;
4109 case fsl_e500mc:
4110 case fsl_e5500:
4111 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4112 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4113 break;
4114 case fsl_e6500:
4115 mmucfg = 0x6510B45;
4116 env->nb_pids = 1;
4117 tlbncfg[0] = 0x08052400;
4118 tlbncfg[1] = 0x40028040;
4119 break;
4120 default:
4121 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4122 env->spr[SPR_PVR]);
4123 }
4124 #endif
4125 /* Cache sizes */
4126 switch (version) {
4127 case fsl_e500v1:
4128 case fsl_e500v2:
4129 env->dcache_line_size = 32;
4130 env->icache_line_size = 32;
4131 break;
4132 case fsl_e500mc:
4133 case fsl_e5500:
4134 env->dcache_line_size = 64;
4135 env->icache_line_size = 64;
4136 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4137 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4138 break;
4139 case fsl_e6500:
4140 env->dcache_line_size = 32;
4141 env->icache_line_size = 32;
4142 l1cfg0 |= 0x0F83820;
4143 l1cfg1 |= 0x0B83820;
4144 break;
4145 default:
4146 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4147 env->spr[SPR_PVR]);
4148 }
4149 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
4150 /* XXX : not implemented */
4151 spr_register(env, SPR_HID0, "HID0",
4152 SPR_NOACCESS, SPR_NOACCESS,
4153 &spr_read_generic, &spr_write_generic,
4154 0x00000000);
4155 /* XXX : not implemented */
4156 spr_register(env, SPR_HID1, "HID1",
4157 SPR_NOACCESS, SPR_NOACCESS,
4158 &spr_read_generic, &spr_write_generic,
4159 0x00000000);
4160 /* XXX : not implemented */
4161 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4162 SPR_NOACCESS, SPR_NOACCESS,
4163 &spr_read_generic, &spr_write_generic,
4164 0x00000000);
4165 /* XXX : not implemented */
4166 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4167 SPR_NOACCESS, SPR_NOACCESS,
4168 &spr_read_generic, &spr_write_generic,
4169 0x00000000);
4170 /* XXX : not implemented */
4171 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4172 SPR_NOACCESS, SPR_NOACCESS,
4173 &spr_read_generic, &spr_write_generic,
4174 0x00000000);
4175 /* XXX : not implemented */
4176 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4177 SPR_NOACCESS, SPR_NOACCESS,
4178 &spr_read_generic, &spr_write_generic,
4179 0x00000000);
4180 /* XXX : not implemented */
4181 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, &spr_write_generic,
4184 0x00000000);
4185 /* XXX : not implemented */
4186 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4187 SPR_NOACCESS, SPR_NOACCESS,
4188 &spr_read_generic, &spr_write_generic,
4189 0x00000000);
4190 /* XXX : not implemented */
4191 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4192 &spr_read_generic, SPR_NOACCESS,
4193 &spr_read_generic, SPR_NOACCESS,
4194 l1cfg0);
4195 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4196 &spr_read_generic, SPR_NOACCESS,
4197 &spr_read_generic, SPR_NOACCESS,
4198 l1cfg1);
4199 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4200 SPR_NOACCESS, SPR_NOACCESS,
4201 &spr_read_generic, &spr_write_e500_l1csr0,
4202 0x00000000);
4203 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_e500_l1csr1,
4206 0x00000000);
4207 if (version != fsl_e500v1 && version != fsl_e500v2) {
4208 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
4209 SPR_NOACCESS, SPR_NOACCESS,
4210 &spr_read_generic, &spr_write_e500_l2csr0,
4211 0x00000000);
4212 }
4213 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4214 SPR_NOACCESS, SPR_NOACCESS,
4215 &spr_read_generic, &spr_write_generic,
4216 0x00000000);
4217 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4218 SPR_NOACCESS, SPR_NOACCESS,
4219 &spr_read_generic, &spr_write_generic,
4220 0x00000000);
4221 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4222 SPR_NOACCESS, SPR_NOACCESS,
4223 &spr_read_generic, &spr_write_booke206_mmucsr0,
4224 0x00000000);
4225 spr_register(env, SPR_BOOKE_EPR, "EPR",
4226 SPR_NOACCESS, SPR_NOACCESS,
4227 &spr_read_generic, SPR_NOACCESS,
4228 0x00000000);
4229 /* XXX better abstract into Emb.xxx features */
4230 if ((version == fsl_e5500) || (version == fsl_e6500)) {
4231 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4232 SPR_NOACCESS, SPR_NOACCESS,
4233 &spr_read_generic, &spr_write_generic,
4234 0x00000000);
4235 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4236 SPR_NOACCESS, SPR_NOACCESS,
4237 &spr_read_mas73, &spr_write_mas73,
4238 0x00000000);
4239 ivpr_mask = (target_ulong)~0xFFFFULL;
4240 }
4241
4242 if (version == fsl_e6500) {
4243 /* Thread identification */
4244 spr_register(env, SPR_TIR, "TIR",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, SPR_NOACCESS,
4247 0x00000000);
4248 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, SPR_NOACCESS,
4251 0x00000004);
4252 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, SPR_NOACCESS,
4255 0x7FFFFFFC);
4256 }
4257
4258 #if !defined(CONFIG_USER_ONLY)
4259 env->nb_tlb = 0;
4260 env->tlb_type = TLB_MAS;
4261 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4262 env->nb_tlb += booke206_tlb_size(env, i);
4263 }
4264 #endif
4265
4266 init_excp_e200(env, ivpr_mask);
4267 /* Allocate hardware IRQ controller */
4268 ppce500_irq_init(env_archcpu(env));
4269 }
4270
4271 static void init_proc_e500v1(CPUPPCState *env)
4272 {
4273 init_proc_e500(env, fsl_e500v1);
4274 }
4275
4276 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4277 {
4278 DeviceClass *dc = DEVICE_CLASS(oc);
4279 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4280
4281 dc->desc = "e500v1 core";
4282 pcc->init_proc = init_proc_e500v1;
4283 pcc->check_pow = check_pow_hid0;
4284 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4285 PPC_SPE | PPC_SPE_SINGLE |
4286 PPC_WRTEE | PPC_RFDI |
4287 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4288 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4289 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4290 pcc->insns_flags2 = PPC2_BOOKE206;
4291 pcc->msr_mask = (1ull << MSR_UCLE) |
4292 (1ull << MSR_SPE) |
4293 (1ull << MSR_POW) |
4294 (1ull << MSR_CE) |
4295 (1ull << MSR_EE) |
4296 (1ull << MSR_PR) |
4297 (1ull << MSR_FP) |
4298 (1ull << MSR_ME) |
4299 (1ull << MSR_FE0) |
4300 (1ull << MSR_DWE) |
4301 (1ull << MSR_DE) |
4302 (1ull << MSR_FE1) |
4303 (1ull << MSR_IR) |
4304 (1ull << MSR_DR);
4305 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4306 pcc->excp_model = POWERPC_EXCP_BOOKE;
4307 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4308 pcc->bfd_mach = bfd_mach_ppc_860;
4309 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4310 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4311 POWERPC_FLAG_BUS_CLK;
4312 }
4313
4314 static void init_proc_e500v2(CPUPPCState *env)
4315 {
4316 init_proc_e500(env, fsl_e500v2);
4317 }
4318
4319 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4320 {
4321 DeviceClass *dc = DEVICE_CLASS(oc);
4322 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4323
4324 dc->desc = "e500v2 core";
4325 pcc->init_proc = init_proc_e500v2;
4326 pcc->check_pow = check_pow_hid0;
4327 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4328 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4329 PPC_WRTEE | PPC_RFDI |
4330 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4331 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4332 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4333 pcc->insns_flags2 = PPC2_BOOKE206;
4334 pcc->msr_mask = (1ull << MSR_UCLE) |
4335 (1ull << MSR_SPE) |
4336 (1ull << MSR_POW) |
4337 (1ull << MSR_CE) |
4338 (1ull << MSR_EE) |
4339 (1ull << MSR_PR) |
4340 (1ull << MSR_FP) |
4341 (1ull << MSR_ME) |
4342 (1ull << MSR_FE0) |
4343 (1ull << MSR_DWE) |
4344 (1ull << MSR_DE) |
4345 (1ull << MSR_FE1) |
4346 (1ull << MSR_IR) |
4347 (1ull << MSR_DR);
4348 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4349 pcc->excp_model = POWERPC_EXCP_BOOKE;
4350 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4351 pcc->bfd_mach = bfd_mach_ppc_860;
4352 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4353 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4354 POWERPC_FLAG_BUS_CLK;
4355 }
4356
4357 static void init_proc_e500mc(CPUPPCState *env)
4358 {
4359 init_proc_e500(env, fsl_e500mc);
4360 }
4361
4362 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4363 {
4364 DeviceClass *dc = DEVICE_CLASS(oc);
4365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4366
4367 dc->desc = "e500mc core";
4368 pcc->init_proc = init_proc_e500mc;
4369 pcc->check_pow = check_pow_none;
4370 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4371 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4372 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4373 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4374 PPC_FLOAT | PPC_FLOAT_FRES |
4375 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4376 PPC_FLOAT_STFIWX | PPC_WAIT |
4377 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4378 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4379 pcc->msr_mask = (1ull << MSR_GS) |
4380 (1ull << MSR_UCLE) |
4381 (1ull << MSR_CE) |
4382 (1ull << MSR_EE) |
4383 (1ull << MSR_PR) |
4384 (1ull << MSR_FP) |
4385 (1ull << MSR_ME) |
4386 (1ull << MSR_FE0) |
4387 (1ull << MSR_DE) |
4388 (1ull << MSR_FE1) |
4389 (1ull << MSR_IR) |
4390 (1ull << MSR_DR) |
4391 (1ull << MSR_PX) |
4392 (1ull << MSR_RI);
4393 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4394 pcc->excp_model = POWERPC_EXCP_BOOKE;
4395 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4396 /* FIXME: figure out the correct flag for e500mc */
4397 pcc->bfd_mach = bfd_mach_ppc_e500;
4398 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4399 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4400 }
4401
4402 #ifdef TARGET_PPC64
4403 static void init_proc_e5500(CPUPPCState *env)
4404 {
4405 init_proc_e500(env, fsl_e5500);
4406 }
4407
4408 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4409 {
4410 DeviceClass *dc = DEVICE_CLASS(oc);
4411 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4412
4413 dc->desc = "e5500 core";
4414 pcc->init_proc = init_proc_e5500;
4415 pcc->check_pow = check_pow_none;
4416 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4417 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4418 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4419 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4420 PPC_FLOAT | PPC_FLOAT_FRES |
4421 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4422 PPC_FLOAT_STFIWX | PPC_WAIT |
4423 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4424 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4425 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4426 PPC2_FP_CVT_S64;
4427 pcc->msr_mask = (1ull << MSR_CM) |
4428 (1ull << MSR_GS) |
4429 (1ull << MSR_UCLE) |
4430 (1ull << MSR_CE) |
4431 (1ull << MSR_EE) |
4432 (1ull << MSR_PR) |
4433 (1ull << MSR_FP) |
4434 (1ull << MSR_ME) |
4435 (1ull << MSR_FE0) |
4436 (1ull << MSR_DE) |
4437 (1ull << MSR_FE1) |
4438 (1ull << MSR_IR) |
4439 (1ull << MSR_DR) |
4440 (1ull << MSR_PX) |
4441 (1ull << MSR_RI);
4442 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4443 pcc->excp_model = POWERPC_EXCP_BOOKE;
4444 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4445 /* FIXME: figure out the correct flag for e5500 */
4446 pcc->bfd_mach = bfd_mach_ppc_e500;
4447 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4448 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4449 }
4450
4451 static void init_proc_e6500(CPUPPCState *env)
4452 {
4453 init_proc_e500(env, fsl_e6500);
4454 }
4455
4456 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
4457 {
4458 DeviceClass *dc = DEVICE_CLASS(oc);
4459 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4460
4461 dc->desc = "e6500 core";
4462 pcc->init_proc = init_proc_e6500;
4463 pcc->check_pow = check_pow_none;
4464 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4465 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4466 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4467 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4468 PPC_FLOAT | PPC_FLOAT_FRES |
4469 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4470 PPC_FLOAT_STFIWX | PPC_WAIT |
4471 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4472 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
4473 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4474 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
4475 pcc->msr_mask = (1ull << MSR_CM) |
4476 (1ull << MSR_GS) |
4477 (1ull << MSR_UCLE) |
4478 (1ull << MSR_CE) |
4479 (1ull << MSR_EE) |
4480 (1ull << MSR_PR) |
4481 (1ull << MSR_FP) |
4482 (1ull << MSR_ME) |
4483 (1ull << MSR_FE0) |
4484 (1ull << MSR_DE) |
4485 (1ull << MSR_FE1) |
4486 (1ull << MSR_IS) |
4487 (1ull << MSR_DS) |
4488 (1ull << MSR_PX) |
4489 (1ull << MSR_RI) |
4490 (1ull << MSR_VR);
4491 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4492 pcc->excp_model = POWERPC_EXCP_BOOKE;
4493 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4494 pcc->bfd_mach = bfd_mach_ppc_e500;
4495 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4496 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
4497 }
4498
4499 #endif
4500
4501 /* Non-embedded PowerPC */
4502
4503 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4504
4505 static void init_proc_601(CPUPPCState *env)
4506 {
4507 register_ne_601_sprs(env);
4508 register_sdr1_sprs(env);
4509 register_601_sprs(env);
4510 /* Hardware implementation registers */
4511 /* XXX : not implemented */
4512 spr_register(env, SPR_HID0, "HID0",
4513 SPR_NOACCESS, SPR_NOACCESS,
4514 &spr_read_generic, &spr_write_hid0_601,
4515 0x80010080);
4516 /* XXX : not implemented */
4517 spr_register(env, SPR_HID1, "HID1",
4518 SPR_NOACCESS, SPR_NOACCESS,
4519 &spr_read_generic, &spr_write_generic,
4520 0x00000000);
4521 /* XXX : not implemented */
4522 spr_register(env, SPR_601_HID2, "HID2",
4523 SPR_NOACCESS, SPR_NOACCESS,
4524 &spr_read_generic, &spr_write_generic,
4525 0x00000000);
4526 /* XXX : not implemented */
4527 spr_register(env, SPR_601_HID5, "HID5",
4528 SPR_NOACCESS, SPR_NOACCESS,
4529 &spr_read_generic, &spr_write_generic,
4530 0x00000000);
4531 /* Memory management */
4532 init_excp_601(env);
4533 /*
4534 * XXX: beware that dcache line size is 64
4535 * but dcbz uses 32 bytes "sectors"
4536 * XXX: this breaks clcs instruction !
4537 */
4538 env->dcache_line_size = 32;
4539 env->icache_line_size = 64;
4540 /* Allocate hardware IRQ controller */
4541 ppc6xx_irq_init(env_archcpu(env));
4542 }
4543
4544 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4545 {
4546 DeviceClass *dc = DEVICE_CLASS(oc);
4547 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4548
4549 dc->desc = "PowerPC 601";
4550 pcc->init_proc = init_proc_601;
4551 pcc->check_pow = check_pow_none;
4552 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4553 PPC_FLOAT |
4554 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4555 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4556 PPC_SEGMENT | PPC_EXTERN;
4557 pcc->msr_mask = (1ull << MSR_EE) |
4558 (1ull << MSR_PR) |
4559 (1ull << MSR_FP) |
4560 (1ull << MSR_ME) |
4561 (1ull << MSR_FE0) |
4562 (1ull << MSR_SE) |
4563 (1ull << MSR_FE1) |
4564 (1ull << MSR_EP) |
4565 (1ull << MSR_IR) |
4566 (1ull << MSR_DR);
4567 pcc->mmu_model = POWERPC_MMU_601;
4568 pcc->excp_model = POWERPC_EXCP_601;
4569 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4570 pcc->bfd_mach = bfd_mach_ppc_601;
4571 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4572 }
4573
4574 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4575
4576 static void init_proc_601v(CPUPPCState *env)
4577 {
4578 init_proc_601(env);
4579 /* XXX : not implemented */
4580 spr_register(env, SPR_601_HID15, "HID15",
4581 SPR_NOACCESS, SPR_NOACCESS,
4582 &spr_read_generic, &spr_write_generic,
4583 0x00000000);
4584 }
4585
4586 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4587 {
4588 DeviceClass *dc = DEVICE_CLASS(oc);
4589 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4590
4591 dc->desc = "PowerPC 601v";
4592 pcc->init_proc = init_proc_601v;
4593 pcc->check_pow = check_pow_none;
4594 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4595 PPC_FLOAT |
4596 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4597 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4598 PPC_SEGMENT | PPC_EXTERN;
4599 pcc->msr_mask = (1ull << MSR_EE) |
4600 (1ull << MSR_PR) |
4601 (1ull << MSR_FP) |
4602 (1ull << MSR_ME) |
4603 (1ull << MSR_FE0) |
4604 (1ull << MSR_SE) |
4605 (1ull << MSR_FE1) |
4606 (1ull << MSR_EP) |
4607 (1ull << MSR_IR) |
4608 (1ull << MSR_DR);
4609 pcc->mmu_model = POWERPC_MMU_601;
4610 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4611 pcc->bfd_mach = bfd_mach_ppc_601;
4612 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4613 }
4614
4615 static void init_proc_602(CPUPPCState *env)
4616 {
4617 register_ne_601_sprs(env);
4618 register_sdr1_sprs(env);
4619 register_602_sprs(env);
4620 /* Time base */
4621 register_tbl(env);
4622 /* hardware implementation registers */
4623 /* XXX : not implemented */
4624 spr_register(env, SPR_HID0, "HID0",
4625 SPR_NOACCESS, SPR_NOACCESS,
4626 &spr_read_generic, &spr_write_generic,
4627 0x00000000);
4628 /* XXX : not implemented */
4629 spr_register(env, SPR_HID1, "HID1",
4630 SPR_NOACCESS, SPR_NOACCESS,
4631 &spr_read_generic, &spr_write_generic,
4632 0x00000000);
4633 /* Memory management */
4634 register_low_BATs(env);
4635 register_6xx_7xx_soft_tlb(env, 64, 2);
4636 init_excp_602(env);
4637 env->dcache_line_size = 32;
4638 env->icache_line_size = 32;
4639 /* Allocate hardware IRQ controller */
4640 ppc6xx_irq_init(env_archcpu(env));
4641 }
4642
4643 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4644 {
4645 DeviceClass *dc = DEVICE_CLASS(oc);
4646 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4647
4648 dc->desc = "PowerPC 602";
4649 pcc->init_proc = init_proc_602;
4650 pcc->check_pow = check_pow_hid0;
4651 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4652 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4653 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4654 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4655 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4656 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4657 PPC_SEGMENT | PPC_602_SPEC;
4658 pcc->msr_mask = (1ull << MSR_VSX) |
4659 (1ull << MSR_SA) |
4660 (1ull << MSR_POW) |
4661 (1ull << MSR_TGPR) |
4662 (1ull << MSR_ILE) |
4663 (1ull << MSR_EE) |
4664 (1ull << MSR_PR) |
4665 (1ull << MSR_FP) |
4666 (1ull << MSR_ME) |
4667 (1ull << MSR_FE0) |
4668 (1ull << MSR_SE) |
4669 (1ull << MSR_DE) |
4670 (1ull << MSR_FE1) |
4671 (1ull << MSR_EP) |
4672 (1ull << MSR_IR) |
4673 (1ull << MSR_DR) |
4674 (1ull << MSR_RI) |
4675 (1ull << MSR_LE);
4676 /* XXX: 602 MMU is quite specific. Should add a special case */
4677 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4678 pcc->excp_model = POWERPC_EXCP_602;
4679 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4680 pcc->bfd_mach = bfd_mach_ppc_602;
4681 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4682 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4683 }
4684
4685 static void init_proc_603(CPUPPCState *env)
4686 {
4687 register_ne_601_sprs(env);
4688 register_sdr1_sprs(env);
4689 register_603_sprs(env);
4690 /* Time base */
4691 register_tbl(env);
4692 /* hardware implementation registers */
4693 /* XXX : not implemented */
4694 spr_register(env, SPR_HID0, "HID0",
4695 SPR_NOACCESS, SPR_NOACCESS,
4696 &spr_read_generic, &spr_write_generic,
4697 0x00000000);
4698 /* XXX : not implemented */
4699 spr_register(env, SPR_HID1, "HID1",
4700 SPR_NOACCESS, SPR_NOACCESS,
4701 &spr_read_generic, &spr_write_generic,
4702 0x00000000);
4703 /* Memory management */
4704 register_low_BATs(env);
4705 register_6xx_7xx_soft_tlb(env, 64, 2);
4706 init_excp_603(env);
4707 env->dcache_line_size = 32;
4708 env->icache_line_size = 32;
4709 /* Allocate hardware IRQ controller */
4710 ppc6xx_irq_init(env_archcpu(env));
4711 }
4712
4713 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4714 {
4715 DeviceClass *dc = DEVICE_CLASS(oc);
4716 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4717
4718 dc->desc = "PowerPC 603";
4719 pcc->init_proc = init_proc_603;
4720 pcc->check_pow = check_pow_hid0;
4721 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4722 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4723 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4724 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4725 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4726 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4727 PPC_SEGMENT | PPC_EXTERN;
4728 pcc->msr_mask = (1ull << MSR_POW) |
4729 (1ull << MSR_TGPR) |
4730 (1ull << MSR_ILE) |
4731 (1ull << MSR_EE) |
4732 (1ull << MSR_PR) |
4733 (1ull << MSR_FP) |
4734 (1ull << MSR_ME) |
4735 (1ull << MSR_FE0) |
4736 (1ull << MSR_SE) |
4737 (1ull << MSR_DE) |
4738 (1ull << MSR_FE1) |
4739 (1ull << MSR_EP) |
4740 (1ull << MSR_IR) |
4741 (1ull << MSR_DR) |
4742 (1ull << MSR_RI) |
4743 (1ull << MSR_LE);
4744 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4745 pcc->excp_model = POWERPC_EXCP_603;
4746 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4747 pcc->bfd_mach = bfd_mach_ppc_603;
4748 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4749 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4750 }
4751
4752 static void init_proc_603E(CPUPPCState *env)
4753 {
4754 register_ne_601_sprs(env);
4755 register_sdr1_sprs(env);
4756 register_603_sprs(env);
4757 /* Time base */
4758 register_tbl(env);
4759 /* hardware implementation registers */
4760 /* XXX : not implemented */
4761 spr_register(env, SPR_HID0, "HID0",
4762 SPR_NOACCESS, SPR_NOACCESS,
4763 &spr_read_generic, &spr_write_generic,
4764 0x00000000);
4765 /* XXX : not implemented */
4766 spr_register(env, SPR_HID1, "HID1",
4767 SPR_NOACCESS, SPR_NOACCESS,
4768 &spr_read_generic, &spr_write_generic,
4769 0x00000000);
4770 /* Memory management */
4771 register_low_BATs(env);
4772 register_6xx_7xx_soft_tlb(env, 64, 2);
4773 init_excp_603(env);
4774 env->dcache_line_size = 32;
4775 env->icache_line_size = 32;
4776 /* Allocate hardware IRQ controller */
4777 ppc6xx_irq_init(env_archcpu(env));
4778 }
4779
4780 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4781 {
4782 DeviceClass *dc = DEVICE_CLASS(oc);
4783 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4784
4785 dc->desc = "PowerPC 603e";
4786 pcc->init_proc = init_proc_603E;
4787 pcc->check_pow = check_pow_hid0;
4788 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4789 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4790 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4791 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4792 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4793 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4794 PPC_SEGMENT | PPC_EXTERN;
4795 pcc->msr_mask = (1ull << MSR_POW) |
4796 (1ull << MSR_TGPR) |
4797 (1ull << MSR_ILE) |
4798 (1ull << MSR_EE) |
4799 (1ull << MSR_PR) |
4800 (1ull << MSR_FP) |
4801 (1ull << MSR_ME) |
4802 (1ull << MSR_FE0) |
4803 (1ull << MSR_SE) |
4804 (1ull << MSR_DE) |
4805 (1ull << MSR_FE1) |
4806 (1ull << MSR_EP) |
4807 (1ull << MSR_IR) |
4808 (1ull << MSR_DR) |
4809 (1ull << MSR_RI) |
4810 (1ull << MSR_LE);
4811 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4812 pcc->excp_model = POWERPC_EXCP_603E;
4813 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4814 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4815 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4816 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4817 }
4818
4819 static void init_proc_604(CPUPPCState *env)
4820 {
4821 register_ne_601_sprs(env);
4822 register_sdr1_sprs(env);
4823 register_604_sprs(env);
4824 /* Time base */
4825 register_tbl(env);
4826 /* Hardware implementation registers */
4827 /* XXX : not implemented */
4828 spr_register(env, SPR_HID0, "HID0",
4829 SPR_NOACCESS, SPR_NOACCESS,
4830 &spr_read_generic, &spr_write_generic,
4831 0x00000000);
4832 /* Memory management */
4833 register_low_BATs(env);
4834 init_excp_604(env);
4835 env->dcache_line_size = 32;
4836 env->icache_line_size = 32;
4837 /* Allocate hardware IRQ controller */
4838 ppc6xx_irq_init(env_archcpu(env));
4839 }
4840
4841 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
4842 {
4843 DeviceClass *dc = DEVICE_CLASS(oc);
4844 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4845
4846 dc->desc = "PowerPC 604";
4847 pcc->init_proc = init_proc_604;
4848 pcc->check_pow = check_pow_nocheck;
4849 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4850 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4851 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4852 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4853 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4854 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4855 PPC_SEGMENT | PPC_EXTERN;
4856 pcc->msr_mask = (1ull << MSR_POW) |
4857 (1ull << MSR_ILE) |
4858 (1ull << MSR_EE) |
4859 (1ull << MSR_PR) |
4860 (1ull << MSR_FP) |
4861 (1ull << MSR_ME) |
4862 (1ull << MSR_FE0) |
4863 (1ull << MSR_SE) |
4864 (1ull << MSR_DE) |
4865 (1ull << MSR_FE1) |
4866 (1ull << MSR_EP) |
4867 (1ull << MSR_IR) |
4868 (1ull << MSR_DR) |
4869 (1ull << MSR_PMM) |
4870 (1ull << MSR_RI) |
4871 (1ull << MSR_LE);
4872 pcc->mmu_model = POWERPC_MMU_32B;
4873 pcc->excp_model = POWERPC_EXCP_604;
4874 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4875 pcc->bfd_mach = bfd_mach_ppc_604;
4876 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4877 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4878 }
4879
4880 static void init_proc_604E(CPUPPCState *env)
4881 {
4882 register_ne_601_sprs(env);
4883 register_sdr1_sprs(env);
4884 register_604_sprs(env);
4885 /* XXX : not implemented */
4886 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
4887 SPR_NOACCESS, SPR_NOACCESS,
4888 &spr_read_generic, &spr_write_generic,
4889 0x00000000);
4890 /* XXX : not implemented */
4891 spr_register(env, SPR_7XX_PMC3, "PMC3",
4892 SPR_NOACCESS, SPR_NOACCESS,
4893 &spr_read_generic, &spr_write_generic,
4894 0x00000000);
4895 /* XXX : not implemented */
4896 spr_register(env, SPR_7XX_PMC4, "PMC4",
4897 SPR_NOACCESS, SPR_NOACCESS,
4898 &spr_read_generic, &spr_write_generic,
4899 0x00000000);
4900 /* Time base */
4901 register_tbl(env);
4902 /* Hardware implementation registers */
4903 /* XXX : not implemented */
4904 spr_register(env, SPR_HID0, "HID0",
4905 SPR_NOACCESS, SPR_NOACCESS,
4906 &spr_read_generic, &spr_write_generic,
4907 0x00000000);
4908 /* XXX : not implemented */
4909 spr_register(env, SPR_HID1, "HID1",
4910 SPR_NOACCESS, SPR_NOACCESS,
4911 &spr_read_generic, &spr_write_generic,
4912 0x00000000);
4913 /* Memory management */
4914 register_low_BATs(env);
4915 init_excp_604(env);
4916 env->dcache_line_size = 32;
4917 env->icache_line_size = 32;
4918 /* Allocate hardware IRQ controller */
4919 ppc6xx_irq_init(env_archcpu(env));
4920 }
4921
4922 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
4923 {
4924 DeviceClass *dc = DEVICE_CLASS(oc);
4925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4926
4927 dc->desc = "PowerPC 604E";
4928 pcc->init_proc = init_proc_604E;
4929 pcc->check_pow = check_pow_nocheck;
4930 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4931 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4932 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4933 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4934 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4935 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4936 PPC_SEGMENT | PPC_EXTERN;
4937 pcc->msr_mask = (1ull << MSR_POW) |
4938 (1ull << MSR_ILE) |
4939 (1ull << MSR_EE) |
4940 (1ull << MSR_PR) |
4941 (1ull << MSR_FP) |
4942 (1ull << MSR_ME) |
4943 (1ull << MSR_FE0) |
4944 (1ull << MSR_SE) |
4945 (1ull << MSR_DE) |
4946 (1ull << MSR_FE1) |
4947 (1ull << MSR_EP) |
4948 (1ull << MSR_IR) |
4949 (1ull << MSR_DR) |
4950 (1ull << MSR_PMM) |
4951 (1ull << MSR_RI) |
4952 (1ull << MSR_LE);
4953 pcc->mmu_model = POWERPC_MMU_32B;
4954 pcc->excp_model = POWERPC_EXCP_604;
4955 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4956 pcc->bfd_mach = bfd_mach_ppc_604;
4957 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4958 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4959 }
4960
4961 static void init_proc_740(CPUPPCState *env)
4962 {
4963 register_ne_601_sprs(env);
4964 register_sdr1_sprs(env);
4965 register_7xx_sprs(env);
4966 /* Time base */
4967 register_tbl(env);
4968 /* Thermal management */
4969 register_thrm_sprs(env);
4970 /* Hardware implementation registers */
4971 /* XXX : not implemented */
4972 spr_register(env, SPR_HID0, "HID0",
4973 SPR_NOACCESS, SPR_NOACCESS,
4974 &spr_read_generic, &spr_write_generic,
4975 0x00000000);
4976 /* XXX : not implemented */
4977 spr_register(env, SPR_HID1, "HID1",
4978 SPR_NOACCESS, SPR_NOACCESS,
4979 &spr_read_generic, &spr_write_generic,
4980 0x00000000);
4981 /* Memory management */
4982 register_low_BATs(env);
4983 init_excp_7x0(env);
4984 env->dcache_line_size = 32;
4985 env->icache_line_size = 32;
4986 /* Allocate hardware IRQ controller */
4987 ppc6xx_irq_init(env_archcpu(env));
4988 }
4989
4990 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
4991 {
4992 DeviceClass *dc = DEVICE_CLASS(oc);
4993 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4994
4995 dc->desc = "PowerPC 740";
4996 pcc->init_proc = init_proc_740;
4997 pcc->check_pow = check_pow_hid0;
4998 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4999 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5000 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5001 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5002 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5003 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5004 PPC_SEGMENT | PPC_EXTERN;
5005 pcc->msr_mask = (1ull << MSR_POW) |
5006 (1ull << MSR_ILE) |
5007 (1ull << MSR_EE) |
5008 (1ull << MSR_PR) |
5009 (1ull << MSR_FP) |
5010 (1ull << MSR_ME) |
5011 (1ull << MSR_FE0) |
5012 (1ull << MSR_SE) |
5013 (1ull << MSR_DE) |
5014 (1ull << MSR_FE1) |
5015 (1ull << MSR_EP) |
5016 (1ull << MSR_IR) |
5017 (1ull << MSR_DR) |
5018 (1ull << MSR_PMM) |
5019 (1ull << MSR_RI) |
5020 (1ull << MSR_LE);
5021 pcc->mmu_model = POWERPC_MMU_32B;
5022 pcc->excp_model = POWERPC_EXCP_7x0;
5023 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5024 pcc->bfd_mach = bfd_mach_ppc_750;
5025 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5026 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5027 }
5028
5029 static void init_proc_750(CPUPPCState *env)
5030 {
5031 register_ne_601_sprs(env);
5032 register_sdr1_sprs(env);
5033 register_7xx_sprs(env);
5034 /* XXX : not implemented */
5035 spr_register(env, SPR_L2CR, "L2CR",
5036 SPR_NOACCESS, SPR_NOACCESS,
5037 &spr_read_generic, spr_access_nop,
5038 0x00000000);
5039 /* Time base */
5040 register_tbl(env);
5041 /* Thermal management */
5042 register_thrm_sprs(env);
5043 /* Hardware implementation registers */
5044 /* XXX : not implemented */
5045 spr_register(env, SPR_HID0, "HID0",
5046 SPR_NOACCESS, SPR_NOACCESS,
5047 &spr_read_generic, &spr_write_generic,
5048 0x00000000);
5049 /* XXX : not implemented */
5050 spr_register(env, SPR_HID1, "HID1",
5051 SPR_NOACCESS, SPR_NOACCESS,
5052 &spr_read_generic, &spr_write_generic,
5053 0x00000000);
5054 /* Memory management */
5055 register_low_BATs(env);
5056 /*
5057 * XXX: high BATs are also present but are known to be bugged on
5058 * die version 1.x
5059 */
5060 init_excp_7x0(env);
5061 env->dcache_line_size = 32;
5062 env->icache_line_size = 32;
5063 /* Allocate hardware IRQ controller */
5064 ppc6xx_irq_init(env_archcpu(env));
5065 }
5066
5067 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5068 {
5069 DeviceClass *dc = DEVICE_CLASS(oc);
5070 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5071
5072 dc->desc = "PowerPC 750";
5073 pcc->init_proc = init_proc_750;
5074 pcc->check_pow = check_pow_hid0;
5075 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5077 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5078 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5079 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5080 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5081 PPC_SEGMENT | PPC_EXTERN;
5082 pcc->msr_mask = (1ull << MSR_POW) |
5083 (1ull << MSR_ILE) |
5084 (1ull << MSR_EE) |
5085 (1ull << MSR_PR) |
5086 (1ull << MSR_FP) |
5087 (1ull << MSR_ME) |
5088 (1ull << MSR_FE0) |
5089 (1ull << MSR_SE) |
5090 (1ull << MSR_DE) |
5091 (1ull << MSR_FE1) |
5092 (1ull << MSR_EP) |
5093 (1ull << MSR_IR) |
5094 (1ull << MSR_DR) |
5095 (1ull << MSR_PMM) |
5096 (1ull << MSR_RI) |
5097 (1ull << MSR_LE);
5098 pcc->mmu_model = POWERPC_MMU_32B;
5099 pcc->excp_model = POWERPC_EXCP_7x0;
5100 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5101 pcc->bfd_mach = bfd_mach_ppc_750;
5102 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5103 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5104 }
5105
5106 static void init_proc_750cl(CPUPPCState *env)
5107 {
5108 register_ne_601_sprs(env);
5109 register_sdr1_sprs(env);
5110 register_7xx_sprs(env);
5111 /* XXX : not implemented */
5112 spr_register(env, SPR_L2CR, "L2CR",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, spr_access_nop,
5115 0x00000000);
5116 /* Time base */
5117 register_tbl(env);
5118 /* Thermal management */
5119 /* Those registers are fake on 750CL */
5120 spr_register(env, SPR_THRM1, "THRM1",
5121 SPR_NOACCESS, SPR_NOACCESS,
5122 &spr_read_generic, &spr_write_generic,
5123 0x00000000);
5124 spr_register(env, SPR_THRM2, "THRM2",
5125 SPR_NOACCESS, SPR_NOACCESS,
5126 &spr_read_generic, &spr_write_generic,
5127 0x00000000);
5128 spr_register(env, SPR_THRM3, "THRM3",
5129 SPR_NOACCESS, SPR_NOACCESS,
5130 &spr_read_generic, &spr_write_generic,
5131 0x00000000);
5132 /* XXX: not implemented */
5133 spr_register(env, SPR_750_TDCL, "TDCL",
5134 SPR_NOACCESS, SPR_NOACCESS,
5135 &spr_read_generic, &spr_write_generic,
5136 0x00000000);
5137 spr_register(env, SPR_750_TDCH, "TDCH",
5138 SPR_NOACCESS, SPR_NOACCESS,
5139 &spr_read_generic, &spr_write_generic,
5140 0x00000000);
5141 /* DMA */
5142 /* XXX : not implemented */
5143 spr_register(env, SPR_750_WPAR, "WPAR",
5144 SPR_NOACCESS, SPR_NOACCESS,
5145 &spr_read_generic, &spr_write_generic,
5146 0x00000000);
5147 spr_register(env, SPR_750_DMAL, "DMAL",
5148 SPR_NOACCESS, SPR_NOACCESS,
5149 &spr_read_generic, &spr_write_generic,
5150 0x00000000);
5151 spr_register(env, SPR_750_DMAU, "DMAU",
5152 SPR_NOACCESS, SPR_NOACCESS,
5153 &spr_read_generic, &spr_write_generic,
5154 0x00000000);
5155 /* Hardware implementation registers */
5156 /* XXX : not implemented */
5157 spr_register(env, SPR_HID0, "HID0",
5158 SPR_NOACCESS, SPR_NOACCESS,
5159 &spr_read_generic, &spr_write_generic,
5160 0x00000000);
5161 /* XXX : not implemented */
5162 spr_register(env, SPR_HID1, "HID1",
5163 SPR_NOACCESS, SPR_NOACCESS,
5164 &spr_read_generic, &spr_write_generic,
5165 0x00000000);
5166 /* XXX : not implemented */
5167 spr_register(env, SPR_750CL_HID2, "HID2",
5168 SPR_NOACCESS, SPR_NOACCESS,
5169 &spr_read_generic, &spr_write_generic,
5170 0x00000000);
5171 /* XXX : not implemented */
5172 spr_register(env, SPR_750CL_HID4, "HID4",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_generic, &spr_write_generic,
5175 0x00000000);
5176 /* Quantization registers */
5177 /* XXX : not implemented */
5178 spr_register(env, SPR_750_GQR0, "GQR0",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 /* XXX : not implemented */
5183 spr_register(env, SPR_750_GQR1, "GQR1",
5184 SPR_NOACCESS, SPR_NOACCESS,
5185 &spr_read_generic, &spr_write_generic,
5186 0x00000000);
5187 /* XXX : not implemented */
5188 spr_register(env, SPR_750_GQR2, "GQR2",
5189 SPR_NOACCESS, SPR_NOACCESS,
5190 &spr_read_generic, &spr_write_generic,
5191 0x00000000);
5192 /* XXX : not implemented */
5193 spr_register(env, SPR_750_GQR3, "GQR3",
5194 SPR_NOACCESS, SPR_NOACCESS,
5195 &spr_read_generic, &spr_write_generic,
5196 0x00000000);
5197 /* XXX : not implemented */
5198 spr_register(env, SPR_750_GQR4, "GQR4",
5199 SPR_NOACCESS, SPR_NOACCESS,
5200 &spr_read_generic, &spr_write_generic,
5201 0x00000000);
5202 /* XXX : not implemented */
5203 spr_register(env, SPR_750_GQR5, "GQR5",
5204 SPR_NOACCESS, SPR_NOACCESS,
5205 &spr_read_generic, &spr_write_generic,
5206 0x00000000);
5207 /* XXX : not implemented */
5208 spr_register(env, SPR_750_GQR6, "GQR6",
5209 SPR_NOACCESS, SPR_NOACCESS,
5210 &spr_read_generic, &spr_write_generic,
5211 0x00000000);
5212 /* XXX : not implemented */
5213 spr_register(env, SPR_750_GQR7, "GQR7",
5214 SPR_NOACCESS, SPR_NOACCESS,
5215 &spr_read_generic, &spr_write_generic,
5216 0x00000000);
5217 /* Memory management */
5218 register_low_BATs(env);
5219 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5220 register_high_BATs(env);
5221 init_excp_750cl(env);
5222 env->dcache_line_size = 32;
5223 env->icache_line_size = 32;
5224 /* Allocate hardware IRQ controller */
5225 ppc6xx_irq_init(env_archcpu(env));
5226 }
5227
5228 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5229 {
5230 DeviceClass *dc = DEVICE_CLASS(oc);
5231 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5232
5233 dc->desc = "PowerPC 750 CL";
5234 pcc->init_proc = init_proc_750cl;
5235 pcc->check_pow = check_pow_hid0;
5236 /*
5237 * XXX: not implemented:
5238 * cache lock instructions:
5239 * dcbz_l
5240 * floating point paired instructions
5241 * psq_lux
5242 * psq_lx
5243 * psq_stux
5244 * psq_stx
5245 * ps_abs
5246 * ps_add
5247 * ps_cmpo0
5248 * ps_cmpo1
5249 * ps_cmpu0
5250 * ps_cmpu1
5251 * ps_div
5252 * ps_madd
5253 * ps_madds0
5254 * ps_madds1
5255 * ps_merge00
5256 * ps_merge01
5257 * ps_merge10
5258 * ps_merge11
5259 * ps_mr
5260 * ps_msub
5261 * ps_mul
5262 * ps_muls0
5263 * ps_muls1
5264 * ps_nabs
5265 * ps_neg
5266 * ps_nmadd
5267 * ps_nmsub
5268 * ps_res
5269 * ps_rsqrte
5270 * ps_sel
5271 * ps_sub
5272 * ps_sum0
5273 * ps_sum1
5274 */
5275 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5276 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5277 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5278 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5279 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5280 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5281 PPC_SEGMENT | PPC_EXTERN;
5282 pcc->msr_mask = (1ull << MSR_POW) |
5283 (1ull << MSR_ILE) |
5284 (1ull << MSR_EE) |
5285 (1ull << MSR_PR) |
5286 (1ull << MSR_FP) |
5287 (1ull << MSR_ME) |
5288 (1ull << MSR_FE0) |
5289 (1ull << MSR_SE) |
5290 (1ull << MSR_DE) |
5291 (1ull << MSR_FE1) |
5292 (1ull << MSR_EP) |
5293 (1ull << MSR_IR) |
5294 (1ull << MSR_DR) |
5295 (1ull << MSR_PMM) |
5296 (1ull << MSR_RI) |
5297 (1ull << MSR_LE);
5298 pcc->mmu_model = POWERPC_MMU_32B;
5299 pcc->excp_model = POWERPC_EXCP_7x0;
5300 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5301 pcc->bfd_mach = bfd_mach_ppc_750;
5302 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5303 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5304 }
5305
5306 static void init_proc_750cx(CPUPPCState *env)
5307 {
5308 register_ne_601_sprs(env);
5309 register_sdr1_sprs(env);
5310 register_7xx_sprs(env);
5311 /* XXX : not implemented */
5312 spr_register(env, SPR_L2CR, "L2CR",
5313 SPR_NOACCESS, SPR_NOACCESS,
5314 &spr_read_generic, spr_access_nop,
5315 0x00000000);
5316 /* Time base */
5317 register_tbl(env);
5318 /* Thermal management */
5319 register_thrm_sprs(env);
5320 /* This register is not implemented but is present for compatibility */
5321 spr_register(env, SPR_SDA, "SDA",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic,
5324 0x00000000);
5325 /* Hardware implementation registers */
5326 /* XXX : not implemented */
5327 spr_register(env, SPR_HID0, "HID0",
5328 SPR_NOACCESS, SPR_NOACCESS,
5329 &spr_read_generic, &spr_write_generic,
5330 0x00000000);
5331 /* XXX : not implemented */
5332 spr_register(env, SPR_HID1, "HID1",
5333 SPR_NOACCESS, SPR_NOACCESS,
5334 &spr_read_generic, &spr_write_generic,
5335 0x00000000);
5336 /* Memory management */
5337 register_low_BATs(env);
5338 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5339 register_high_BATs(env);
5340 init_excp_750cx(env);
5341 env->dcache_line_size = 32;
5342 env->icache_line_size = 32;
5343 /* Allocate hardware IRQ controller */
5344 ppc6xx_irq_init(env_archcpu(env));
5345 }
5346
5347 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5348 {
5349 DeviceClass *dc = DEVICE_CLASS(oc);
5350 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5351
5352 dc->desc = "PowerPC 750CX";
5353 pcc->init_proc = init_proc_750cx;
5354 pcc->check_pow = check_pow_hid0;
5355 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5356 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5357 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5358 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5359 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5360 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5361 PPC_SEGMENT | PPC_EXTERN;
5362 pcc->msr_mask = (1ull << MSR_POW) |
5363 (1ull << MSR_ILE) |
5364 (1ull << MSR_EE) |
5365 (1ull << MSR_PR) |
5366 (1ull << MSR_FP) |
5367 (1ull << MSR_ME) |
5368 (1ull << MSR_FE0) |
5369 (1ull << MSR_SE) |
5370 (1ull << MSR_DE) |
5371 (1ull << MSR_FE1) |
5372 (1ull << MSR_EP) |
5373 (1ull << MSR_IR) |
5374 (1ull << MSR_DR) |
5375 (1ull << MSR_PMM) |
5376 (1ull << MSR_RI) |
5377 (1ull << MSR_LE);
5378 pcc->mmu_model = POWERPC_MMU_32B;
5379 pcc->excp_model = POWERPC_EXCP_7x0;
5380 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5381 pcc->bfd_mach = bfd_mach_ppc_750;
5382 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5383 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5384 }
5385
5386 static void init_proc_750fx(CPUPPCState *env)
5387 {
5388 register_ne_601_sprs(env);
5389 register_sdr1_sprs(env);
5390 register_7xx_sprs(env);
5391 /* XXX : not implemented */
5392 spr_register(env, SPR_L2CR, "L2CR",
5393 SPR_NOACCESS, SPR_NOACCESS,
5394 &spr_read_generic, spr_access_nop,
5395 0x00000000);
5396 /* Time base */
5397 register_tbl(env);
5398 /* Thermal management */
5399 register_thrm_sprs(env);
5400 /* XXX : not implemented */
5401 spr_register(env, SPR_750_THRM4, "THRM4",
5402 SPR_NOACCESS, SPR_NOACCESS,
5403 &spr_read_generic, &spr_write_generic,
5404 0x00000000);
5405 /* Hardware implementation registers */
5406 /* XXX : not implemented */
5407 spr_register(env, SPR_HID0, "HID0",
5408 SPR_NOACCESS, SPR_NOACCESS,
5409 &spr_read_generic, &spr_write_generic,
5410 0x00000000);
5411 /* XXX : not implemented */
5412 spr_register(env, SPR_HID1, "HID1",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 &spr_read_generic, &spr_write_generic,
5415 0x00000000);
5416 /* XXX : not implemented */
5417 spr_register(env, SPR_750FX_HID2, "HID2",
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 &spr_read_generic, &spr_write_generic,
5420 0x00000000);
5421 /* Memory management */
5422 register_low_BATs(env);
5423 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5424 register_high_BATs(env);
5425 init_excp_7x0(env);
5426 env->dcache_line_size = 32;
5427 env->icache_line_size = 32;
5428 /* Allocate hardware IRQ controller */
5429 ppc6xx_irq_init(env_archcpu(env));
5430 }
5431
5432 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5433 {
5434 DeviceClass *dc = DEVICE_CLASS(oc);
5435 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5436
5437 dc->desc = "PowerPC 750FX";
5438 pcc->init_proc = init_proc_750fx;
5439 pcc->check_pow = check_pow_hid0;
5440 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5441 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5442 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5443 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5444 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5445 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5446 PPC_SEGMENT | PPC_EXTERN;
5447 pcc->msr_mask = (1ull << MSR_POW) |
5448 (1ull << MSR_ILE) |
5449 (1ull << MSR_EE) |
5450 (1ull << MSR_PR) |
5451 (1ull << MSR_FP) |
5452 (1ull << MSR_ME) |
5453 (1ull << MSR_FE0) |
5454 (1ull << MSR_SE) |
5455 (1ull << MSR_DE) |
5456 (1ull << MSR_FE1) |
5457 (1ull << MSR_EP) |
5458 (1ull << MSR_IR) |
5459 (1ull << MSR_DR) |
5460 (1ull << MSR_PMM) |
5461 (1ull << MSR_RI) |
5462 (1ull << MSR_LE);
5463 pcc->mmu_model = POWERPC_MMU_32B;
5464 pcc->excp_model = POWERPC_EXCP_7x0;
5465 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5466 pcc->bfd_mach = bfd_mach_ppc_750;
5467 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5468 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5469 }
5470
5471 static void init_proc_750gx(CPUPPCState *env)
5472 {
5473 register_ne_601_sprs(env);
5474 register_sdr1_sprs(env);
5475 register_7xx_sprs(env);
5476 /* XXX : not implemented (XXX: different from 750fx) */
5477 spr_register(env, SPR_L2CR, "L2CR",
5478 SPR_NOACCESS, SPR_NOACCESS,
5479 &spr_read_generic, spr_access_nop,
5480 0x00000000);
5481 /* Time base */
5482 register_tbl(env);
5483 /* Thermal management */
5484 register_thrm_sprs(env);
5485 /* XXX : not implemented */
5486 spr_register(env, SPR_750_THRM4, "THRM4",
5487 SPR_NOACCESS, SPR_NOACCESS,
5488 &spr_read_generic, &spr_write_generic,
5489 0x00000000);
5490 /* Hardware implementation registers */
5491 /* XXX : not implemented (XXX: different from 750fx) */
5492 spr_register(env, SPR_HID0, "HID0",
5493 SPR_NOACCESS, SPR_NOACCESS,
5494 &spr_read_generic, &spr_write_generic,
5495 0x00000000);
5496 /* XXX : not implemented */
5497 spr_register(env, SPR_HID1, "HID1",
5498 SPR_NOACCESS, SPR_NOACCESS,
5499 &spr_read_generic, &spr_write_generic,
5500 0x00000000);
5501 /* XXX : not implemented (XXX: different from 750fx) */
5502 spr_register(env, SPR_750FX_HID2, "HID2",
5503 SPR_NOACCESS, SPR_NOACCESS,
5504 &spr_read_generic, &spr_write_generic,
5505 0x00000000);
5506 /* Memory management */
5507 register_low_BATs(env);
5508 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5509 register_high_BATs(env);
5510 init_excp_7x0(env);
5511 env->dcache_line_size = 32;
5512 env->icache_line_size = 32;
5513 /* Allocate hardware IRQ controller */
5514 ppc6xx_irq_init(env_archcpu(env));
5515 }
5516
5517 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5518 {
5519 DeviceClass *dc = DEVICE_CLASS(oc);
5520 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5521
5522 dc->desc = "PowerPC 750GX";
5523 pcc->init_proc = init_proc_750gx;
5524 pcc->check_pow = check_pow_hid0;
5525 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5526 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5527 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5528 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5529 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5530 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5531 PPC_SEGMENT | PPC_EXTERN;
5532 pcc->msr_mask = (1ull << MSR_POW) |
5533 (1ull << MSR_ILE) |
5534 (1ull << MSR_EE) |
5535 (1ull << MSR_PR) |
5536 (1ull << MSR_FP) |
5537 (1ull << MSR_ME) |
5538 (1ull << MSR_FE0) |
5539 (1ull << MSR_SE) |
5540 (1ull << MSR_DE) |
5541 (1ull << MSR_FE1) |
5542 (1ull << MSR_EP) |
5543 (1ull << MSR_IR) |
5544 (1ull << MSR_DR) |
5545 (1ull << MSR_PMM) |
5546 (1ull << MSR_RI) |
5547 (1ull << MSR_LE);
5548 pcc->mmu_model = POWERPC_MMU_32B;
5549 pcc->excp_model = POWERPC_EXCP_7x0;
5550 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5551 pcc->bfd_mach = bfd_mach_ppc_750;
5552 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5553 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5554 }
5555
5556 static void init_proc_745(CPUPPCState *env)
5557 {
5558 register_ne_601_sprs(env);
5559 register_sdr1_sprs(env);
5560 register_7xx_sprs(env);
5561 register_G2_755_sprs(env);
5562 /* Time base */
5563 register_tbl(env);
5564 /* Thermal management */
5565 register_thrm_sprs(env);
5566 /* Hardware implementation registers */
5567 /* XXX : not implemented */
5568 spr_register(env, SPR_HID0, "HID0",
5569 SPR_NOACCESS, SPR_NOACCESS,
5570 &spr_read_generic, &spr_write_generic,
5571 0x00000000);
5572 /* XXX : not implemented */
5573 spr_register(env, SPR_HID1, "HID1",
5574 SPR_NOACCESS, SPR_NOACCESS,
5575 &spr_read_generic, &spr_write_generic,
5576 0x00000000);
5577 /* XXX : not implemented */
5578 spr_register(env, SPR_HID2, "HID2",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
5582 /* Memory management */
5583 register_low_BATs(env);
5584 register_high_BATs(env);
5585 register_6xx_7xx_soft_tlb(env, 64, 2);
5586 init_excp_7x5(env);
5587 env->dcache_line_size = 32;
5588 env->icache_line_size = 32;
5589 /* Allocate hardware IRQ controller */
5590 ppc6xx_irq_init(env_archcpu(env));
5591 }
5592
5593 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5594 {
5595 DeviceClass *dc = DEVICE_CLASS(oc);
5596 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5597
5598 dc->desc = "PowerPC 745";
5599 pcc->init_proc = init_proc_745;
5600 pcc->check_pow = check_pow_hid0;
5601 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5602 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5603 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5604 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5605 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5606 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5607 PPC_SEGMENT | PPC_EXTERN;
5608 pcc->msr_mask = (1ull << MSR_POW) |
5609 (1ull << MSR_ILE) |
5610 (1ull << MSR_EE) |
5611 (1ull << MSR_PR) |
5612 (1ull << MSR_FP) |
5613 (1ull << MSR_ME) |
5614 (1ull << MSR_FE0) |
5615 (1ull << MSR_SE) |
5616 (1ull << MSR_DE) |
5617 (1ull << MSR_FE1) |
5618 (1ull << MSR_EP) |
5619 (1ull << MSR_IR) |
5620 (1ull << MSR_DR) |
5621 (1ull << MSR_PMM) |
5622 (1ull << MSR_RI) |
5623 (1ull << MSR_LE);
5624 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5625 pcc->excp_model = POWERPC_EXCP_7x5;
5626 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5627 pcc->bfd_mach = bfd_mach_ppc_750;
5628 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5629 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5630 }
5631
5632 static void init_proc_755(CPUPPCState *env)
5633 {
5634 register_ne_601_sprs(env);
5635 register_sdr1_sprs(env);
5636 register_7xx_sprs(env);
5637 register_G2_755_sprs(env);
5638 /* Time base */
5639 register_tbl(env);
5640 /* L2 cache control */
5641 /* XXX : not implemented */
5642 spr_register(env, SPR_L2CR, "L2CR",
5643 SPR_NOACCESS, SPR_NOACCESS,
5644 &spr_read_generic, spr_access_nop,
5645 0x00000000);
5646 /* XXX : not implemented */
5647 spr_register(env, SPR_L2PMCR, "L2PMCR",
5648 SPR_NOACCESS, SPR_NOACCESS,
5649 &spr_read_generic, &spr_write_generic,
5650 0x00000000);
5651 /* Thermal management */
5652 register_thrm_sprs(env);
5653 /* Hardware implementation registers */
5654 /* XXX : not implemented */
5655 spr_register(env, SPR_HID0, "HID0",
5656 SPR_NOACCESS, SPR_NOACCESS,
5657 &spr_read_generic, &spr_write_generic,
5658 0x00000000);
5659 /* XXX : not implemented */
5660 spr_register(env, SPR_HID1, "HID1",
5661 SPR_NOACCESS, SPR_NOACCESS,
5662 &spr_read_generic, &spr_write_generic,
5663 0x00000000);
5664 /* XXX : not implemented */
5665 spr_register(env, SPR_HID2, "HID2",
5666 SPR_NOACCESS, SPR_NOACCESS,
5667 &spr_read_generic, &spr_write_generic,
5668 0x00000000);
5669 /* Memory management */
5670 register_low_BATs(env);
5671 register_high_BATs(env);
5672 register_6xx_7xx_soft_tlb(env, 64, 2);
5673 init_excp_7x5(env);
5674 env->dcache_line_size = 32;
5675 env->icache_line_size = 32;
5676 /* Allocate hardware IRQ controller */
5677 ppc6xx_irq_init(env_archcpu(env));
5678 }
5679
5680 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5681 {
5682 DeviceClass *dc = DEVICE_CLASS(oc);
5683 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5684
5685 dc->desc = "PowerPC 755";
5686 pcc->init_proc = init_proc_755;
5687 pcc->check_pow = check_pow_hid0;
5688 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5689 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5690 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5691 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5692 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5693 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5694 PPC_SEGMENT | PPC_EXTERN;
5695 pcc->msr_mask = (1ull << MSR_POW) |
5696 (1ull << MSR_ILE) |
5697 (1ull << MSR_EE) |
5698 (1ull << MSR_PR) |
5699 (1ull << MSR_FP) |
5700 (1ull << MSR_ME) |
5701 (1ull << MSR_FE0) |
5702 (1ull << MSR_SE) |
5703 (1ull << MSR_DE) |
5704 (1ull << MSR_FE1) |
5705 (1ull << MSR_EP) |
5706 (1ull << MSR_IR) |
5707 (1ull << MSR_DR) |
5708 (1ull << MSR_PMM) |
5709 (1ull << MSR_RI) |
5710 (1ull << MSR_LE);
5711 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5712 pcc->excp_model = POWERPC_EXCP_7x5;
5713 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5714 pcc->bfd_mach = bfd_mach_ppc_750;
5715 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5716 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5717 }
5718
5719 static void init_proc_7400(CPUPPCState *env)
5720 {
5721 register_ne_601_sprs(env);
5722 register_sdr1_sprs(env);
5723 register_7xx_sprs(env);
5724 /* Time base */
5725 register_tbl(env);
5726 /* 74xx specific SPR */
5727 register_74xx_sprs(env);
5728 vscr_init(env, 0x00010000);
5729 /* XXX : not implemented */
5730 spr_register(env, SPR_UBAMR, "UBAMR",
5731 &spr_read_ureg, SPR_NOACCESS,
5732 &spr_read_ureg, SPR_NOACCESS,
5733 0x00000000);
5734 /* XXX: this seems not implemented on all revisions. */
5735 /* XXX : not implemented */
5736 spr_register(env, SPR_MSSCR1, "MSSCR1",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_read_generic, &spr_write_generic,
5739 0x00000000);
5740 /* Thermal management */
5741 register_thrm_sprs(env);
5742 /* Memory management */
5743 register_low_BATs(env);
5744 init_excp_7400(env);
5745 env->dcache_line_size = 32;
5746 env->icache_line_size = 32;
5747 /* Allocate hardware IRQ controller */
5748 ppc6xx_irq_init(env_archcpu(env));
5749 }
5750
5751 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5752 {
5753 DeviceClass *dc = DEVICE_CLASS(oc);
5754 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5755
5756 dc->desc = "PowerPC 7400 (aka G4)";
5757 pcc->init_proc = init_proc_7400;
5758 pcc->check_pow = check_pow_hid0;
5759 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5760 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5761 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5762 PPC_FLOAT_STFIWX |
5763 PPC_CACHE | PPC_CACHE_ICBI |
5764 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5765 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5766 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5767 PPC_MEM_TLBIA |
5768 PPC_SEGMENT | PPC_EXTERN |
5769 PPC_ALTIVEC;
5770 pcc->msr_mask = (1ull << MSR_VR) |
5771 (1ull << MSR_POW) |
5772 (1ull << MSR_ILE) |
5773 (1ull << MSR_EE) |
5774 (1ull << MSR_PR) |
5775 (1ull << MSR_FP) |
5776 (1ull << MSR_ME) |
5777 (1ull << MSR_FE0) |
5778 (1ull << MSR_SE) |
5779 (1ull << MSR_DE) |
5780 (1ull << MSR_FE1) |
5781 (1ull << MSR_EP) |
5782 (1ull << MSR_IR) |
5783 (1ull << MSR_DR) |
5784 (1ull << MSR_PMM) |
5785 (1ull << MSR_RI) |
5786 (1ull << MSR_LE);
5787 pcc->mmu_model = POWERPC_MMU_32B;
5788 pcc->excp_model = POWERPC_EXCP_74xx;
5789 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5790 pcc->bfd_mach = bfd_mach_ppc_7400;
5791 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5792 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5793 POWERPC_FLAG_BUS_CLK;
5794 }
5795
5796 static void init_proc_7410(CPUPPCState *env)
5797 {
5798 register_ne_601_sprs(env);
5799 register_sdr1_sprs(env);
5800 register_7xx_sprs(env);
5801 /* Time base */
5802 register_tbl(env);
5803 /* 74xx specific SPR */
5804 register_74xx_sprs(env);
5805 vscr_init(env, 0x00010000);
5806 /* XXX : not implemented */
5807 spr_register(env, SPR_UBAMR, "UBAMR",
5808 &spr_read_ureg, SPR_NOACCESS,
5809 &spr_read_ureg, SPR_NOACCESS,
5810 0x00000000);
5811 /* Thermal management */
5812 register_thrm_sprs(env);
5813 /* L2PMCR */
5814 /* XXX : not implemented */
5815 spr_register(env, SPR_L2PMCR, "L2PMCR",
5816 SPR_NOACCESS, SPR_NOACCESS,
5817 &spr_read_generic, &spr_write_generic,
5818 0x00000000);
5819 /* LDSTDB */
5820 /* XXX : not implemented */
5821 spr_register(env, SPR_LDSTDB, "LDSTDB",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, &spr_write_generic,
5824 0x00000000);
5825 /* Memory management */
5826 register_low_BATs(env);
5827 init_excp_7400(env);
5828 env->dcache_line_size = 32;
5829 env->icache_line_size = 32;
5830 /* Allocate hardware IRQ controller */
5831 ppc6xx_irq_init(env_archcpu(env));
5832 }
5833
5834 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5835 {
5836 DeviceClass *dc = DEVICE_CLASS(oc);
5837 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5838
5839 dc->desc = "PowerPC 7410 (aka G4)";
5840 pcc->init_proc = init_proc_7410;
5841 pcc->check_pow = check_pow_hid0;
5842 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5843 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5844 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5845 PPC_FLOAT_STFIWX |
5846 PPC_CACHE | PPC_CACHE_ICBI |
5847 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5848 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5849 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5850 PPC_MEM_TLBIA |
5851 PPC_SEGMENT | PPC_EXTERN |
5852 PPC_ALTIVEC;
5853 pcc->msr_mask = (1ull << MSR_VR) |
5854 (1ull << MSR_POW) |
5855 (1ull << MSR_ILE) |
5856 (1ull << MSR_EE) |
5857 (1ull << MSR_PR) |
5858 (1ull << MSR_FP) |
5859 (1ull << MSR_ME) |
5860 (1ull << MSR_FE0) |
5861 (1ull << MSR_SE) |
5862 (1ull << MSR_DE) |
5863 (1ull << MSR_FE1) |
5864 (1ull << MSR_EP) |
5865 (1ull << MSR_IR) |
5866 (1ull << MSR_DR) |
5867 (1ull << MSR_PMM) |
5868 (1ull << MSR_RI) |
5869 (1ull << MSR_LE);
5870 pcc->mmu_model = POWERPC_MMU_32B;
5871 pcc->excp_model = POWERPC_EXCP_74xx;
5872 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5873 pcc->bfd_mach = bfd_mach_ppc_7400;
5874 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5875 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5876 POWERPC_FLAG_BUS_CLK;
5877 }
5878
5879 static void init_proc_7440(CPUPPCState *env)
5880 {
5881 register_ne_601_sprs(env);
5882 register_sdr1_sprs(env);
5883 register_7xx_sprs(env);
5884 /* Time base */
5885 register_tbl(env);
5886 /* 74xx specific SPR */
5887 register_74xx_sprs(env);
5888 vscr_init(env, 0x00010000);
5889 /* XXX : not implemented */
5890 spr_register(env, SPR_UBAMR, "UBAMR",
5891 &spr_read_ureg, SPR_NOACCESS,
5892 &spr_read_ureg, SPR_NOACCESS,
5893 0x00000000);
5894 /* LDSTCR */
5895 /* XXX : not implemented */
5896 spr_register(env, SPR_LDSTCR, "LDSTCR",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 /* ICTRL */
5901 /* XXX : not implemented */
5902 spr_register(env, SPR_ICTRL, "ICTRL",
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0x00000000);
5906 /* MSSSR0 */
5907 /* XXX : not implemented */
5908 spr_register(env, SPR_MSSSR0, "MSSSR0",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 &spr_read_generic, &spr_write_generic,
5911 0x00000000);
5912 /* PMC */
5913 /* XXX : not implemented */
5914 spr_register(env, SPR_7XX_PMC5, "PMC5",
5915 SPR_NOACCESS, SPR_NOACCESS,
5916 &spr_read_generic, &spr_write_generic,
5917 0x00000000);
5918 /* XXX : not implemented */
5919 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5920 &spr_read_ureg, SPR_NOACCESS,
5921 &spr_read_ureg, SPR_NOACCESS,
5922 0x00000000);
5923 /* XXX : not implemented */
5924 spr_register(env, SPR_7XX_PMC6, "PMC6",
5925 SPR_NOACCESS, SPR_NOACCESS,
5926 &spr_read_generic, &spr_write_generic,
5927 0x00000000);
5928 /* XXX : not implemented */
5929 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5930 &spr_read_ureg, SPR_NOACCESS,
5931 &spr_read_ureg, SPR_NOACCESS,
5932 0x00000000);
5933 /* Memory management */
5934 register_low_BATs(env);
5935 register_74xx_soft_tlb(env, 128, 2);
5936 init_excp_7450(env);
5937 env->dcache_line_size = 32;
5938 env->icache_line_size = 32;
5939 /* Allocate hardware IRQ controller */
5940 ppc6xx_irq_init(env_archcpu(env));
5941 }
5942
5943 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5944 {
5945 DeviceClass *dc = DEVICE_CLASS(oc);
5946 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5947
5948 dc->desc = "PowerPC 7440 (aka G4)";
5949 pcc->init_proc = init_proc_7440;
5950 pcc->check_pow = check_pow_hid0_74xx;
5951 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5952 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5953 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5954 PPC_FLOAT_STFIWX |
5955 PPC_CACHE | PPC_CACHE_ICBI |
5956 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5957 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5958 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5959 PPC_MEM_TLBIA | PPC_74xx_TLB |
5960 PPC_SEGMENT | PPC_EXTERN |
5961 PPC_ALTIVEC;
5962 pcc->msr_mask = (1ull << MSR_VR) |
5963 (1ull << MSR_POW) |
5964 (1ull << MSR_ILE) |
5965 (1ull << MSR_EE) |
5966 (1ull << MSR_PR) |
5967 (1ull << MSR_FP) |
5968 (1ull << MSR_ME) |
5969 (1ull << MSR_FE0) |
5970 (1ull << MSR_SE) |
5971 (1ull << MSR_DE) |
5972 (1ull << MSR_FE1) |
5973 (1ull << MSR_EP) |
5974 (1ull << MSR_IR) |
5975 (1ull << MSR_DR) |
5976 (1ull << MSR_PMM) |
5977 (1ull << MSR_RI) |
5978 (1ull << MSR_LE);
5979 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
5980 pcc->excp_model = POWERPC_EXCP_74xx;
5981 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5982 pcc->bfd_mach = bfd_mach_ppc_7400;
5983 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5984 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5985 POWERPC_FLAG_BUS_CLK;
5986 }
5987
5988 static void init_proc_7450(CPUPPCState *env)
5989 {
5990 register_ne_601_sprs(env);
5991 register_sdr1_sprs(env);
5992 register_7xx_sprs(env);
5993 /* Time base */
5994 register_tbl(env);
5995 /* 74xx specific SPR */
5996 register_74xx_sprs(env);
5997 vscr_init(env, 0x00010000);
5998 /* Level 3 cache control */
5999 register_l3_ctrl(env);
6000 /* L3ITCR1 */
6001 /* XXX : not implemented */
6002 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6003 SPR_NOACCESS, SPR_NOACCESS,
6004 &spr_read_generic, &spr_write_generic,
6005 0x00000000);
6006 /* L3ITCR2 */
6007 /* XXX : not implemented */
6008 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6009 SPR_NOACCESS, SPR_NOACCESS,
6010 &spr_read_generic, &spr_write_generic,
6011 0x00000000);
6012 /* L3ITCR3 */
6013 /* XXX : not implemented */
6014 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6015 SPR_NOACCESS, SPR_NOACCESS,
6016 &spr_read_generic, &spr_write_generic,
6017 0x00000000);
6018 /* L3OHCR */
6019 /* XXX : not implemented */
6020 spr_register(env, SPR_L3OHCR, "L3OHCR",
6021 SPR_NOACCESS, SPR_NOACCESS,
6022 &spr_read_generic, &spr_write_generic,
6023 0x00000000);
6024 /* XXX : not implemented */
6025 spr_register(env, SPR_UBAMR, "UBAMR",
6026 &spr_read_ureg, SPR_NOACCESS,
6027 &spr_read_ureg, SPR_NOACCESS,
6028 0x00000000);
6029 /* LDSTCR */
6030 /* XXX : not implemented */
6031 spr_register(env, SPR_LDSTCR, "LDSTCR",
6032 SPR_NOACCESS, SPR_NOACCESS,
6033 &spr_read_generic, &spr_write_generic,
6034 0x00000000);
6035 /* ICTRL */
6036 /* XXX : not implemented */
6037 spr_register(env, SPR_ICTRL, "ICTRL",
6038 SPR_NOACCESS, SPR_NOACCESS,
6039 &spr_read_generic, &spr_write_generic,
6040 0x00000000);
6041 /* MSSSR0 */
6042 /* XXX : not implemented */
6043 spr_register(env, SPR_MSSSR0, "MSSSR0",
6044 SPR_NOACCESS, SPR_NOACCESS,
6045 &spr_read_generic, &spr_write_generic,
6046 0x00000000);
6047 /* PMC */
6048 /* XXX : not implemented */
6049 spr_register(env, SPR_7XX_PMC5, "PMC5",
6050 SPR_NOACCESS, SPR_NOACCESS,
6051 &spr_read_generic, &spr_write_generic,
6052 0x00000000);
6053 /* XXX : not implemented */
6054 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6055 &spr_read_ureg, SPR_NOACCESS,
6056 &spr_read_ureg, SPR_NOACCESS,
6057 0x00000000);
6058 /* XXX : not implemented */
6059 spr_register(env, SPR_7XX_PMC6, "PMC6",
6060 SPR_NOACCESS, SPR_NOACCESS,
6061 &spr_read_generic, &spr_write_generic,
6062 0x00000000);
6063 /* XXX : not implemented */
6064 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6065 &spr_read_ureg, SPR_NOACCESS,
6066 &spr_read_ureg, SPR_NOACCESS,
6067 0x00000000);
6068 /* Memory management */
6069 register_low_BATs(env);
6070 register_74xx_soft_tlb(env, 128, 2);
6071 init_excp_7450(env);
6072 env->dcache_line_size = 32;
6073 env->icache_line_size = 32;
6074 /* Allocate hardware IRQ controller */
6075 ppc6xx_irq_init(env_archcpu(env));
6076 }
6077
6078 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6079 {
6080 DeviceClass *dc = DEVICE_CLASS(oc);
6081 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6082
6083 dc->desc = "PowerPC 7450 (aka G4)";
6084 pcc->init_proc = init_proc_7450;
6085 pcc->check_pow = check_pow_hid0_74xx;
6086 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6087 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6088 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6089 PPC_FLOAT_STFIWX |
6090 PPC_CACHE | PPC_CACHE_ICBI |
6091 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6092 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6093 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6094 PPC_MEM_TLBIA | PPC_74xx_TLB |
6095 PPC_SEGMENT | PPC_EXTERN |
6096 PPC_ALTIVEC;
6097 pcc->msr_mask = (1ull << MSR_VR) |
6098 (1ull << MSR_POW) |
6099 (1ull << MSR_ILE) |
6100 (1ull << MSR_EE) |
6101 (1ull << MSR_PR) |
6102 (1ull << MSR_FP) |
6103 (1ull << MSR_ME) |
6104 (1ull << MSR_FE0) |
6105 (1ull << MSR_SE) |
6106 (1ull << MSR_DE) |
6107 (1ull << MSR_FE1) |
6108 (1ull << MSR_EP) |
6109 (1ull << MSR_IR) |
6110 (1ull << MSR_DR) |
6111 (1ull << MSR_PMM) |
6112 (1ull << MSR_RI) |
6113 (1ull << MSR_LE);
6114 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6115 pcc->excp_model = POWERPC_EXCP_74xx;
6116 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6117 pcc->bfd_mach = bfd_mach_ppc_7400;
6118 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6119 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6120 POWERPC_FLAG_BUS_CLK;
6121 }
6122
6123 static void init_proc_7445(CPUPPCState *env)
6124 {
6125 register_ne_601_sprs(env);
6126 register_sdr1_sprs(env);
6127 register_7xx_sprs(env);
6128 /* Time base */
6129 register_tbl(env);
6130 /* 74xx specific SPR */
6131 register_74xx_sprs(env);
6132 vscr_init(env, 0x00010000);
6133 /* LDSTCR */
6134 /* XXX : not implemented */
6135 spr_register(env, SPR_LDSTCR, "LDSTCR",
6136 SPR_NOACCESS, SPR_NOACCESS,
6137 &spr_read_generic, &spr_write_generic,
6138 0x00000000);
6139 /* ICTRL */
6140 /* XXX : not implemented */
6141 spr_register(env, SPR_ICTRL, "ICTRL",
6142 SPR_NOACCESS, SPR_NOACCESS,
6143 &spr_read_generic, &spr_write_generic,
6144 0x00000000);
6145 /* MSSSR0 */
6146 /* XXX : not implemented */
6147 spr_register(env, SPR_MSSSR0, "MSSSR0",
6148 SPR_NOACCESS, SPR_NOACCESS,
6149 &spr_read_generic, &spr_write_generic,
6150 0x00000000);
6151 /* PMC */
6152 /* XXX : not implemented */
6153 spr_register(env, SPR_7XX_PMC5, "PMC5",
6154 SPR_NOACCESS, SPR_NOACCESS,
6155 &spr_read_generic, &spr_write_generic,
6156 0x00000000);
6157 /* XXX : not implemented */
6158 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6159 &spr_read_ureg, SPR_NOACCESS,
6160 &spr_read_ureg, SPR_NOACCESS,
6161 0x00000000);
6162 /* XXX : not implemented */
6163 spr_register(env, SPR_7XX_PMC6, "PMC6",
6164 SPR_NOACCESS, SPR_NOACCESS,
6165 &spr_read_generic, &spr_write_generic,
6166 0x00000000);
6167 /* XXX : not implemented */
6168 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6169 &spr_read_ureg, SPR_NOACCESS,
6170 &spr_read_ureg, SPR_NOACCESS,
6171 0x00000000);
6172 /* SPRGs */
6173 spr_register(env, SPR_SPRG4, "SPRG4",
6174 SPR_NOACCESS, SPR_NOACCESS,
6175 &spr_read_generic, &spr_write_generic,
6176 0x00000000);
6177 spr_register(env, SPR_USPRG4, "USPRG4",
6178 &spr_read_ureg, SPR_NOACCESS,
6179 &spr_read_ureg, SPR_NOACCESS,
6180 0x00000000);
6181 spr_register(env, SPR_SPRG5, "SPRG5",
6182 SPR_NOACCESS, SPR_NOACCESS,
6183 &spr_read_generic, &spr_write_generic,
6184 0x00000000);
6185 spr_register(env, SPR_USPRG5, "USPRG5",
6186 &spr_read_ureg, SPR_NOACCESS,
6187 &spr_read_ureg, SPR_NOACCESS,
6188 0x00000000);
6189 spr_register(env, SPR_SPRG6, "SPRG6",
6190 SPR_NOACCESS, SPR_NOACCESS,
6191 &spr_read_generic, &spr_write_generic,
6192 0x00000000);
6193 spr_register(env, SPR_USPRG6, "USPRG6",
6194 &spr_read_ureg, SPR_NOACCESS,
6195 &spr_read_ureg, SPR_NOACCESS,
6196 0x00000000);
6197 spr_register(env, SPR_SPRG7, "SPRG7",
6198 SPR_NOACCESS, SPR_NOACCESS,
6199 &spr_read_generic, &spr_write_generic,
6200 0x00000000);
6201 spr_register(env, SPR_USPRG7, "USPRG7",
6202 &spr_read_ureg, SPR_NOACCESS,
6203 &spr_read_ureg, SPR_NOACCESS,
6204 0x00000000);
6205 /* Memory management */
6206 register_low_BATs(env);
6207 register_high_BATs(env);
6208 register_74xx_soft_tlb(env, 128, 2);
6209 init_excp_7450(env);
6210 env->dcache_line_size = 32;
6211 env->icache_line_size = 32;
6212 /* Allocate hardware IRQ controller */
6213 ppc6xx_irq_init(env_archcpu(env));
6214 }
6215
6216 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6217 {
6218 DeviceClass *dc = DEVICE_CLASS(oc);
6219 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6220
6221 dc->desc = "PowerPC 7445 (aka G4)";
6222 pcc->init_proc = init_proc_7445;
6223 pcc->check_pow = check_pow_hid0_74xx;
6224 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6225 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6226 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6227 PPC_FLOAT_STFIWX |
6228 PPC_CACHE | PPC_CACHE_ICBI |
6229 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6230 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6232 PPC_MEM_TLBIA | PPC_74xx_TLB |
6233 PPC_SEGMENT | PPC_EXTERN |
6234 PPC_ALTIVEC;
6235 pcc->msr_mask = (1ull << MSR_VR) |
6236 (1ull << MSR_POW) |
6237 (1ull << MSR_ILE) |
6238 (1ull << MSR_EE) |
6239 (1ull << MSR_PR) |
6240 (1ull << MSR_FP) |
6241 (1ull << MSR_ME) |
6242 (1ull << MSR_FE0) |
6243 (1ull << MSR_SE) |
6244 (1ull << MSR_DE) |
6245 (1ull << MSR_FE1) |
6246 (1ull << MSR_EP) |
6247 (1ull << MSR_IR) |
6248 (1ull << MSR_DR) |
6249 (1ull << MSR_PMM) |
6250 (1ull << MSR_RI) |
6251 (1ull << MSR_LE);
6252 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6253 pcc->excp_model = POWERPC_EXCP_74xx;
6254 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6255 pcc->bfd_mach = bfd_mach_ppc_7400;
6256 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6257 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6258 POWERPC_FLAG_BUS_CLK;
6259 }
6260
6261 static void init_proc_7455(CPUPPCState *env)
6262 {
6263 register_ne_601_sprs(env);
6264 register_sdr1_sprs(env);
6265 register_7xx_sprs(env);
6266 /* Time base */
6267 register_tbl(env);
6268 /* 74xx specific SPR */
6269 register_74xx_sprs(env);
6270 vscr_init(env, 0x00010000);
6271 /* Level 3 cache control */
6272 register_l3_ctrl(env);
6273 /* LDSTCR */
6274 /* XXX : not implemented */
6275 spr_register(env, SPR_LDSTCR, "LDSTCR",
6276 SPR_NOACCESS, SPR_NOACCESS,
6277 &spr_read_generic, &spr_write_generic,
6278 0x00000000);
6279 /* ICTRL */
6280 /* XXX : not implemented */
6281 spr_register(env, SPR_ICTRL, "ICTRL",
6282 SPR_NOACCESS, SPR_NOACCESS,
6283 &spr_read_generic, &spr_write_generic,
6284 0x00000000);
6285 /* MSSSR0 */
6286 /* XXX : not implemented */
6287 spr_register(env, SPR_MSSSR0, "MSSSR0",
6288 SPR_NOACCESS, SPR_NOACCESS,
6289 &spr_read_generic, &spr_write_generic,
6290 0x00000000);
6291 /* PMC */
6292 /* XXX : not implemented */
6293 spr_register(env, SPR_7XX_PMC5, "PMC5",
6294 SPR_NOACCESS, SPR_NOACCESS,
6295 &spr_read_generic, &spr_write_generic,
6296 0x00000000);
6297 /* XXX : not implemented */
6298 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6299 &spr_read_ureg, SPR_NOACCESS,
6300 &spr_read_ureg, SPR_NOACCESS,
6301 0x00000000);
6302 /* XXX : not implemented */
6303 spr_register(env, SPR_7XX_PMC6, "PMC6",
6304 SPR_NOACCESS, SPR_NOACCESS,
6305 &spr_read_generic, &spr_write_generic,
6306 0x00000000);
6307 /* XXX : not implemented */
6308 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6309 &spr_read_ureg, SPR_NOACCESS,
6310 &spr_read_ureg, SPR_NOACCESS,
6311 0x00000000);
6312 /* SPRGs */
6313 spr_register(env, SPR_SPRG4, "SPRG4",
6314 SPR_NOACCESS, SPR_NOACCESS,
6315 &spr_read_generic, &spr_write_generic,
6316 0x00000000);
6317 spr_register(env, SPR_USPRG4, "USPRG4",
6318 &spr_read_ureg, SPR_NOACCESS,
6319 &spr_read_ureg, SPR_NOACCESS,
6320 0x00000000);
6321 spr_register(env, SPR_SPRG5, "SPRG5",
6322 SPR_NOACCESS, SPR_NOACCESS,
6323 &spr_read_generic, &spr_write_generic,
6324 0x00000000);
6325 spr_register(env, SPR_USPRG5, "USPRG5",
6326 &spr_read_ureg, SPR_NOACCESS,
6327 &spr_read_ureg, SPR_NOACCESS,
6328 0x00000000);
6329 spr_register(env, SPR_SPRG6, "SPRG6",
6330 SPR_NOACCESS, SPR_NOACCESS,
6331 &spr_read_generic, &spr_write_generic,
6332 0x00000000);
6333 spr_register(env, SPR_USPRG6, "USPRG6",
6334 &spr_read_ureg, SPR_NOACCESS,
6335 &spr_read_ureg, SPR_NOACCESS,
6336 0x00000000);
6337 spr_register(env, SPR_SPRG7, "SPRG7",
6338 SPR_NOACCESS, SPR_NOACCESS,
6339 &spr_read_generic, &spr_write_generic,
6340 0x00000000);
6341 spr_register(env, SPR_USPRG7, "USPRG7",
6342 &spr_read_ureg, SPR_NOACCESS,
6343 &spr_read_ureg, SPR_NOACCESS,
6344 0x00000000);
6345 /* Memory management */
6346 register_low_BATs(env);
6347 register_high_BATs(env);
6348 register_74xx_soft_tlb(env, 128, 2);
6349 init_excp_7450(env);
6350 env->dcache_line_size = 32;
6351 env->icache_line_size = 32;
6352 /* Allocate hardware IRQ controller */
6353 ppc6xx_irq_init(env_archcpu(env));
6354 }
6355
6356 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6357 {
6358 DeviceClass *dc = DEVICE_CLASS(oc);
6359 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6360
6361 dc->desc = "PowerPC 7455 (aka G4)";
6362 pcc->init_proc = init_proc_7455;
6363 pcc->check_pow = check_pow_hid0_74xx;
6364 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6365 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6366 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6367 PPC_FLOAT_STFIWX |
6368 PPC_CACHE | PPC_CACHE_ICBI |
6369 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6370 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6371 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6372 PPC_MEM_TLBIA | PPC_74xx_TLB |
6373 PPC_SEGMENT | PPC_EXTERN |
6374 PPC_ALTIVEC;
6375 pcc->msr_mask = (1ull << MSR_VR) |
6376 (1ull << MSR_POW) |
6377 (1ull << MSR_ILE) |
6378 (1ull << MSR_EE) |
6379 (1ull << MSR_PR) |
6380 (1ull << MSR_FP) |
6381 (1ull << MSR_ME) |
6382 (1ull << MSR_FE0) |
6383 (1ull << MSR_SE) |
6384 (1ull << MSR_DE) |
6385 (1ull << MSR_FE1) |
6386 (1ull << MSR_EP) |
6387 (1ull << MSR_IR) |
6388 (1ull << MSR_DR) |
6389 (1ull << MSR_PMM) |
6390 (1ull << MSR_RI) |
6391 (1ull << MSR_LE);
6392 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6393 pcc->excp_model = POWERPC_EXCP_74xx;
6394 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6395 pcc->bfd_mach = bfd_mach_ppc_7400;
6396 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6397 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6398 POWERPC_FLAG_BUS_CLK;
6399 }
6400
6401 static void init_proc_7457(CPUPPCState *env)
6402 {
6403 register_ne_601_sprs(env);
6404 register_sdr1_sprs(env);
6405 register_7xx_sprs(env);
6406 /* Time base */
6407 register_tbl(env);
6408 /* 74xx specific SPR */
6409 register_74xx_sprs(env);
6410 vscr_init(env, 0x00010000);
6411 /* Level 3 cache control */
6412 register_l3_ctrl(env);
6413 /* L3ITCR1 */
6414 /* XXX : not implemented */
6415 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6416 SPR_NOACCESS, SPR_NOACCESS,
6417 &spr_read_generic, &spr_write_generic,
6418 0x00000000);
6419 /* L3ITCR2 */
6420 /* XXX : not implemented */
6421 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6422 SPR_NOACCESS, SPR_NOACCESS,
6423 &spr_read_generic, &spr_write_generic,
6424 0x00000000);
6425 /* L3ITCR3 */
6426 /* XXX : not implemented */
6427 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6428 SPR_NOACCESS, SPR_NOACCESS,
6429 &spr_read_generic, &spr_write_generic,
6430 0x00000000);
6431 /* L3OHCR */
6432 /* XXX : not implemented */
6433 spr_register(env, SPR_L3OHCR, "L3OHCR",
6434 SPR_NOACCESS, SPR_NOACCESS,
6435 &spr_read_generic, &spr_write_generic,
6436 0x00000000);
6437 /* LDSTCR */
6438 /* XXX : not implemented */
6439 spr_register(env, SPR_LDSTCR, "LDSTCR",
6440 SPR_NOACCESS, SPR_NOACCESS,
6441 &spr_read_generic, &spr_write_generic,
6442 0x00000000);
6443 /* ICTRL */
6444 /* XXX : not implemented */
6445 spr_register(env, SPR_ICTRL, "ICTRL",
6446 SPR_NOACCESS, SPR_NOACCESS,
6447 &spr_read_generic, &spr_write_generic,
6448 0x00000000);
6449 /* MSSSR0 */
6450 /* XXX : not implemented */
6451 spr_register(env, SPR_MSSSR0, "MSSSR0",
6452 SPR_NOACCESS, SPR_NOACCESS,
6453 &spr_read_generic, &spr_write_generic,
6454 0x00000000);
6455 /* PMC */
6456 /* XXX : not implemented */
6457 spr_register(env, SPR_7XX_PMC5, "PMC5",
6458 SPR_NOACCESS, SPR_NOACCESS,
6459 &spr_read_generic, &spr_write_generic,
6460 0x00000000);
6461 /* XXX : not implemented */
6462 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6463 &spr_read_ureg, SPR_NOACCESS,
6464 &spr_read_ureg, SPR_NOACCESS,
6465 0x00000000);
6466 /* XXX : not implemented */
6467 spr_register(env, SPR_7XX_PMC6, "PMC6",
6468 SPR_NOACCESS, SPR_NOACCESS,
6469 &spr_read_generic, &spr_write_generic,
6470 0x00000000);
6471 /* XXX : not implemented */
6472 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6473 &spr_read_ureg, SPR_NOACCESS,
6474 &spr_read_ureg, SPR_NOACCESS,
6475 0x00000000);
6476 /* SPRGs */
6477 spr_register(env, SPR_SPRG4, "SPRG4",
6478 SPR_NOACCESS, SPR_NOACCESS,
6479 &spr_read_generic, &spr_write_generic,
6480 0x00000000);
6481 spr_register(env, SPR_USPRG4, "USPRG4",
6482 &spr_read_ureg, SPR_NOACCESS,
6483 &spr_read_ureg, SPR_NOACCESS,
6484 0x00000000);
6485 spr_register(env, SPR_SPRG5, "SPRG5",
6486 SPR_NOACCESS, SPR_NOACCESS,
6487 &spr_read_generic, &spr_write_generic,
6488 0x00000000);
6489 spr_register(env, SPR_USPRG5, "USPRG5",
6490 &spr_read_ureg, SPR_NOACCESS,
6491 &spr_read_ureg, SPR_NOACCESS,
6492 0x00000000);
6493 spr_register(env, SPR_SPRG6, "SPRG6",
6494 SPR_NOACCESS, SPR_NOACCESS,
6495 &spr_read_generic, &spr_write_generic,
6496 0x00000000);
6497 spr_register(env, SPR_USPRG6, "USPRG6",
6498 &spr_read_ureg, SPR_NOACCESS,
6499 &spr_read_ureg, SPR_NOACCESS,
6500 0x00000000);
6501 spr_register(env, SPR_SPRG7, "SPRG7",
6502 SPR_NOACCESS, SPR_NOACCESS,
6503 &spr_read_generic, &spr_write_generic,
6504 0x00000000);
6505 spr_register(env, SPR_USPRG7, "USPRG7",
6506 &spr_read_ureg, SPR_NOACCESS,
6507 &spr_read_ureg, SPR_NOACCESS,
6508 0x00000000);
6509 /* Memory management */
6510 register_low_BATs(env);
6511 register_high_BATs(env);
6512 register_74xx_soft_tlb(env, 128, 2);
6513 init_excp_7450(env);
6514 env->dcache_line_size = 32;
6515 env->icache_line_size = 32;
6516 /* Allocate hardware IRQ controller */
6517 ppc6xx_irq_init(env_archcpu(env));
6518 }
6519
6520 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6521 {
6522 DeviceClass *dc = DEVICE_CLASS(oc);
6523 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6524
6525 dc->desc = "PowerPC 7457 (aka G4)";
6526 pcc->init_proc = init_proc_7457;
6527 pcc->check_pow = check_pow_hid0_74xx;
6528 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6529 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6530 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6531 PPC_FLOAT_STFIWX |
6532 PPC_CACHE | PPC_CACHE_ICBI |
6533 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6534 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6535 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6536 PPC_MEM_TLBIA | PPC_74xx_TLB |
6537 PPC_SEGMENT | PPC_EXTERN |
6538 PPC_ALTIVEC;
6539 pcc->msr_mask = (1ull << MSR_VR) |
6540 (1ull << MSR_POW) |
6541 (1ull << MSR_ILE) |
6542 (1ull << MSR_EE) |
6543 (1ull << MSR_PR) |
6544 (1ull << MSR_FP) |
6545 (1ull << MSR_ME) |
6546 (1ull << MSR_FE0) |
6547 (1ull << MSR_SE) |
6548 (1ull << MSR_DE) |
6549 (1ull << MSR_FE1) |
6550 (1ull << MSR_EP) |
6551 (1ull << MSR_IR) |
6552 (1ull << MSR_DR) |
6553 (1ull << MSR_PMM) |
6554 (1ull << MSR_RI) |
6555 (1ull << MSR_LE);
6556 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6557 pcc->excp_model = POWERPC_EXCP_74xx;
6558 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6559 pcc->bfd_mach = bfd_mach_ppc_7400;
6560 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6561 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6562 POWERPC_FLAG_BUS_CLK;
6563 }
6564
6565 static void init_proc_e600(CPUPPCState *env)
6566 {
6567 register_ne_601_sprs(env);
6568 register_sdr1_sprs(env);
6569 register_7xx_sprs(env);
6570 /* Time base */
6571 register_tbl(env);
6572 /* 74xx specific SPR */
6573 register_74xx_sprs(env);
6574 vscr_init(env, 0x00010000);
6575 /* XXX : not implemented */
6576 spr_register(env, SPR_UBAMR, "UBAMR",
6577 &spr_read_ureg, SPR_NOACCESS,
6578 &spr_read_ureg, SPR_NOACCESS,
6579 0x00000000);
6580 /* XXX : not implemented */
6581 spr_register(env, SPR_LDSTCR, "LDSTCR",
6582 SPR_NOACCESS, SPR_NOACCESS,
6583 &spr_read_generic, &spr_write_generic,
6584 0x00000000);
6585 /* XXX : not implemented */
6586 spr_register(env, SPR_ICTRL, "ICTRL",
6587 SPR_NOACCESS, SPR_NOACCESS,
6588 &spr_read_generic, &spr_write_generic,
6589 0x00000000);
6590 /* XXX : not implemented */
6591 spr_register(env, SPR_MSSSR0, "MSSSR0",
6592 SPR_NOACCESS, SPR_NOACCESS,
6593 &spr_read_generic, &spr_write_generic,
6594 0x00000000);
6595 /* XXX : not implemented */
6596 spr_register(env, SPR_7XX_PMC5, "PMC5",
6597 SPR_NOACCESS, SPR_NOACCESS,
6598 &spr_read_generic, &spr_write_generic,
6599 0x00000000);
6600 /* XXX : not implemented */
6601 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6602 &spr_read_ureg, SPR_NOACCESS,
6603 &spr_read_ureg, SPR_NOACCESS,
6604 0x00000000);
6605 /* XXX : not implemented */
6606 spr_register(env, SPR_7XX_PMC6, "PMC6",
6607 SPR_NOACCESS, SPR_NOACCESS,
6608 &spr_read_generic, &spr_write_generic,
6609 0x00000000);
6610 /* XXX : not implemented */
6611 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6612 &spr_read_ureg, SPR_NOACCESS,
6613 &spr_read_ureg, SPR_NOACCESS,
6614 0x00000000);
6615 /* SPRGs */
6616 spr_register(env, SPR_SPRG4, "SPRG4",
6617 SPR_NOACCESS, SPR_NOACCESS,
6618 &spr_read_generic, &spr_write_generic,
6619 0x00000000);
6620 spr_register(env, SPR_USPRG4, "USPRG4",
6621 &spr_read_ureg, SPR_NOACCESS,
6622 &spr_read_ureg, SPR_NOACCESS,
6623 0x00000000);
6624 spr_register(env, SPR_SPRG5, "SPRG5",
6625 SPR_NOACCESS, SPR_NOACCESS,
6626 &spr_read_generic, &spr_write_generic,
6627 0x00000000);
6628 spr_register(env, SPR_USPRG5, "USPRG5",
6629 &spr_read_ureg, SPR_NOACCESS,
6630 &spr_read_ureg, SPR_NOACCESS,
6631 0x00000000);
6632 spr_register(env, SPR_SPRG6, "SPRG6",
6633 SPR_NOACCESS, SPR_NOACCESS,
6634 &spr_read_generic, &spr_write_generic,
6635 0x00000000);
6636 spr_register(env, SPR_USPRG6, "USPRG6",
6637 &spr_read_ureg, SPR_NOACCESS,
6638 &spr_read_ureg, SPR_NOACCESS,
6639 0x00000000);
6640 spr_register(env, SPR_SPRG7, "SPRG7",
6641 SPR_NOACCESS, SPR_NOACCESS,
6642 &spr_read_generic, &spr_write_generic,
6643 0x00000000);
6644 spr_register(env, SPR_USPRG7, "USPRG7",
6645 &spr_read_ureg, SPR_NOACCESS,
6646 &spr_read_ureg, SPR_NOACCESS,
6647 0x00000000);
6648 /* Memory management */
6649 register_low_BATs(env);
6650 register_high_BATs(env);
6651 register_74xx_soft_tlb(env, 128, 2);
6652 init_excp_7450(env);
6653 env->dcache_line_size = 32;
6654 env->icache_line_size = 32;
6655 /* Allocate hardware IRQ controller */
6656 ppc6xx_irq_init(env_archcpu(env));
6657 }
6658
6659 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6660 {
6661 DeviceClass *dc = DEVICE_CLASS(oc);
6662 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6663
6664 dc->desc = "PowerPC e600";
6665 pcc->init_proc = init_proc_e600;
6666 pcc->check_pow = check_pow_hid0_74xx;
6667 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6668 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6669 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6670 PPC_FLOAT_STFIWX |
6671 PPC_CACHE | PPC_CACHE_ICBI |
6672 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6673 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6674 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6675 PPC_MEM_TLBIA | PPC_74xx_TLB |
6676 PPC_SEGMENT | PPC_EXTERN |
6677 PPC_ALTIVEC;
6678 pcc->insns_flags2 = PPC_NONE;
6679 pcc->msr_mask = (1ull << MSR_VR) |
6680 (1ull << MSR_POW) |
6681 (1ull << MSR_ILE) |
6682 (1ull << MSR_EE) |
6683 (1ull << MSR_PR) |
6684 (1ull << MSR_FP) |
6685 (1ull << MSR_ME) |
6686 (1ull << MSR_FE0) |
6687 (1ull << MSR_SE) |
6688 (1ull << MSR_DE) |
6689 (1ull << MSR_FE1) |
6690 (1ull << MSR_EP) |
6691 (1ull << MSR_IR) |
6692 (1ull << MSR_DR) |
6693 (1ull << MSR_PMM) |
6694 (1ull << MSR_RI) |
6695 (1ull << MSR_LE);
6696 pcc->mmu_model = POWERPC_MMU_32B;
6697 pcc->excp_model = POWERPC_EXCP_74xx;
6698 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6699 pcc->bfd_mach = bfd_mach_ppc_7400;
6700 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6701 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6702 POWERPC_FLAG_BUS_CLK;
6703 }
6704
6705 #if defined(TARGET_PPC64)
6706 #if defined(CONFIG_USER_ONLY)
6707 #define POWERPC970_HID5_INIT 0x00000080
6708 #else
6709 #define POWERPC970_HID5_INIT 0x00000000
6710 #endif
6711
6712 static int check_pow_970(CPUPPCState *env)
6713 {
6714 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
6715 return 1;
6716 }
6717
6718 return 0;
6719 }
6720
6721 static void register_970_hid_sprs(CPUPPCState *env)
6722 {
6723 /* Hardware implementation registers */
6724 /* XXX : not implemented */
6725 spr_register(env, SPR_HID0, "HID0",
6726 SPR_NOACCESS, SPR_NOACCESS,
6727 &spr_read_generic, &spr_write_clear,
6728 0x60000000);
6729 spr_register(env, SPR_HID1, "HID1",
6730 SPR_NOACCESS, SPR_NOACCESS,
6731 &spr_read_generic, &spr_write_generic,
6732 0x00000000);
6733 spr_register(env, SPR_970_HID5, "HID5",
6734 SPR_NOACCESS, SPR_NOACCESS,
6735 &spr_read_generic, &spr_write_generic,
6736 POWERPC970_HID5_INIT);
6737 }
6738
6739 static void register_970_hior_sprs(CPUPPCState *env)
6740 {
6741 spr_register(env, SPR_HIOR, "SPR_HIOR",
6742 SPR_NOACCESS, SPR_NOACCESS,
6743 &spr_read_hior, &spr_write_hior,
6744 0x00000000);
6745 }
6746
6747 static void register_book3s_ctrl_sprs(CPUPPCState *env)
6748 {
6749 spr_register(env, SPR_CTRL, "SPR_CTRL",
6750 SPR_NOACCESS, SPR_NOACCESS,
6751 SPR_NOACCESS, &spr_write_generic,
6752 0x00000000);
6753 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6754 &spr_read_ureg, SPR_NOACCESS,
6755 &spr_read_ureg, SPR_NOACCESS,
6756 0x00000000);
6757 }
6758
6759 static void register_book3s_altivec_sprs(CPUPPCState *env)
6760 {
6761 if (!(env->insns_flags & PPC_ALTIVEC)) {
6762 return;
6763 }
6764
6765 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
6766 &spr_read_generic, &spr_write_generic,
6767 &spr_read_generic, &spr_write_generic,
6768 KVM_REG_PPC_VRSAVE, 0x00000000);
6769
6770 }
6771
6772 static void register_book3s_dbg_sprs(CPUPPCState *env)
6773 {
6774 /*
6775 * TODO: different specs define different scopes for these,
6776 * will have to address this:
6777 * 970: super/write and super/read
6778 * powerisa 2.03..2.04: hypv/write and super/read.
6779 * powerisa 2.05 and newer: hypv/write and hypv/read.
6780 */
6781 spr_register_kvm(env, SPR_DABR, "DABR",
6782 SPR_NOACCESS, SPR_NOACCESS,
6783 &spr_read_generic, &spr_write_generic,
6784 KVM_REG_PPC_DABR, 0x00000000);
6785 spr_register_kvm(env, SPR_DABRX, "DABRX",
6786 SPR_NOACCESS, SPR_NOACCESS,
6787 &spr_read_generic, &spr_write_generic,
6788 KVM_REG_PPC_DABRX, 0x00000000);
6789 }
6790
6791 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
6792 {
6793 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 SPR_NOACCESS, SPR_NOACCESS,
6796 &spr_read_generic, &spr_write_generic,
6797 KVM_REG_PPC_DAWR, 0x00000000);
6798 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
6799 SPR_NOACCESS, SPR_NOACCESS,
6800 SPR_NOACCESS, SPR_NOACCESS,
6801 &spr_read_generic, &spr_write_generic,
6802 KVM_REG_PPC_DAWRX, 0x00000000);
6803 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
6804 SPR_NOACCESS, SPR_NOACCESS,
6805 SPR_NOACCESS, SPR_NOACCESS,
6806 &spr_read_generic, &spr_write_generic,
6807 KVM_REG_PPC_CIABR, 0x00000000);
6808 }
6809
6810 static void register_970_dbg_sprs(CPUPPCState *env)
6811 {
6812 /* Breakpoints */
6813 spr_register(env, SPR_IABR, "IABR",
6814 SPR_NOACCESS, SPR_NOACCESS,
6815 &spr_read_generic, &spr_write_generic,
6816 0x00000000);
6817 }
6818
6819 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
6820 {
6821 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
6822 SPR_NOACCESS, SPR_NOACCESS,
6823 &spr_read_generic, &spr_write_generic,
6824 KVM_REG_PPC_MMCR0, 0x00000000);
6825 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
6826 SPR_NOACCESS, SPR_NOACCESS,
6827 &spr_read_generic, &spr_write_generic,
6828 KVM_REG_PPC_MMCR1, 0x00000000);
6829 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
6830 SPR_NOACCESS, SPR_NOACCESS,
6831 &spr_read_generic, &spr_write_generic,
6832 KVM_REG_PPC_MMCRA, 0x00000000);
6833 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
6834 SPR_NOACCESS, SPR_NOACCESS,
6835 &spr_read_generic, &spr_write_generic,
6836 KVM_REG_PPC_PMC1, 0x00000000);
6837 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
6838 SPR_NOACCESS, SPR_NOACCESS,
6839 &spr_read_generic, &spr_write_generic,
6840 KVM_REG_PPC_PMC2, 0x00000000);
6841 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
6842 SPR_NOACCESS, SPR_NOACCESS,
6843 &spr_read_generic, &spr_write_generic,
6844 KVM_REG_PPC_PMC3, 0x00000000);
6845 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
6846 SPR_NOACCESS, SPR_NOACCESS,
6847 &spr_read_generic, &spr_write_generic,
6848 KVM_REG_PPC_PMC4, 0x00000000);
6849 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
6850 SPR_NOACCESS, SPR_NOACCESS,
6851 &spr_read_generic, &spr_write_generic,
6852 KVM_REG_PPC_PMC5, 0x00000000);
6853 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
6854 SPR_NOACCESS, SPR_NOACCESS,
6855 &spr_read_generic, &spr_write_generic,
6856 KVM_REG_PPC_PMC6, 0x00000000);
6857 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
6858 SPR_NOACCESS, SPR_NOACCESS,
6859 &spr_read_generic, &spr_write_generic,
6860 KVM_REG_PPC_SIAR, 0x00000000);
6861 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
6862 SPR_NOACCESS, SPR_NOACCESS,
6863 &spr_read_generic, &spr_write_generic,
6864 KVM_REG_PPC_SDAR, 0x00000000);
6865 }
6866
6867 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
6868 {
6869 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
6870 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
6871 &spr_read_ureg, &spr_write_ureg,
6872 0x00000000);
6873 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
6874 &spr_read_ureg, SPR_NOACCESS,
6875 &spr_read_ureg, &spr_write_ureg,
6876 0x00000000);
6877 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
6878 &spr_read_ureg, SPR_NOACCESS,
6879 &spr_read_ureg, &spr_write_ureg,
6880 0x00000000);
6881 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
6882 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6883 &spr_read_ureg, &spr_write_ureg,
6884 0x00000000);
6885 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
6886 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6887 &spr_read_ureg, &spr_write_ureg,
6888 0x00000000);
6889 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
6890 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6891 &spr_read_ureg, &spr_write_ureg,
6892 0x00000000);
6893 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
6894 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6895 &spr_read_ureg, &spr_write_ureg,
6896 0x00000000);
6897 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
6898 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
6899 &spr_read_ureg, &spr_write_ureg,
6900 0x00000000);
6901 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
6902 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
6903 &spr_read_ureg, &spr_write_ureg,
6904 0x00000000);
6905 spr_register(env, SPR_POWER_USIAR, "USIAR",
6906 &spr_read_ureg, SPR_NOACCESS,
6907 &spr_read_ureg, &spr_write_ureg,
6908 0x00000000);
6909 spr_register(env, SPR_POWER_USDAR, "USDAR",
6910 &spr_read_ureg, SPR_NOACCESS,
6911 &spr_read_ureg, &spr_write_ureg,
6912 0x00000000);
6913 }
6914
6915 static void register_970_pmu_sup_sprs(CPUPPCState *env)
6916 {
6917 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
6918 SPR_NOACCESS, SPR_NOACCESS,
6919 &spr_read_generic, &spr_write_generic,
6920 KVM_REG_PPC_PMC7, 0x00000000);
6921 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
6922 SPR_NOACCESS, SPR_NOACCESS,
6923 &spr_read_generic, &spr_write_generic,
6924 KVM_REG_PPC_PMC8, 0x00000000);
6925 }
6926
6927 static void register_970_pmu_user_sprs(CPUPPCState *env)
6928 {
6929 spr_register(env, SPR_970_UPMC7, "UPMC7",
6930 &spr_read_ureg, SPR_NOACCESS,
6931 &spr_read_ureg, &spr_write_ureg,
6932 0x00000000);
6933 spr_register(env, SPR_970_UPMC8, "UPMC8",
6934 &spr_read_ureg, SPR_NOACCESS,
6935 &spr_read_ureg, &spr_write_ureg,
6936 0x00000000);
6937 }
6938
6939 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
6940 {
6941 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
6942 SPR_NOACCESS, SPR_NOACCESS,
6943 &spr_read_generic, &spr_write_generic,
6944 KVM_REG_PPC_MMCR2, 0x00000000);
6945 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
6946 SPR_NOACCESS, SPR_NOACCESS,
6947 &spr_read_generic, &spr_write_generic,
6948 KVM_REG_PPC_MMCRS, 0x00000000);
6949 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
6950 SPR_NOACCESS, SPR_NOACCESS,
6951 &spr_read_generic, &spr_write_generic,
6952 KVM_REG_PPC_SIER, 0x00000000);
6953 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
6954 SPR_NOACCESS, SPR_NOACCESS,
6955 &spr_read_generic, &spr_write_generic,
6956 KVM_REG_PPC_SPMC1, 0x00000000);
6957 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
6958 SPR_NOACCESS, SPR_NOACCESS,
6959 &spr_read_generic, &spr_write_generic,
6960 KVM_REG_PPC_SPMC2, 0x00000000);
6961 spr_register_kvm(env, SPR_TACR, "TACR",
6962 SPR_NOACCESS, SPR_NOACCESS,
6963 &spr_read_generic, &spr_write_generic,
6964 KVM_REG_PPC_TACR, 0x00000000);
6965 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
6966 SPR_NOACCESS, SPR_NOACCESS,
6967 &spr_read_generic, &spr_write_generic,
6968 KVM_REG_PPC_TCSCR, 0x00000000);
6969 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
6970 SPR_NOACCESS, SPR_NOACCESS,
6971 &spr_read_generic, &spr_write_generic,
6972 KVM_REG_PPC_CSIGR, 0x00000000);
6973 }
6974
6975 static void register_power8_pmu_user_sprs(CPUPPCState *env)
6976 {
6977 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
6978 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
6979 &spr_read_ureg, &spr_write_ureg,
6980 0x00000000);
6981 spr_register(env, SPR_POWER_USIER, "USIER",
6982 &spr_read_generic, SPR_NOACCESS,
6983 &spr_read_generic, &spr_write_generic,
6984 0x00000000);
6985 }
6986
6987 static void register_power5p_ear_sprs(CPUPPCState *env)
6988 {
6989 /* External access control */
6990 spr_register(env, SPR_EAR, "EAR",
6991 SPR_NOACCESS, SPR_NOACCESS,
6992 &spr_read_generic, &spr_write_generic,
6993 0x00000000);
6994 }
6995
6996 static void register_power5p_tb_sprs(CPUPPCState *env)
6997 {
6998 /* TBU40 (High 40 bits of the Timebase register */
6999 spr_register_hv(env, SPR_TBU40, "TBU40",
7000 SPR_NOACCESS, SPR_NOACCESS,
7001 SPR_NOACCESS, SPR_NOACCESS,
7002 SPR_NOACCESS, &spr_write_tbu40,
7003 0x00000000);
7004 }
7005
7006 static void register_970_lpar_sprs(CPUPPCState *env)
7007 {
7008 #if !defined(CONFIG_USER_ONLY)
7009 /*
7010 * PPC970: HID4 covers things later controlled by the LPCR and
7011 * RMOR in later CPUs, but with a different encoding. We only
7012 * support the 970 in "Apple mode" which has all hypervisor
7013 * facilities disabled by strapping, so we can basically just
7014 * ignore it
7015 */
7016 spr_register(env, SPR_970_HID4, "HID4",
7017 SPR_NOACCESS, SPR_NOACCESS,
7018 &spr_read_generic, &spr_write_generic,
7019 0x00000000);
7020 #endif
7021 }
7022
7023 static void register_power5p_lpar_sprs(CPUPPCState *env)
7024 {
7025 #if !defined(CONFIG_USER_ONLY)
7026 /* Logical partitionning */
7027 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7028 SPR_NOACCESS, SPR_NOACCESS,
7029 SPR_NOACCESS, SPR_NOACCESS,
7030 &spr_read_generic, &spr_write_lpcr,
7031 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7032 spr_register_hv(env, SPR_HDEC, "HDEC",
7033 SPR_NOACCESS, SPR_NOACCESS,
7034 SPR_NOACCESS, SPR_NOACCESS,
7035 &spr_read_hdecr, &spr_write_hdecr, 0);
7036 #endif
7037 }
7038
7039 static void register_book3s_ids_sprs(CPUPPCState *env)
7040 {
7041 /* FIXME: Will need to deal with thread vs core only SPRs */
7042
7043 /* Processor identification */
7044 spr_register_hv(env, SPR_PIR, "PIR",
7045 SPR_NOACCESS, SPR_NOACCESS,
7046 &spr_read_generic, SPR_NOACCESS,
7047 &spr_read_generic, NULL,
7048 0x00000000);
7049 spr_register_hv(env, SPR_HID0, "HID0",
7050 SPR_NOACCESS, SPR_NOACCESS,
7051 SPR_NOACCESS, SPR_NOACCESS,
7052 &spr_read_generic, &spr_write_generic,
7053 0x00000000);
7054 spr_register_hv(env, SPR_TSCR, "TSCR",
7055 SPR_NOACCESS, SPR_NOACCESS,
7056 SPR_NOACCESS, SPR_NOACCESS,
7057 &spr_read_generic, &spr_write_generic,
7058 0x00000000);
7059 spr_register_hv(env, SPR_HMER, "HMER",
7060 SPR_NOACCESS, SPR_NOACCESS,
7061 SPR_NOACCESS, SPR_NOACCESS,
7062 &spr_read_generic, &spr_write_hmer,
7063 0x00000000);
7064 spr_register_hv(env, SPR_HMEER, "HMEER",
7065 SPR_NOACCESS, SPR_NOACCESS,
7066 SPR_NOACCESS, SPR_NOACCESS,
7067 &spr_read_generic, &spr_write_generic,
7068 0x00000000);
7069 spr_register_hv(env, SPR_TFMR, "TFMR",
7070 SPR_NOACCESS, SPR_NOACCESS,
7071 SPR_NOACCESS, SPR_NOACCESS,
7072 &spr_read_generic, &spr_write_generic,
7073 0x00000000);
7074 spr_register_hv(env, SPR_LPIDR, "LPIDR",
7075 SPR_NOACCESS, SPR_NOACCESS,
7076 SPR_NOACCESS, SPR_NOACCESS,
7077 &spr_read_generic, &spr_write_lpidr,
7078 0x00000000);
7079 spr_register_hv(env, SPR_HFSCR, "HFSCR",
7080 SPR_NOACCESS, SPR_NOACCESS,
7081 SPR_NOACCESS, SPR_NOACCESS,
7082 &spr_read_generic, &spr_write_generic,
7083 0x00000000);
7084 spr_register_hv(env, SPR_MMCRC, "MMCRC",
7085 SPR_NOACCESS, SPR_NOACCESS,
7086 SPR_NOACCESS, SPR_NOACCESS,
7087 &spr_read_generic, &spr_write_generic,
7088 0x00000000);
7089 spr_register_hv(env, SPR_MMCRH, "MMCRH",
7090 SPR_NOACCESS, SPR_NOACCESS,
7091 SPR_NOACCESS, SPR_NOACCESS,
7092 &spr_read_generic, &spr_write_generic,
7093 0x00000000);
7094 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7095 SPR_NOACCESS, SPR_NOACCESS,
7096 SPR_NOACCESS, SPR_NOACCESS,
7097 &spr_read_generic, &spr_write_generic,
7098 0x00000000);
7099 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7100 SPR_NOACCESS, SPR_NOACCESS,
7101 SPR_NOACCESS, SPR_NOACCESS,
7102 &spr_read_generic, &spr_write_generic,
7103 0x00000000);
7104 spr_register_hv(env, SPR_HSRR0, "HSRR0",
7105 SPR_NOACCESS, SPR_NOACCESS,
7106 SPR_NOACCESS, SPR_NOACCESS,
7107 &spr_read_generic, &spr_write_generic,
7108 0x00000000);
7109 spr_register_hv(env, SPR_HSRR1, "HSRR1",
7110 SPR_NOACCESS, SPR_NOACCESS,
7111 SPR_NOACCESS, SPR_NOACCESS,
7112 &spr_read_generic, &spr_write_generic,
7113 0x00000000);
7114 spr_register_hv(env, SPR_HDAR, "HDAR",
7115 SPR_NOACCESS, SPR_NOACCESS,
7116 SPR_NOACCESS, SPR_NOACCESS,
7117 &spr_read_generic, &spr_write_generic,
7118 0x00000000);
7119 spr_register_hv(env, SPR_HDSISR, "HDSISR",
7120 SPR_NOACCESS, SPR_NOACCESS,
7121 SPR_NOACCESS, SPR_NOACCESS,
7122 &spr_read_generic, &spr_write_generic,
7123 0x00000000);
7124 spr_register_hv(env, SPR_HRMOR, "HRMOR",
7125 SPR_NOACCESS, SPR_NOACCESS,
7126 SPR_NOACCESS, SPR_NOACCESS,
7127 &spr_read_generic, &spr_write_generic,
7128 0x00000000);
7129 }
7130
7131 static void register_rmor_sprs(CPUPPCState *env)
7132 {
7133 spr_register_hv(env, SPR_RMOR, "RMOR",
7134 SPR_NOACCESS, SPR_NOACCESS,
7135 SPR_NOACCESS, SPR_NOACCESS,
7136 &spr_read_generic, &spr_write_generic,
7137 0x00000000);
7138 }
7139
7140 static void register_power8_ids_sprs(CPUPPCState *env)
7141 {
7142 /* Thread identification */
7143 spr_register(env, SPR_TIR, "TIR",
7144 SPR_NOACCESS, SPR_NOACCESS,
7145 &spr_read_generic, SPR_NOACCESS,
7146 0x00000000);
7147 }
7148
7149 static void register_book3s_purr_sprs(CPUPPCState *env)
7150 {
7151 #if !defined(CONFIG_USER_ONLY)
7152 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7153 spr_register_kvm_hv(env, SPR_PURR, "PURR",
7154 &spr_read_purr, SPR_NOACCESS,
7155 &spr_read_purr, SPR_NOACCESS,
7156 &spr_read_purr, &spr_write_purr,
7157 KVM_REG_PPC_PURR, 0x00000000);
7158 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
7159 &spr_read_purr, SPR_NOACCESS,
7160 &spr_read_purr, SPR_NOACCESS,
7161 &spr_read_purr, &spr_write_purr,
7162 KVM_REG_PPC_SPURR, 0x00000000);
7163 #endif
7164 }
7165
7166 static void register_power6_dbg_sprs(CPUPPCState *env)
7167 {
7168 #if !defined(CONFIG_USER_ONLY)
7169 spr_register(env, SPR_CFAR, "SPR_CFAR",
7170 SPR_NOACCESS, SPR_NOACCESS,
7171 &spr_read_cfar, &spr_write_cfar,
7172 0x00000000);
7173 #endif
7174 }
7175
7176 static void register_power5p_common_sprs(CPUPPCState *env)
7177 {
7178 spr_register_kvm(env, SPR_PPR, "PPR",
7179 &spr_read_generic, &spr_write_generic,
7180 &spr_read_generic, &spr_write_generic,
7181 KVM_REG_PPC_PPR, 0x00000000);
7182 }
7183
7184 static void register_power6_common_sprs(CPUPPCState *env)
7185 {
7186 #if !defined(CONFIG_USER_ONLY)
7187 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7188 SPR_NOACCESS, SPR_NOACCESS,
7189 &spr_read_generic, &spr_write_generic,
7190 KVM_REG_PPC_DSCR, 0x00000000);
7191 #endif
7192 /*
7193 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7194 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
7195 */
7196 spr_register_hv(env, SPR_PCR, "PCR",
7197 SPR_NOACCESS, SPR_NOACCESS,
7198 SPR_NOACCESS, SPR_NOACCESS,
7199 &spr_read_generic, &spr_write_pcr,
7200 0x00000000);
7201 }
7202
7203 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
7204 {
7205 spr_register_kvm(env, SPR_TAR, "TAR",
7206 &spr_read_tar, &spr_write_tar,
7207 &spr_read_generic, &spr_write_generic,
7208 KVM_REG_PPC_TAR, 0x00000000);
7209 }
7210
7211 static void register_power8_tm_sprs(CPUPPCState *env)
7212 {
7213 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7214 &spr_read_tm, &spr_write_tm,
7215 &spr_read_tm, &spr_write_tm,
7216 KVM_REG_PPC_TFHAR, 0x00000000);
7217 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7218 &spr_read_tm, &spr_write_tm,
7219 &spr_read_tm, &spr_write_tm,
7220 KVM_REG_PPC_TFIAR, 0x00000000);
7221 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7222 &spr_read_tm, &spr_write_tm,
7223 &spr_read_tm, &spr_write_tm,
7224 KVM_REG_PPC_TEXASR, 0x00000000);
7225 spr_register(env, SPR_TEXASRU, "TEXASRU",
7226 &spr_read_tm_upper32, &spr_write_tm_upper32,
7227 &spr_read_tm_upper32, &spr_write_tm_upper32,
7228 0x00000000);
7229 }
7230
7231 static void register_power8_ebb_sprs(CPUPPCState *env)
7232 {
7233 spr_register(env, SPR_BESCRS, "BESCRS",
7234 &spr_read_ebb, &spr_write_ebb,
7235 &spr_read_generic, &spr_write_generic,
7236 0x00000000);
7237 spr_register(env, SPR_BESCRSU, "BESCRSU",
7238 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7239 &spr_read_prev_upper32, &spr_write_prev_upper32,
7240 0x00000000);
7241 spr_register(env, SPR_BESCRR, "BESCRR",
7242 &spr_read_ebb, &spr_write_ebb,
7243 &spr_read_generic, &spr_write_generic,
7244 0x00000000);
7245 spr_register(env, SPR_BESCRRU, "BESCRRU",
7246 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7247 &spr_read_prev_upper32, &spr_write_prev_upper32,
7248 0x00000000);
7249 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7250 &spr_read_ebb, &spr_write_ebb,
7251 &spr_read_generic, &spr_write_generic,
7252 KVM_REG_PPC_EBBHR, 0x00000000);
7253 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7254 &spr_read_ebb, &spr_write_ebb,
7255 &spr_read_generic, &spr_write_generic,
7256 KVM_REG_PPC_EBBRR, 0x00000000);
7257 spr_register_kvm(env, SPR_BESCR, "BESCR",
7258 &spr_read_ebb, &spr_write_ebb,
7259 &spr_read_generic, &spr_write_generic,
7260 KVM_REG_PPC_BESCR, 0x00000000);
7261 }
7262
7263 /* Virtual Time Base */
7264 static void register_vtb_sprs(CPUPPCState *env)
7265 {
7266 spr_register_kvm_hv(env, SPR_VTB, "VTB",
7267 SPR_NOACCESS, SPR_NOACCESS,
7268 &spr_read_vtb, SPR_NOACCESS,
7269 &spr_read_vtb, &spr_write_vtb,
7270 KVM_REG_PPC_VTB, 0x00000000);
7271 }
7272
7273 static void register_power8_fscr_sprs(CPUPPCState *env)
7274 {
7275 #if defined(CONFIG_USER_ONLY)
7276 target_ulong initval = 1ULL << FSCR_TAR;
7277 #else
7278 target_ulong initval = 0;
7279 #endif
7280 spr_register_kvm(env, SPR_FSCR, "FSCR",
7281 SPR_NOACCESS, SPR_NOACCESS,
7282 &spr_read_generic, &spr_write_generic,
7283 KVM_REG_PPC_FSCR, initval);
7284 }
7285
7286 static void register_power8_pspb_sprs(CPUPPCState *env)
7287 {
7288 spr_register_kvm(env, SPR_PSPB, "PSPB",
7289 SPR_NOACCESS, SPR_NOACCESS,
7290 &spr_read_generic, &spr_write_generic32,
7291 KVM_REG_PPC_PSPB, 0);
7292 }
7293
7294 static void register_power8_dpdes_sprs(CPUPPCState *env)
7295 {
7296 #if !defined(CONFIG_USER_ONLY)
7297 /* Directed Privileged Door-bell Exception State, used for IPI */
7298 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
7299 SPR_NOACCESS, SPR_NOACCESS,
7300 &spr_read_dpdes, SPR_NOACCESS,
7301 &spr_read_dpdes, &spr_write_dpdes,
7302 KVM_REG_PPC_DPDES, 0x00000000);
7303 #endif
7304 }
7305
7306 static void register_power8_ic_sprs(CPUPPCState *env)
7307 {
7308 #if !defined(CONFIG_USER_ONLY)
7309 spr_register_hv(env, SPR_IC, "IC",
7310 SPR_NOACCESS, SPR_NOACCESS,
7311 &spr_read_generic, SPR_NOACCESS,
7312 &spr_read_generic, &spr_write_generic,
7313 0);
7314 #endif
7315 }
7316
7317 static void register_power8_book4_sprs(CPUPPCState *env)
7318 {
7319 /* Add a number of P8 book4 registers */
7320 #if !defined(CONFIG_USER_ONLY)
7321 spr_register_kvm(env, SPR_ACOP, "ACOP",
7322 SPR_NOACCESS, SPR_NOACCESS,
7323 &spr_read_generic, &spr_write_generic,
7324 KVM_REG_PPC_ACOP, 0);
7325 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7326 SPR_NOACCESS, SPR_NOACCESS,
7327 &spr_read_generic, &spr_write_pidr,
7328 KVM_REG_PPC_PID, 0);
7329 spr_register_kvm(env, SPR_WORT, "WORT",
7330 SPR_NOACCESS, SPR_NOACCESS,
7331 &spr_read_generic, &spr_write_generic,
7332 KVM_REG_PPC_WORT, 0);
7333 #endif
7334 }
7335
7336 static void register_power7_book4_sprs(CPUPPCState *env)
7337 {
7338 /* Add a number of P7 book4 registers */
7339 #if !defined(CONFIG_USER_ONLY)
7340 spr_register_kvm(env, SPR_ACOP, "ACOP",
7341 SPR_NOACCESS, SPR_NOACCESS,
7342 &spr_read_generic, &spr_write_generic,
7343 KVM_REG_PPC_ACOP, 0);
7344 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7345 SPR_NOACCESS, SPR_NOACCESS,
7346 &spr_read_generic, &spr_write_generic,
7347 KVM_REG_PPC_PID, 0);
7348 #endif
7349 }
7350
7351 static void register_power8_rpr_sprs(CPUPPCState *env)
7352 {
7353 #if !defined(CONFIG_USER_ONLY)
7354 spr_register_hv(env, SPR_RPR, "RPR",
7355 SPR_NOACCESS, SPR_NOACCESS,
7356 SPR_NOACCESS, SPR_NOACCESS,
7357 &spr_read_generic, &spr_write_generic,
7358 0x00000103070F1F3F);
7359 #endif
7360 }
7361
7362 static void register_power9_mmu_sprs(CPUPPCState *env)
7363 {
7364 #if !defined(CONFIG_USER_ONLY)
7365 /* Partition Table Control */
7366 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
7367 SPR_NOACCESS, SPR_NOACCESS,
7368 SPR_NOACCESS, SPR_NOACCESS,
7369 &spr_read_generic, &spr_write_ptcr,
7370 KVM_REG_PPC_PTCR, 0x00000000);
7371 /* Address Segment Descriptor Register */
7372 spr_register_hv(env, SPR_ASDR, "ASDR",
7373 SPR_NOACCESS, SPR_NOACCESS,
7374 SPR_NOACCESS, SPR_NOACCESS,
7375 &spr_read_generic, &spr_write_generic,
7376 0x0000000000000000);
7377 #endif
7378 }
7379
7380 static void init_proc_book3s_common(CPUPPCState *env)
7381 {
7382 register_ne_601_sprs(env);
7383 register_tbl(env);
7384 register_usprg3_sprs(env);
7385 register_book3s_altivec_sprs(env);
7386 register_book3s_pmu_sup_sprs(env);
7387 register_book3s_pmu_user_sprs(env);
7388 register_book3s_ctrl_sprs(env);
7389 /*
7390 * Can't find information on what this should be on reset. This
7391 * value is the one used by 74xx processors.
7392 */
7393 vscr_init(env, 0x00010000);
7394 }
7395
7396 static void init_proc_970(CPUPPCState *env)
7397 {
7398 /* Common Registers */
7399 init_proc_book3s_common(env);
7400 register_sdr1_sprs(env);
7401 register_book3s_dbg_sprs(env);
7402
7403 /* 970 Specific Registers */
7404 register_970_hid_sprs(env);
7405 register_970_hior_sprs(env);
7406 register_low_BATs(env);
7407 register_970_pmu_sup_sprs(env);
7408 register_970_pmu_user_sprs(env);
7409 register_970_lpar_sprs(env);
7410 register_970_dbg_sprs(env);
7411
7412 /* env variables */
7413 env->dcache_line_size = 128;
7414 env->icache_line_size = 128;
7415
7416 /* Allocate hardware IRQ controller */
7417 init_excp_970(env);
7418 ppc970_irq_init(env_archcpu(env));
7419 }
7420
7421 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7422 {
7423 DeviceClass *dc = DEVICE_CLASS(oc);
7424 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7425
7426 dc->desc = "PowerPC 970";
7427 pcc->init_proc = init_proc_970;
7428 pcc->check_pow = check_pow_970;
7429 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7430 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7431 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7432 PPC_FLOAT_STFIWX |
7433 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7434 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7435 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7436 PPC_64B | PPC_ALTIVEC |
7437 PPC_SEGMENT_64B | PPC_SLBI;
7438 pcc->insns_flags2 = PPC2_FP_CVT_S64;
7439 pcc->msr_mask = (1ull << MSR_SF) |
7440 (1ull << MSR_VR) |
7441 (1ull << MSR_POW) |
7442 (1ull << MSR_EE) |
7443 (1ull << MSR_PR) |
7444 (1ull << MSR_FP) |
7445 (1ull << MSR_ME) |
7446 (1ull << MSR_FE0) |
7447 (1ull << MSR_SE) |
7448 (1ull << MSR_DE) |
7449 (1ull << MSR_FE1) |
7450 (1ull << MSR_IR) |
7451 (1ull << MSR_DR) |
7452 (1ull << MSR_PMM) |
7453 (1ull << MSR_RI);
7454 pcc->mmu_model = POWERPC_MMU_64B;
7455 #if defined(CONFIG_SOFTMMU)
7456 pcc->hash64_opts = &ppc_hash64_opts_basic;
7457 #endif
7458 pcc->excp_model = POWERPC_EXCP_970;
7459 pcc->bus_model = PPC_FLAGS_INPUT_970;
7460 pcc->bfd_mach = bfd_mach_ppc64;
7461 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7462 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7463 POWERPC_FLAG_BUS_CLK;
7464 pcc->l1_dcache_size = 0x8000;
7465 pcc->l1_icache_size = 0x10000;
7466 }
7467
7468 static void init_proc_power5plus(CPUPPCState *env)
7469 {
7470 /* Common Registers */
7471 init_proc_book3s_common(env);
7472 register_sdr1_sprs(env);
7473 register_book3s_dbg_sprs(env);
7474
7475 /* POWER5+ Specific Registers */
7476 register_970_hid_sprs(env);
7477 register_970_hior_sprs(env);
7478 register_low_BATs(env);
7479 register_970_pmu_sup_sprs(env);
7480 register_970_pmu_user_sprs(env);
7481 register_power5p_common_sprs(env);
7482 register_power5p_lpar_sprs(env);
7483 register_power5p_ear_sprs(env);
7484 register_power5p_tb_sprs(env);
7485
7486 /* env variables */
7487 env->dcache_line_size = 128;
7488 env->icache_line_size = 128;
7489
7490 /* Allocate hardware IRQ controller */
7491 init_excp_970(env);
7492 ppc970_irq_init(env_archcpu(env));
7493 }
7494
7495 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7496 {
7497 DeviceClass *dc = DEVICE_CLASS(oc);
7498 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7499
7500 dc->fw_name = "PowerPC,POWER5";
7501 dc->desc = "POWER5+";
7502 pcc->init_proc = init_proc_power5plus;
7503 pcc->check_pow = check_pow_970;
7504 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7505 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7506 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7507 PPC_FLOAT_STFIWX |
7508 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7509 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7510 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7511 PPC_64B |
7512 PPC_SEGMENT_64B | PPC_SLBI;
7513 pcc->insns_flags2 = PPC2_FP_CVT_S64;
7514 pcc->msr_mask = (1ull << MSR_SF) |
7515 (1ull << MSR_VR) |
7516 (1ull << MSR_POW) |
7517 (1ull << MSR_EE) |
7518 (1ull << MSR_PR) |
7519 (1ull << MSR_FP) |
7520 (1ull << MSR_ME) |
7521 (1ull << MSR_FE0) |
7522 (1ull << MSR_SE) |
7523 (1ull << MSR_DE) |
7524 (1ull << MSR_FE1) |
7525 (1ull << MSR_IR) |
7526 (1ull << MSR_DR) |
7527 (1ull << MSR_PMM) |
7528 (1ull << MSR_RI);
7529 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
7530 LPCR_RMI | LPCR_HDICE;
7531 pcc->mmu_model = POWERPC_MMU_2_03;
7532 #if defined(CONFIG_SOFTMMU)
7533 pcc->hash64_opts = &ppc_hash64_opts_basic;
7534 pcc->lrg_decr_bits = 32;
7535 #endif
7536 pcc->excp_model = POWERPC_EXCP_970;
7537 pcc->bus_model = PPC_FLAGS_INPUT_970;
7538 pcc->bfd_mach = bfd_mach_ppc64;
7539 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7540 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7541 POWERPC_FLAG_BUS_CLK;
7542 pcc->l1_dcache_size = 0x8000;
7543 pcc->l1_icache_size = 0x10000;
7544 }
7545
7546 static void init_proc_POWER7(CPUPPCState *env)
7547 {
7548 /* Common Registers */
7549 init_proc_book3s_common(env);
7550 register_sdr1_sprs(env);
7551 register_book3s_dbg_sprs(env);
7552
7553 /* POWER7 Specific Registers */
7554 register_book3s_ids_sprs(env);
7555 register_rmor_sprs(env);
7556 register_amr_sprs(env);
7557 register_book3s_purr_sprs(env);
7558 register_power5p_common_sprs(env);
7559 register_power5p_lpar_sprs(env);
7560 register_power5p_ear_sprs(env);
7561 register_power5p_tb_sprs(env);
7562 register_power6_common_sprs(env);
7563 register_power6_dbg_sprs(env);
7564 register_power7_book4_sprs(env);
7565
7566 /* env variables */
7567 env->dcache_line_size = 128;
7568 env->icache_line_size = 128;
7569
7570 /* Allocate hardware IRQ controller */
7571 init_excp_POWER7(env);
7572 ppcPOWER7_irq_init(env_archcpu(env));
7573 }
7574
7575 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
7576 {
7577 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
7578 return true;
7579 }
7580 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
7581 return true;
7582 }
7583 return false;
7584 }
7585
7586 static bool cpu_has_work_POWER7(CPUState *cs)
7587 {
7588 PowerPCCPU *cpu = POWERPC_CPU(cs);
7589 CPUPPCState *env = &cpu->env;
7590
7591 if (cs->halted) {
7592 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7593 return false;
7594 }
7595 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7596 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
7597 return true;
7598 }
7599 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7600 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
7601 return true;
7602 }
7603 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7604 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7605 return true;
7606 }
7607 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7608 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7609 return true;
7610 }
7611 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7612 return true;
7613 }
7614 return false;
7615 } else {
7616 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7617 }
7618 }
7619
7620 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7621 {
7622 DeviceClass *dc = DEVICE_CLASS(oc);
7623 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7624 CPUClass *cc = CPU_CLASS(oc);
7625
7626 dc->fw_name = "PowerPC,POWER7";
7627 dc->desc = "POWER7";
7628 pcc->pvr_match = ppc_pvr_match_power7;
7629 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
7630 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7631 pcc->init_proc = init_proc_POWER7;
7632 pcc->check_pow = check_pow_nocheck;
7633 cc->has_work = cpu_has_work_POWER7;
7634 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7635 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7636 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7637 PPC_FLOAT_FRSQRTES |
7638 PPC_FLOAT_STFIWX |
7639 PPC_FLOAT_EXT |
7640 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7641 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7642 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7643 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7644 PPC_SEGMENT_64B | PPC_SLBI |
7645 PPC_POPCNTB | PPC_POPCNTWD |
7646 PPC_CILDST;
7647 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7648 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7649 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7650 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
7651 PPC2_PM_ISA206;
7652 pcc->msr_mask = (1ull << MSR_SF) |
7653 (1ull << MSR_VR) |
7654 (1ull << MSR_VSX) |
7655 (1ull << MSR_EE) |
7656 (1ull << MSR_PR) |
7657 (1ull << MSR_FP) |
7658 (1ull << MSR_ME) |
7659 (1ull << MSR_FE0) |
7660 (1ull << MSR_SE) |
7661 (1ull << MSR_DE) |
7662 (1ull << MSR_FE1) |
7663 (1ull << MSR_IR) |
7664 (1ull << MSR_DR) |
7665 (1ull << MSR_PMM) |
7666 (1ull << MSR_RI) |
7667 (1ull << MSR_LE);
7668 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
7669 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7670 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
7671 LPCR_MER | LPCR_TC |
7672 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
7673 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
7674 pcc->mmu_model = POWERPC_MMU_2_06;
7675 #if defined(CONFIG_SOFTMMU)
7676 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7677 pcc->lrg_decr_bits = 32;
7678 #endif
7679 pcc->excp_model = POWERPC_EXCP_POWER7;
7680 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7681 pcc->bfd_mach = bfd_mach_ppc64;
7682 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7683 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7684 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7685 POWERPC_FLAG_VSX;
7686 pcc->l1_dcache_size = 0x8000;
7687 pcc->l1_icache_size = 0x8000;
7688 }
7689
7690 static void init_proc_POWER8(CPUPPCState *env)
7691 {
7692 /* Common Registers */
7693 init_proc_book3s_common(env);
7694 register_sdr1_sprs(env);
7695 register_book3s_207_dbg_sprs(env);
7696
7697 /* POWER8 Specific Registers */
7698 register_book3s_ids_sprs(env);
7699 register_rmor_sprs(env);
7700 register_amr_sprs(env);
7701 register_iamr_sprs(env);
7702 register_book3s_purr_sprs(env);
7703 register_power5p_common_sprs(env);
7704 register_power5p_lpar_sprs(env);
7705 register_power5p_ear_sprs(env);
7706 register_power5p_tb_sprs(env);
7707 register_power6_common_sprs(env);
7708 register_power6_dbg_sprs(env);
7709 register_power8_tce_address_control_sprs(env);
7710 register_power8_ids_sprs(env);
7711 register_power8_ebb_sprs(env);
7712 register_power8_fscr_sprs(env);
7713 register_power8_pmu_sup_sprs(env);
7714 register_power8_pmu_user_sprs(env);
7715 register_power8_tm_sprs(env);
7716 register_power8_pspb_sprs(env);
7717 register_power8_dpdes_sprs(env);
7718 register_vtb_sprs(env);
7719 register_power8_ic_sprs(env);
7720 register_power8_book4_sprs(env);
7721 register_power8_rpr_sprs(env);
7722
7723 /* env variables */
7724 env->dcache_line_size = 128;
7725 env->icache_line_size = 128;
7726
7727 /* Allocate hardware IRQ controller */
7728 init_excp_POWER8(env);
7729 ppcPOWER7_irq_init(env_archcpu(env));
7730 }
7731
7732 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
7733 {
7734 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
7735 return true;
7736 }
7737 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
7738 return true;
7739 }
7740 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
7741 return true;
7742 }
7743 return false;
7744 }
7745
7746 static bool cpu_has_work_POWER8(CPUState *cs)
7747 {
7748 PowerPCCPU *cpu = POWERPC_CPU(cs);
7749 CPUPPCState *env = &cpu->env;
7750
7751 if (cs->halted) {
7752 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7753 return false;
7754 }
7755 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7756 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
7757 return true;
7758 }
7759 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7760 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
7761 return true;
7762 }
7763 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7764 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7765 return true;
7766 }
7767 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7768 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7769 return true;
7770 }
7771 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7772 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
7773 return true;
7774 }
7775 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7776 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
7777 return true;
7778 }
7779 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7780 return true;
7781 }
7782 return false;
7783 } else {
7784 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7785 }
7786 }
7787
7788 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7789 {
7790 DeviceClass *dc = DEVICE_CLASS(oc);
7791 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7792 CPUClass *cc = CPU_CLASS(oc);
7793
7794 dc->fw_name = "PowerPC,POWER8";
7795 dc->desc = "POWER8";
7796 pcc->pvr_match = ppc_pvr_match_power8;
7797 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7798 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7799 pcc->init_proc = init_proc_POWER8;
7800 pcc->check_pow = check_pow_nocheck;
7801 cc->has_work = cpu_has_work_POWER8;
7802 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7803 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7804 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7805 PPC_FLOAT_FRSQRTES |
7806 PPC_FLOAT_STFIWX |
7807 PPC_FLOAT_EXT |
7808 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7809 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7810 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7811 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7812 PPC_SEGMENT_64B | PPC_SLBI |
7813 PPC_POPCNTB | PPC_POPCNTWD |
7814 PPC_CILDST;
7815 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7816 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7817 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7818 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7819 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7820 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7821 PPC2_TM | PPC2_PM_ISA206;
7822 pcc->msr_mask = (1ull << MSR_SF) |
7823 (1ull << MSR_HV) |
7824 (1ull << MSR_TM) |
7825 (1ull << MSR_VR) |
7826 (1ull << MSR_VSX) |
7827 (1ull << MSR_EE) |
7828 (1ull << MSR_PR) |
7829 (1ull << MSR_FP) |
7830 (1ull << MSR_ME) |
7831 (1ull << MSR_FE0) |
7832 (1ull << MSR_SE) |
7833 (1ull << MSR_DE) |
7834 (1ull << MSR_FE1) |
7835 (1ull << MSR_IR) |
7836 (1ull << MSR_DR) |
7837 (1ull << MSR_PMM) |
7838 (1ull << MSR_RI) |
7839 (1ull << MSR_TS0) |
7840 (1ull << MSR_TS1) |
7841 (1ull << MSR_LE);
7842 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
7843 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7844 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
7845 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
7846 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
7847 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
7848 LPCR_P8_PECE3 | LPCR_P8_PECE4;
7849 pcc->mmu_model = POWERPC_MMU_2_07;
7850 #if defined(CONFIG_SOFTMMU)
7851 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7852 pcc->lrg_decr_bits = 32;
7853 pcc->n_host_threads = 8;
7854 #endif
7855 pcc->excp_model = POWERPC_EXCP_POWER8;
7856 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7857 pcc->bfd_mach = bfd_mach_ppc64;
7858 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7859 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7860 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7861 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
7862 pcc->l1_dcache_size = 0x8000;
7863 pcc->l1_icache_size = 0x8000;
7864 }
7865
7866 #ifdef CONFIG_SOFTMMU
7867 /*
7868 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
7869 * Encoded as array of int_32s in the form:
7870 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
7871 * x -> AP encoding
7872 * y -> radix mode supported page size (encoded as a shift)
7873 */
7874 static struct ppc_radix_page_info POWER9_radix_page_info = {
7875 .count = 4,
7876 .entries = {
7877 0x0000000c, /* 4K - enc: 0x0 */
7878 0xa0000010, /* 64K - enc: 0x5 */
7879 0x20000015, /* 2M - enc: 0x1 */
7880 0x4000001e /* 1G - enc: 0x2 */
7881 }
7882 };
7883 #endif /* CONFIG_SOFTMMU */
7884
7885 static void init_proc_POWER9(CPUPPCState *env)
7886 {
7887 /* Common Registers */
7888 init_proc_book3s_common(env);
7889 register_book3s_207_dbg_sprs(env);
7890
7891 /* POWER8 Specific Registers */
7892 register_book3s_ids_sprs(env);
7893 register_amr_sprs(env);
7894 register_iamr_sprs(env);
7895 register_book3s_purr_sprs(env);
7896 register_power5p_common_sprs(env);
7897 register_power5p_lpar_sprs(env);
7898 register_power5p_ear_sprs(env);
7899 register_power5p_tb_sprs(env);
7900 register_power6_common_sprs(env);
7901 register_power6_dbg_sprs(env);
7902 register_power8_tce_address_control_sprs(env);
7903 register_power8_ids_sprs(env);
7904 register_power8_ebb_sprs(env);
7905 register_power8_fscr_sprs(env);
7906 register_power8_pmu_sup_sprs(env);
7907 register_power8_pmu_user_sprs(env);
7908 register_power8_tm_sprs(env);
7909 register_power8_pspb_sprs(env);
7910 register_power8_dpdes_sprs(env);
7911 register_vtb_sprs(env);
7912 register_power8_ic_sprs(env);
7913 register_power8_book4_sprs(env);
7914 register_power8_rpr_sprs(env);
7915 register_power9_mmu_sprs(env);
7916
7917 /* POWER9 Specific registers */
7918 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
7919 spr_read_generic, spr_write_generic,
7920 KVM_REG_PPC_TIDR, 0);
7921
7922 /* FIXME: Filter fields properly based on privilege level */
7923 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7924 spr_read_generic, spr_write_generic,
7925 KVM_REG_PPC_PSSCR, 0);
7926
7927 /* env variables */
7928 env->dcache_line_size = 128;
7929 env->icache_line_size = 128;
7930
7931 /* Allocate hardware IRQ controller */
7932 init_excp_POWER9(env);
7933 ppcPOWER9_irq_init(env_archcpu(env));
7934 }
7935
7936 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
7937 {
7938 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
7939 return true;
7940 }
7941 return false;
7942 }
7943
7944 static bool cpu_has_work_POWER9(CPUState *cs)
7945 {
7946 PowerPCCPU *cpu = POWERPC_CPU(cs);
7947 CPUPPCState *env = &cpu->env;
7948
7949 if (cs->halted) {
7950 uint64_t psscr = env->spr[SPR_PSSCR];
7951
7952 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7953 return false;
7954 }
7955
7956 /* If EC is clear, just return true on any pending interrupt */
7957 if (!(psscr & PSSCR_EC)) {
7958 return true;
7959 }
7960 /* External Exception */
7961 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7962 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7963 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7964 if (heic == 0 || !msr_hv || msr_pr) {
7965 return true;
7966 }
7967 }
7968 /* Decrementer Exception */
7969 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7970 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7971 return true;
7972 }
7973 /* Machine Check or Hypervisor Maintenance Exception */
7974 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7975 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7976 return true;
7977 }
7978 /* Privileged Doorbell Exception */
7979 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7980 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7981 return true;
7982 }
7983 /* Hypervisor Doorbell Exception */
7984 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7985 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7986 return true;
7987 }
7988 /* Hypervisor virtualization exception */
7989 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7990 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7991 return true;
7992 }
7993 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7994 return true;
7995 }
7996 return false;
7997 } else {
7998 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7999 }
8000 }
8001
8002 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8003 {
8004 DeviceClass *dc = DEVICE_CLASS(oc);
8005 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8006 CPUClass *cc = CPU_CLASS(oc);
8007
8008 dc->fw_name = "PowerPC,POWER9";
8009 dc->desc = "POWER9";
8010 pcc->pvr_match = ppc_pvr_match_power9;
8011 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8012 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8013 PCR_COMPAT_2_05;
8014 pcc->init_proc = init_proc_POWER9;
8015 pcc->check_pow = check_pow_nocheck;
8016 cc->has_work = cpu_has_work_POWER9;
8017 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8018 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8019 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8020 PPC_FLOAT_FRSQRTES |
8021 PPC_FLOAT_STFIWX |
8022 PPC_FLOAT_EXT |
8023 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8024 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8025 PPC_MEM_TLBSYNC |
8026 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8027 PPC_SEGMENT_64B | PPC_SLBI |
8028 PPC_POPCNTB | PPC_POPCNTWD |
8029 PPC_CILDST;
8030 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8031 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8032 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8033 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8034 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8035 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8036 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
8037 pcc->msr_mask = (1ull << MSR_SF) |
8038 (1ull << MSR_HV) |
8039 (1ull << MSR_TM) |
8040 (1ull << MSR_VR) |
8041 (1ull << MSR_VSX) |
8042 (1ull << MSR_EE) |
8043 (1ull << MSR_PR) |
8044 (1ull << MSR_FP) |
8045 (1ull << MSR_ME) |
8046 (1ull << MSR_FE0) |
8047 (1ull << MSR_SE) |
8048 (1ull << MSR_DE) |
8049 (1ull << MSR_FE1) |
8050 (1ull << MSR_IR) |
8051 (1ull << MSR_DR) |
8052 (1ull << MSR_PMM) |
8053 (1ull << MSR_RI) |
8054 (1ull << MSR_LE);
8055 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8056 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8057 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8058 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8059 LPCR_DEE | LPCR_OEE))
8060 | LPCR_MER | LPCR_GTSE | LPCR_TC |
8061 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8062 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8063 pcc->mmu_model = POWERPC_MMU_3_00;
8064 #if defined(CONFIG_SOFTMMU)
8065 /* segment page size remain the same */
8066 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8067 pcc->radix_page_info = &POWER9_radix_page_info;
8068 pcc->lrg_decr_bits = 56;
8069 pcc->n_host_threads = 4;
8070 #endif
8071 pcc->excp_model = POWERPC_EXCP_POWER9;
8072 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8073 pcc->bfd_mach = bfd_mach_ppc64;
8074 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8075 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8076 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8077 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8078 pcc->l1_dcache_size = 0x8000;
8079 pcc->l1_icache_size = 0x8000;
8080 }
8081
8082 #ifdef CONFIG_SOFTMMU
8083 /*
8084 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8085 * Encoded as array of int_32s in the form:
8086 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8087 * x -> AP encoding
8088 * y -> radix mode supported page size (encoded as a shift)
8089 */
8090 static struct ppc_radix_page_info POWER10_radix_page_info = {
8091 .count = 4,
8092 .entries = {
8093 0x0000000c, /* 4K - enc: 0x0 */
8094 0xa0000010, /* 64K - enc: 0x5 */
8095 0x20000015, /* 2M - enc: 0x1 */
8096 0x4000001e /* 1G - enc: 0x2 */
8097 }
8098 };
8099 #endif /* CONFIG_SOFTMMU */
8100
8101 static void init_proc_POWER10(CPUPPCState *env)
8102 {
8103 /* Common Registers */
8104 init_proc_book3s_common(env);
8105 register_book3s_207_dbg_sprs(env);
8106
8107 /* POWER8 Specific Registers */
8108 register_book3s_ids_sprs(env);
8109 register_amr_sprs(env);
8110 register_iamr_sprs(env);
8111 register_book3s_purr_sprs(env);
8112 register_power5p_common_sprs(env);
8113 register_power5p_lpar_sprs(env);
8114 register_power5p_ear_sprs(env);
8115 register_power6_common_sprs(env);
8116 register_power6_dbg_sprs(env);
8117 register_power8_tce_address_control_sprs(env);
8118 register_power8_ids_sprs(env);
8119 register_power8_ebb_sprs(env);
8120 register_power8_fscr_sprs(env);
8121 register_power8_pmu_sup_sprs(env);
8122 register_power8_pmu_user_sprs(env);
8123 register_power8_tm_sprs(env);
8124 register_power8_pspb_sprs(env);
8125 register_vtb_sprs(env);
8126 register_power8_ic_sprs(env);
8127 register_power8_book4_sprs(env);
8128 register_power8_rpr_sprs(env);
8129 register_power9_mmu_sprs(env);
8130
8131 /* FIXME: Filter fields properly based on privilege level */
8132 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8133 spr_read_generic, spr_write_generic,
8134 KVM_REG_PPC_PSSCR, 0);
8135
8136 /* env variables */
8137 env->dcache_line_size = 128;
8138 env->icache_line_size = 128;
8139
8140 /* Allocate hardware IRQ controller */
8141 init_excp_POWER10(env);
8142 ppcPOWER9_irq_init(env_archcpu(env));
8143 }
8144
8145 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
8146 {
8147 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
8148 return true;
8149 }
8150 return false;
8151 }
8152
8153 static bool cpu_has_work_POWER10(CPUState *cs)
8154 {
8155 PowerPCCPU *cpu = POWERPC_CPU(cs);
8156 CPUPPCState *env = &cpu->env;
8157
8158 if (cs->halted) {
8159 uint64_t psscr = env->spr[SPR_PSSCR];
8160
8161 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8162 return false;
8163 }
8164
8165 /* If EC is clear, just return true on any pending interrupt */
8166 if (!(psscr & PSSCR_EC)) {
8167 return true;
8168 }
8169 /* External Exception */
8170 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8171 (env->spr[SPR_LPCR] & LPCR_EEE)) {
8172 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8173 if (heic == 0 || !msr_hv || msr_pr) {
8174 return true;
8175 }
8176 }
8177 /* Decrementer Exception */
8178 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8179 (env->spr[SPR_LPCR] & LPCR_DEE)) {
8180 return true;
8181 }
8182 /* Machine Check or Hypervisor Maintenance Exception */
8183 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8184 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8185 return true;
8186 }
8187 /* Privileged Doorbell Exception */
8188 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8189 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8190 return true;
8191 }
8192 /* Hypervisor Doorbell Exception */
8193 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8194 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8195 return true;
8196 }
8197 /* Hypervisor virtualization exception */
8198 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8199 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8200 return true;
8201 }
8202 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8203 return true;
8204 }
8205 return false;
8206 } else {
8207 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8208 }
8209 }
8210
8211 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
8212 {
8213 DeviceClass *dc = DEVICE_CLASS(oc);
8214 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8215 CPUClass *cc = CPU_CLASS(oc);
8216
8217 dc->fw_name = "PowerPC,POWER10";
8218 dc->desc = "POWER10";
8219 pcc->pvr_match = ppc_pvr_match_power10;
8220 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
8221 PCR_COMPAT_3_00;
8222 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
8223 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8224 pcc->init_proc = init_proc_POWER10;
8225 pcc->check_pow = check_pow_nocheck;
8226 cc->has_work = cpu_has_work_POWER10;
8227 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8228 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8229 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8230 PPC_FLOAT_FRSQRTES |
8231 PPC_FLOAT_STFIWX |
8232 PPC_FLOAT_EXT |
8233 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8234 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8235 PPC_MEM_TLBSYNC |
8236 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8237 PPC_SEGMENT_64B | PPC_SLBI |
8238 PPC_POPCNTB | PPC_POPCNTWD |
8239 PPC_CILDST;
8240 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8241 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8242 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8243 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8244 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8245 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8246 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
8247 pcc->msr_mask = (1ull << MSR_SF) |
8248 (1ull << MSR_HV) |
8249 (1ull << MSR_TM) |
8250 (1ull << MSR_VR) |
8251 (1ull << MSR_VSX) |
8252 (1ull << MSR_EE) |
8253 (1ull << MSR_PR) |
8254 (1ull << MSR_FP) |
8255 (1ull << MSR_ME) |
8256 (1ull << MSR_FE0) |
8257 (1ull << MSR_SE) |
8258 (1ull << MSR_DE) |
8259 (1ull << MSR_FE1) |
8260 (1ull << MSR_IR) |
8261 (1ull << MSR_DR) |
8262 (1ull << MSR_PMM) |
8263 (1ull << MSR_RI) |
8264 (1ull << MSR_LE);
8265 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8266 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8267 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8268 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8269 LPCR_DEE | LPCR_OEE))
8270 | LPCR_MER | LPCR_GTSE | LPCR_TC |
8271 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8272 /* DD2 adds an extra HAIL bit */
8273 pcc->lpcr_mask |= LPCR_HAIL;
8274
8275 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8276 pcc->mmu_model = POWERPC_MMU_3_00;
8277 #if defined(CONFIG_SOFTMMU)
8278 /* segment page size remain the same */
8279 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8280 pcc->radix_page_info = &POWER10_radix_page_info;
8281 pcc->lrg_decr_bits = 56;
8282 #endif
8283 pcc->excp_model = POWERPC_EXCP_POWER10;
8284 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8285 pcc->bfd_mach = bfd_mach_ppc64;
8286 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8287 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8288 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8289 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8290 pcc->l1_dcache_size = 0x8000;
8291 pcc->l1_icache_size = 0x8000;
8292 }
8293
8294 #if !defined(CONFIG_USER_ONLY)
8295 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8296 {
8297 CPUPPCState *env = &cpu->env;
8298
8299 cpu->vhyp = vhyp;
8300
8301 /*
8302 * With a virtual hypervisor mode we never allow the CPU to go
8303 * hypervisor mode itself
8304 */
8305 env->msr_mask &= ~MSR_HVB;
8306 }
8307
8308 #endif /* !defined(CONFIG_USER_ONLY) */
8309
8310 #endif /* defined(TARGET_PPC64) */
8311
8312 /*****************************************************************************/
8313 /* Generic CPU instantiation routine */
8314 static void init_ppc_proc(PowerPCCPU *cpu)
8315 {
8316 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8317 CPUPPCState *env = &cpu->env;
8318 #if !defined(CONFIG_USER_ONLY)
8319 int i;
8320
8321 env->irq_inputs = NULL;
8322 /* Set all exception vectors to an invalid address */
8323 for (i = 0; i < POWERPC_EXCP_NB; i++) {
8324 env->excp_vectors[i] = (target_ulong)(-1ULL);
8325 }
8326 env->ivor_mask = 0x00000000;
8327 env->ivpr_mask = 0x00000000;
8328 /* Default MMU definitions */
8329 env->nb_BATs = 0;
8330 env->nb_tlb = 0;
8331 env->nb_ways = 0;
8332 env->tlb_type = TLB_NONE;
8333 #endif
8334 /* Register SPR common to all PowerPC implementations */
8335 register_generic_sprs(env);
8336 spr_register(env, SPR_PVR, "PVR",
8337 /* Linux permits userspace to read PVR */
8338 #if defined(CONFIG_LINUX_USER)
8339 &spr_read_generic,
8340 #else
8341 SPR_NOACCESS,
8342 #endif
8343 SPR_NOACCESS,
8344 &spr_read_generic, SPR_NOACCESS,
8345 pcc->pvr);
8346 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8347 if (pcc->svr != POWERPC_SVR_NONE) {
8348 if (pcc->svr & POWERPC_SVR_E500) {
8349 spr_register(env, SPR_E500_SVR, "SVR",
8350 SPR_NOACCESS, SPR_NOACCESS,
8351 &spr_read_generic, SPR_NOACCESS,
8352 pcc->svr & ~POWERPC_SVR_E500);
8353 } else {
8354 spr_register(env, SPR_SVR, "SVR",
8355 SPR_NOACCESS, SPR_NOACCESS,
8356 &spr_read_generic, SPR_NOACCESS,
8357 pcc->svr);
8358 }
8359 }
8360 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8361 (*pcc->init_proc)(env);
8362
8363 #if !defined(CONFIG_USER_ONLY)
8364 ppc_gdb_gen_spr_xml(cpu);
8365 #endif
8366
8367 /* MSR bits & flags consistency checks */
8368 if (env->msr_mask & (1 << 25)) {
8369 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8370 case POWERPC_FLAG_SPE:
8371 case POWERPC_FLAG_VRE:
8372 break;
8373 default:
8374 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8375 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8376 exit(1);
8377 }
8378 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8379 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8380 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8381 exit(1);
8382 }
8383 if (env->msr_mask & (1 << 17)) {
8384 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8385 case POWERPC_FLAG_TGPR:
8386 case POWERPC_FLAG_CE:
8387 break;
8388 default:
8389 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8390 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8391 exit(1);
8392 }
8393 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8394 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8395 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8396 exit(1);
8397 }
8398 if (env->msr_mask & (1 << 10)) {
8399 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8400 POWERPC_FLAG_UBLE)) {
8401 case POWERPC_FLAG_SE:
8402 case POWERPC_FLAG_DWE:
8403 case POWERPC_FLAG_UBLE:
8404 break;
8405 default:
8406 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8407 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8408 "POWERPC_FLAG_UBLE\n");
8409 exit(1);
8410 }
8411 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8412 POWERPC_FLAG_UBLE)) {
8413 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8414 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8415 "POWERPC_FLAG_UBLE\n");
8416 exit(1);
8417 }
8418 if (env->msr_mask & (1 << 9)) {
8419 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8420 case POWERPC_FLAG_BE:
8421 case POWERPC_FLAG_DE:
8422 break;
8423 default:
8424 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8425 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8426 exit(1);
8427 }
8428 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8429 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8430 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8431 exit(1);
8432 }
8433 if (env->msr_mask & (1 << 2)) {
8434 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8435 case POWERPC_FLAG_PX:
8436 case POWERPC_FLAG_PMM:
8437 break;
8438 default:
8439 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8440 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8441 exit(1);
8442 }
8443 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8444 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8445 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8446 exit(1);
8447 }
8448 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8449 fprintf(stderr, "PowerPC flags inconsistency\n"
8450 "Should define the time-base and decrementer clock source\n");
8451 exit(1);
8452 }
8453 /* Allocate TLBs buffer when needed */
8454 #if !defined(CONFIG_USER_ONLY)
8455 if (env->nb_tlb != 0) {
8456 int nb_tlb = env->nb_tlb;
8457 if (env->id_tlbs != 0) {
8458 nb_tlb *= 2;
8459 }
8460 switch (env->tlb_type) {
8461 case TLB_6XX:
8462 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
8463 break;
8464 case TLB_EMB:
8465 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
8466 break;
8467 case TLB_MAS:
8468 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
8469 break;
8470 }
8471 /* Pre-compute some useful values */
8472 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8473 }
8474 if (env->irq_inputs == NULL) {
8475 warn_report("no internal IRQ controller registered."
8476 " Attempt QEMU to crash very soon !");
8477 }
8478 #endif
8479 if (env->check_pow == NULL) {
8480 warn_report("no power management check handler registered."
8481 " Attempt QEMU to crash very soon !");
8482 }
8483 }
8484
8485
8486 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
8487 {
8488 CPUState *cs = CPU(dev);
8489 PowerPCCPU *cpu = POWERPC_CPU(dev);
8490 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8491 Error *local_err = NULL;
8492
8493 cpu_exec_realizefn(cs, &local_err);
8494 if (local_err != NULL) {
8495 error_propagate(errp, local_err);
8496 return;
8497 }
8498 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
8499 cpu->vcpu_id = cs->cpu_index;
8500 }
8501
8502 if (tcg_enabled()) {
8503 if (ppc_fixup_cpu(cpu) != 0) {
8504 error_setg(errp, "Unable to emulate selected CPU with TCG");
8505 goto unrealize;
8506 }
8507 }
8508
8509 create_ppc_opcodes(cpu, &local_err);
8510 if (local_err != NULL) {
8511 error_propagate(errp, local_err);
8512 goto unrealize;
8513 }
8514 init_ppc_proc(cpu);
8515
8516 ppc_gdb_init(cs, pcc);
8517 qemu_init_vcpu(cs);
8518
8519 pcc->parent_realize(dev, errp);
8520
8521 return;
8522
8523 unrealize:
8524 cpu_exec_unrealizefn(cs);
8525 }
8526
8527 static void ppc_cpu_unrealize(DeviceState *dev)
8528 {
8529 PowerPCCPU *cpu = POWERPC_CPU(dev);
8530 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8531
8532 pcc->parent_unrealize(dev);
8533
8534 cpu_remove_sync(CPU(cpu));
8535
8536 destroy_ppc_opcodes(cpu);
8537 }
8538
8539 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8540 {
8541 ObjectClass *oc = (ObjectClass *)a;
8542 uint32_t pvr = *(uint32_t *)b;
8543 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8544
8545 /* -cpu host does a PVR lookup during construction */
8546 if (unlikely(strcmp(object_class_get_name(oc),
8547 TYPE_HOST_POWERPC_CPU) == 0)) {
8548 return -1;
8549 }
8550
8551 return pcc->pvr == pvr ? 0 : -1;
8552 }
8553
8554 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8555 {
8556 GSList *list, *item;
8557 PowerPCCPUClass *pcc = NULL;
8558
8559 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8560 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8561 if (item != NULL) {
8562 pcc = POWERPC_CPU_CLASS(item->data);
8563 }
8564 g_slist_free(list);
8565
8566 return pcc;
8567 }
8568
8569 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8570 {
8571 ObjectClass *oc = (ObjectClass *)a;
8572 uint32_t pvr = *(uint32_t *)b;
8573 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8574
8575 /* -cpu host does a PVR lookup during construction */
8576 if (unlikely(strcmp(object_class_get_name(oc),
8577 TYPE_HOST_POWERPC_CPU) == 0)) {
8578 return -1;
8579 }
8580
8581 if (pcc->pvr_match(pcc, pvr)) {
8582 return 0;
8583 }
8584
8585 return -1;
8586 }
8587
8588 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8589 {
8590 GSList *list, *item;
8591 PowerPCCPUClass *pcc = NULL;
8592
8593 list = object_class_get_list(TYPE_POWERPC_CPU, true);
8594 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8595 if (item != NULL) {
8596 pcc = POWERPC_CPU_CLASS(item->data);
8597 }
8598 g_slist_free(list);
8599
8600 return pcc;
8601 }
8602
8603 static const char *ppc_cpu_lookup_alias(const char *alias)
8604 {
8605 int ai;
8606
8607 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
8608 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
8609 return ppc_cpu_aliases[ai].model;
8610 }
8611 }
8612
8613 return NULL;
8614 }
8615
8616 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8617 {
8618 char *cpu_model, *typename;
8619 ObjectClass *oc;
8620 const char *p;
8621 unsigned long pvr;
8622
8623 /*
8624 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
8625 * 0x prefix if present)
8626 */
8627 if (!qemu_strtoul(name, &p, 16, &pvr)) {
8628 int len = p - name;
8629 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
8630 if ((len == 8) && (*p == '\0')) {
8631 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
8632 }
8633 }
8634
8635 cpu_model = g_ascii_strdown(name, -1);
8636 p = ppc_cpu_lookup_alias(cpu_model);
8637 if (p) {
8638 g_free(cpu_model);
8639 cpu_model = g_strdup(p);
8640 }
8641
8642 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
8643 oc = object_class_by_name(typename);
8644 g_free(typename);
8645 g_free(cpu_model);
8646
8647 return oc;
8648 }
8649
8650 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
8651 {
8652 ObjectClass *oc = OBJECT_CLASS(pcc);
8653
8654 while (oc && !object_class_is_abstract(oc)) {
8655 oc = object_class_get_parent(oc);
8656 }
8657 assert(oc);
8658
8659 return POWERPC_CPU_CLASS(oc);
8660 }
8661
8662 /* Sort by PVR, ordering special case "host" last. */
8663 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8664 {
8665 ObjectClass *oc_a = (ObjectClass *)a;
8666 ObjectClass *oc_b = (ObjectClass *)b;
8667 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8668 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8669 const char *name_a = object_class_get_name(oc_a);
8670 const char *name_b = object_class_get_name(oc_b);
8671
8672 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8673 return 1;
8674 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8675 return -1;
8676 } else {
8677 /* Avoid an integer overflow during subtraction */
8678 if (pcc_a->pvr < pcc_b->pvr) {
8679 return -1;
8680 } else if (pcc_a->pvr > pcc_b->pvr) {
8681 return 1;
8682 } else {
8683 return 0;
8684 }
8685 }
8686 }
8687
8688 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8689 {
8690 ObjectClass *oc = data;
8691 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8692 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
8693 const char *typename = object_class_get_name(oc);
8694 char *name;
8695 int i;
8696
8697 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8698 return;
8699 }
8700
8701 name = g_strndup(typename,
8702 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8703 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
8704 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8705 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8706 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8707
8708 if (alias_oc != oc) {
8709 continue;
8710 }
8711 /*
8712 * If running with KVM, we might update the family alias later, so
8713 * avoid printing the wrong alias here and use "preferred" instead
8714 */
8715 if (strcmp(alias->alias, family->desc) == 0) {
8716 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
8717 alias->alias, family->desc);
8718 } else {
8719 qemu_printf("PowerPC %-16s (alias for %s)\n",
8720 alias->alias, name);
8721 }
8722 }
8723 g_free(name);
8724 }
8725
8726 void ppc_cpu_list(void)
8727 {
8728 GSList *list;
8729
8730 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8731 list = g_slist_sort(list, ppc_cpu_list_compare);
8732 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
8733 g_slist_free(list);
8734
8735 #ifdef CONFIG_KVM
8736 qemu_printf("\n");
8737 qemu_printf("PowerPC %s\n", "host");
8738 #endif
8739 }
8740
8741 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8742 {
8743 ObjectClass *oc = data;
8744 CpuDefinitionInfoList **first = user_data;
8745 const char *typename;
8746 CpuDefinitionInfo *info;
8747
8748 typename = object_class_get_name(oc);
8749 info = g_malloc0(sizeof(*info));
8750 info->name = g_strndup(typename,
8751 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8752
8753 QAPI_LIST_PREPEND(*first, info);
8754 }
8755
8756 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
8757 {
8758 CpuDefinitionInfoList *cpu_list = NULL;
8759 GSList *list;
8760 int i;
8761
8762 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8763 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8764 g_slist_free(list);
8765
8766 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8767 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8768 ObjectClass *oc;
8769 CpuDefinitionInfo *info;
8770
8771 oc = ppc_cpu_class_by_name(alias->model);
8772 if (oc == NULL) {
8773 continue;
8774 }
8775
8776 info = g_malloc0(sizeof(*info));
8777 info->name = g_strdup(alias->alias);
8778 info->q_typename = g_strdup(object_class_get_name(oc));
8779
8780 QAPI_LIST_PREPEND(cpu_list, info);
8781 }
8782
8783 return cpu_list;
8784 }
8785
8786 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
8787 {
8788 PowerPCCPU *cpu = POWERPC_CPU(cs);
8789
8790 cpu->env.nip = value;
8791 }
8792
8793 static bool ppc_cpu_has_work(CPUState *cs)
8794 {
8795 PowerPCCPU *cpu = POWERPC_CPU(cs);
8796 CPUPPCState *env = &cpu->env;
8797
8798 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8799 }
8800
8801 static void ppc_cpu_reset(DeviceState *dev)
8802 {
8803 CPUState *s = CPU(dev);
8804 PowerPCCPU *cpu = POWERPC_CPU(s);
8805 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8806 CPUPPCState *env = &cpu->env;
8807 target_ulong msr;
8808 int i;
8809
8810 pcc->parent_reset(dev);
8811
8812 msr = (target_ulong)0;
8813 msr |= (target_ulong)MSR_HVB;
8814 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8815 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8816 msr |= (target_ulong)1 << MSR_EP;
8817 #if defined(DO_SINGLE_STEP) && 0
8818 /* Single step trace mode */
8819 msr |= (target_ulong)1 << MSR_SE;
8820 msr |= (target_ulong)1 << MSR_BE;
8821 #endif
8822 #if defined(CONFIG_USER_ONLY)
8823 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8824 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
8825 msr |= (target_ulong)1 << MSR_FE1;
8826 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8827 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
8828 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8829 msr |= (target_ulong)1 << MSR_PR;
8830 #if defined(TARGET_PPC64)
8831 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
8832 #endif
8833 #if !defined(TARGET_WORDS_BIGENDIAN)
8834 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
8835 if (!((env->msr_mask >> MSR_LE) & 1)) {
8836 fprintf(stderr, "Selected CPU does not support little-endian.\n");
8837 exit(1);
8838 }
8839 #endif
8840 #endif
8841
8842 #if defined(TARGET_PPC64)
8843 if (mmu_is_64bit(env->mmu_model)) {
8844 msr |= (1ULL << MSR_SF);
8845 }
8846 #endif
8847
8848 hreg_store_msr(env, msr, 1);
8849
8850 #if !defined(CONFIG_USER_ONLY)
8851 env->nip = env->hreset_vector | env->excp_prefix;
8852 #if defined(CONFIG_TCG)
8853 if (env->mmu_model != POWERPC_MMU_REAL) {
8854 ppc_tlb_invalidate_all(env);
8855 }
8856 #endif /* CONFIG_TCG */
8857 #endif
8858
8859 hreg_compute_hflags(env);
8860 env->reserve_addr = (target_ulong)-1ULL;
8861 /* Be sure no exception or interrupt is pending */
8862 env->pending_interrupts = 0;
8863 s->exception_index = POWERPC_EXCP_NONE;
8864 env->error_code = 0;
8865 ppc_irq_reset(cpu);
8866
8867 /* tininess for underflow is detected before rounding */
8868 set_float_detect_tininess(float_tininess_before_rounding,
8869 &env->fp_status);
8870
8871 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
8872 ppc_spr_t *spr = &env->spr_cb[i];
8873
8874 if (!spr->name) {
8875 continue;
8876 }
8877 env->spr[i] = spr->default_value;
8878 }
8879 }
8880
8881 #ifndef CONFIG_USER_ONLY
8882
8883 static bool ppc_cpu_is_big_endian(CPUState *cs)
8884 {
8885 PowerPCCPU *cpu = POWERPC_CPU(cs);
8886 CPUPPCState *env = &cpu->env;
8887
8888 cpu_synchronize_state(cs);
8889
8890 return !msr_le;
8891 }
8892
8893 #ifdef CONFIG_TCG
8894 static void ppc_cpu_exec_enter(CPUState *cs)
8895 {
8896 PowerPCCPU *cpu = POWERPC_CPU(cs);
8897
8898 if (cpu->vhyp) {
8899 PPCVirtualHypervisorClass *vhc =
8900 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
8901 vhc->cpu_exec_enter(cpu->vhyp, cpu);
8902 }
8903 }
8904
8905 static void ppc_cpu_exec_exit(CPUState *cs)
8906 {
8907 PowerPCCPU *cpu = POWERPC_CPU(cs);
8908
8909 if (cpu->vhyp) {
8910 PPCVirtualHypervisorClass *vhc =
8911 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
8912 vhc->cpu_exec_exit(cpu->vhyp, cpu);
8913 }
8914 }
8915 #endif /* CONFIG_TCG */
8916
8917 #endif /* !CONFIG_USER_ONLY */
8918
8919 static void ppc_cpu_instance_init(Object *obj)
8920 {
8921 PowerPCCPU *cpu = POWERPC_CPU(obj);
8922 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8923 CPUPPCState *env = &cpu->env;
8924
8925 cpu_set_cpustate_pointers(cpu);
8926 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
8927
8928 env->msr_mask = pcc->msr_mask;
8929 env->mmu_model = pcc->mmu_model;
8930 env->excp_model = pcc->excp_model;
8931 env->bus_model = pcc->bus_model;
8932 env->insns_flags = pcc->insns_flags;
8933 env->insns_flags2 = pcc->insns_flags2;
8934 env->flags = pcc->flags;
8935 env->bfd_mach = pcc->bfd_mach;
8936 env->check_pow = pcc->check_pow;
8937
8938 /*
8939 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
8940 * msr_mask. The mask can later be cleared by PAPR mode but the hv
8941 * mode support will remain, thus enforcing that we cannot use
8942 * priv. instructions in guest in PAPR mode. For 970 we currently
8943 * simply don't set HV in msr_mask thus simulating an "Apple mode"
8944 * 970. If we ever want to support 970 HV mode, we'll have to add
8945 * a processor attribute of some sort.
8946 */
8947 #if !defined(CONFIG_USER_ONLY)
8948 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
8949 #endif
8950
8951 ppc_hash64_init(cpu);
8952 }
8953
8954 static void ppc_cpu_instance_finalize(Object *obj)
8955 {
8956 PowerPCCPU *cpu = POWERPC_CPU(obj);
8957
8958 ppc_hash64_finalize(cpu);
8959 }
8960
8961 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
8962 {
8963 return pcc->pvr == pvr;
8964 }
8965
8966 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
8967 {
8968 PowerPCCPU *cpu = POWERPC_CPU(cs);
8969 CPUPPCState *env = &cpu->env;
8970
8971 if ((env->hflags >> MSR_LE) & 1) {
8972 info->endian = BFD_ENDIAN_LITTLE;
8973 }
8974 info->mach = env->bfd_mach;
8975 if (!env->bfd_mach) {
8976 #ifdef TARGET_PPC64
8977 info->mach = bfd_mach_ppc64;
8978 #else
8979 info->mach = bfd_mach_ppc;
8980 #endif
8981 }
8982 info->disassembler_options = (char *)"any";
8983 info->print_insn = print_insn_ppc;
8984
8985 info->cap_arch = CS_ARCH_PPC;
8986 #ifdef TARGET_PPC64
8987 info->cap_mode = CS_MODE_64;
8988 #endif
8989 }
8990
8991 static Property ppc_cpu_properties[] = {
8992 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
8993 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
8994 false),
8995 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
8996 false),
8997 DEFINE_PROP_END_OF_LIST(),
8998 };
8999
9000 #ifndef CONFIG_USER_ONLY
9001 #include "hw/core/sysemu-cpu-ops.h"
9002
9003 static const struct SysemuCPUOps ppc_sysemu_ops = {
9004 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
9005 .write_elf32_note = ppc32_cpu_write_elf32_note,
9006 .write_elf64_note = ppc64_cpu_write_elf64_note,
9007 .virtio_is_big_endian = ppc_cpu_is_big_endian,
9008 .legacy_vmsd = &vmstate_ppc_cpu,
9009 };
9010 #endif
9011
9012 #ifdef CONFIG_TCG
9013 #include "hw/core/tcg-cpu-ops.h"
9014
9015 static const struct TCGCPUOps ppc_tcg_ops = {
9016 .initialize = ppc_translate_init,
9017
9018 #ifdef CONFIG_USER_ONLY
9019 .record_sigsegv = ppc_cpu_record_sigsegv,
9020 #else
9021 .tlb_fill = ppc_cpu_tlb_fill,
9022 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
9023 .do_interrupt = ppc_cpu_do_interrupt,
9024 .cpu_exec_enter = ppc_cpu_exec_enter,
9025 .cpu_exec_exit = ppc_cpu_exec_exit,
9026 .do_unaligned_access = ppc_cpu_do_unaligned_access,
9027 #endif /* !CONFIG_USER_ONLY */
9028 };
9029 #endif /* CONFIG_TCG */
9030
9031 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9032 {
9033 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9034 CPUClass *cc = CPU_CLASS(oc);
9035 DeviceClass *dc = DEVICE_CLASS(oc);
9036
9037 device_class_set_parent_realize(dc, ppc_cpu_realize,
9038 &pcc->parent_realize);
9039 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
9040 &pcc->parent_unrealize);
9041 pcc->pvr_match = ppc_pvr_match_default;
9042 device_class_set_props(dc, ppc_cpu_properties);
9043
9044 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
9045
9046 cc->class_by_name = ppc_cpu_class_by_name;
9047 cc->has_work = ppc_cpu_has_work;
9048 cc->dump_state = ppc_cpu_dump_state;
9049 cc->set_pc = ppc_cpu_set_pc;
9050 cc->gdb_read_register = ppc_cpu_gdb_read_register;
9051 cc->gdb_write_register = ppc_cpu_gdb_write_register;
9052 #ifndef CONFIG_USER_ONLY
9053 cc->sysemu_ops = &ppc_sysemu_ops;
9054 #endif
9055
9056 cc->gdb_num_core_regs = 71;
9057 #ifndef CONFIG_USER_ONLY
9058 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
9059 #endif
9060 #ifdef USE_APPLE_GDB
9061 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
9062 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
9063 cc->gdb_num_core_regs = 71 + 32;
9064 #endif
9065
9066 cc->gdb_arch_name = ppc_gdb_arch_name;
9067 #if defined(TARGET_PPC64)
9068 cc->gdb_core_xml_file = "power64-core.xml";
9069 #else
9070 cc->gdb_core_xml_file = "power-core.xml";
9071 #endif
9072 cc->disas_set_info = ppc_disas_set_info;
9073
9074 dc->fw_name = "PowerPC,UNKNOWN";
9075
9076 #ifdef CONFIG_TCG
9077 cc->tcg_ops = &ppc_tcg_ops;
9078 #endif /* CONFIG_TCG */
9079 }
9080
9081 static const TypeInfo ppc_cpu_type_info = {
9082 .name = TYPE_POWERPC_CPU,
9083 .parent = TYPE_CPU,
9084 .instance_size = sizeof(PowerPCCPU),
9085 .instance_align = __alignof__(PowerPCCPU),
9086 .instance_init = ppc_cpu_instance_init,
9087 .instance_finalize = ppc_cpu_instance_finalize,
9088 .abstract = true,
9089 .class_size = sizeof(PowerPCCPUClass),
9090 .class_init = ppc_cpu_class_init,
9091 };
9092
9093 #ifndef CONFIG_USER_ONLY
9094 static const TypeInfo ppc_vhyp_type_info = {
9095 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
9096 .parent = TYPE_INTERFACE,
9097 .class_size = sizeof(PPCVirtualHypervisorClass),
9098 };
9099 #endif
9100
9101 static void ppc_cpu_register_types(void)
9102 {
9103 type_register_static(&ppc_cpu_type_info);
9104 #ifndef CONFIG_USER_ONLY
9105 type_register_static(&ppc_vhyp_type_info);
9106 #endif
9107 }
9108
9109 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
9110 {
9111 #define RGPL 4
9112 #define RFPL 4
9113
9114 PowerPCCPU *cpu = POWERPC_CPU(cs);
9115 CPUPPCState *env = &cpu->env;
9116 int i;
9117
9118 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9119 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
9120 env->nip, env->lr, env->ctr, cpu_read_xer(env),
9121 cs->cpu_index);
9122 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9123 "%08x iidx %d didx %d\n",
9124 env->msr, env->spr[SPR_HID0], env->hflags,
9125 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
9126 #if !defined(NO_TIMER_DUMP)
9127 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9128 #if !defined(CONFIG_USER_ONLY)
9129 " DECR " TARGET_FMT_lu
9130 #endif
9131 "\n",
9132 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9133 #if !defined(CONFIG_USER_ONLY)
9134 , cpu_ppc_load_decr(env)
9135 #endif
9136 );
9137 #endif
9138 for (i = 0; i < 32; i++) {
9139 if ((i & (RGPL - 1)) == 0) {
9140 qemu_fprintf(f, "GPR%02d", i);
9141 }
9142 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9143 if ((i & (RGPL - 1)) == (RGPL - 1)) {
9144 qemu_fprintf(f, "\n");
9145 }
9146 }
9147 qemu_fprintf(f, "CR ");
9148 for (i = 0; i < 8; i++)
9149 qemu_fprintf(f, "%01x", env->crf[i]);
9150 qemu_fprintf(f, " [");
9151 for (i = 0; i < 8; i++) {
9152 char a = '-';
9153 if (env->crf[i] & 0x08) {
9154 a = 'L';
9155 } else if (env->crf[i] & 0x04) {
9156 a = 'G';
9157 } else if (env->crf[i] & 0x02) {
9158 a = 'E';
9159 }
9160 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9161 }
9162 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9163 env->reserve_addr);
9164
9165 if (flags & CPU_DUMP_FPU) {
9166 for (i = 0; i < 32; i++) {
9167 if ((i & (RFPL - 1)) == 0) {
9168 qemu_fprintf(f, "FPR%02d", i);
9169 }
9170 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
9171 if ((i & (RFPL - 1)) == (RFPL - 1)) {
9172 qemu_fprintf(f, "\n");
9173 }
9174 }
9175 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9176 }
9177
9178 #if !defined(CONFIG_USER_ONLY)
9179 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9180 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9181 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9182 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9183
9184 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9185 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9186 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9187 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9188
9189 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9190 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9191 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9192 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9193
9194 #if defined(TARGET_PPC64)
9195 if (env->excp_model == POWERPC_EXCP_POWER7 ||
9196 env->excp_model == POWERPC_EXCP_POWER8 ||
9197 env->excp_model == POWERPC_EXCP_POWER9 ||
9198 env->excp_model == POWERPC_EXCP_POWER10) {
9199 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
9200 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
9201 }
9202 #endif
9203 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9204 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9205 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9206 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9207 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9208
9209 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9210 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9211 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9212 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9213
9214 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9215 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9216 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9217 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9218
9219 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9220 " EPR " TARGET_FMT_lx "\n",
9221 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9222 env->spr[SPR_BOOKE_EPR]);
9223
9224 /* FSL-specific */
9225 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9226 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9227 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9228 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9229
9230 /*
9231 * IVORs are left out as they are large and do not change often --
9232 * they can be read with "p $ivor0", "p $ivor1", etc.
9233 */
9234 }
9235
9236 #if defined(TARGET_PPC64)
9237 if (env->flags & POWERPC_FLAG_CFAR) {
9238 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9239 }
9240 #endif
9241
9242 if (env->spr_cb[SPR_LPCR].name) {
9243 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
9244 }
9245
9246 switch (env->mmu_model) {
9247 case POWERPC_MMU_32B:
9248 case POWERPC_MMU_601:
9249 case POWERPC_MMU_SOFT_6xx:
9250 case POWERPC_MMU_SOFT_74xx:
9251 #if defined(TARGET_PPC64)
9252 case POWERPC_MMU_64B:
9253 case POWERPC_MMU_2_03:
9254 case POWERPC_MMU_2_06:
9255 case POWERPC_MMU_2_07:
9256 case POWERPC_MMU_3_00:
9257 #endif
9258 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
9259 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
9260 }
9261 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
9262 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
9263 }
9264 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
9265 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
9266 break;
9267 case POWERPC_MMU_BOOKE206:
9268 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9269 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9270 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9271 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9272
9273 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9274 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9275 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9276 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9277
9278 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9279 " TLB1CFG " TARGET_FMT_lx "\n",
9280 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9281 env->spr[SPR_BOOKE_TLB1CFG]);
9282 break;
9283 default:
9284 break;
9285 }
9286 #endif
9287
9288 #undef RGPL
9289 #undef RFPL
9290 }
9291 type_init(ppc_cpu_register_types)
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