2 * PowerPC exception emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
26 #include "helper_regs.h"
29 //#define DEBUG_SOFTWARE_TLB
30 //#define DEBUG_EXCEPTIONS
32 #ifdef DEBUG_EXCEPTIONS
33 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
35 # define LOG_EXCP(...) do { } while (0)
38 /*****************************************************************************/
39 /* Exception processing */
40 #if defined(CONFIG_USER_ONLY)
41 void ppc_cpu_do_interrupt(CPUState
*cs
)
43 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
44 CPUPPCState
*env
= &cpu
->env
;
46 cs
->exception_index
= POWERPC_EXCP_NONE
;
50 static void ppc_hw_interrupt(CPUPPCState
*env
)
52 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
54 cs
->exception_index
= POWERPC_EXCP_NONE
;
57 #else /* defined(CONFIG_USER_ONLY) */
58 static inline void dump_syscall(CPUPPCState
*env
)
60 qemu_log_mask(CPU_LOG_INT
, "syscall r0=%016" PRIx64
" r3=%016" PRIx64
61 " r4=%016" PRIx64
" r5=%016" PRIx64
" r6=%016" PRIx64
62 " nip=" TARGET_FMT_lx
"\n",
63 ppc_dump_gpr(env
, 0), ppc_dump_gpr(env
, 3),
64 ppc_dump_gpr(env
, 4), ppc_dump_gpr(env
, 5),
65 ppc_dump_gpr(env
, 6), env
->nip
);
68 static int powerpc_reset_wakeup(CPUState
*cs
, CPUPPCState
*env
, int excp
,
71 /* We no longer are in a PM state */
72 env
->resume_as_sreset
= false;
74 /* Pretend to be returning from doze always as we don't lose state */
75 *msr
|= (0x1ull
<< (63 - 47));
77 /* Machine checks are sent normally */
78 if (excp
== POWERPC_EXCP_MCHECK
) {
82 case POWERPC_EXCP_RESET
:
83 *msr
|= 0x4ull
<< (63 - 45);
85 case POWERPC_EXCP_EXTERNAL
:
86 *msr
|= 0x8ull
<< (63 - 45);
88 case POWERPC_EXCP_DECR
:
89 *msr
|= 0x6ull
<< (63 - 45);
91 case POWERPC_EXCP_SDOOR
:
92 *msr
|= 0x5ull
<< (63 - 45);
94 case POWERPC_EXCP_SDOOR_HV
:
95 *msr
|= 0x3ull
<< (63 - 45);
97 case POWERPC_EXCP_HV_MAINT
:
98 *msr
|= 0xaull
<< (63 - 45);
100 case POWERPC_EXCP_HVIRT
:
101 *msr
|= 0x9ull
<< (63 - 45);
104 cpu_abort(cs
, "Unsupported exception %d in Power Save mode\n",
107 return POWERPC_EXCP_RESET
;
111 /* Note that this function should be greatly optimized
112 * when called with a constant excp, from ppc_hw_interrupt
114 static inline void powerpc_excp(PowerPCCPU
*cpu
, int excp_model
, int excp
)
116 CPUState
*cs
= CPU(cpu
);
117 CPUPPCState
*env
= &cpu
->env
;
118 target_ulong msr
, new_msr
, vector
;
119 int srr0
, srr1
, asrr0
, asrr1
, lev
, ail
;
122 qemu_log_mask(CPU_LOG_INT
, "Raise exception at " TARGET_FMT_lx
123 " => %08x (%02x)\n", env
->nip
, excp
, env
->error_code
);
125 /* new srr1 value excluding must-be-zero bits */
126 if (excp_model
== POWERPC_EXCP_BOOKE
) {
129 msr
= env
->msr
& ~0x783f0000ULL
;
132 /* new interrupt handler msr preserves existing HV and ME unless
133 * explicitly overriden
135 new_msr
= env
->msr
& (((target_ulong
)1 << MSR_ME
) | MSR_HVB
);
137 /* target registers */
144 * check for special resume at 0x100 from doze/nap/sleep/winkle on
147 if (env
->resume_as_sreset
) {
148 excp
= powerpc_reset_wakeup(cs
, env
, excp
, &msr
);
151 /* Exception targetting modifiers
153 * LPES0 is supported on POWER7/8/9
154 * LPES1 is not supported (old iSeries mode)
156 * On anything else, we behave as if LPES0 is 1
157 * (externals don't alter MSR:HV)
159 * AIL is initialized here but can be cleared by
160 * selected exceptions
162 #if defined(TARGET_PPC64)
163 if (excp_model
== POWERPC_EXCP_POWER7
||
164 excp_model
== POWERPC_EXCP_POWER8
||
165 excp_model
== POWERPC_EXCP_POWER9
) {
166 lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
167 if (excp_model
!= POWERPC_EXCP_POWER7
) {
168 ail
= (env
->spr
[SPR_LPCR
] & LPCR_AIL
) >> LPCR_AIL_SHIFT
;
173 #endif /* defined(TARGET_PPC64) */
179 /* Hypervisor emulation assistance interrupt only exists on server
180 * arch 2.05 server or later. We also don't want to generate it if
181 * we don't have HVB in msr_mask (PAPR mode).
183 if (excp
== POWERPC_EXCP_HV_EMU
184 #if defined(TARGET_PPC64)
185 && !((env
->mmu_model
& POWERPC_MMU_64
) && (env
->msr_mask
& MSR_HVB
))
186 #endif /* defined(TARGET_PPC64) */
189 excp
= POWERPC_EXCP_PROGRAM
;
193 case POWERPC_EXCP_NONE
:
194 /* Should never happen */
196 case POWERPC_EXCP_CRITICAL
: /* Critical input */
197 switch (excp_model
) {
198 case POWERPC_EXCP_40x
:
202 case POWERPC_EXCP_BOOKE
:
203 srr0
= SPR_BOOKE_CSRR0
;
204 srr1
= SPR_BOOKE_CSRR1
;
206 case POWERPC_EXCP_G2
:
212 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
214 /* Machine check exception is not enabled.
215 * Enter checkstop state.
217 fprintf(stderr
, "Machine check while not allowed. "
218 "Entering checkstop state\n");
219 if (qemu_log_separate()) {
220 qemu_log("Machine check while not allowed. "
221 "Entering checkstop state\n");
224 cpu_interrupt_exittb(cs
);
226 if (env
->msr_mask
& MSR_HVB
) {
227 /* ISA specifies HV, but can be delivered to guest with HV clear
228 * (e.g., see FWNMI in PAPR).
230 new_msr
|= (target_ulong
)MSR_HVB
;
234 /* machine check exceptions don't have ME set */
235 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
237 /* XXX: should also have something loaded in DAR / DSISR */
238 switch (excp_model
) {
239 case POWERPC_EXCP_40x
:
243 case POWERPC_EXCP_BOOKE
:
244 /* FIXME: choose one or the other based on CPU type */
245 srr0
= SPR_BOOKE_MCSRR0
;
246 srr1
= SPR_BOOKE_MCSRR1
;
247 asrr0
= SPR_BOOKE_CSRR0
;
248 asrr1
= SPR_BOOKE_CSRR1
;
254 case POWERPC_EXCP_DSI
: /* Data storage exception */
255 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx
" DAR=" TARGET_FMT_lx
256 "\n", env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
258 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
259 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx
", nip=" TARGET_FMT_lx
260 "\n", msr
, env
->nip
);
261 msr
|= env
->error_code
;
263 case POWERPC_EXCP_EXTERNAL
: /* External input */
267 new_msr
|= (target_ulong
)MSR_HVB
;
268 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
272 if (env
->mpic_proxy
) {
273 /* IACK the IRQ on delivery */
274 env
->spr
[SPR_BOOKE_EPR
] = ldl_phys(cs
->as
, env
->mpic_iack
);
277 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
278 /* Get rS/rD and rA from faulting opcode */
279 /* Note: the opcode fields will not be set properly for a direct
280 * store load/store, but nobody cares as nobody actually uses
281 * direct store segments.
283 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
285 case POWERPC_EXCP_PROGRAM
: /* Program exception */
286 switch (env
->error_code
& ~0xF) {
287 case POWERPC_EXCP_FP
:
288 if ((msr_fe0
== 0 && msr_fe1
== 0) || msr_fp
== 0) {
289 LOG_EXCP("Ignore floating point exception\n");
290 cs
->exception_index
= POWERPC_EXCP_NONE
;
295 /* FP exceptions always have NIP pointing to the faulting
296 * instruction, so always use store_next and claim we are
297 * precise in the MSR.
300 env
->spr
[SPR_BOOKE_ESR
] = ESR_FP
;
302 case POWERPC_EXCP_INVAL
:
303 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx
"\n", env
->nip
);
305 env
->spr
[SPR_BOOKE_ESR
] = ESR_PIL
;
307 case POWERPC_EXCP_PRIV
:
309 env
->spr
[SPR_BOOKE_ESR
] = ESR_PPR
;
311 case POWERPC_EXCP_TRAP
:
313 env
->spr
[SPR_BOOKE_ESR
] = ESR_PTR
;
316 /* Should never occur */
317 cpu_abort(cs
, "Invalid program exception %d. Aborting\n",
322 case POWERPC_EXCP_SYSCALL
: /* System call exception */
324 lev
= env
->error_code
;
326 /* We need to correct the NIP which in this case is supposed
327 * to point to the next instruction
331 /* "PAPR mode" built-in hypercall emulation */
332 if ((lev
== 1) && cpu
->vhyp
) {
333 PPCVirtualHypervisorClass
*vhc
=
334 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
335 vhc
->hypercall(cpu
->vhyp
, cpu
);
339 new_msr
|= (target_ulong
)MSR_HVB
;
342 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
343 case POWERPC_EXCP_APU
: /* Auxiliary processor unavailable */
344 case POWERPC_EXCP_DECR
: /* Decrementer exception */
346 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
348 LOG_EXCP("FIT exception\n");
350 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
351 LOG_EXCP("WDT exception\n");
352 switch (excp_model
) {
353 case POWERPC_EXCP_BOOKE
:
354 srr0
= SPR_BOOKE_CSRR0
;
355 srr1
= SPR_BOOKE_CSRR1
;
361 case POWERPC_EXCP_DTLB
: /* Data TLB error */
362 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
364 case POWERPC_EXCP_DEBUG
: /* Debug interrupt */
365 if (env
->flags
& POWERPC_FLAG_DE
) {
366 /* FIXME: choose one or the other based on CPU type */
367 srr0
= SPR_BOOKE_DSRR0
;
368 srr1
= SPR_BOOKE_DSRR1
;
369 asrr0
= SPR_BOOKE_CSRR0
;
370 asrr1
= SPR_BOOKE_CSRR1
;
371 /* DBSR already modified by caller */
373 cpu_abort(cs
, "Debug exception triggered on unsupported model\n");
376 case POWERPC_EXCP_SPEU
: /* SPE/embedded floating-point unavailable */
377 env
->spr
[SPR_BOOKE_ESR
] = ESR_SPV
;
379 case POWERPC_EXCP_EFPDI
: /* Embedded floating-point data interrupt */
381 cpu_abort(cs
, "Embedded floating point data exception "
382 "is not implemented yet !\n");
383 env
->spr
[SPR_BOOKE_ESR
] = ESR_SPV
;
385 case POWERPC_EXCP_EFPRI
: /* Embedded floating-point round interrupt */
387 cpu_abort(cs
, "Embedded floating point round exception "
388 "is not implemented yet !\n");
389 env
->spr
[SPR_BOOKE_ESR
] = ESR_SPV
;
391 case POWERPC_EXCP_EPERFM
: /* Embedded performance monitor interrupt */
394 "Performance counter exception is not implemented yet !\n");
396 case POWERPC_EXCP_DOORI
: /* Embedded doorbell interrupt */
398 case POWERPC_EXCP_DOORCI
: /* Embedded doorbell critical interrupt */
399 srr0
= SPR_BOOKE_CSRR0
;
400 srr1
= SPR_BOOKE_CSRR1
;
402 case POWERPC_EXCP_RESET
: /* System reset exception */
403 /* A power-saving exception sets ME, otherwise it is unchanged */
405 /* indicate that we resumed from power save mode */
407 new_msr
|= ((target_ulong
)1 << MSR_ME
);
409 if (env
->msr_mask
& MSR_HVB
) {
410 /* ISA specifies HV, but can be delivered to guest with HV clear
411 * (e.g., see FWNMI in PAPR, NMI injection in QEMU).
413 new_msr
|= (target_ulong
)MSR_HVB
;
416 cpu_abort(cs
, "Trying to deliver power-saving system reset "
417 "exception %d with no HV support\n", excp
);
422 case POWERPC_EXCP_DSEG
: /* Data segment exception */
423 case POWERPC_EXCP_ISEG
: /* Instruction segment exception */
424 case POWERPC_EXCP_TRACE
: /* Trace exception */
426 case POWERPC_EXCP_HDECR
: /* Hypervisor decrementer exception */
427 case POWERPC_EXCP_HDSI
: /* Hypervisor data storage exception */
428 case POWERPC_EXCP_HISI
: /* Hypervisor instruction storage exception */
429 case POWERPC_EXCP_HDSEG
: /* Hypervisor data segment exception */
430 case POWERPC_EXCP_HISEG
: /* Hypervisor instruction segment exception */
431 case POWERPC_EXCP_SDOOR_HV
: /* Hypervisor Doorbell interrupt */
432 case POWERPC_EXCP_HV_EMU
:
433 case POWERPC_EXCP_HVIRT
: /* Hypervisor virtualization */
436 new_msr
|= (target_ulong
)MSR_HVB
;
437 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
439 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
440 case POWERPC_EXCP_VSXU
: /* VSX unavailable exception */
441 case POWERPC_EXCP_FU
: /* Facility unavailable exception */
443 env
->spr
[SPR_FSCR
] |= ((target_ulong
)env
->error_code
<< 56);
446 case POWERPC_EXCP_PIT
: /* Programmable interval timer interrupt */
447 LOG_EXCP("PIT exception\n");
449 case POWERPC_EXCP_IO
: /* IO error exception */
451 cpu_abort(cs
, "601 IO error exception is not implemented yet !\n");
453 case POWERPC_EXCP_RUNM
: /* Run mode exception */
455 cpu_abort(cs
, "601 run mode exception is not implemented yet !\n");
457 case POWERPC_EXCP_EMUL
: /* Emulation trap exception */
459 cpu_abort(cs
, "602 emulation trap exception "
460 "is not implemented yet !\n");
462 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
463 switch (excp_model
) {
464 case POWERPC_EXCP_602
:
465 case POWERPC_EXCP_603
:
466 case POWERPC_EXCP_603E
:
467 case POWERPC_EXCP_G2
:
469 case POWERPC_EXCP_7x5
:
471 case POWERPC_EXCP_74xx
:
474 cpu_abort(cs
, "Invalid instruction TLB miss exception\n");
478 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
479 switch (excp_model
) {
480 case POWERPC_EXCP_602
:
481 case POWERPC_EXCP_603
:
482 case POWERPC_EXCP_603E
:
483 case POWERPC_EXCP_G2
:
485 case POWERPC_EXCP_7x5
:
487 case POWERPC_EXCP_74xx
:
490 cpu_abort(cs
, "Invalid data load TLB miss exception\n");
494 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
495 switch (excp_model
) {
496 case POWERPC_EXCP_602
:
497 case POWERPC_EXCP_603
:
498 case POWERPC_EXCP_603E
:
499 case POWERPC_EXCP_G2
:
501 /* Swap temporary saved registers with GPRs */
502 if (!(new_msr
& ((target_ulong
)1 << MSR_TGPR
))) {
503 new_msr
|= (target_ulong
)1 << MSR_TGPR
;
504 hreg_swap_gpr_tgpr(env
);
507 case POWERPC_EXCP_7x5
:
509 #if defined(DEBUG_SOFTWARE_TLB)
510 if (qemu_log_enabled()) {
512 target_ulong
*miss
, *cmp
;
515 if (excp
== POWERPC_EXCP_IFTLB
) {
518 miss
= &env
->spr
[SPR_IMISS
];
519 cmp
= &env
->spr
[SPR_ICMP
];
521 if (excp
== POWERPC_EXCP_DLTLB
) {
527 miss
= &env
->spr
[SPR_DMISS
];
528 cmp
= &env
->spr
[SPR_DCMP
];
530 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx
" %cC "
531 TARGET_FMT_lx
" H1 " TARGET_FMT_lx
" H2 "
532 TARGET_FMT_lx
" %08x\n", es
, en
, *miss
, en
, *cmp
,
533 env
->spr
[SPR_HASH1
], env
->spr
[SPR_HASH2
],
537 msr
|= env
->crf
[0] << 28;
538 msr
|= env
->error_code
; /* key, D/I, S/L bits */
539 /* Set way using a LRU mechanism */
540 msr
|= ((env
->last_way
+ 1) & (env
->nb_ways
- 1)) << 17;
542 case POWERPC_EXCP_74xx
:
544 #if defined(DEBUG_SOFTWARE_TLB)
545 if (qemu_log_enabled()) {
547 target_ulong
*miss
, *cmp
;
550 if (excp
== POWERPC_EXCP_IFTLB
) {
553 miss
= &env
->spr
[SPR_TLBMISS
];
554 cmp
= &env
->spr
[SPR_PTEHI
];
556 if (excp
== POWERPC_EXCP_DLTLB
) {
562 miss
= &env
->spr
[SPR_TLBMISS
];
563 cmp
= &env
->spr
[SPR_PTEHI
];
565 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx
" %cC "
566 TARGET_FMT_lx
" %08x\n", es
, en
, *miss
, en
, *cmp
,
570 msr
|= env
->error_code
; /* key bit */
573 cpu_abort(cs
, "Invalid data store TLB miss exception\n");
577 case POWERPC_EXCP_FPA
: /* Floating-point assist exception */
579 cpu_abort(cs
, "Floating point assist exception "
580 "is not implemented yet !\n");
582 case POWERPC_EXCP_DABR
: /* Data address breakpoint */
584 cpu_abort(cs
, "DABR exception is not implemented yet !\n");
586 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
588 cpu_abort(cs
, "IABR exception is not implemented yet !\n");
590 case POWERPC_EXCP_SMI
: /* System management interrupt */
592 cpu_abort(cs
, "SMI exception is not implemented yet !\n");
594 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
596 cpu_abort(cs
, "Thermal management exception "
597 "is not implemented yet !\n");
599 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor interrupt */
602 "Performance counter exception is not implemented yet !\n");
604 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
606 cpu_abort(cs
, "VPU assist exception is not implemented yet !\n");
608 case POWERPC_EXCP_SOFTP
: /* Soft patch exception */
611 "970 soft-patch exception is not implemented yet !\n");
613 case POWERPC_EXCP_MAINT
: /* Maintenance exception */
616 "970 maintenance exception is not implemented yet !\n");
618 case POWERPC_EXCP_MEXTBR
: /* Maskable external breakpoint */
620 cpu_abort(cs
, "Maskable external exception "
621 "is not implemented yet !\n");
623 case POWERPC_EXCP_NMEXTBR
: /* Non maskable external breakpoint */
625 cpu_abort(cs
, "Non maskable external exception "
626 "is not implemented yet !\n");
630 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
635 env
->spr
[srr0
] = env
->nip
;
638 env
->spr
[srr1
] = msr
;
641 if (!(env
->msr_mask
& MSR_HVB
)) {
642 if (new_msr
& MSR_HVB
) {
643 cpu_abort(cs
, "Trying to deliver HV exception (MSR) %d with "
644 "no HV support\n", excp
);
646 if (srr0
== SPR_HSRR0
) {
647 cpu_abort(cs
, "Trying to deliver HV exception (HSRR) %d with "
648 "no HV support\n", excp
);
652 /* If any alternate SRR register are defined, duplicate saved values */
654 env
->spr
[asrr0
] = env
->spr
[srr0
];
657 env
->spr
[asrr1
] = env
->spr
[srr1
];
660 /* Sort out endianness of interrupt, this differs depending on the
661 * CPU, the HV mode, etc...
664 if (excp_model
== POWERPC_EXCP_POWER7
) {
665 if (!(new_msr
& MSR_HVB
) && (env
->spr
[SPR_LPCR
] & LPCR_ILE
)) {
666 new_msr
|= (target_ulong
)1 << MSR_LE
;
668 } else if (excp_model
== POWERPC_EXCP_POWER8
) {
669 if (new_msr
& MSR_HVB
) {
670 if (env
->spr
[SPR_HID0
] & HID0_HILE
) {
671 new_msr
|= (target_ulong
)1 << MSR_LE
;
673 } else if (env
->spr
[SPR_LPCR
] & LPCR_ILE
) {
674 new_msr
|= (target_ulong
)1 << MSR_LE
;
676 } else if (excp_model
== POWERPC_EXCP_POWER9
) {
677 if (new_msr
& MSR_HVB
) {
678 if (env
->spr
[SPR_HID0
] & HID0_POWER9_HILE
) {
679 new_msr
|= (target_ulong
)1 << MSR_LE
;
681 } else if (env
->spr
[SPR_LPCR
] & LPCR_ILE
) {
682 new_msr
|= (target_ulong
)1 << MSR_LE
;
684 } else if (msr_ile
) {
685 new_msr
|= (target_ulong
)1 << MSR_LE
;
689 new_msr
|= (target_ulong
)1 << MSR_LE
;
693 /* Jump to handler */
694 vector
= env
->excp_vectors
[excp
];
695 if (vector
== (target_ulong
)-1ULL) {
696 cpu_abort(cs
, "Raised an exception without defined vector %d\n",
699 vector
|= env
->excp_prefix
;
701 /* AIL only works if there is no HV transition and we are running with
702 * translations enabled
704 if (!((msr
>> MSR_IR
) & 1) || !((msr
>> MSR_DR
) & 1) ||
705 ((new_msr
& MSR_HVB
) && !(msr
& MSR_HVB
))) {
710 new_msr
|= (1 << MSR_IR
) | (1 << MSR_DR
);
715 case AIL_C000_0000_0000_4000
:
716 vector
|= 0xc000000000004000ull
;
719 cpu_abort(cs
, "Invalid AIL combination %d\n", ail
);
724 #if defined(TARGET_PPC64)
725 if (excp_model
== POWERPC_EXCP_BOOKE
) {
726 if (env
->spr
[SPR_BOOKE_EPCR
] & EPCR_ICM
) {
727 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
728 new_msr
|= (target_ulong
)1 << MSR_CM
;
730 vector
= (uint32_t)vector
;
733 if (!msr_isf
&& !(env
->mmu_model
& POWERPC_MMU_64
)) {
734 vector
= (uint32_t)vector
;
736 new_msr
|= (target_ulong
)1 << MSR_SF
;
740 /* We don't use hreg_store_msr here as already have treated
741 * any special case that could occur. Just store MSR and update hflags
743 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
744 * will prevent setting of the HV bit which some exceptions might need
747 env
->msr
= new_msr
& env
->msr_mask
;
748 hreg_compute_hflags(env
);
750 /* Reset exception state */
751 cs
->exception_index
= POWERPC_EXCP_NONE
;
754 /* Reset the reservation */
755 env
->reserve_addr
= -1;
757 /* Any interrupt is context synchronizing, check if TCG TLB
758 * needs a delayed flush on ppc64
760 check_tlb_flush(env
, false);
763 void ppc_cpu_do_interrupt(CPUState
*cs
)
765 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
766 CPUPPCState
*env
= &cpu
->env
;
768 powerpc_excp(cpu
, env
->excp_model
, cs
->exception_index
);
771 static void ppc_hw_interrupt(CPUPPCState
*env
)
773 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
777 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_RESET
)) {
778 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_RESET
);
779 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_RESET
);
782 /* Machine check exception */
783 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_MCK
)) {
784 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_MCK
);
785 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_MCHECK
);
789 /* External debug exception */
790 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DEBUG
)) {
791 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DEBUG
);
792 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_DEBUG
);
798 * For interrupts that gate on MSR:EE, we need to do something a
799 * bit more subtle, as we need to let them through even when EE is
800 * clear when coming out of some power management states (in order
801 * for them to become a 0x100).
803 async_deliver
= (msr_ee
!= 0) || env
->resume_as_sreset
;
805 /* Hypervisor decrementer exception */
806 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_HDECR
)) {
807 /* LPCR will be clear when not supported so this will work */
808 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
809 if ((async_deliver
|| msr_hv
== 0) && hdice
) {
810 /* HDEC clears on delivery */
811 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_HDECR
);
812 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_HDECR
);
817 /* Hypervisor virtualization interrupt */
818 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_HVIRT
)) {
819 /* LPCR will be clear when not supported so this will work */
820 bool hvice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HVICE
);
821 if ((async_deliver
|| msr_hv
== 0) && hvice
) {
822 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_HVIRT
);
827 /* External interrupt can ignore MSR:EE under some circumstances */
828 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_EXT
)) {
829 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
830 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
831 /* HEIC blocks delivery to the hypervisor */
832 if ((async_deliver
&& !(heic
&& msr_hv
&& !msr_pr
)) ||
833 (env
->has_hv_mode
&& msr_hv
== 0 && !lpes0
)) {
834 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_EXTERNAL
);
839 /* External critical interrupt */
840 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_CEXT
)) {
841 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_CRITICAL
);
845 if (async_deliver
!= 0) {
846 /* Watchdog timer on embedded PowerPC */
847 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_WDT
)) {
848 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_WDT
);
849 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_WDT
);
852 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_CDOORBELL
)) {
853 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_CDOORBELL
);
854 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_DOORCI
);
857 /* Fixed interval timer on embedded PowerPC */
858 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_FIT
)) {
859 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_FIT
);
860 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_FIT
);
863 /* Programmable interval timer on embedded PowerPC */
864 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_PIT
)) {
865 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_PIT
);
866 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_PIT
);
869 /* Decrementer exception */
870 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DECR
)) {
871 if (ppc_decr_clear_on_delivery(env
)) {
872 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DECR
);
874 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_DECR
);
877 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DOORBELL
)) {
878 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DOORBELL
);
879 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_DOORI
);
882 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_HDOORBELL
)) {
883 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_HDOORBELL
);
884 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_SDOOR_HV
);
887 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_PERFM
)) {
888 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_PERFM
);
889 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_PERFM
);
892 /* Thermal interrupt */
893 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_THERM
)) {
894 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_THERM
);
895 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_THERM
);
900 if (env
->resume_as_sreset
) {
902 * This is a bug ! It means that has_work took us out of halt without
903 * anything to deliver while in a PM state that requires getting
906 * This means we will incorrectly execute past the power management
907 * instruction instead of triggering a reset.
909 * It generally means a discrepancy between the wakup conditions in the
910 * processor has_work implementation and the logic in this function.
912 cpu_abort(CPU(ppc_env_get_cpu(env
)),
913 "Wakeup from PM state but interrupt Undelivered");
917 void ppc_cpu_do_system_reset(CPUState
*cs
)
919 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
920 CPUPPCState
*env
= &cpu
->env
;
922 powerpc_excp(cpu
, env
->excp_model
, POWERPC_EXCP_RESET
);
924 #endif /* !CONFIG_USER_ONLY */
926 bool ppc_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
928 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
929 CPUPPCState
*env
= &cpu
->env
;
931 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
932 ppc_hw_interrupt(env
);
933 if (env
->pending_interrupts
== 0) {
934 cs
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
941 #if defined(DEBUG_OP)
942 static void cpu_dump_rfi(target_ulong RA
, target_ulong msr
)
944 qemu_log("Return from exception at " TARGET_FMT_lx
" with flags "
945 TARGET_FMT_lx
"\n", RA
, msr
);
949 /*****************************************************************************/
950 /* Exceptions processing helpers */
952 void raise_exception_err_ra(CPUPPCState
*env
, uint32_t exception
,
953 uint32_t error_code
, uintptr_t raddr
)
955 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
957 cs
->exception_index
= exception
;
958 env
->error_code
= error_code
;
959 cpu_loop_exit_restore(cs
, raddr
);
962 void raise_exception_err(CPUPPCState
*env
, uint32_t exception
,
965 raise_exception_err_ra(env
, exception
, error_code
, 0);
968 void raise_exception(CPUPPCState
*env
, uint32_t exception
)
970 raise_exception_err_ra(env
, exception
, 0, 0);
973 void raise_exception_ra(CPUPPCState
*env
, uint32_t exception
,
976 raise_exception_err_ra(env
, exception
, 0, raddr
);
979 void helper_raise_exception_err(CPUPPCState
*env
, uint32_t exception
,
982 raise_exception_err_ra(env
, exception
, error_code
, 0);
985 void helper_raise_exception(CPUPPCState
*env
, uint32_t exception
)
987 raise_exception_err_ra(env
, exception
, 0, 0);
990 #if !defined(CONFIG_USER_ONLY)
991 void helper_store_msr(CPUPPCState
*env
, target_ulong val
)
993 uint32_t excp
= hreg_store_msr(env
, val
, 0);
996 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
997 cpu_interrupt_exittb(cs
);
998 raise_exception(env
, excp
);
1002 #if defined(TARGET_PPC64)
1003 void helper_pminsn(CPUPPCState
*env
, powerpc_pm_insn_t insn
)
1007 cs
= CPU(ppc_env_get_cpu(env
));
1010 /* The architecture specifies that HDEC interrupts are
1011 * discarded in PM states
1013 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_HDECR
);
1015 /* Condition for waking up at 0x100 */
1016 env
->resume_as_sreset
= (insn
!= PPC_PM_STOP
) ||
1017 (env
->spr
[SPR_PSSCR
] & PSSCR_EC
);
1019 #endif /* defined(TARGET_PPC64) */
1021 static inline void do_rfi(CPUPPCState
*env
, target_ulong nip
, target_ulong msr
)
1023 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
1025 /* MSR:POW cannot be set by any form of rfi */
1026 msr
&= ~(1ULL << MSR_POW
);
1028 #if defined(TARGET_PPC64)
1029 /* Switching to 32-bit ? Crop the nip */
1030 if (!msr_is_64bit(env
, msr
)) {
1031 nip
= (uint32_t)nip
;
1034 nip
= (uint32_t)nip
;
1036 /* XXX: beware: this is false if VLE is supported */
1037 env
->nip
= nip
& ~((target_ulong
)0x00000003);
1038 hreg_store_msr(env
, msr
, 1);
1039 #if defined(DEBUG_OP)
1040 cpu_dump_rfi(env
->nip
, env
->msr
);
1042 /* No need to raise an exception here,
1043 * as rfi is always the last insn of a TB
1045 cpu_interrupt_exittb(cs
);
1046 /* Reset the reservation */
1047 env
->reserve_addr
= -1;
1049 /* Context synchronizing: check if TCG TLB needs flush */
1050 check_tlb_flush(env
, false);
1053 void helper_rfi(CPUPPCState
*env
)
1055 do_rfi(env
, env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
] & 0xfffffffful
);
1058 #define MSR_BOOK3S_MASK
1059 #if defined(TARGET_PPC64)
1060 void helper_rfid(CPUPPCState
*env
)
1062 /* The architeture defines a number of rules for which bits
1063 * can change but in practice, we handle this in hreg_store_msr()
1064 * which will be called by do_rfi(), so there is no need to filter
1067 do_rfi(env
, env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
]);
1070 void helper_hrfid(CPUPPCState
*env
)
1072 do_rfi(env
, env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
1076 /*****************************************************************************/
1077 /* Embedded PowerPC specific helpers */
1078 void helper_40x_rfci(CPUPPCState
*env
)
1080 do_rfi(env
, env
->spr
[SPR_40x_SRR2
], env
->spr
[SPR_40x_SRR3
]);
1083 void helper_rfci(CPUPPCState
*env
)
1085 do_rfi(env
, env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
]);
1088 void helper_rfdi(CPUPPCState
*env
)
1090 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
1091 do_rfi(env
, env
->spr
[SPR_BOOKE_DSRR0
], env
->spr
[SPR_BOOKE_DSRR1
]);
1094 void helper_rfmci(CPUPPCState
*env
)
1096 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
1097 do_rfi(env
, env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
1101 void helper_tw(CPUPPCState
*env
, target_ulong arg1
, target_ulong arg2
,
1104 if (!likely(!(((int32_t)arg1
< (int32_t)arg2
&& (flags
& 0x10)) ||
1105 ((int32_t)arg1
> (int32_t)arg2
&& (flags
& 0x08)) ||
1106 ((int32_t)arg1
== (int32_t)arg2
&& (flags
& 0x04)) ||
1107 ((uint32_t)arg1
< (uint32_t)arg2
&& (flags
& 0x02)) ||
1108 ((uint32_t)arg1
> (uint32_t)arg2
&& (flags
& 0x01))))) {
1109 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
1110 POWERPC_EXCP_TRAP
, GETPC());
1114 #if defined(TARGET_PPC64)
1115 void helper_td(CPUPPCState
*env
, target_ulong arg1
, target_ulong arg2
,
1118 if (!likely(!(((int64_t)arg1
< (int64_t)arg2
&& (flags
& 0x10)) ||
1119 ((int64_t)arg1
> (int64_t)arg2
&& (flags
& 0x08)) ||
1120 ((int64_t)arg1
== (int64_t)arg2
&& (flags
& 0x04)) ||
1121 ((uint64_t)arg1
< (uint64_t)arg2
&& (flags
& 0x02)) ||
1122 ((uint64_t)arg1
> (uint64_t)arg2
&& (flags
& 0x01))))) {
1123 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
1124 POWERPC_EXCP_TRAP
, GETPC());
1129 #if !defined(CONFIG_USER_ONLY)
1130 /*****************************************************************************/
1131 /* PowerPC 601 specific instructions (POWER bridge) */
1133 void helper_rfsvc(CPUPPCState
*env
)
1135 do_rfi(env
, env
->lr
, env
->ctr
& 0x0000FFFF);
1138 /* Embedded.Processor Control */
1139 static int dbell2irq(target_ulong rb
)
1141 int msg
= rb
& DBELL_TYPE_MASK
;
1145 case DBELL_TYPE_DBELL
:
1146 irq
= PPC_INTERRUPT_DOORBELL
;
1148 case DBELL_TYPE_DBELL_CRIT
:
1149 irq
= PPC_INTERRUPT_CDOORBELL
;
1151 case DBELL_TYPE_G_DBELL
:
1152 case DBELL_TYPE_G_DBELL_CRIT
:
1153 case DBELL_TYPE_G_DBELL_MC
:
1162 void helper_msgclr(CPUPPCState
*env
, target_ulong rb
)
1164 int irq
= dbell2irq(rb
);
1170 env
->pending_interrupts
&= ~(1 << irq
);
1173 void helper_msgsnd(target_ulong rb
)
1175 int irq
= dbell2irq(rb
);
1176 int pir
= rb
& DBELL_PIRTAG_MASK
;
1183 qemu_mutex_lock_iothread();
1185 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1186 CPUPPCState
*cenv
= &cpu
->env
;
1188 if ((rb
& DBELL_BRDCAST
) || (cenv
->spr
[SPR_BOOKE_PIR
] == pir
)) {
1189 cenv
->pending_interrupts
|= 1 << irq
;
1190 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
1193 qemu_mutex_unlock_iothread();
1196 /* Server Processor Control */
1197 static int book3s_dbell2irq(target_ulong rb
)
1199 int msg
= rb
& DBELL_TYPE_MASK
;
1201 /* A Directed Hypervisor Doorbell message is sent only if the
1202 * message type is 5. All other types are reserved and the
1203 * instruction is a no-op */
1204 return msg
== DBELL_TYPE_DBELL_SERVER
? PPC_INTERRUPT_HDOORBELL
: -1;
1207 void helper_book3s_msgclr(CPUPPCState
*env
, target_ulong rb
)
1209 int irq
= book3s_dbell2irq(rb
);
1215 env
->pending_interrupts
&= ~(1 << irq
);
1218 void helper_book3s_msgsnd(target_ulong rb
)
1220 int irq
= book3s_dbell2irq(rb
);
1221 int pir
= rb
& DBELL_PROCIDTAG_MASK
;
1228 qemu_mutex_lock_iothread();
1230 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1231 CPUPPCState
*cenv
= &cpu
->env
;
1233 /* TODO: broadcast message to all threads of the same processor */
1234 if (cenv
->spr_cb
[SPR_PIR
].default_value
== pir
) {
1235 cenv
->pending_interrupts
|= 1 << irq
;
1236 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
1239 qemu_mutex_unlock_iothread();
1243 void ppc_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
1244 MMUAccessType access_type
,
1245 int mmu_idx
, uintptr_t retaddr
)
1247 CPUPPCState
*env
= cs
->env_ptr
;
1250 /* Restore state and reload the insn we executed, for filling in DSISR. */
1251 cpu_restore_state(cs
, retaddr
, true);
1252 insn
= cpu_ldl_code(env
, env
->nip
);
1254 cs
->exception_index
= POWERPC_EXCP_ALIGN
;
1255 env
->error_code
= insn
& 0x03FF0000;