2 * PowerPC exception emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
23 #include "exec/exec-all.h"
25 #include "helper_regs.h"
26 #include "hw/ppc/ppc.h"
31 #include "sysemu/tcg.h"
32 #include "exec/helper-proto.h"
33 #include "exec/cpu_ldst.h"
36 /*****************************************************************************/
37 /* Exception processing */
38 #ifndef CONFIG_USER_ONLY
40 static const char *powerpc_excp_name(int excp
)
43 case POWERPC_EXCP_CRITICAL
: return "CRITICAL";
44 case POWERPC_EXCP_MCHECK
: return "MCHECK";
45 case POWERPC_EXCP_DSI
: return "DSI";
46 case POWERPC_EXCP_ISI
: return "ISI";
47 case POWERPC_EXCP_EXTERNAL
: return "EXTERNAL";
48 case POWERPC_EXCP_ALIGN
: return "ALIGN";
49 case POWERPC_EXCP_PROGRAM
: return "PROGRAM";
50 case POWERPC_EXCP_FPU
: return "FPU";
51 case POWERPC_EXCP_SYSCALL
: return "SYSCALL";
52 case POWERPC_EXCP_APU
: return "APU";
53 case POWERPC_EXCP_DECR
: return "DECR";
54 case POWERPC_EXCP_FIT
: return "FIT";
55 case POWERPC_EXCP_WDT
: return "WDT";
56 case POWERPC_EXCP_DTLB
: return "DTLB";
57 case POWERPC_EXCP_ITLB
: return "ITLB";
58 case POWERPC_EXCP_DEBUG
: return "DEBUG";
59 case POWERPC_EXCP_SPEU
: return "SPEU";
60 case POWERPC_EXCP_EFPDI
: return "EFPDI";
61 case POWERPC_EXCP_EFPRI
: return "EFPRI";
62 case POWERPC_EXCP_EPERFM
: return "EPERFM";
63 case POWERPC_EXCP_DOORI
: return "DOORI";
64 case POWERPC_EXCP_DOORCI
: return "DOORCI";
65 case POWERPC_EXCP_GDOORI
: return "GDOORI";
66 case POWERPC_EXCP_GDOORCI
: return "GDOORCI";
67 case POWERPC_EXCP_HYPPRIV
: return "HYPPRIV";
68 case POWERPC_EXCP_RESET
: return "RESET";
69 case POWERPC_EXCP_DSEG
: return "DSEG";
70 case POWERPC_EXCP_ISEG
: return "ISEG";
71 case POWERPC_EXCP_HDECR
: return "HDECR";
72 case POWERPC_EXCP_TRACE
: return "TRACE";
73 case POWERPC_EXCP_HDSI
: return "HDSI";
74 case POWERPC_EXCP_HISI
: return "HISI";
75 case POWERPC_EXCP_HDSEG
: return "HDSEG";
76 case POWERPC_EXCP_HISEG
: return "HISEG";
77 case POWERPC_EXCP_VPU
: return "VPU";
78 case POWERPC_EXCP_PIT
: return "PIT";
79 case POWERPC_EXCP_EMUL
: return "EMUL";
80 case POWERPC_EXCP_IFTLB
: return "IFTLB";
81 case POWERPC_EXCP_DLTLB
: return "DLTLB";
82 case POWERPC_EXCP_DSTLB
: return "DSTLB";
83 case POWERPC_EXCP_FPA
: return "FPA";
84 case POWERPC_EXCP_DABR
: return "DABR";
85 case POWERPC_EXCP_IABR
: return "IABR";
86 case POWERPC_EXCP_SMI
: return "SMI";
87 case POWERPC_EXCP_PERFM
: return "PERFM";
88 case POWERPC_EXCP_THERM
: return "THERM";
89 case POWERPC_EXCP_VPUA
: return "VPUA";
90 case POWERPC_EXCP_SOFTP
: return "SOFTP";
91 case POWERPC_EXCP_MAINT
: return "MAINT";
92 case POWERPC_EXCP_MEXTBR
: return "MEXTBR";
93 case POWERPC_EXCP_NMEXTBR
: return "NMEXTBR";
94 case POWERPC_EXCP_ITLBE
: return "ITLBE";
95 case POWERPC_EXCP_DTLBE
: return "DTLBE";
96 case POWERPC_EXCP_VSXU
: return "VSXU";
97 case POWERPC_EXCP_FU
: return "FU";
98 case POWERPC_EXCP_HV_EMU
: return "HV_EMU";
99 case POWERPC_EXCP_HV_MAINT
: return "HV_MAINT";
100 case POWERPC_EXCP_HV_FU
: return "HV_FU";
101 case POWERPC_EXCP_SDOOR
: return "SDOOR";
102 case POWERPC_EXCP_SDOOR_HV
: return "SDOOR_HV";
103 case POWERPC_EXCP_HVIRT
: return "HVIRT";
104 case POWERPC_EXCP_SYSCALL_VECTORED
: return "SYSCALL_VECTORED";
106 g_assert_not_reached();
110 static void dump_syscall(CPUPPCState
*env
)
112 qemu_log_mask(CPU_LOG_INT
, "syscall r0=%016" PRIx64
113 " r3=%016" PRIx64
" r4=%016" PRIx64
" r5=%016" PRIx64
114 " r6=%016" PRIx64
" r7=%016" PRIx64
" r8=%016" PRIx64
115 " nip=" TARGET_FMT_lx
"\n",
116 ppc_dump_gpr(env
, 0), ppc_dump_gpr(env
, 3),
117 ppc_dump_gpr(env
, 4), ppc_dump_gpr(env
, 5),
118 ppc_dump_gpr(env
, 6), ppc_dump_gpr(env
, 7),
119 ppc_dump_gpr(env
, 8), env
->nip
);
122 static void dump_hcall(CPUPPCState
*env
)
124 qemu_log_mask(CPU_LOG_INT
, "hypercall r3=%016" PRIx64
125 " r4=%016" PRIx64
" r5=%016" PRIx64
" r6=%016" PRIx64
126 " r7=%016" PRIx64
" r8=%016" PRIx64
" r9=%016" PRIx64
127 " r10=%016" PRIx64
" r11=%016" PRIx64
" r12=%016" PRIx64
128 " nip=" TARGET_FMT_lx
"\n",
129 ppc_dump_gpr(env
, 3), ppc_dump_gpr(env
, 4),
130 ppc_dump_gpr(env
, 5), ppc_dump_gpr(env
, 6),
131 ppc_dump_gpr(env
, 7), ppc_dump_gpr(env
, 8),
132 ppc_dump_gpr(env
, 9), ppc_dump_gpr(env
, 10),
133 ppc_dump_gpr(env
, 11), ppc_dump_gpr(env
, 12),
138 /* Return true iff byteswap is needed to load instruction */
139 static inline bool insn_need_byteswap(CPUArchState
*env
)
141 /* SYSTEM builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
142 return !!(env
->msr
& ((target_ulong
)1 << MSR_LE
));
145 static uint32_t ppc_ldl_code(CPUArchState
*env
, target_ulong addr
)
147 uint32_t insn
= cpu_ldl_code(env
, addr
);
149 if (insn_need_byteswap(env
)) {
150 insn
= bswap32(insn
);
157 static void ppc_excp_debug_sw_tlb(CPUPPCState
*env
, int excp
)
160 target_ulong
*miss
, *cmp
;
163 if (!qemu_loglevel_mask(CPU_LOG_MMU
)) {
167 if (excp
== POWERPC_EXCP_IFTLB
) {
170 miss
= &env
->spr
[SPR_IMISS
];
171 cmp
= &env
->spr
[SPR_ICMP
];
173 if (excp
== POWERPC_EXCP_DLTLB
) {
179 miss
= &env
->spr
[SPR_DMISS
];
180 cmp
= &env
->spr
[SPR_DCMP
];
182 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx
" %cC "
183 TARGET_FMT_lx
" H1 " TARGET_FMT_lx
" H2 "
184 TARGET_FMT_lx
" %08x\n", es
, en
, *miss
, en
, *cmp
,
185 env
->spr
[SPR_HASH1
], env
->spr
[SPR_HASH2
],
190 static int powerpc_reset_wakeup(CPUPPCState
*env
, int excp
, target_ulong
*msr
)
192 /* We no longer are in a PM state */
193 env
->resume_as_sreset
= false;
195 /* Pretend to be returning from doze always as we don't lose state */
196 *msr
|= SRR1_WS_NOLOSS
;
198 /* Machine checks are sent normally */
199 if (excp
== POWERPC_EXCP_MCHECK
) {
203 case POWERPC_EXCP_RESET
:
204 *msr
|= SRR1_WAKERESET
;
206 case POWERPC_EXCP_EXTERNAL
:
209 case POWERPC_EXCP_DECR
:
210 *msr
|= SRR1_WAKEDEC
;
212 case POWERPC_EXCP_SDOOR
:
213 *msr
|= SRR1_WAKEDBELL
;
215 case POWERPC_EXCP_SDOOR_HV
:
216 *msr
|= SRR1_WAKEHDBELL
;
218 case POWERPC_EXCP_HV_MAINT
:
219 *msr
|= SRR1_WAKEHMI
;
221 case POWERPC_EXCP_HVIRT
:
222 *msr
|= SRR1_WAKEHVI
;
225 cpu_abort(env_cpu(env
),
226 "Unsupported exception %d in Power Save mode\n", excp
);
228 return POWERPC_EXCP_RESET
;
232 * AIL - Alternate Interrupt Location, a mode that allows interrupts to be
233 * taken with the MMU on, and which uses an alternate location (e.g., so the
234 * kernel/hv can map the vectors there with an effective address).
236 * An interrupt is considered to be taken "with AIL" or "AIL applies" if they
237 * are delivered in this way. AIL requires the LPCR to be set to enable this
238 * mode, and then a number of conditions have to be true for AIL to apply.
240 * First of all, SRESET, MCE, and HMI are always delivered without AIL, because
241 * they specifically want to be in real mode (e.g., the MCE might be signaling
242 * a SLB multi-hit which requires SLB flush before the MMU can be enabled).
244 * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV],
245 * whether or not the interrupt changes MSR[HV] from 0 to 1, and the current
246 * radix mode (LPCR[HR]).
248 * POWER8, POWER9 with LPCR[HR]=0
249 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
250 * +-----------+-------------+---------+-------------+-----+
251 * | a | 00/01/10 | x | x | 0 |
252 * | a | 11 | 0 | 1 | 0 |
253 * | a | 11 | 1 | 1 | a |
254 * | a | 11 | 0 | 0 | a |
255 * +-------------------------------------------------------+
257 * POWER9 with LPCR[HR]=1
258 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
259 * +-----------+-------------+---------+-------------+-----+
260 * | a | 00/01/10 | x | x | 0 |
261 * | a | 11 | x | x | a |
262 * +-------------------------------------------------------+
264 * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to
265 * the hypervisor in AIL mode if the guest is radix. This is good for
266 * performance but allows the guest to influence the AIL of hypervisor
267 * interrupts using its MSR, and also the hypervisor must disallow guest
268 * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to
269 * use AIL for its MSR[HV] 0->1 interrupts.
271 * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to
272 * interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and
275 * HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1.
277 * POWER10 behaviour is
278 * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
279 * +-----------+------------+-------------+---------+-------------+-----+
280 * | a | h | 00/01/10 | 0 | 0 | 0 |
281 * | a | h | 11 | 0 | 0 | a |
282 * | a | h | x | 0 | 1 | h |
283 * | a | h | 00/01/10 | 1 | 1 | 0 |
284 * | a | h | 11 | 1 | 1 | h |
285 * +--------------------------------------------------------------------+
287 static void ppc_excp_apply_ail(PowerPCCPU
*cpu
, int excp
, target_ulong msr
,
288 target_ulong
*new_msr
, target_ulong
*vector
)
290 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
291 CPUPPCState
*env
= &cpu
->env
;
292 bool mmu_all_on
= ((msr
>> MSR_IR
) & 1) && ((msr
>> MSR_DR
) & 1);
293 bool hv_escalation
= !(msr
& MSR_HVB
) && (*new_msr
& MSR_HVB
);
296 if (excp
== POWERPC_EXCP_MCHECK
||
297 excp
== POWERPC_EXCP_RESET
||
298 excp
== POWERPC_EXCP_HV_MAINT
) {
299 /* SRESET, MCE, HMI never apply AIL */
303 if (!(pcc
->lpcr_mask
& LPCR_AIL
)) {
304 /* This CPU does not have AIL */
309 if (!(pcc
->lpcr_mask
& LPCR_HAIL
)) {
311 /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */
314 if (hv_escalation
&& !(env
->spr
[SPR_LPCR
] & LPCR_HR
)) {
316 * AIL does not work if there is a MSR[HV] 0->1 transition and the
317 * partition is in HPT mode. For radix guests, such interrupts are
318 * allowed to be delivered to the hypervisor in ail mode.
323 ail
= (env
->spr
[SPR_LPCR
] & LPCR_AIL
) >> LPCR_AIL_SHIFT
;
328 /* AIL=1 is reserved, treat it like AIL=0 */
334 if (!mmu_all_on
&& !hv_escalation
) {
336 * AIL works for HV interrupts even with guest MSR[IR/DR] disabled.
337 * Guest->guest and HV->HV interrupts do require MMU on.
342 if (*new_msr
& MSR_HVB
) {
343 if (!(env
->spr
[SPR_LPCR
] & LPCR_HAIL
)) {
344 /* HV interrupts depend on LPCR[HAIL] */
347 ail
= 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */
349 ail
= (env
->spr
[SPR_LPCR
] & LPCR_AIL
) >> LPCR_AIL_SHIFT
;
354 if (ail
== 1 || ail
== 2) {
355 /* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */
361 * AIL applies, so the new MSR gets IR and DR set, and an offset applied
364 *new_msr
|= (1 << MSR_IR
) | (1 << MSR_DR
);
366 if (excp
!= POWERPC_EXCP_SYSCALL_VECTORED
) {
368 *vector
|= 0x0000000000018000ull
;
369 } else if (ail
== 3) {
370 *vector
|= 0xc000000000004000ull
;
374 * scv AIL is a little different. AIL=2 does not change the address,
375 * only the MSR. AIL=3 replaces the 0x17000 base with 0xc...3000.
378 *vector
&= ~0x0000000000017000ull
; /* Un-apply the base offset */
379 *vector
|= 0xc000000000003000ull
; /* Apply scv's AIL=3 offset */
383 #endif /* TARGET_PPC64 */
385 static void powerpc_reset_excp_state(PowerPCCPU
*cpu
)
387 CPUState
*cs
= CPU(cpu
);
388 CPUPPCState
*env
= &cpu
->env
;
390 /* Reset exception state */
391 cs
->exception_index
= POWERPC_EXCP_NONE
;
395 static void powerpc_set_excp_state(PowerPCCPU
*cpu
, target_ulong vector
,
398 CPUPPCState
*env
= &cpu
->env
;
400 assert((msr
& env
->msr_mask
) == msr
);
403 * We don't use hreg_store_msr here as already have treated any
404 * special case that could occur. Just store MSR and update hflags
406 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it will
407 * prevent setting of the HV bit which some exceptions might need to do.
411 hreg_compute_hflags(env
);
412 ppc_maybe_interrupt(env
);
414 powerpc_reset_excp_state(cpu
);
417 * Any interrupt is context synchronizing, check if TCG TLB needs
418 * a delayed flush on ppc64
420 check_tlb_flush(env
, false);
422 /* Reset the reservation */
423 env
->reserve_addr
= -1;
426 static void powerpc_mcheck_checkstop(CPUPPCState
*env
)
428 CPUState
*cs
= env_cpu(env
);
430 if (FIELD_EX64(env
->msr
, MSR
, ME
)) {
434 /* Machine check exception is not enabled. Enter checkstop state. */
435 fprintf(stderr
, "Machine check while not allowed. "
436 "Entering checkstop state\n");
437 if (qemu_log_separate()) {
438 qemu_log("Machine check while not allowed. "
439 "Entering checkstop state\n");
442 cpu_interrupt_exittb(cs
);
445 static void powerpc_excp_40x(PowerPCCPU
*cpu
, int excp
)
447 CPUPPCState
*env
= &cpu
->env
;
448 target_ulong msr
, new_msr
, vector
;
449 int srr0
= SPR_SRR0
, srr1
= SPR_SRR1
;
451 /* new srr1 value excluding must-be-zero bits */
452 msr
= env
->msr
& ~0x783f0000ULL
;
454 /* new interrupt handler msr preserves ME unless explicitly overridden */
455 new_msr
= env
->msr
& (((target_ulong
)1 << MSR_ME
));
457 /* HV emu assistance interrupt only exists on server arch 2.05 or later */
458 if (excp
== POWERPC_EXCP_HV_EMU
) {
459 excp
= POWERPC_EXCP_PROGRAM
;
462 vector
= env
->excp_vectors
[excp
];
463 if (vector
== (target_ulong
)-1ULL) {
464 cpu_abort(env_cpu(env
),
465 "Raised an exception without defined vector %d\n", excp
);
467 vector
|= env
->excp_prefix
;
470 case POWERPC_EXCP_CRITICAL
: /* Critical input */
474 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
475 powerpc_mcheck_checkstop(env
);
476 /* machine check exceptions don't have ME set */
477 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
481 case POWERPC_EXCP_DSI
: /* Data storage exception */
482 trace_ppc_excp_dsi(env
->spr
[SPR_40x_ESR
], env
->spr
[SPR_40x_DEAR
]);
484 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
485 trace_ppc_excp_isi(msr
, env
->nip
);
487 case POWERPC_EXCP_EXTERNAL
: /* External input */
489 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
491 case POWERPC_EXCP_PROGRAM
: /* Program exception */
492 switch (env
->error_code
& ~0xF) {
493 case POWERPC_EXCP_FP
:
494 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
495 trace_ppc_excp_fp_ignore();
496 powerpc_reset_excp_state(cpu
);
499 env
->spr
[SPR_40x_ESR
] = ESR_FP
;
501 case POWERPC_EXCP_INVAL
:
502 trace_ppc_excp_inval(env
->nip
);
503 env
->spr
[SPR_40x_ESR
] = ESR_PIL
;
505 case POWERPC_EXCP_PRIV
:
506 env
->spr
[SPR_40x_ESR
] = ESR_PPR
;
508 case POWERPC_EXCP_TRAP
:
509 env
->spr
[SPR_40x_ESR
] = ESR_PTR
;
512 cpu_abort(env_cpu(env
), "Invalid program exception %d. Aborting\n",
517 case POWERPC_EXCP_SYSCALL
: /* System call exception */
521 * We need to correct the NIP which in this case is supposed
522 * to point to the next instruction
526 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
527 trace_ppc_excp_print("FIT");
529 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
530 trace_ppc_excp_print("WDT");
532 case POWERPC_EXCP_DTLB
: /* Data TLB error */
533 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
535 case POWERPC_EXCP_PIT
: /* Programmable interval timer interrupt */
536 trace_ppc_excp_print("PIT");
538 case POWERPC_EXCP_DEBUG
: /* Debug interrupt */
539 cpu_abort(env_cpu(env
), "%s exception not implemented\n",
540 powerpc_excp_name(excp
));
543 cpu_abort(env_cpu(env
), "Invalid PowerPC exception %d. Aborting\n",
548 env
->spr
[srr0
] = env
->nip
;
549 env
->spr
[srr1
] = msr
;
550 powerpc_set_excp_state(cpu
, vector
, new_msr
);
553 static void powerpc_excp_6xx(PowerPCCPU
*cpu
, int excp
)
555 CPUPPCState
*env
= &cpu
->env
;
556 target_ulong msr
, new_msr
, vector
;
558 /* new srr1 value excluding must-be-zero bits */
559 msr
= env
->msr
& ~0x783f0000ULL
;
561 /* new interrupt handler msr preserves ME unless explicitly overridden */
562 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
564 /* HV emu assistance interrupt only exists on server arch 2.05 or later */
565 if (excp
== POWERPC_EXCP_HV_EMU
) {
566 excp
= POWERPC_EXCP_PROGRAM
;
569 vector
= env
->excp_vectors
[excp
];
570 if (vector
== (target_ulong
)-1ULL) {
571 cpu_abort(env_cpu(env
),
572 "Raised an exception without defined vector %d\n", excp
);
574 vector
|= env
->excp_prefix
;
577 case POWERPC_EXCP_CRITICAL
: /* Critical input */
579 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
580 powerpc_mcheck_checkstop(env
);
581 /* machine check exceptions don't have ME set */
582 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
584 case POWERPC_EXCP_DSI
: /* Data storage exception */
585 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
587 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
588 trace_ppc_excp_isi(msr
, env
->nip
);
589 msr
|= env
->error_code
;
591 case POWERPC_EXCP_EXTERNAL
: /* External input */
593 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
594 /* Get rS/rD and rA from faulting opcode */
596 * Note: the opcode fields will not be set properly for a
597 * direct store load/store, but nobody cares as nobody
598 * actually uses direct store segments.
600 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
602 case POWERPC_EXCP_PROGRAM
: /* Program exception */
603 switch (env
->error_code
& ~0xF) {
604 case POWERPC_EXCP_FP
:
605 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
606 trace_ppc_excp_fp_ignore();
607 powerpc_reset_excp_state(cpu
);
611 * NIP always points to the faulting instruction for FP exceptions,
612 * so always use store_next and claim we are precise in the MSR.
616 case POWERPC_EXCP_INVAL
:
617 trace_ppc_excp_inval(env
->nip
);
620 case POWERPC_EXCP_PRIV
:
623 case POWERPC_EXCP_TRAP
:
627 /* Should never occur */
628 cpu_abort(env_cpu(env
), "Invalid program exception %d. Aborting\n",
633 case POWERPC_EXCP_SYSCALL
: /* System call exception */
637 * We need to correct the NIP which in this case is supposed
638 * to point to the next instruction
642 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
643 case POWERPC_EXCP_DECR
: /* Decrementer exception */
645 case POWERPC_EXCP_DTLB
: /* Data TLB error */
646 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
648 case POWERPC_EXCP_RESET
: /* System reset exception */
649 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
650 cpu_abort(env_cpu(env
),
651 "Trying to deliver power-saving system reset exception "
652 "%d with no HV support\n", excp
);
655 case POWERPC_EXCP_TRACE
: /* Trace exception */
657 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
658 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
659 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
660 /* Swap temporary saved registers with GPRs */
661 if (!(new_msr
& ((target_ulong
)1 << MSR_TGPR
))) {
662 new_msr
|= (target_ulong
)1 << MSR_TGPR
;
663 hreg_swap_gpr_tgpr(env
);
666 ppc_excp_debug_sw_tlb(env
, excp
);
668 msr
|= env
->crf
[0] << 28;
669 msr
|= env
->error_code
; /* key, D/I, S/L bits */
670 /* Set way using a LRU mechanism */
671 msr
|= ((env
->last_way
+ 1) & (env
->nb_ways
- 1)) << 17;
673 case POWERPC_EXCP_FPA
: /* Floating-point assist exception */
674 case POWERPC_EXCP_DABR
: /* Data address breakpoint */
675 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
676 case POWERPC_EXCP_SMI
: /* System management interrupt */
677 case POWERPC_EXCP_MEXTBR
: /* Maskable external breakpoint */
678 case POWERPC_EXCP_NMEXTBR
: /* Non maskable external breakpoint */
679 cpu_abort(env_cpu(env
), "%s exception not implemented\n",
680 powerpc_excp_name(excp
));
683 cpu_abort(env_cpu(env
), "Invalid PowerPC exception %d. Aborting\n",
688 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
689 new_msr
|= (target_ulong
)1 << MSR_LE
;
691 env
->spr
[SPR_SRR0
] = env
->nip
;
692 env
->spr
[SPR_SRR1
] = msr
;
693 powerpc_set_excp_state(cpu
, vector
, new_msr
);
696 static void powerpc_excp_7xx(PowerPCCPU
*cpu
, int excp
)
698 CPUPPCState
*env
= &cpu
->env
;
699 target_ulong msr
, new_msr
, vector
;
701 /* new srr1 value excluding must-be-zero bits */
702 msr
= env
->msr
& ~0x783f0000ULL
;
704 /* new interrupt handler msr preserves ME unless explicitly overridden */
705 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
707 /* HV emu assistance interrupt only exists on server arch 2.05 or later */
708 if (excp
== POWERPC_EXCP_HV_EMU
) {
709 excp
= POWERPC_EXCP_PROGRAM
;
712 vector
= env
->excp_vectors
[excp
];
713 if (vector
== (target_ulong
)-1ULL) {
714 cpu_abort(env_cpu(env
),
715 "Raised an exception without defined vector %d\n", excp
);
717 vector
|= env
->excp_prefix
;
720 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
721 powerpc_mcheck_checkstop(env
);
722 /* machine check exceptions don't have ME set */
723 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
725 case POWERPC_EXCP_DSI
: /* Data storage exception */
726 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
728 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
729 trace_ppc_excp_isi(msr
, env
->nip
);
730 msr
|= env
->error_code
;
732 case POWERPC_EXCP_EXTERNAL
: /* External input */
734 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
735 /* Get rS/rD and rA from faulting opcode */
737 * Note: the opcode fields will not be set properly for a
738 * direct store load/store, but nobody cares as nobody
739 * actually uses direct store segments.
741 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
743 case POWERPC_EXCP_PROGRAM
: /* Program exception */
744 switch (env
->error_code
& ~0xF) {
745 case POWERPC_EXCP_FP
:
746 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
747 trace_ppc_excp_fp_ignore();
748 powerpc_reset_excp_state(cpu
);
752 * NIP always points to the faulting instruction for FP exceptions,
753 * so always use store_next and claim we are precise in the MSR.
757 case POWERPC_EXCP_INVAL
:
758 trace_ppc_excp_inval(env
->nip
);
761 case POWERPC_EXCP_PRIV
:
764 case POWERPC_EXCP_TRAP
:
768 /* Should never occur */
769 cpu_abort(env_cpu(env
), "Invalid program exception %d. Aborting\n",
774 case POWERPC_EXCP_SYSCALL
: /* System call exception */
776 int lev
= env
->error_code
;
778 if (lev
== 1 && cpu
->vhyp
) {
785 * We need to correct the NIP which in this case is supposed
786 * to point to the next instruction
791 * The Virtual Open Firmware (VOF) relies on the 'sc 1'
792 * instruction to communicate with QEMU. The pegasos2 machine
793 * uses VOF and the 7xx CPUs, so although the 7xx don't have
794 * HV mode, we need to keep hypercall support.
796 if (lev
== 1 && cpu
->vhyp
) {
797 PPCVirtualHypervisorClass
*vhc
=
798 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
799 vhc
->hypercall(cpu
->vhyp
, cpu
);
800 powerpc_reset_excp_state(cpu
);
806 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
807 case POWERPC_EXCP_DECR
: /* Decrementer exception */
809 case POWERPC_EXCP_RESET
: /* System reset exception */
810 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
811 cpu_abort(env_cpu(env
),
812 "Trying to deliver power-saving system reset exception "
813 "%d with no HV support\n", excp
);
816 case POWERPC_EXCP_TRACE
: /* Trace exception */
818 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
819 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
820 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
821 ppc_excp_debug_sw_tlb(env
, excp
);
822 msr
|= env
->crf
[0] << 28;
823 msr
|= env
->error_code
; /* key, D/I, S/L bits */
824 /* Set way using a LRU mechanism */
825 msr
|= ((env
->last_way
+ 1) & (env
->nb_ways
- 1)) << 17;
827 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
828 case POWERPC_EXCP_SMI
: /* System management interrupt */
829 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
830 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor interrupt */
831 cpu_abort(env_cpu(env
), "%s exception not implemented\n",
832 powerpc_excp_name(excp
));
835 cpu_abort(env_cpu(env
), "Invalid PowerPC exception %d. Aborting\n",
840 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
841 new_msr
|= (target_ulong
)1 << MSR_LE
;
843 env
->spr
[SPR_SRR0
] = env
->nip
;
844 env
->spr
[SPR_SRR1
] = msr
;
845 powerpc_set_excp_state(cpu
, vector
, new_msr
);
848 static void powerpc_excp_74xx(PowerPCCPU
*cpu
, int excp
)
850 CPUPPCState
*env
= &cpu
->env
;
851 target_ulong msr
, new_msr
, vector
;
853 /* new srr1 value excluding must-be-zero bits */
854 msr
= env
->msr
& ~0x783f0000ULL
;
856 /* new interrupt handler msr preserves ME unless explicitly overridden */
857 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
859 /* HV emu assistance interrupt only exists on server arch 2.05 or later */
860 if (excp
== POWERPC_EXCP_HV_EMU
) {
861 excp
= POWERPC_EXCP_PROGRAM
;
864 vector
= env
->excp_vectors
[excp
];
865 if (vector
== (target_ulong
)-1ULL) {
866 cpu_abort(env_cpu(env
),
867 "Raised an exception without defined vector %d\n", excp
);
869 vector
|= env
->excp_prefix
;
872 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
873 powerpc_mcheck_checkstop(env
);
874 /* machine check exceptions don't have ME set */
875 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
877 case POWERPC_EXCP_DSI
: /* Data storage exception */
878 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
880 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
881 trace_ppc_excp_isi(msr
, env
->nip
);
882 msr
|= env
->error_code
;
884 case POWERPC_EXCP_EXTERNAL
: /* External input */
886 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
887 /* Get rS/rD and rA from faulting opcode */
889 * Note: the opcode fields will not be set properly for a
890 * direct store load/store, but nobody cares as nobody
891 * actually uses direct store segments.
893 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
895 case POWERPC_EXCP_PROGRAM
: /* Program exception */
896 switch (env
->error_code
& ~0xF) {
897 case POWERPC_EXCP_FP
:
898 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
899 trace_ppc_excp_fp_ignore();
900 powerpc_reset_excp_state(cpu
);
904 * NIP always points to the faulting instruction for FP exceptions,
905 * so always use store_next and claim we are precise in the MSR.
909 case POWERPC_EXCP_INVAL
:
910 trace_ppc_excp_inval(env
->nip
);
913 case POWERPC_EXCP_PRIV
:
916 case POWERPC_EXCP_TRAP
:
920 /* Should never occur */
921 cpu_abort(env_cpu(env
), "Invalid program exception %d. Aborting\n",
926 case POWERPC_EXCP_SYSCALL
: /* System call exception */
928 int lev
= env
->error_code
;
930 if (lev
== 1 && cpu
->vhyp
) {
937 * We need to correct the NIP which in this case is supposed
938 * to point to the next instruction
943 * The Virtual Open Firmware (VOF) relies on the 'sc 1'
944 * instruction to communicate with QEMU. The pegasos2 machine
945 * uses VOF and the 74xx CPUs, so although the 74xx don't have
946 * HV mode, we need to keep hypercall support.
948 if (lev
== 1 && cpu
->vhyp
) {
949 PPCVirtualHypervisorClass
*vhc
=
950 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
951 vhc
->hypercall(cpu
->vhyp
, cpu
);
952 powerpc_reset_excp_state(cpu
);
958 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
959 case POWERPC_EXCP_DECR
: /* Decrementer exception */
961 case POWERPC_EXCP_RESET
: /* System reset exception */
962 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
963 cpu_abort(env_cpu(env
),
964 "Trying to deliver power-saving system reset "
965 "exception %d with no HV support\n", excp
);
968 case POWERPC_EXCP_TRACE
: /* Trace exception */
970 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
972 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
973 case POWERPC_EXCP_SMI
: /* System management interrupt */
974 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
975 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor interrupt */
976 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
977 cpu_abort(env_cpu(env
), "%s exception not implemented\n",
978 powerpc_excp_name(excp
));
981 cpu_abort(env_cpu(env
), "Invalid PowerPC exception %d. Aborting\n",
986 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
987 new_msr
|= (target_ulong
)1 << MSR_LE
;
989 env
->spr
[SPR_SRR0
] = env
->nip
;
990 env
->spr
[SPR_SRR1
] = msr
;
991 powerpc_set_excp_state(cpu
, vector
, new_msr
);
994 static void powerpc_excp_booke(PowerPCCPU
*cpu
, int excp
)
996 CPUPPCState
*env
= &cpu
->env
;
997 target_ulong msr
, new_msr
, vector
;
998 int srr0
= SPR_SRR0
, srr1
= SPR_SRR1
;
1001 * Book E does not play games with certain bits of xSRR1 being MSR save
1002 * bits and others being error status. xSRR1 is the old MSR, period.
1006 /* new interrupt handler msr preserves ME unless explicitly overridden */
1007 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
1009 /* HV emu assistance interrupt only exists on server arch 2.05 or later */
1010 if (excp
== POWERPC_EXCP_HV_EMU
) {
1011 excp
= POWERPC_EXCP_PROGRAM
;
1016 * SPEU and VPU share the same IVOR but they exist in different
1017 * processors. SPEU is e500v1/2 only and VPU is e6500 only.
1019 if (excp
== POWERPC_EXCP_VPU
) {
1020 excp
= POWERPC_EXCP_SPEU
;
1024 vector
= env
->excp_vectors
[excp
];
1025 if (vector
== (target_ulong
)-1ULL) {
1026 cpu_abort(env_cpu(env
),
1027 "Raised an exception without defined vector %d\n", excp
);
1029 vector
|= env
->excp_prefix
;
1032 case POWERPC_EXCP_CRITICAL
: /* Critical input */
1033 srr0
= SPR_BOOKE_CSRR0
;
1034 srr1
= SPR_BOOKE_CSRR1
;
1036 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
1037 powerpc_mcheck_checkstop(env
);
1038 /* machine check exceptions don't have ME set */
1039 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
1041 /* FIXME: choose one or the other based on CPU type */
1042 srr0
= SPR_BOOKE_MCSRR0
;
1043 srr1
= SPR_BOOKE_MCSRR1
;
1045 env
->spr
[SPR_BOOKE_CSRR0
] = env
->nip
;
1046 env
->spr
[SPR_BOOKE_CSRR1
] = msr
;
1049 case POWERPC_EXCP_DSI
: /* Data storage exception */
1050 trace_ppc_excp_dsi(env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
1052 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
1053 trace_ppc_excp_isi(msr
, env
->nip
);
1055 case POWERPC_EXCP_EXTERNAL
: /* External input */
1056 if (env
->mpic_proxy
) {
1057 CPUState
*cs
= env_cpu(env
);
1058 /* IACK the IRQ on delivery */
1059 env
->spr
[SPR_BOOKE_EPR
] = ldl_phys(cs
->as
, env
->mpic_iack
);
1062 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
1064 case POWERPC_EXCP_PROGRAM
: /* Program exception */
1065 switch (env
->error_code
& ~0xF) {
1066 case POWERPC_EXCP_FP
:
1067 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
1068 trace_ppc_excp_fp_ignore();
1069 powerpc_reset_excp_state(cpu
);
1073 * NIP always points to the faulting instruction for FP exceptions,
1074 * so always use store_next and claim we are precise in the MSR.
1077 env
->spr
[SPR_BOOKE_ESR
] = ESR_FP
;
1079 case POWERPC_EXCP_INVAL
:
1080 trace_ppc_excp_inval(env
->nip
);
1082 env
->spr
[SPR_BOOKE_ESR
] = ESR_PIL
;
1084 case POWERPC_EXCP_PRIV
:
1086 env
->spr
[SPR_BOOKE_ESR
] = ESR_PPR
;
1088 case POWERPC_EXCP_TRAP
:
1090 env
->spr
[SPR_BOOKE_ESR
] = ESR_PTR
;
1093 /* Should never occur */
1094 cpu_abort(env_cpu(env
), "Invalid program exception %d. Aborting\n",
1099 case POWERPC_EXCP_SYSCALL
: /* System call exception */
1103 * We need to correct the NIP which in this case is supposed
1104 * to point to the next instruction
1108 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1109 case POWERPC_EXCP_APU
: /* Auxiliary processor unavailable */
1110 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1112 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
1114 trace_ppc_excp_print("FIT");
1116 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
1117 trace_ppc_excp_print("WDT");
1118 srr0
= SPR_BOOKE_CSRR0
;
1119 srr1
= SPR_BOOKE_CSRR1
;
1121 case POWERPC_EXCP_DTLB
: /* Data TLB error */
1122 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
1124 case POWERPC_EXCP_DEBUG
: /* Debug interrupt */
1125 if (env
->flags
& POWERPC_FLAG_DE
) {
1126 /* FIXME: choose one or the other based on CPU type */
1127 srr0
= SPR_BOOKE_DSRR0
;
1128 srr1
= SPR_BOOKE_DSRR1
;
1130 env
->spr
[SPR_BOOKE_CSRR0
] = env
->nip
;
1131 env
->spr
[SPR_BOOKE_CSRR1
] = msr
;
1133 /* DBSR already modified by caller */
1135 cpu_abort(env_cpu(env
),
1136 "Debug exception triggered on unsupported model\n");
1139 case POWERPC_EXCP_SPEU
: /* SPE/embedded floating-point unavailable/VPU */
1140 env
->spr
[SPR_BOOKE_ESR
] = ESR_SPV
;
1142 case POWERPC_EXCP_DOORI
: /* Embedded doorbell interrupt */
1144 case POWERPC_EXCP_DOORCI
: /* Embedded doorbell critical interrupt */
1145 srr0
= SPR_BOOKE_CSRR0
;
1146 srr1
= SPR_BOOKE_CSRR1
;
1148 case POWERPC_EXCP_RESET
: /* System reset exception */
1149 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
1150 cpu_abort(env_cpu(env
),
1151 "Trying to deliver power-saving system reset "
1152 "exception %d with no HV support\n", excp
);
1155 case POWERPC_EXCP_EFPDI
: /* Embedded floating-point data interrupt */
1156 case POWERPC_EXCP_EFPRI
: /* Embedded floating-point round interrupt */
1157 cpu_abort(env_cpu(env
), "%s exception not implemented\n",
1158 powerpc_excp_name(excp
));
1161 cpu_abort(env_cpu(env
), "Invalid PowerPC exception %d. Aborting\n",
1167 if (env
->spr
[SPR_BOOKE_EPCR
] & EPCR_ICM
) {
1168 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
1169 new_msr
|= (target_ulong
)1 << MSR_CM
;
1171 vector
= (uint32_t)vector
;
1175 env
->spr
[srr0
] = env
->nip
;
1176 env
->spr
[srr1
] = msr
;
1177 powerpc_set_excp_state(cpu
, vector
, new_msr
);
1181 * When running a nested HV guest under vhyp, external interrupts are
1182 * delivered as HVIRT.
1184 static bool books_vhyp_promotes_external_to_hvirt(PowerPCCPU
*cpu
)
1187 return vhyp_cpu_in_nested(cpu
);
1194 * When running under vhyp, hcalls are always intercepted and sent to the
1195 * vhc->hypercall handler.
1197 static bool books_vhyp_handles_hcall(PowerPCCPU
*cpu
)
1200 return !vhyp_cpu_in_nested(cpu
);
1206 * When running a nested KVM HV guest under vhyp, HV exceptions are not
1207 * delivered to the guest (because there is no concept of HV support), but
1208 * rather they are sent to the vhyp to exit from the L2 back to the L1 and
1209 * return from the H_ENTER_NESTED hypercall.
1211 static bool books_vhyp_handles_hv_excp(PowerPCCPU
*cpu
)
1214 return vhyp_cpu_in_nested(cpu
);
1220 static bool is_prefix_insn(CPUPPCState
*env
, uint32_t insn
)
1222 if (!(env
->insns_flags2
& PPC2_ISA310
)) {
1225 return ((insn
& 0xfc000000) == 0x04000000);
1228 static bool is_prefix_insn_excp(PowerPCCPU
*cpu
, int excp
)
1230 CPUPPCState
*env
= &cpu
->env
;
1232 if (!(env
->insns_flags2
& PPC2_ISA310
)) {
1236 if (!tcg_enabled()) {
1238 * This does not load instructions and set the prefix bit correctly
1239 * for injected interrupts with KVM. That may have to be discovered
1240 * and set by the KVM layer before injecting.
1246 case POWERPC_EXCP_MCHECK
:
1247 if (!(env
->error_code
& PPC_BIT(42))) {
1249 * Fetch attempt caused a machine check, so attempting to fetch
1250 * again would cause a recursive machine check.
1255 case POWERPC_EXCP_HDSI
:
1256 /* HDSI PRTABLE_FAULT has the originating access type in error_code */
1257 if ((env
->spr
[SPR_HDSISR
] & DSISR_PRTABLE_FAULT
) &&
1258 (env
->error_code
== MMU_INST_FETCH
)) {
1260 * Fetch failed due to partition scope translation, so prefix
1261 * indication is not relevant (and attempting to load the
1262 * instruction at NIP would cause recursive faults with the same
1269 case POWERPC_EXCP_DSI
:
1270 case POWERPC_EXCP_DSEG
:
1271 case POWERPC_EXCP_ALIGN
:
1272 case POWERPC_EXCP_PROGRAM
:
1273 case POWERPC_EXCP_FPU
:
1274 case POWERPC_EXCP_TRACE
:
1275 case POWERPC_EXCP_HV_EMU
:
1276 case POWERPC_EXCP_VPU
:
1277 case POWERPC_EXCP_VSXU
:
1278 case POWERPC_EXCP_FU
:
1279 case POWERPC_EXCP_HV_FU
:
1285 return is_prefix_insn(env
, ppc_ldl_code(env
, env
->nip
));
1288 static bool is_prefix_insn_excp(PowerPCCPU
*cpu
, int excp
)
1294 static void powerpc_excp_books(PowerPCCPU
*cpu
, int excp
)
1296 CPUPPCState
*env
= &cpu
->env
;
1297 target_ulong msr
, new_msr
, vector
;
1298 int srr0
= SPR_SRR0
, srr1
= SPR_SRR1
, lev
= -1;
1300 /* new srr1 value excluding must-be-zero bits */
1301 msr
= env
->msr
& ~0x783f0000ULL
;
1304 * new interrupt handler msr preserves HV and ME unless explicitly
1307 new_msr
= env
->msr
& (((target_ulong
)1 << MSR_ME
) | MSR_HVB
);
1310 * check for special resume at 0x100 from doze/nap/sleep/winkle on
1313 if (env
->resume_as_sreset
) {
1314 excp
= powerpc_reset_wakeup(env
, excp
, &msr
);
1318 * We don't want to generate a Hypervisor Emulation Assistance
1319 * Interrupt if we don't have HVB in msr_mask (PAPR mode),
1320 * unless running a nested-hv guest, in which case the L1
1321 * kernel wants the interrupt.
1323 if (excp
== POWERPC_EXCP_HV_EMU
&& !(env
->msr_mask
& MSR_HVB
) &&
1324 !books_vhyp_handles_hv_excp(cpu
)) {
1325 excp
= POWERPC_EXCP_PROGRAM
;
1328 vector
= env
->excp_vectors
[excp
];
1329 if (vector
== (target_ulong
)-1ULL) {
1330 cpu_abort(env_cpu(env
),
1331 "Raised an exception without defined vector %d\n", excp
);
1333 vector
|= env
->excp_prefix
;
1335 if (is_prefix_insn_excp(cpu
, excp
)) {
1340 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
1341 powerpc_mcheck_checkstop(env
);
1342 if (env
->msr_mask
& MSR_HVB
) {
1344 * ISA specifies HV, but can be delivered to guest with HV
1345 * clear (e.g., see FWNMI in PAPR).
1347 new_msr
|= (target_ulong
)MSR_HVB
;
1349 /* HV machine check exceptions don't have ME set */
1350 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
1353 msr
|= env
->error_code
;
1356 case POWERPC_EXCP_DSI
: /* Data storage exception */
1357 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
1359 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
1360 trace_ppc_excp_isi(msr
, env
->nip
);
1361 msr
|= env
->error_code
;
1363 case POWERPC_EXCP_EXTERNAL
: /* External input */
1367 /* LPES0 is only taken into consideration if we support HV mode */
1368 if (!env
->has_hv_mode
) {
1371 lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
1373 new_msr
|= (target_ulong
)MSR_HVB
;
1374 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1380 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
1381 /* Optional DSISR update was removed from ISA v3.0 */
1382 if (!(env
->insns_flags2
& PPC2_ISA300
)) {
1383 /* Get rS/rD and rA from faulting opcode */
1385 * Note: the opcode fields will not be set properly for a
1386 * direct store load/store, but nobody cares as nobody
1387 * actually uses direct store segments.
1389 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
1392 case POWERPC_EXCP_PROGRAM
: /* Program exception */
1393 switch (env
->error_code
& ~0xF) {
1394 case POWERPC_EXCP_FP
:
1395 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
1396 trace_ppc_excp_fp_ignore();
1397 powerpc_reset_excp_state(cpu
);
1401 * NIP always points to the faulting instruction for FP exceptions,
1402 * so always use store_next and claim we are precise in the MSR.
1406 case POWERPC_EXCP_INVAL
:
1407 trace_ppc_excp_inval(env
->nip
);
1410 case POWERPC_EXCP_PRIV
:
1413 case POWERPC_EXCP_TRAP
:
1417 /* Should never occur */
1418 cpu_abort(env_cpu(env
), "Invalid program exception %d. Aborting\n",
1423 case POWERPC_EXCP_SYSCALL
: /* System call exception */
1424 lev
= env
->error_code
;
1426 if (lev
== 1 && cpu
->vhyp
) {
1433 * We need to correct the NIP which in this case is supposed
1434 * to point to the next instruction
1438 /* "PAPR mode" built-in hypercall emulation */
1439 if (lev
== 1 && books_vhyp_handles_hcall(cpu
)) {
1440 PPCVirtualHypervisorClass
*vhc
=
1441 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
1442 vhc
->hypercall(cpu
->vhyp
, cpu
);
1443 powerpc_reset_excp_state(cpu
);
1446 if (env
->insns_flags2
& PPC2_ISA310
) {
1447 /* ISAv3.1 puts LEV into SRR1 */
1451 new_msr
|= (target_ulong
)MSR_HVB
;
1454 case POWERPC_EXCP_SYSCALL_VECTORED
: /* scv exception */
1455 lev
= env
->error_code
;
1458 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_EE
);
1459 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1461 vector
+= lev
* 0x20;
1466 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1467 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1469 case POWERPC_EXCP_RESET
: /* System reset exception */
1470 /* A power-saving exception sets ME, otherwise it is unchanged */
1471 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
1472 /* indicate that we resumed from power save mode */
1474 new_msr
|= ((target_ulong
)1 << MSR_ME
);
1476 if (env
->msr_mask
& MSR_HVB
) {
1478 * ISA specifies HV, but can be delivered to guest with HV
1479 * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
1481 new_msr
|= (target_ulong
)MSR_HVB
;
1483 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
1484 cpu_abort(env_cpu(env
),
1485 "Trying to deliver power-saving system reset "
1486 "exception %d with no HV support\n", excp
);
1490 case POWERPC_EXCP_TRACE
: /* Trace exception */
1491 msr
|= env
->error_code
;
1493 case POWERPC_EXCP_DSEG
: /* Data segment exception */
1494 case POWERPC_EXCP_ISEG
: /* Instruction segment exception */
1495 case POWERPC_EXCP_SDOOR
: /* Doorbell interrupt */
1496 case POWERPC_EXCP_PERFM
: /* Performance monitor interrupt */
1498 case POWERPC_EXCP_HISI
: /* Hypervisor instruction storage exception */
1499 msr
|= env
->error_code
;
1501 case POWERPC_EXCP_HDECR
: /* Hypervisor decrementer exception */
1502 case POWERPC_EXCP_HDSI
: /* Hypervisor data storage exception */
1503 case POWERPC_EXCP_SDOOR_HV
: /* Hypervisor Doorbell interrupt */
1504 case POWERPC_EXCP_HVIRT
: /* Hypervisor virtualization */
1507 new_msr
|= (target_ulong
)MSR_HVB
;
1508 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1511 case POWERPC_EXCP_HV_EMU
: {
1512 uint32_t insn
= ppc_ldl_code(env
, env
->nip
);
1513 env
->spr
[SPR_HEIR
] = insn
;
1514 if (is_prefix_insn(env
, insn
)) {
1515 uint32_t insn2
= ppc_ldl_code(env
, env
->nip
+ 4);
1516 env
->spr
[SPR_HEIR
] <<= 32;
1517 env
->spr
[SPR_HEIR
] |= insn2
;
1521 new_msr
|= (target_ulong
)MSR_HVB
;
1522 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1526 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
1527 case POWERPC_EXCP_VSXU
: /* VSX unavailable exception */
1528 case POWERPC_EXCP_FU
: /* Facility unavailable exception */
1529 env
->spr
[SPR_FSCR
] |= ((target_ulong
)env
->error_code
<< 56);
1531 case POWERPC_EXCP_HV_FU
: /* Hypervisor Facility Unavailable Exception */
1532 env
->spr
[SPR_HFSCR
] |= ((target_ulong
)env
->error_code
<< FSCR_IC_POS
);
1535 new_msr
|= (target_ulong
)MSR_HVB
;
1536 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1538 case POWERPC_EXCP_PERFM_EBB
: /* Performance Monitor EBB Exception */
1539 case POWERPC_EXCP_EXTERNAL_EBB
: /* External EBB Exception */
1540 env
->spr
[SPR_BESCR
] &= ~BESCR_GE
;
1543 * Save NIP for rfebb insn in SPR_EBBRR. Next nip is
1544 * stored in the EBB Handler SPR_EBBHR.
1546 env
->spr
[SPR_EBBRR
] = env
->nip
;
1547 powerpc_set_excp_state(cpu
, env
->spr
[SPR_EBBHR
], env
->msr
);
1550 * This exception is handled in userspace. No need to proceed.
1553 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
1554 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
1555 case POWERPC_EXCP_MAINT
: /* Maintenance exception */
1556 case POWERPC_EXCP_HV_MAINT
: /* Hypervisor Maintenance exception */
1557 cpu_abort(env_cpu(env
), "%s exception not implemented\n",
1558 powerpc_excp_name(excp
));
1561 cpu_abort(env_cpu(env
), "Invalid PowerPC exception %d. Aborting\n",
1566 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
1567 new_msr
|= (target_ulong
)1 << MSR_LE
;
1569 new_msr
|= (target_ulong
)1 << MSR_SF
;
1571 if (excp
!= POWERPC_EXCP_SYSCALL_VECTORED
) {
1572 env
->spr
[srr0
] = env
->nip
;
1573 env
->spr
[srr1
] = msr
;
1576 if ((new_msr
& MSR_HVB
) && books_vhyp_handles_hv_excp(cpu
)) {
1577 PPCVirtualHypervisorClass
*vhc
=
1578 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
1579 /* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */
1580 vhc
->deliver_hv_excp(cpu
, excp
);
1581 powerpc_reset_excp_state(cpu
);
1584 if (!(env
->msr_mask
& MSR_HVB
) && srr0
== SPR_HSRR0
) {
1585 cpu_abort(env_cpu(env
), "Trying to deliver HV exception (HSRR) %d "
1586 "with no HV support\n", excp
);
1588 /* This can update new_msr and vector if AIL applies */
1589 ppc_excp_apply_ail(cpu
, excp
, msr
, &new_msr
, &vector
);
1590 powerpc_set_excp_state(cpu
, vector
, new_msr
);
1594 static inline void powerpc_excp_books(PowerPCCPU
*cpu
, int excp
)
1596 g_assert_not_reached();
1598 #endif /* TARGET_PPC64 */
1600 static void powerpc_excp(PowerPCCPU
*cpu
, int excp
)
1602 CPUPPCState
*env
= &cpu
->env
;
1604 if (excp
<= POWERPC_EXCP_NONE
|| excp
>= POWERPC_EXCP_NB
) {
1605 cpu_abort(env_cpu(env
), "Invalid PowerPC exception %d. Aborting\n",
1609 qemu_log_mask(CPU_LOG_INT
, "Raise exception at " TARGET_FMT_lx
1610 " => %s (%d) error=%02x\n", env
->nip
, powerpc_excp_name(excp
),
1611 excp
, env
->error_code
);
1612 env
->excp_stats
[excp
]++;
1614 switch (env
->excp_model
) {
1615 case POWERPC_EXCP_40x
:
1616 powerpc_excp_40x(cpu
, excp
);
1618 case POWERPC_EXCP_6xx
:
1619 powerpc_excp_6xx(cpu
, excp
);
1621 case POWERPC_EXCP_7xx
:
1622 powerpc_excp_7xx(cpu
, excp
);
1624 case POWERPC_EXCP_74xx
:
1625 powerpc_excp_74xx(cpu
, excp
);
1627 case POWERPC_EXCP_BOOKE
:
1628 powerpc_excp_booke(cpu
, excp
);
1630 case POWERPC_EXCP_970
:
1631 case POWERPC_EXCP_POWER7
:
1632 case POWERPC_EXCP_POWER8
:
1633 case POWERPC_EXCP_POWER9
:
1634 case POWERPC_EXCP_POWER10
:
1635 powerpc_excp_books(cpu
, excp
);
1638 g_assert_not_reached();
1642 void ppc_cpu_do_interrupt(CPUState
*cs
)
1644 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1646 powerpc_excp(cpu
, cs
->exception_index
);
1650 #define P7_UNUSED_INTERRUPTS \
1651 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_HVIRT | PPC_INTERRUPT_CEXT | \
1652 PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
1653 PPC_INTERRUPT_PIT | PPC_INTERRUPT_DOORBELL | PPC_INTERRUPT_HDOORBELL | \
1654 PPC_INTERRUPT_THERM | PPC_INTERRUPT_EBB)
1656 static int p7_interrupt_powersave(CPUPPCState
*env
)
1658 if ((env
->pending_interrupts
& PPC_INTERRUPT_EXT
) &&
1659 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE0
)) {
1660 return PPC_INTERRUPT_EXT
;
1662 if ((env
->pending_interrupts
& PPC_INTERRUPT_DECR
) &&
1663 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE1
)) {
1664 return PPC_INTERRUPT_DECR
;
1666 if ((env
->pending_interrupts
& PPC_INTERRUPT_MCK
) &&
1667 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE2
)) {
1668 return PPC_INTERRUPT_MCK
;
1670 if ((env
->pending_interrupts
& PPC_INTERRUPT_HMI
) &&
1671 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE2
)) {
1672 return PPC_INTERRUPT_HMI
;
1674 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
1675 return PPC_INTERRUPT_RESET
;
1680 static int p7_next_unmasked_interrupt(CPUPPCState
*env
)
1682 CPUState
*cs
= env_cpu(env
);
1684 /* Ignore MSR[EE] when coming out of some power management states */
1685 bool msr_ee
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
1687 assert((env
->pending_interrupts
& P7_UNUSED_INTERRUPTS
) == 0);
1690 /* LPCR[PECE] controls which interrupts can exit power-saving mode */
1691 return p7_interrupt_powersave(env
);
1694 /* Machine check exception */
1695 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
1696 return PPC_INTERRUPT_MCK
;
1699 /* Hypervisor decrementer exception */
1700 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
1701 /* LPCR will be clear when not supported so this will work */
1702 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
1703 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
1704 /* HDEC clears on delivery */
1705 return PPC_INTERRUPT_HDECR
;
1709 /* External interrupt can ignore MSR:EE under some circumstances */
1710 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
1711 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
1712 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
1713 /* HEIC blocks delivery to the hypervisor */
1714 if ((msr_ee
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
1715 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
1716 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
1717 return PPC_INTERRUPT_EXT
;
1721 /* Decrementer exception */
1722 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
1723 return PPC_INTERRUPT_DECR
;
1725 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
1726 return PPC_INTERRUPT_PERFM
;
1733 #define P8_UNUSED_INTERRUPTS \
1734 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_HVIRT | \
1735 PPC_INTERRUPT_CEXT | PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | \
1736 PPC_INTERRUPT_FIT | PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM)
1738 static int p8_interrupt_powersave(CPUPPCState
*env
)
1740 if ((env
->pending_interrupts
& PPC_INTERRUPT_EXT
) &&
1741 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE2
)) {
1742 return PPC_INTERRUPT_EXT
;
1744 if ((env
->pending_interrupts
& PPC_INTERRUPT_DECR
) &&
1745 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE3
)) {
1746 return PPC_INTERRUPT_DECR
;
1748 if ((env
->pending_interrupts
& PPC_INTERRUPT_MCK
) &&
1749 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE4
)) {
1750 return PPC_INTERRUPT_MCK
;
1752 if ((env
->pending_interrupts
& PPC_INTERRUPT_HMI
) &&
1753 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE4
)) {
1754 return PPC_INTERRUPT_HMI
;
1756 if ((env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) &&
1757 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE0
)) {
1758 return PPC_INTERRUPT_DOORBELL
;
1760 if ((env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) &&
1761 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE1
)) {
1762 return PPC_INTERRUPT_HDOORBELL
;
1764 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
1765 return PPC_INTERRUPT_RESET
;
1770 static int p8_next_unmasked_interrupt(CPUPPCState
*env
)
1772 CPUState
*cs
= env_cpu(env
);
1774 /* Ignore MSR[EE] when coming out of some power management states */
1775 bool msr_ee
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
1777 assert((env
->pending_interrupts
& P8_UNUSED_INTERRUPTS
) == 0);
1780 /* LPCR[PECE] controls which interrupts can exit power-saving mode */
1781 return p8_interrupt_powersave(env
);
1784 /* Machine check exception */
1785 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
1786 return PPC_INTERRUPT_MCK
;
1789 /* Hypervisor decrementer exception */
1790 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
1791 /* LPCR will be clear when not supported so this will work */
1792 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
1793 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
1794 /* HDEC clears on delivery */
1795 return PPC_INTERRUPT_HDECR
;
1799 /* External interrupt can ignore MSR:EE under some circumstances */
1800 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
1801 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
1802 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
1803 /* HEIC blocks delivery to the hypervisor */
1804 if ((msr_ee
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
1805 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
1806 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
1807 return PPC_INTERRUPT_EXT
;
1811 /* Decrementer exception */
1812 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
1813 return PPC_INTERRUPT_DECR
;
1815 if (env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) {
1816 return PPC_INTERRUPT_DOORBELL
;
1818 if (env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) {
1819 return PPC_INTERRUPT_HDOORBELL
;
1821 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
1822 return PPC_INTERRUPT_PERFM
;
1825 if (env
->pending_interrupts
& PPC_INTERRUPT_EBB
) {
1827 * EBB exception must be taken in problem state and
1828 * with BESCR_GE set.
1830 if (FIELD_EX64(env
->msr
, MSR
, PR
) &&
1831 (env
->spr
[SPR_BESCR
] & BESCR_GE
)) {
1832 return PPC_INTERRUPT_EBB
;
1840 #define P9_UNUSED_INTERRUPTS \
1841 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_CEXT | \
1842 PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
1843 PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM)
1845 static int p9_interrupt_powersave(CPUPPCState
*env
)
1847 /* External Exception */
1848 if ((env
->pending_interrupts
& PPC_INTERRUPT_EXT
) &&
1849 (env
->spr
[SPR_LPCR
] & LPCR_EEE
)) {
1850 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
1851 if (!heic
|| !FIELD_EX64_HV(env
->msr
) ||
1852 FIELD_EX64(env
->msr
, MSR
, PR
)) {
1853 return PPC_INTERRUPT_EXT
;
1856 /* Decrementer Exception */
1857 if ((env
->pending_interrupts
& PPC_INTERRUPT_DECR
) &&
1858 (env
->spr
[SPR_LPCR
] & LPCR_DEE
)) {
1859 return PPC_INTERRUPT_DECR
;
1861 /* Machine Check or Hypervisor Maintenance Exception */
1862 if (env
->spr
[SPR_LPCR
] & LPCR_OEE
) {
1863 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
1864 return PPC_INTERRUPT_MCK
;
1866 if (env
->pending_interrupts
& PPC_INTERRUPT_HMI
) {
1867 return PPC_INTERRUPT_HMI
;
1870 /* Privileged Doorbell Exception */
1871 if ((env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) &&
1872 (env
->spr
[SPR_LPCR
] & LPCR_PDEE
)) {
1873 return PPC_INTERRUPT_DOORBELL
;
1875 /* Hypervisor Doorbell Exception */
1876 if ((env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) &&
1877 (env
->spr
[SPR_LPCR
] & LPCR_HDEE
)) {
1878 return PPC_INTERRUPT_HDOORBELL
;
1880 /* Hypervisor virtualization exception */
1881 if ((env
->pending_interrupts
& PPC_INTERRUPT_HVIRT
) &&
1882 (env
->spr
[SPR_LPCR
] & LPCR_HVEE
)) {
1883 return PPC_INTERRUPT_HVIRT
;
1885 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
1886 return PPC_INTERRUPT_RESET
;
1891 static int p9_next_unmasked_interrupt(CPUPPCState
*env
)
1893 CPUState
*cs
= env_cpu(env
);
1895 /* Ignore MSR[EE] when coming out of some power management states */
1896 bool msr_ee
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
1898 assert((env
->pending_interrupts
& P9_UNUSED_INTERRUPTS
) == 0);
1901 if (env
->spr
[SPR_PSSCR
] & PSSCR_EC
) {
1903 * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can
1904 * wakeup the processor
1906 return p9_interrupt_powersave(env
);
1909 * When it's clear, any system-caused exception exits power-saving
1910 * mode, even the ones that gate on MSR[EE].
1916 /* Machine check exception */
1917 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
1918 return PPC_INTERRUPT_MCK
;
1921 /* Hypervisor decrementer exception */
1922 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
1923 /* LPCR will be clear when not supported so this will work */
1924 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
1925 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
1926 /* HDEC clears on delivery */
1927 return PPC_INTERRUPT_HDECR
;
1931 /* Hypervisor virtualization interrupt */
1932 if (env
->pending_interrupts
& PPC_INTERRUPT_HVIRT
) {
1933 /* LPCR will be clear when not supported so this will work */
1934 bool hvice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HVICE
);
1935 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hvice
) {
1936 return PPC_INTERRUPT_HVIRT
;
1940 /* External interrupt can ignore MSR:EE under some circumstances */
1941 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
1942 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
1943 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
1944 /* HEIC blocks delivery to the hypervisor */
1945 if ((msr_ee
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
1946 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
1947 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
1948 return PPC_INTERRUPT_EXT
;
1952 /* Decrementer exception */
1953 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
1954 return PPC_INTERRUPT_DECR
;
1956 if (env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) {
1957 return PPC_INTERRUPT_DOORBELL
;
1959 if (env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) {
1960 return PPC_INTERRUPT_HDOORBELL
;
1962 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
1963 return PPC_INTERRUPT_PERFM
;
1966 if (env
->pending_interrupts
& PPC_INTERRUPT_EBB
) {
1968 * EBB exception must be taken in problem state and
1969 * with BESCR_GE set.
1971 if (FIELD_EX64(env
->msr
, MSR
, PR
) &&
1972 (env
->spr
[SPR_BESCR
] & BESCR_GE
)) {
1973 return PPC_INTERRUPT_EBB
;
1980 #endif /* TARGET_PPC64 */
1982 static int ppc_next_unmasked_interrupt(CPUPPCState
*env
)
1985 switch (env
->excp_model
) {
1986 case POWERPC_EXCP_POWER7
:
1987 return p7_next_unmasked_interrupt(env
);
1988 case POWERPC_EXCP_POWER8
:
1989 return p8_next_unmasked_interrupt(env
);
1990 case POWERPC_EXCP_POWER9
:
1991 case POWERPC_EXCP_POWER10
:
1992 return p9_next_unmasked_interrupt(env
);
1999 /* External reset */
2000 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
2001 return PPC_INTERRUPT_RESET
;
2003 /* Machine check exception */
2004 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
2005 return PPC_INTERRUPT_MCK
;
2008 /* External debug exception */
2009 if (env
->pending_interrupts
& PPC_INTERRUPT_DEBUG
) {
2010 return PPC_INTERRUPT_DEBUG
;
2015 * For interrupts that gate on MSR:EE, we need to do something a
2016 * bit more subtle, as we need to let them through even when EE is
2017 * clear when coming out of some power management states (in order
2018 * for them to become a 0x100).
2020 async_deliver
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
2022 /* Hypervisor decrementer exception */
2023 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
2024 /* LPCR will be clear when not supported so this will work */
2025 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
2026 if ((async_deliver
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
2027 /* HDEC clears on delivery */
2028 return PPC_INTERRUPT_HDECR
;
2032 /* Hypervisor virtualization interrupt */
2033 if (env
->pending_interrupts
& PPC_INTERRUPT_HVIRT
) {
2034 /* LPCR will be clear when not supported so this will work */
2035 bool hvice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HVICE
);
2036 if ((async_deliver
|| !FIELD_EX64_HV(env
->msr
)) && hvice
) {
2037 return PPC_INTERRUPT_HVIRT
;
2041 /* External interrupt can ignore MSR:EE under some circumstances */
2042 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
2043 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
2044 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
2045 /* HEIC blocks delivery to the hypervisor */
2046 if ((async_deliver
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
2047 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
2048 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
2049 return PPC_INTERRUPT_EXT
;
2052 if (FIELD_EX64(env
->msr
, MSR
, CE
)) {
2053 /* External critical interrupt */
2054 if (env
->pending_interrupts
& PPC_INTERRUPT_CEXT
) {
2055 return PPC_INTERRUPT_CEXT
;
2058 if (async_deliver
!= 0) {
2059 /* Watchdog timer on embedded PowerPC */
2060 if (env
->pending_interrupts
& PPC_INTERRUPT_WDT
) {
2061 return PPC_INTERRUPT_WDT
;
2063 if (env
->pending_interrupts
& PPC_INTERRUPT_CDOORBELL
) {
2064 return PPC_INTERRUPT_CDOORBELL
;
2066 /* Fixed interval timer on embedded PowerPC */
2067 if (env
->pending_interrupts
& PPC_INTERRUPT_FIT
) {
2068 return PPC_INTERRUPT_FIT
;
2070 /* Programmable interval timer on embedded PowerPC */
2071 if (env
->pending_interrupts
& PPC_INTERRUPT_PIT
) {
2072 return PPC_INTERRUPT_PIT
;
2074 /* Decrementer exception */
2075 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
2076 return PPC_INTERRUPT_DECR
;
2078 if (env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) {
2079 return PPC_INTERRUPT_DOORBELL
;
2081 if (env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) {
2082 return PPC_INTERRUPT_HDOORBELL
;
2084 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
2085 return PPC_INTERRUPT_PERFM
;
2087 /* Thermal interrupt */
2088 if (env
->pending_interrupts
& PPC_INTERRUPT_THERM
) {
2089 return PPC_INTERRUPT_THERM
;
2092 if (env
->pending_interrupts
& PPC_INTERRUPT_EBB
) {
2094 * EBB exception must be taken in problem state and
2095 * with BESCR_GE set.
2097 if (FIELD_EX64(env
->msr
, MSR
, PR
) &&
2098 (env
->spr
[SPR_BESCR
] & BESCR_GE
)) {
2099 return PPC_INTERRUPT_EBB
;
2108 * Sets CPU_INTERRUPT_HARD if there is at least one unmasked interrupt to be
2109 * delivered and clears CPU_INTERRUPT_HARD otherwise.
2111 * This method is called by ppc_set_interrupt when an interrupt is raised or
2112 * lowered, and should also be called whenever an interrupt masking condition
2114 * - When relevant bits of MSR are altered, like EE, HV, PR, etc.;
2115 * - When relevant bits of LPCR are altered, like PECE, HDICE, HVICE, etc.;
2116 * - When PSSCR[EC] or env->resume_as_sreset are changed;
2117 * - When cs->halted is changed and the CPU has a different interrupt masking
2118 * logic in power-saving mode (e.g., POWER7/8/9/10);
2120 void ppc_maybe_interrupt(CPUPPCState
*env
)
2122 CPUState
*cs
= env_cpu(env
);
2125 if (ppc_next_unmasked_interrupt(env
)) {
2126 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
2128 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
2133 static void p7_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2135 PowerPCCPU
*cpu
= env_archcpu(env
);
2137 switch (interrupt
) {
2138 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2139 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2140 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2143 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2144 /* HDEC clears on delivery */
2145 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2146 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2149 case PPC_INTERRUPT_EXT
:
2150 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2151 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2153 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2157 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2158 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2160 case PPC_INTERRUPT_PERFM
:
2161 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2162 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2166 * This is a bug ! It means that has_work took us out of halt without
2167 * anything to deliver while in a PM state that requires getting
2170 * This means we will incorrectly execute past the power management
2171 * instruction instead of triggering a reset.
2173 * It generally means a discrepancy between the wakeup conditions in the
2174 * processor has_work implementation and the logic in this function.
2176 assert(!env
->resume_as_sreset
);
2179 cpu_abort(env_cpu(env
), "Invalid PowerPC interrupt %d. Aborting\n",
2184 static void p8_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2186 PowerPCCPU
*cpu
= env_archcpu(env
);
2188 switch (interrupt
) {
2189 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2190 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2191 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2194 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2195 /* HDEC clears on delivery */
2196 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2197 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2200 case PPC_INTERRUPT_EXT
:
2201 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2202 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2204 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2208 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2209 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2211 case PPC_INTERRUPT_DOORBELL
:
2212 env
->pending_interrupts
&= ~PPC_INTERRUPT_DOORBELL
;
2213 if (is_book3s_arch2x(env
)) {
2214 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR
);
2216 powerpc_excp(cpu
, POWERPC_EXCP_DOORI
);
2219 case PPC_INTERRUPT_HDOORBELL
:
2220 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDOORBELL
;
2221 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR_HV
);
2223 case PPC_INTERRUPT_PERFM
:
2224 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2225 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2227 case PPC_INTERRUPT_EBB
: /* EBB exception */
2228 env
->pending_interrupts
&= ~PPC_INTERRUPT_EBB
;
2229 if (env
->spr
[SPR_BESCR
] & BESCR_PMEO
) {
2230 powerpc_excp(cpu
, POWERPC_EXCP_PERFM_EBB
);
2231 } else if (env
->spr
[SPR_BESCR
] & BESCR_EEO
) {
2232 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL_EBB
);
2237 * This is a bug ! It means that has_work took us out of halt without
2238 * anything to deliver while in a PM state that requires getting
2241 * This means we will incorrectly execute past the power management
2242 * instruction instead of triggering a reset.
2244 * It generally means a discrepancy between the wakeup conditions in the
2245 * processor has_work implementation and the logic in this function.
2247 assert(!env
->resume_as_sreset
);
2250 cpu_abort(env_cpu(env
), "Invalid PowerPC interrupt %d. Aborting\n",
2255 static void p9_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2257 PowerPCCPU
*cpu
= env_archcpu(env
);
2258 CPUState
*cs
= env_cpu(env
);
2260 if (cs
->halted
&& !(env
->spr
[SPR_PSSCR
] & PSSCR_EC
) &&
2261 !FIELD_EX64(env
->msr
, MSR
, EE
)) {
2263 * A pending interrupt took us out of power-saving, but MSR[EE] says
2264 * that we should return to NIP+4 instead of delivering it.
2269 switch (interrupt
) {
2270 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2271 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2272 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2275 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2276 /* HDEC clears on delivery */
2277 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2278 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2280 case PPC_INTERRUPT_HVIRT
: /* Hypervisor virtualization interrupt */
2281 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2284 case PPC_INTERRUPT_EXT
:
2285 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2286 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2288 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2292 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2293 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2295 case PPC_INTERRUPT_DOORBELL
:
2296 env
->pending_interrupts
&= ~PPC_INTERRUPT_DOORBELL
;
2297 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR
);
2299 case PPC_INTERRUPT_HDOORBELL
:
2300 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDOORBELL
;
2301 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR_HV
);
2303 case PPC_INTERRUPT_PERFM
:
2304 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2305 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2307 case PPC_INTERRUPT_EBB
: /* EBB exception */
2308 env
->pending_interrupts
&= ~PPC_INTERRUPT_EBB
;
2309 if (env
->spr
[SPR_BESCR
] & BESCR_PMEO
) {
2310 powerpc_excp(cpu
, POWERPC_EXCP_PERFM_EBB
);
2311 } else if (env
->spr
[SPR_BESCR
] & BESCR_EEO
) {
2312 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL_EBB
);
2317 * This is a bug ! It means that has_work took us out of halt without
2318 * anything to deliver while in a PM state that requires getting
2321 * This means we will incorrectly execute past the power management
2322 * instruction instead of triggering a reset.
2324 * It generally means a discrepancy between the wakeup conditions in the
2325 * processor has_work implementation and the logic in this function.
2327 assert(!env
->resume_as_sreset
);
2330 cpu_abort(env_cpu(env
), "Invalid PowerPC interrupt %d. Aborting\n",
2334 #endif /* TARGET_PPC64 */
2336 static void ppc_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2339 switch (env
->excp_model
) {
2340 case POWERPC_EXCP_POWER7
:
2341 return p7_deliver_interrupt(env
, interrupt
);
2342 case POWERPC_EXCP_POWER8
:
2343 return p8_deliver_interrupt(env
, interrupt
);
2344 case POWERPC_EXCP_POWER9
:
2345 case POWERPC_EXCP_POWER10
:
2346 return p9_deliver_interrupt(env
, interrupt
);
2351 PowerPCCPU
*cpu
= env_archcpu(env
);
2353 switch (interrupt
) {
2354 case PPC_INTERRUPT_RESET
: /* External reset */
2355 env
->pending_interrupts
&= ~PPC_INTERRUPT_RESET
;
2356 powerpc_excp(cpu
, POWERPC_EXCP_RESET
);
2358 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2359 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2360 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2363 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2364 /* HDEC clears on delivery */
2365 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2366 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2368 case PPC_INTERRUPT_HVIRT
: /* Hypervisor virtualization interrupt */
2369 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2372 case PPC_INTERRUPT_EXT
:
2373 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2374 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2376 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2379 case PPC_INTERRUPT_CEXT
: /* External critical interrupt */
2380 powerpc_excp(cpu
, POWERPC_EXCP_CRITICAL
);
2383 case PPC_INTERRUPT_WDT
: /* Watchdog timer on embedded PowerPC */
2384 env
->pending_interrupts
&= ~PPC_INTERRUPT_WDT
;
2385 powerpc_excp(cpu
, POWERPC_EXCP_WDT
);
2387 case PPC_INTERRUPT_CDOORBELL
:
2388 env
->pending_interrupts
&= ~PPC_INTERRUPT_CDOORBELL
;
2389 powerpc_excp(cpu
, POWERPC_EXCP_DOORCI
);
2391 case PPC_INTERRUPT_FIT
: /* Fixed interval timer on embedded PowerPC */
2392 env
->pending_interrupts
&= ~PPC_INTERRUPT_FIT
;
2393 powerpc_excp(cpu
, POWERPC_EXCP_FIT
);
2395 case PPC_INTERRUPT_PIT
: /* Programmable interval timer on embedded ppc */
2396 env
->pending_interrupts
&= ~PPC_INTERRUPT_PIT
;
2397 powerpc_excp(cpu
, POWERPC_EXCP_PIT
);
2399 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2400 if (ppc_decr_clear_on_delivery(env
)) {
2401 env
->pending_interrupts
&= ~PPC_INTERRUPT_DECR
;
2403 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2405 case PPC_INTERRUPT_DOORBELL
:
2406 env
->pending_interrupts
&= ~PPC_INTERRUPT_DOORBELL
;
2407 if (is_book3s_arch2x(env
)) {
2408 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR
);
2410 powerpc_excp(cpu
, POWERPC_EXCP_DOORI
);
2413 case PPC_INTERRUPT_HDOORBELL
:
2414 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDOORBELL
;
2415 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR_HV
);
2417 case PPC_INTERRUPT_PERFM
:
2418 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2419 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2421 case PPC_INTERRUPT_THERM
: /* Thermal interrupt */
2422 env
->pending_interrupts
&= ~PPC_INTERRUPT_THERM
;
2423 powerpc_excp(cpu
, POWERPC_EXCP_THERM
);
2425 case PPC_INTERRUPT_EBB
: /* EBB exception */
2426 env
->pending_interrupts
&= ~PPC_INTERRUPT_EBB
;
2427 if (env
->spr
[SPR_BESCR
] & BESCR_PMEO
) {
2428 powerpc_excp(cpu
, POWERPC_EXCP_PERFM_EBB
);
2429 } else if (env
->spr
[SPR_BESCR
] & BESCR_EEO
) {
2430 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL_EBB
);
2435 * This is a bug ! It means that has_work took us out of halt without
2436 * anything to deliver while in a PM state that requires getting
2439 * This means we will incorrectly execute past the power management
2440 * instruction instead of triggering a reset.
2442 * It generally means a discrepancy between the wakeup conditions in the
2443 * processor has_work implementation and the logic in this function.
2445 assert(!env
->resume_as_sreset
);
2448 cpu_abort(env_cpu(env
), "Invalid PowerPC interrupt %d. Aborting\n",
2453 void ppc_cpu_do_system_reset(CPUState
*cs
)
2455 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2457 powerpc_excp(cpu
, POWERPC_EXCP_RESET
);
2460 void ppc_cpu_do_fwnmi_machine_check(CPUState
*cs
, target_ulong vector
)
2462 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2463 CPUPPCState
*env
= &cpu
->env
;
2464 target_ulong msr
= 0;
2467 * Set MSR and NIP for the handler, SRR0/1, DAR and DSISR have already
2470 msr
= (1ULL << MSR_ME
);
2471 msr
|= env
->msr
& (1ULL << MSR_SF
);
2472 if (ppc_interrupts_little_endian(cpu
, false)) {
2473 msr
|= (1ULL << MSR_LE
);
2476 /* Anything for nested required here? MSR[HV] bit? */
2478 powerpc_set_excp_state(cpu
, vector
, msr
);
2481 bool ppc_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
2483 CPUPPCState
*env
= cpu_env(cs
);
2486 if ((interrupt_request
& CPU_INTERRUPT_HARD
) == 0) {
2490 interrupt
= ppc_next_unmasked_interrupt(env
);
2491 if (interrupt
== 0) {
2495 ppc_deliver_interrupt(env
, interrupt
);
2496 if (env
->pending_interrupts
== 0) {
2497 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
2502 #endif /* !CONFIG_USER_ONLY */
2504 /*****************************************************************************/
2505 /* Exceptions processing helpers */
2507 void raise_exception_err_ra(CPUPPCState
*env
, uint32_t exception
,
2508 uint32_t error_code
, uintptr_t raddr
)
2510 CPUState
*cs
= env_cpu(env
);
2512 cs
->exception_index
= exception
;
2513 env
->error_code
= error_code
;
2514 cpu_loop_exit_restore(cs
, raddr
);
2517 void raise_exception_err(CPUPPCState
*env
, uint32_t exception
,
2518 uint32_t error_code
)
2520 raise_exception_err_ra(env
, exception
, error_code
, 0);
2523 void raise_exception(CPUPPCState
*env
, uint32_t exception
)
2525 raise_exception_err_ra(env
, exception
, 0, 0);
2528 void raise_exception_ra(CPUPPCState
*env
, uint32_t exception
,
2531 raise_exception_err_ra(env
, exception
, 0, raddr
);
2535 void helper_raise_exception_err(CPUPPCState
*env
, uint32_t exception
,
2536 uint32_t error_code
)
2538 raise_exception_err_ra(env
, exception
, error_code
, 0);
2541 void helper_raise_exception(CPUPPCState
*env
, uint32_t exception
)
2543 raise_exception_err_ra(env
, exception
, 0, 0);
2546 #ifndef CONFIG_USER_ONLY
2547 void helper_store_msr(CPUPPCState
*env
, target_ulong val
)
2549 uint32_t excp
= hreg_store_msr(env
, val
, 0);
2552 cpu_interrupt_exittb(env_cpu(env
));
2553 raise_exception(env
, excp
);
2557 void helper_ppc_maybe_interrupt(CPUPPCState
*env
)
2559 ppc_maybe_interrupt(env
);
2563 void helper_scv(CPUPPCState
*env
, uint32_t lev
)
2565 if (env
->spr
[SPR_FSCR
] & (1ull << FSCR_SCV
)) {
2566 raise_exception_err(env
, POWERPC_EXCP_SYSCALL_VECTORED
, lev
);
2568 raise_exception_err(env
, POWERPC_EXCP_FU
, FSCR_IC_SCV
);
2572 void helper_pminsn(CPUPPCState
*env
, uint32_t insn
)
2574 CPUState
*cs
= env_cpu(env
);
2578 /* Condition for waking up at 0x100 */
2579 env
->resume_as_sreset
= (insn
!= PPC_PM_STOP
) ||
2580 (env
->spr
[SPR_PSSCR
] & PSSCR_EC
);
2582 /* HDECR is not to wake from PM state, it may have already fired */
2583 if (env
->resume_as_sreset
) {
2584 PowerPCCPU
*cpu
= env_archcpu(env
);
2585 ppc_set_irq(cpu
, PPC_INTERRUPT_HDECR
, 0);
2588 ppc_maybe_interrupt(env
);
2590 #endif /* TARGET_PPC64 */
2592 static void do_rfi(CPUPPCState
*env
, target_ulong nip
, target_ulong msr
)
2594 /* MSR:POW cannot be set by any form of rfi */
2595 msr
&= ~(1ULL << MSR_POW
);
2597 /* MSR:TGPR cannot be set by any form of rfi */
2598 if (env
->flags
& POWERPC_FLAG_TGPR
)
2599 msr
&= ~(1ULL << MSR_TGPR
);
2602 /* Switching to 32-bit ? Crop the nip */
2603 if (!msr_is_64bit(env
, msr
)) {
2604 nip
= (uint32_t)nip
;
2607 nip
= (uint32_t)nip
;
2609 /* XXX: beware: this is false if VLE is supported */
2610 env
->nip
= nip
& ~((target_ulong
)0x00000003);
2611 hreg_store_msr(env
, msr
, 1);
2612 trace_ppc_excp_rfi(env
->nip
, env
->msr
);
2614 * No need to raise an exception here, as rfi is always the last
2617 cpu_interrupt_exittb(env_cpu(env
));
2618 /* Reset the reservation */
2619 env
->reserve_addr
= -1;
2621 /* Context synchronizing: check if TCG TLB needs flush */
2622 check_tlb_flush(env
, false);
2625 void helper_rfi(CPUPPCState
*env
)
2627 do_rfi(env
, env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
] & 0xfffffffful
);
2631 void helper_rfid(CPUPPCState
*env
)
2634 * The architecture defines a number of rules for which bits can
2635 * change but in practice, we handle this in hreg_store_msr()
2636 * which will be called by do_rfi(), so there is no need to filter
2639 do_rfi(env
, env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
]);
2642 void helper_rfscv(CPUPPCState
*env
)
2644 do_rfi(env
, env
->lr
, env
->ctr
);
2647 void helper_hrfid(CPUPPCState
*env
)
2649 do_rfi(env
, env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
2652 void helper_rfebb(CPUPPCState
*env
, target_ulong s
)
2654 target_ulong msr
= env
->msr
;
2657 * Handling of BESCR bits 32:33 according to PowerISA v3.1:
2659 * "If BESCR 32:33 != 0b00 the instruction is treated as if
2660 * the instruction form were invalid."
2662 if (env
->spr
[SPR_BESCR
] & BESCR_INVALID
) {
2663 raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
2664 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
2667 env
->nip
= env
->spr
[SPR_EBBRR
];
2669 /* Switching to 32-bit ? Crop the nip */
2670 if (!msr_is_64bit(env
, msr
)) {
2671 env
->nip
= (uint32_t)env
->spr
[SPR_EBBRR
];
2675 env
->spr
[SPR_BESCR
] |= BESCR_GE
;
2677 env
->spr
[SPR_BESCR
] &= ~BESCR_GE
;
2682 * Triggers or queues an 'ebb_excp' EBB exception. All checks
2683 * but FSCR, HFSCR and msr_pr must be done beforehand.
2685 * PowerISA v3.1 isn't clear about whether an EBB should be
2686 * postponed or cancelled if the EBB facility is unavailable.
2687 * Our assumption here is that the EBB is cancelled if both
2688 * FSCR and HFSCR EBB facilities aren't available.
2690 static void do_ebb(CPUPPCState
*env
, int ebb_excp
)
2692 PowerPCCPU
*cpu
= env_archcpu(env
);
2695 * FSCR_EBB and FSCR_IC_EBB are the same bits used with
2698 helper_fscr_facility_check(env
, FSCR_EBB
, 0, FSCR_IC_EBB
);
2699 helper_hfscr_facility_check(env
, FSCR_EBB
, "EBB", FSCR_IC_EBB
);
2701 if (ebb_excp
== POWERPC_EXCP_PERFM_EBB
) {
2702 env
->spr
[SPR_BESCR
] |= BESCR_PMEO
;
2703 } else if (ebb_excp
== POWERPC_EXCP_EXTERNAL_EBB
) {
2704 env
->spr
[SPR_BESCR
] |= BESCR_EEO
;
2707 if (FIELD_EX64(env
->msr
, MSR
, PR
)) {
2708 powerpc_excp(cpu
, ebb_excp
);
2710 ppc_set_irq(cpu
, PPC_INTERRUPT_EBB
, 1);
2714 void raise_ebb_perfm_exception(CPUPPCState
*env
)
2716 bool perfm_ebb_enabled
= env
->spr
[SPR_POWER_MMCR0
] & MMCR0_EBE
&&
2717 env
->spr
[SPR_BESCR
] & BESCR_PME
&&
2718 env
->spr
[SPR_BESCR
] & BESCR_GE
;
2720 if (!perfm_ebb_enabled
) {
2724 do_ebb(env
, POWERPC_EXCP_PERFM_EBB
);
2726 #endif /* TARGET_PPC64 */
2728 /*****************************************************************************/
2729 /* Embedded PowerPC specific helpers */
2730 void helper_40x_rfci(CPUPPCState
*env
)
2732 do_rfi(env
, env
->spr
[SPR_40x_SRR2
], env
->spr
[SPR_40x_SRR3
]);
2735 void helper_rfci(CPUPPCState
*env
)
2737 do_rfi(env
, env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
]);
2740 void helper_rfdi(CPUPPCState
*env
)
2742 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
2743 do_rfi(env
, env
->spr
[SPR_BOOKE_DSRR0
], env
->spr
[SPR_BOOKE_DSRR1
]);
2746 void helper_rfmci(CPUPPCState
*env
)
2748 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
2749 do_rfi(env
, env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
2751 #endif /* !CONFIG_USER_ONLY */
2753 void helper_tw(CPUPPCState
*env
, target_ulong arg1
, target_ulong arg2
,
2756 if (!likely(!(((int32_t)arg1
< (int32_t)arg2
&& (flags
& 0x10)) ||
2757 ((int32_t)arg1
> (int32_t)arg2
&& (flags
& 0x08)) ||
2758 ((int32_t)arg1
== (int32_t)arg2
&& (flags
& 0x04)) ||
2759 ((uint32_t)arg1
< (uint32_t)arg2
&& (flags
& 0x02)) ||
2760 ((uint32_t)arg1
> (uint32_t)arg2
&& (flags
& 0x01))))) {
2761 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
2762 POWERPC_EXCP_TRAP
, GETPC());
2767 void helper_td(CPUPPCState
*env
, target_ulong arg1
, target_ulong arg2
,
2770 if (!likely(!(((int64_t)arg1
< (int64_t)arg2
&& (flags
& 0x10)) ||
2771 ((int64_t)arg1
> (int64_t)arg2
&& (flags
& 0x08)) ||
2772 ((int64_t)arg1
== (int64_t)arg2
&& (flags
& 0x04)) ||
2773 ((uint64_t)arg1
< (uint64_t)arg2
&& (flags
& 0x02)) ||
2774 ((uint64_t)arg1
> (uint64_t)arg2
&& (flags
& 0x01))))) {
2775 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
2776 POWERPC_EXCP_TRAP
, GETPC());
2779 #endif /* TARGET_PPC64 */
2781 static uint32_t helper_SIMON_LIKE_32_64(uint32_t x
, uint64_t key
, uint32_t lane
)
2783 const uint16_t c
= 0xfffc;
2784 const uint64_t z0
= 0xfa2561cdf44ac398ULL
;
2785 uint16_t z
= 0, temp
;
2786 uint16_t k
[32], eff_k
[32], xleft
[33], xright
[33], fxleft
[32];
2788 for (int i
= 3; i
>= 0; i
--) {
2789 k
[i
] = key
& 0xffff;
2792 xleft
[0] = x
& 0xffff;
2793 xright
[0] = (x
>> 16) & 0xffff;
2795 for (int i
= 0; i
< 28; i
++) {
2796 z
= (z0
>> (63 - i
)) & 1;
2797 temp
= ror16(k
[i
+ 3], 3) ^ k
[i
+ 1];
2798 k
[i
+ 4] = c
^ z
^ k
[i
] ^ temp
^ ror16(temp
, 1);
2801 for (int i
= 0; i
< 8; i
++) {
2802 eff_k
[4 * i
+ 0] = k
[4 * i
+ ((0 + lane
) % 4)];
2803 eff_k
[4 * i
+ 1] = k
[4 * i
+ ((1 + lane
) % 4)];
2804 eff_k
[4 * i
+ 2] = k
[4 * i
+ ((2 + lane
) % 4)];
2805 eff_k
[4 * i
+ 3] = k
[4 * i
+ ((3 + lane
) % 4)];
2808 for (int i
= 0; i
< 32; i
++) {
2809 fxleft
[i
] = (rol16(xleft
[i
], 1) &
2810 rol16(xleft
[i
], 8)) ^ rol16(xleft
[i
], 2);
2811 xleft
[i
+ 1] = xright
[i
] ^ fxleft
[i
] ^ eff_k
[i
];
2812 xright
[i
+ 1] = xleft
[i
];
2815 return (((uint32_t)xright
[32]) << 16) | xleft
[32];
2818 static uint64_t hash_digest(uint64_t ra
, uint64_t rb
, uint64_t key
)
2820 uint64_t stage0_h
= 0ULL, stage0_l
= 0ULL;
2821 uint64_t stage1_h
, stage1_l
;
2823 for (int i
= 0; i
< 4; i
++) {
2824 stage0_h
|= ror64(rb
& 0xff, 8 * (2 * i
+ 1));
2825 stage0_h
|= ((ra
>> 32) & 0xff) << (8 * 2 * i
);
2826 stage0_l
|= ror64((rb
>> 32) & 0xff, 8 * (2 * i
+ 1));
2827 stage0_l
|= (ra
& 0xff) << (8 * 2 * i
);
2832 stage1_h
= (uint64_t)helper_SIMON_LIKE_32_64(stage0_h
>> 32, key
, 0) << 32;
2833 stage1_h
|= helper_SIMON_LIKE_32_64(stage0_h
, key
, 1);
2834 stage1_l
= (uint64_t)helper_SIMON_LIKE_32_64(stage0_l
>> 32, key
, 2) << 32;
2835 stage1_l
|= helper_SIMON_LIKE_32_64(stage0_l
, key
, 3);
2837 return stage1_h
^ stage1_l
;
2840 static void do_hash(CPUPPCState
*env
, target_ulong ea
, target_ulong ra
,
2841 target_ulong rb
, uint64_t key
, bool store
)
2843 uint64_t calculated_hash
= hash_digest(ra
, rb
, key
), loaded_hash
;
2846 cpu_stq_data_ra(env
, ea
, calculated_hash
, GETPC());
2848 loaded_hash
= cpu_ldq_data_ra(env
, ea
, GETPC());
2849 if (loaded_hash
!= calculated_hash
) {
2850 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
2851 POWERPC_EXCP_TRAP
, GETPC());
2856 #include "qemu/guest-random.h"
2859 #define HELPER_HASH(op, key, store, dexcr_aspect) \
2860 void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
2863 if (env->msr & R_MSR_PR_MASK) { \
2864 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \
2865 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
2867 } else if (!(env->msr & R_MSR_HV_MASK)) { \
2868 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \
2869 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
2871 } else if (!(env->msr & R_MSR_S_MASK)) { \
2872 if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \
2876 do_hash(env, ea, ra, rb, key, store); \
2879 #define HELPER_HASH(op, key, store, dexcr_aspect) \
2880 void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
2883 do_hash(env, ea, ra, rb, key, store); \
2885 #endif /* TARGET_PPC64 */
2887 HELPER_HASH(HASHST
, env
->spr
[SPR_HASHKEYR
], true, NPHIE
)
2888 HELPER_HASH(HASHCHK
, env
->spr
[SPR_HASHKEYR
], false, NPHIE
)
2889 HELPER_HASH(HASHSTP
, env
->spr
[SPR_HASHPKEYR
], true, PHIE
)
2890 HELPER_HASH(HASHCHKP
, env
->spr
[SPR_HASHPKEYR
], false, PHIE
)
2892 #ifndef CONFIG_USER_ONLY
2893 /* Embedded.Processor Control */
2894 static int dbell2irq(target_ulong rb
)
2896 int msg
= rb
& DBELL_TYPE_MASK
;
2900 case DBELL_TYPE_DBELL
:
2901 irq
= PPC_INTERRUPT_DOORBELL
;
2903 case DBELL_TYPE_DBELL_CRIT
:
2904 irq
= PPC_INTERRUPT_CDOORBELL
;
2906 case DBELL_TYPE_G_DBELL
:
2907 case DBELL_TYPE_G_DBELL_CRIT
:
2908 case DBELL_TYPE_G_DBELL_MC
:
2917 void helper_msgclr(CPUPPCState
*env
, target_ulong rb
)
2919 int irq
= dbell2irq(rb
);
2925 ppc_set_irq(env_archcpu(env
), irq
, 0);
2928 void helper_msgsnd(target_ulong rb
)
2930 int irq
= dbell2irq(rb
);
2931 int pir
= rb
& DBELL_PIRTAG_MASK
;
2940 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2941 CPUPPCState
*cenv
= &cpu
->env
;
2943 if ((rb
& DBELL_BRDCAST
) || (cenv
->spr
[SPR_BOOKE_PIR
] == pir
)) {
2944 ppc_set_irq(cpu
, irq
, 1);
2950 /* Server Processor Control */
2952 static bool dbell_type_server(target_ulong rb
)
2955 * A Directed Hypervisor Doorbell message is sent only if the
2956 * message type is 5. All other types are reserved and the
2957 * instruction is a no-op
2959 return (rb
& DBELL_TYPE_MASK
) == DBELL_TYPE_DBELL_SERVER
;
2962 void helper_book3s_msgclr(CPUPPCState
*env
, target_ulong rb
)
2964 if (!dbell_type_server(rb
)) {
2968 ppc_set_irq(env_archcpu(env
), PPC_INTERRUPT_HDOORBELL
, 0);
2971 static void book3s_msgsnd_common(int pir
, int irq
)
2977 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2978 CPUPPCState
*cenv
= &cpu
->env
;
2980 /* TODO: broadcast message to all threads of the same processor */
2981 if (cenv
->spr_cb
[SPR_PIR
].default_value
== pir
) {
2982 ppc_set_irq(cpu
, irq
, 1);
2988 void helper_book3s_msgsnd(target_ulong rb
)
2990 int pir
= rb
& DBELL_PROCIDTAG_MASK
;
2992 if (!dbell_type_server(rb
)) {
2996 book3s_msgsnd_common(pir
, PPC_INTERRUPT_HDOORBELL
);
3000 void helper_book3s_msgclrp(CPUPPCState
*env
, target_ulong rb
)
3002 helper_hfscr_facility_check(env
, HFSCR_MSGP
, "msgclrp", HFSCR_IC_MSGP
);
3004 if (!dbell_type_server(rb
)) {
3008 ppc_set_irq(env_archcpu(env
), PPC_INTERRUPT_DOORBELL
, 0);
3012 * sends a message to another thread on the same
3013 * multi-threaded processor
3015 void helper_book3s_msgsndp(CPUPPCState
*env
, target_ulong rb
)
3017 CPUState
*cs
= env_cpu(env
);
3018 PowerPCCPU
*cpu
= env_archcpu(env
);
3020 uint32_t nr_threads
= cs
->nr_threads
;
3021 int ttir
= rb
& PPC_BITMASK(57, 63);
3023 helper_hfscr_facility_check(env
, HFSCR_MSGP
, "msgsndp", HFSCR_IC_MSGP
);
3025 if (!(env
->flags
& POWERPC_FLAG_SMT_1LPAR
)) {
3026 nr_threads
= 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/
3029 if (!dbell_type_server(rb
) || ttir
>= nr_threads
) {
3033 if (nr_threads
== 1) {
3034 ppc_set_irq(cpu
, PPC_INTERRUPT_DOORBELL
, 1);
3038 /* Does iothread need to be locked for walking CPU list? */
3040 THREAD_SIBLING_FOREACH(cs
, ccs
) {
3041 PowerPCCPU
*ccpu
= POWERPC_CPU(ccs
);
3042 uint32_t thread_id
= ppc_cpu_tir(ccpu
);
3044 if (ttir
== thread_id
) {
3045 ppc_set_irq(ccpu
, PPC_INTERRUPT_DOORBELL
, 1);
3051 g_assert_not_reached();
3053 #endif /* TARGET_PPC64 */
3055 /* Single-step tracing */
3056 void helper_book3s_trace(CPUPPCState
*env
, target_ulong prev_ip
)
3058 uint32_t error_code
= 0;
3059 if (env
->insns_flags2
& PPC2_ISA207S
) {
3060 /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemented. */
3061 env
->spr
[SPR_POWER_SIAR
] = prev_ip
;
3062 error_code
= PPC_BIT(33);
3064 raise_exception_err(env
, POWERPC_EXCP_TRACE
, error_code
);
3067 void ppc_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
3068 MMUAccessType access_type
,
3069 int mmu_idx
, uintptr_t retaddr
)
3071 CPUPPCState
*env
= cpu_env(cs
);
3074 /* Restore state and reload the insn we executed, for filling in DSISR. */
3075 cpu_restore_state(cs
, retaddr
);
3076 insn
= ppc_ldl_code(env
, env
->nip
);
3078 switch (env
->mmu_model
) {
3079 case POWERPC_MMU_SOFT_4xx
:
3080 env
->spr
[SPR_40x_DEAR
] = vaddr
;
3082 case POWERPC_MMU_BOOKE
:
3083 case POWERPC_MMU_BOOKE206
:
3084 env
->spr
[SPR_BOOKE_DEAR
] = vaddr
;
3087 env
->spr
[SPR_DAR
] = vaddr
;
3091 cs
->exception_index
= POWERPC_EXCP_ALIGN
;
3092 env
->error_code
= insn
& 0x03FF0000;
3096 void ppc_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
3097 vaddr vaddr
, unsigned size
,
3098 MMUAccessType access_type
,
3099 int mmu_idx
, MemTxAttrs attrs
,
3100 MemTxResult response
, uintptr_t retaddr
)
3102 CPUPPCState
*env
= cpu_env(cs
);
3104 switch (env
->excp_model
) {
3105 #if defined(TARGET_PPC64)
3106 case POWERPC_EXCP_POWER8
:
3107 case POWERPC_EXCP_POWER9
:
3108 case POWERPC_EXCP_POWER10
:
3110 * Machine check codes can be found in processor User Manual or
3111 * Linux or skiboot source.
3113 if (access_type
== MMU_DATA_LOAD
) {
3114 env
->spr
[SPR_DAR
] = vaddr
;
3115 env
->spr
[SPR_DSISR
] = PPC_BIT(57);
3116 env
->error_code
= PPC_BIT(42);
3118 } else if (access_type
== MMU_DATA_STORE
) {
3120 * MCE for stores in POWER is asynchronous so hardware does
3121 * not set DAR, but QEMU can do better.
3123 env
->spr
[SPR_DAR
] = vaddr
;
3124 env
->error_code
= PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45);
3125 env
->error_code
|= PPC_BIT(42);
3127 } else { /* Fetch */
3129 * is_prefix_insn_excp() tests !PPC_BIT(42) to avoid fetching
3130 * the instruction, so that must always be clear for fetches.
3132 env
->error_code
= PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45);
3138 * TODO: Check behaviour for other CPUs, for now do nothing.
3139 * Could add a basic MCE even if real hardware ignores.
3144 cs
->exception_index
= POWERPC_EXCP_MCHECK
;
3145 cpu_loop_exit_restore(cs
, retaddr
);
3148 void ppc_cpu_debug_excp_handler(CPUState
*cs
)
3150 #if defined(TARGET_PPC64)
3151 CPUPPCState
*env
= cpu_env(cs
);
3153 if (env
->insns_flags2
& PPC2_ISA207S
) {
3154 if (cs
->watchpoint_hit
) {
3155 if (cs
->watchpoint_hit
->flags
& BP_CPU
) {
3156 env
->spr
[SPR_DAR
] = cs
->watchpoint_hit
->hitaddr
;
3157 env
->spr
[SPR_DSISR
] = PPC_BIT(41);
3158 cs
->watchpoint_hit
= NULL
;
3159 raise_exception(env
, POWERPC_EXCP_DSI
);
3161 cs
->watchpoint_hit
= NULL
;
3162 } else if (cpu_breakpoint_test(cs
, env
->nip
, BP_CPU
)) {
3163 raise_exception_err(env
, POWERPC_EXCP_TRACE
,
3164 PPC_BIT(33) | PPC_BIT(43));
3170 bool ppc_cpu_debug_check_breakpoint(CPUState
*cs
)
3172 #if defined(TARGET_PPC64)
3173 CPUPPCState
*env
= cpu_env(cs
);
3175 if (env
->insns_flags2
& PPC2_ISA207S
) {
3178 priv
= env
->spr
[SPR_CIABR
] & PPC_BITMASK(62, 63);
3180 case 0x1: /* problem */
3181 return env
->msr
& ((target_ulong
)1 << MSR_PR
);
3182 case 0x2: /* supervisor */
3183 return (!(env
->msr
& ((target_ulong
)1 << MSR_PR
)) &&
3184 !(env
->msr
& ((target_ulong
)1 << MSR_HV
)));
3185 case 0x3: /* hypervisor */
3186 return (!(env
->msr
& ((target_ulong
)1 << MSR_PR
)) &&
3187 (env
->msr
& ((target_ulong
)1 << MSR_HV
)));
3189 g_assert_not_reached();
3197 bool ppc_cpu_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
3199 #if defined(TARGET_PPC64)
3200 CPUPPCState
*env
= cpu_env(cs
);
3202 if (env
->insns_flags2
& PPC2_ISA207S
) {
3203 if (wp
== env
->dawr0_watchpoint
) {
3204 uint32_t dawrx
= env
->spr
[SPR_DAWRX0
];
3205 bool wt
= extract32(dawrx
, PPC_BIT_NR(59), 1);
3206 bool wti
= extract32(dawrx
, PPC_BIT_NR(60), 1);
3207 bool hv
= extract32(dawrx
, PPC_BIT_NR(61), 1);
3208 bool sv
= extract32(dawrx
, PPC_BIT_NR(62), 1);
3209 bool pr
= extract32(dawrx
, PPC_BIT_NR(62), 1);
3211 if ((env
->msr
& ((target_ulong
)1 << MSR_PR
)) && !pr
) {
3213 } else if ((env
->msr
& ((target_ulong
)1 << MSR_HV
)) && !hv
) {
3220 if (env
->msr
& ((target_ulong
)1 << MSR_DR
)) {
3239 #endif /* !CONFIG_USER_ONLY */
3240 #endif /* CONFIG_TCG */