2 * PowerPC floating point and SPE emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
24 #include "fpu/softfloat.h"
26 static inline float128
float128_snan_to_qnan(float128 x
)
30 r
.high
= x
.high
| 0x0000800000000000;
35 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37 #define float16_snan_to_qnan(x) ((x) | 0x0200)
39 static inline bool fp_exceptions_enabled(CPUPPCState
*env
)
41 #ifdef CONFIG_USER_ONLY
44 return (env
->msr
& ((1U << MSR_FE0
) | (1U << MSR_FE1
))) != 0;
48 /*****************************************************************************/
49 /* Floating point operations helpers */
52 * This is the non-arithmatic conversion that happens e.g. on loads.
53 * In the Power ISA pseudocode, this is called DOUBLE.
55 uint64_t helper_todouble(uint32_t arg
)
57 uint32_t abs_arg
= arg
& 0x7fffffff;
60 if (likely(abs_arg
>= 0x00800000)) {
61 /* Normalized operand, or Inf, or NaN. */
62 ret
= (uint64_t)extract32(arg
, 30, 2) << 62;
63 ret
|= ((extract32(arg
, 30, 1) ^ 1) * (uint64_t)7) << 59;
64 ret
|= (uint64_t)extract32(arg
, 0, 30) << 29;
66 /* Zero or Denormalized operand. */
67 ret
= (uint64_t)extract32(arg
, 31, 1) << 63;
68 if (unlikely(abs_arg
!= 0)) {
69 /* Denormalized operand. */
70 int shift
= clz32(abs_arg
) - 9;
71 int exp
= -126 - shift
+ 1023;
72 ret
|= (uint64_t)exp
<< 52;
73 ret
|= abs_arg
<< (shift
+ 29);
80 * This is the non-arithmatic conversion that happens e.g. on stores.
81 * In the Power ISA pseudocode, this is called SINGLE.
83 uint32_t helper_tosingle(uint64_t arg
)
85 int exp
= extract64(arg
, 52, 11);
88 if (likely(exp
> 896)) {
89 /* No denormalization required (includes Inf, NaN). */
90 ret
= extract64(arg
, 62, 2) << 30;
91 ret
|= extract64(arg
, 29, 30);
94 * Zero or Denormal result. If the exponent is in bounds for
95 * a single-precision denormal result, extract the proper
96 * bits. If the input is not zero, and the exponent is out of
97 * bounds, then the result is undefined; this underflows to
100 ret
= extract64(arg
, 63, 1) << 31;
101 if (unlikely(exp
>= 874)) {
102 /* Denormal result. */
103 ret
|= ((1ULL << 52) | extract64(arg
, 0, 52)) >> (896 + 30 - exp
);
109 static inline int ppc_float32_get_unbiased_exp(float32 f
)
111 return ((f
>> 23) & 0xFF) - 127;
114 static inline int ppc_float64_get_unbiased_exp(float64 f
)
116 return ((f
>> 52) & 0x7FF) - 1023;
119 /* Classify a floating-point number. */
130 #define COMPUTE_CLASS(tp) \
131 static int tp##_classify(tp arg) \
133 int ret = tp##_is_neg(arg) * is_neg; \
134 if (unlikely(tp##_is_any_nan(arg))) { \
135 float_status dummy = { }; /* snan_bit_is_one = 0 */ \
136 ret |= (tp##_is_signaling_nan(arg, &dummy) \
137 ? is_snan : is_qnan); \
138 } else if (unlikely(tp##_is_infinity(arg))) { \
140 } else if (tp##_is_zero(arg)) { \
142 } else if (tp##_is_zero_or_denormal(arg)) { \
143 ret |= is_denormal; \
150 COMPUTE_CLASS(float16
)
151 COMPUTE_CLASS(float32
)
152 COMPUTE_CLASS(float64
)
153 COMPUTE_CLASS(float128
)
155 static void set_fprf_from_class(CPUPPCState
*env
, int class)
157 static const uint8_t fprf
[6][2] = {
158 { 0x04, 0x08 }, /* normalized */
159 { 0x02, 0x12 }, /* zero */
160 { 0x14, 0x18 }, /* denormalized */
161 { 0x05, 0x09 }, /* infinity */
162 { 0x11, 0x11 }, /* qnan */
163 { 0x00, 0x00 }, /* snan -- flags are undefined */
165 bool isneg
= class & is_neg
;
167 env
->fpscr
&= ~(0x1F << FPSCR_FPRF
);
168 env
->fpscr
|= fprf
[ctz32(class)][isneg
] << FPSCR_FPRF
;
171 #define COMPUTE_FPRF(tp) \
172 void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
174 set_fprf_from_class(env, tp##_classify(arg)); \
177 COMPUTE_FPRF(float16
)
178 COMPUTE_FPRF(float32
)
179 COMPUTE_FPRF(float64
)
180 COMPUTE_FPRF(float128
)
182 /* Floating-point invalid operations exception */
183 static void finish_invalid_op_excp(CPUPPCState
*env
, int op
, uintptr_t retaddr
)
185 /* Update the floating-point invalid operation summary */
186 env
->fpscr
|= 1 << FPSCR_VX
;
187 /* Update the floating-point exception summary */
190 /* Update the floating-point enabled exception summary */
191 env
->fpscr
|= 1 << FPSCR_FEX
;
192 if (fp_exceptions_enabled(env
)) {
193 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
194 POWERPC_EXCP_FP
| op
, retaddr
);
199 static void finish_invalid_op_arith(CPUPPCState
*env
, int op
,
200 bool set_fpcc
, uintptr_t retaddr
)
202 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
205 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
206 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
209 finish_invalid_op_excp(env
, op
, retaddr
);
213 static void float_invalid_op_vxsnan(CPUPPCState
*env
, uintptr_t retaddr
)
215 env
->fpscr
|= 1 << FPSCR_VXSNAN
;
216 finish_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, retaddr
);
219 /* Magnitude subtraction of infinities */
220 static void float_invalid_op_vxisi(CPUPPCState
*env
, bool set_fpcc
,
223 env
->fpscr
|= 1 << FPSCR_VXISI
;
224 finish_invalid_op_arith(env
, POWERPC_EXCP_FP_VXISI
, set_fpcc
, retaddr
);
227 /* Division of infinity by infinity */
228 static void float_invalid_op_vxidi(CPUPPCState
*env
, bool set_fpcc
,
231 env
->fpscr
|= 1 << FPSCR_VXIDI
;
232 finish_invalid_op_arith(env
, POWERPC_EXCP_FP_VXIDI
, set_fpcc
, retaddr
);
235 /* Division of zero by zero */
236 static void float_invalid_op_vxzdz(CPUPPCState
*env
, bool set_fpcc
,
239 env
->fpscr
|= 1 << FPSCR_VXZDZ
;
240 finish_invalid_op_arith(env
, POWERPC_EXCP_FP_VXZDZ
, set_fpcc
, retaddr
);
243 /* Multiplication of zero by infinity */
244 static void float_invalid_op_vximz(CPUPPCState
*env
, bool set_fpcc
,
247 env
->fpscr
|= 1 << FPSCR_VXIMZ
;
248 finish_invalid_op_arith(env
, POWERPC_EXCP_FP_VXIMZ
, set_fpcc
, retaddr
);
251 /* Square root of a negative number */
252 static void float_invalid_op_vxsqrt(CPUPPCState
*env
, bool set_fpcc
,
255 env
->fpscr
|= 1 << FPSCR_VXSQRT
;
256 finish_invalid_op_arith(env
, POWERPC_EXCP_FP_VXSQRT
, set_fpcc
, retaddr
);
259 /* Ordered comparison of NaN */
260 static void float_invalid_op_vxvc(CPUPPCState
*env
, bool set_fpcc
,
263 env
->fpscr
|= 1 << FPSCR_VXVC
;
265 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
266 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
268 /* Update the floating-point invalid operation summary */
269 env
->fpscr
|= 1 << FPSCR_VX
;
270 /* Update the floating-point exception summary */
272 /* We must update the target FPR before raising the exception */
274 CPUState
*cs
= env_cpu(env
);
276 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
277 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_VXVC
;
278 /* Update the floating-point enabled exception summary */
279 env
->fpscr
|= 1 << FPSCR_FEX
;
280 /* Exception is differed */
284 /* Invalid conversion */
285 static void float_invalid_op_vxcvi(CPUPPCState
*env
, bool set_fpcc
,
288 env
->fpscr
|= 1 << FPSCR_VXCVI
;
289 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
292 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
293 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
296 finish_invalid_op_excp(env
, POWERPC_EXCP_FP_VXCVI
, retaddr
);
299 static inline void float_zero_divide_excp(CPUPPCState
*env
, uintptr_t raddr
)
301 env
->fpscr
|= 1 << FPSCR_ZX
;
302 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
303 /* Update the floating-point exception summary */
306 /* Update the floating-point enabled exception summary */
307 env
->fpscr
|= 1 << FPSCR_FEX
;
308 if (fp_exceptions_enabled(env
)) {
309 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
310 POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
,
316 static inline void float_overflow_excp(CPUPPCState
*env
)
318 CPUState
*cs
= env_cpu(env
);
320 env
->fpscr
|= 1 << FPSCR_OX
;
321 /* Update the floating-point exception summary */
324 /* XXX: should adjust the result */
325 /* Update the floating-point enabled exception summary */
326 env
->fpscr
|= 1 << FPSCR_FEX
;
327 /* We must update the target FPR before raising the exception */
328 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
329 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
331 env
->fpscr
|= 1 << FPSCR_XX
;
332 env
->fpscr
|= 1 << FPSCR_FI
;
336 static inline void float_underflow_excp(CPUPPCState
*env
)
338 CPUState
*cs
= env_cpu(env
);
340 env
->fpscr
|= 1 << FPSCR_UX
;
341 /* Update the floating-point exception summary */
344 /* XXX: should adjust the result */
345 /* Update the floating-point enabled exception summary */
346 env
->fpscr
|= 1 << FPSCR_FEX
;
347 /* We must update the target FPR before raising the exception */
348 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
349 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
353 static inline void float_inexact_excp(CPUPPCState
*env
)
355 CPUState
*cs
= env_cpu(env
);
357 env
->fpscr
|= 1 << FPSCR_FI
;
358 env
->fpscr
|= 1 << FPSCR_XX
;
359 /* Update the floating-point exception summary */
362 /* Update the floating-point enabled exception summary */
363 env
->fpscr
|= 1 << FPSCR_FEX
;
364 /* We must update the target FPR before raising the exception */
365 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
366 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
370 static inline void fpscr_set_rounding_mode(CPUPPCState
*env
)
374 /* Set rounding mode */
377 /* Best approximation (round to nearest) */
378 rnd_type
= float_round_nearest_even
;
381 /* Smaller magnitude (round toward zero) */
382 rnd_type
= float_round_to_zero
;
385 /* Round toward +infinite */
386 rnd_type
= float_round_up
;
390 /* Round toward -infinite */
391 rnd_type
= float_round_down
;
394 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
397 void helper_fpscr_clrbit(CPUPPCState
*env
, uint32_t bit
)
401 prev
= (env
->fpscr
>> bit
) & 1;
402 env
->fpscr
&= ~(1 << bit
);
407 fpscr_set_rounding_mode(env
);
419 /* Set VX bit to zero */
420 env
->fpscr
&= ~(1 << FPSCR_VX
);
433 /* Set the FEX bit */
434 env
->fpscr
&= ~(1 << FPSCR_FEX
);
443 void helper_fpscr_setbit(CPUPPCState
*env
, uint32_t bit
)
445 CPUState
*cs
= env_cpu(env
);
448 prev
= (env
->fpscr
>> bit
) & 1;
449 env
->fpscr
|= 1 << bit
;
491 env
->fpscr
|= 1 << FPSCR_VX
;
500 env
->error_code
= POWERPC_EXCP_FP
;
502 env
->error_code
|= POWERPC_EXCP_FP_VXSNAN
;
505 env
->error_code
|= POWERPC_EXCP_FP_VXISI
;
508 env
->error_code
|= POWERPC_EXCP_FP_VXIDI
;
511 env
->error_code
|= POWERPC_EXCP_FP_VXZDZ
;
514 env
->error_code
|= POWERPC_EXCP_FP_VXIMZ
;
517 env
->error_code
|= POWERPC_EXCP_FP_VXVC
;
520 env
->error_code
|= POWERPC_EXCP_FP_VXSOFT
;
523 env
->error_code
|= POWERPC_EXCP_FP_VXSQRT
;
526 env
->error_code
|= POWERPC_EXCP_FP_VXCVI
;
534 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
541 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
548 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
;
555 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
561 fpscr_set_rounding_mode(env
);
566 /* Update the floating-point enabled exception summary */
567 env
->fpscr
|= 1 << FPSCR_FEX
;
568 /* We have to update Rc1 before raising the exception */
569 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
575 void helper_store_fpscr(CPUPPCState
*env
, uint64_t arg
, uint32_t mask
)
577 CPUState
*cs
= env_cpu(env
);
578 target_ulong prev
, new;
582 new = (target_ulong
)arg
;
583 new &= ~0x60000000LL
;
584 new |= prev
& 0x60000000LL
;
585 for (i
= 0; i
< sizeof(target_ulong
) * 2; i
++) {
586 if (mask
& (1 << i
)) {
587 env
->fpscr
&= ~(0xFLL
<< (4 * i
));
588 env
->fpscr
|= new & (0xFLL
<< (4 * i
));
591 /* Update VX and FEX */
593 env
->fpscr
|= 1 << FPSCR_VX
;
595 env
->fpscr
&= ~(1 << FPSCR_VX
);
597 if ((fpscr_ex
& fpscr_eex
) != 0) {
598 env
->fpscr
|= 1 << FPSCR_FEX
;
599 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
600 /* XXX: we should compute it properly */
601 env
->error_code
= POWERPC_EXCP_FP
;
603 env
->fpscr
&= ~(1 << FPSCR_FEX
);
605 fpscr_set_rounding_mode(env
);
608 void store_fpscr(CPUPPCState
*env
, uint64_t arg
, uint32_t mask
)
610 helper_store_fpscr(env
, arg
, mask
);
613 static void do_float_check_status(CPUPPCState
*env
, uintptr_t raddr
)
615 CPUState
*cs
= env_cpu(env
);
616 int status
= get_float_exception_flags(&env
->fp_status
);
617 bool inexact_happened
= false;
619 if (status
& float_flag_overflow
) {
620 float_overflow_excp(env
);
621 } else if (status
& float_flag_underflow
) {
622 float_underflow_excp(env
);
623 } else if (status
& float_flag_inexact
) {
624 float_inexact_excp(env
);
625 inexact_happened
= true;
628 /* if the inexact flag was not set */
629 if (inexact_happened
== false) {
630 env
->fpscr
&= ~(1 << FPSCR_FI
); /* clear the FPSCR[FI] bit */
633 if (cs
->exception_index
== POWERPC_EXCP_PROGRAM
&&
634 (env
->error_code
& POWERPC_EXCP_FP
)) {
635 /* Differred floating-point exception after target FPR update */
636 if (fp_exceptions_enabled(env
)) {
637 raise_exception_err_ra(env
, cs
->exception_index
,
638 env
->error_code
, raddr
);
643 void helper_float_check_status(CPUPPCState
*env
)
645 do_float_check_status(env
, GETPC());
648 void helper_reset_fpstatus(CPUPPCState
*env
)
650 set_float_exception_flags(0, &env
->fp_status
);
653 static void float_invalid_op_addsub(CPUPPCState
*env
, bool set_fpcc
,
654 uintptr_t retaddr
, int classes
)
656 if ((classes
& ~is_neg
) == is_inf
) {
657 /* Magnitude subtraction of infinities */
658 float_invalid_op_vxisi(env
, set_fpcc
, retaddr
);
659 } else if (classes
& is_snan
) {
660 float_invalid_op_vxsnan(env
, retaddr
);
665 float64
helper_fadd(CPUPPCState
*env
, float64 arg1
, float64 arg2
)
667 float64 ret
= float64_add(arg1
, arg2
, &env
->fp_status
);
668 int status
= get_float_exception_flags(&env
->fp_status
);
670 if (unlikely(status
& float_flag_invalid
)) {
671 float_invalid_op_addsub(env
, 1, GETPC(),
672 float64_classify(arg1
) |
673 float64_classify(arg2
));
680 float64
helper_fsub(CPUPPCState
*env
, float64 arg1
, float64 arg2
)
682 float64 ret
= float64_sub(arg1
, arg2
, &env
->fp_status
);
683 int status
= get_float_exception_flags(&env
->fp_status
);
685 if (unlikely(status
& float_flag_invalid
)) {
686 float_invalid_op_addsub(env
, 1, GETPC(),
687 float64_classify(arg1
) |
688 float64_classify(arg2
));
694 static void float_invalid_op_mul(CPUPPCState
*env
, bool set_fprc
,
695 uintptr_t retaddr
, int classes
)
697 if ((classes
& (is_zero
| is_inf
)) == (is_zero
| is_inf
)) {
698 /* Multiplication of zero by infinity */
699 float_invalid_op_vximz(env
, set_fprc
, retaddr
);
700 } else if (classes
& is_snan
) {
701 float_invalid_op_vxsnan(env
, retaddr
);
706 float64
helper_fmul(CPUPPCState
*env
, float64 arg1
, float64 arg2
)
708 float64 ret
= float64_mul(arg1
, arg2
, &env
->fp_status
);
709 int status
= get_float_exception_flags(&env
->fp_status
);
711 if (unlikely(status
& float_flag_invalid
)) {
712 float_invalid_op_mul(env
, 1, GETPC(),
713 float64_classify(arg1
) |
714 float64_classify(arg2
));
720 static void float_invalid_op_div(CPUPPCState
*env
, bool set_fprc
,
721 uintptr_t retaddr
, int classes
)
724 if (classes
== is_inf
) {
725 /* Division of infinity by infinity */
726 float_invalid_op_vxidi(env
, set_fprc
, retaddr
);
727 } else if (classes
== is_zero
) {
728 /* Division of zero by zero */
729 float_invalid_op_vxzdz(env
, set_fprc
, retaddr
);
730 } else if (classes
& is_snan
) {
731 float_invalid_op_vxsnan(env
, retaddr
);
736 float64
helper_fdiv(CPUPPCState
*env
, float64 arg1
, float64 arg2
)
738 float64 ret
= float64_div(arg1
, arg2
, &env
->fp_status
);
739 int status
= get_float_exception_flags(&env
->fp_status
);
741 if (unlikely(status
)) {
742 if (status
& float_flag_invalid
) {
743 float_invalid_op_div(env
, 1, GETPC(),
744 float64_classify(arg1
) |
745 float64_classify(arg2
));
747 if (status
& float_flag_divbyzero
) {
748 float_zero_divide_excp(env
, GETPC());
755 static void float_invalid_cvt(CPUPPCState
*env
, bool set_fprc
,
756 uintptr_t retaddr
, int class1
)
758 float_invalid_op_vxcvi(env
, set_fprc
, retaddr
);
759 if (class1
& is_snan
) {
760 float_invalid_op_vxsnan(env
, retaddr
);
764 #define FPU_FCTI(op, cvt, nanval) \
765 uint64_t helper_##op(CPUPPCState *env, float64 arg) \
767 uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
768 int status = get_float_exception_flags(&env->fp_status); \
770 if (unlikely(status)) { \
771 if (status & float_flag_invalid) { \
772 float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
775 do_float_check_status(env, GETPC()); \
780 FPU_FCTI(fctiw
, int32
, 0x80000000U
)
781 FPU_FCTI(fctiwz
, int32_round_to_zero
, 0x80000000U
)
782 FPU_FCTI(fctiwu
, uint32
, 0x00000000U
)
783 FPU_FCTI(fctiwuz
, uint32_round_to_zero
, 0x00000000U
)
784 FPU_FCTI(fctid
, int64
, 0x8000000000000000ULL
)
785 FPU_FCTI(fctidz
, int64_round_to_zero
, 0x8000000000000000ULL
)
786 FPU_FCTI(fctidu
, uint64
, 0x0000000000000000ULL
)
787 FPU_FCTI(fctiduz
, uint64_round_to_zero
, 0x0000000000000000ULL
)
789 #define FPU_FCFI(op, cvtr, is_single) \
790 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
795 float32 tmp = cvtr(arg, &env->fp_status); \
796 farg.d = float32_to_float64(tmp, &env->fp_status); \
798 farg.d = cvtr(arg, &env->fp_status); \
800 do_float_check_status(env, GETPC()); \
804 FPU_FCFI(fcfid
, int64_to_float64
, 0)
805 FPU_FCFI(fcfids
, int64_to_float32
, 1)
806 FPU_FCFI(fcfidu
, uint64_to_float64
, 0)
807 FPU_FCFI(fcfidus
, uint64_to_float32
, 1)
809 static inline uint64_t do_fri(CPUPPCState
*env
, uint64_t arg
,
816 if (unlikely(float64_is_signaling_nan(farg
.d
, &env
->fp_status
))) {
818 float_invalid_op_vxsnan(env
, GETPC());
819 farg
.ll
= arg
| 0x0008000000000000ULL
;
821 int inexact
= get_float_exception_flags(&env
->fp_status
) &
823 set_float_rounding_mode(rounding_mode
, &env
->fp_status
);
824 farg
.ll
= float64_round_to_int(farg
.d
, &env
->fp_status
);
825 /* Restore rounding mode from FPSCR */
826 fpscr_set_rounding_mode(env
);
828 /* fri* does not set FPSCR[XX] */
830 env
->fp_status
.float_exception_flags
&= ~float_flag_inexact
;
833 do_float_check_status(env
, GETPC());
837 uint64_t helper_frin(CPUPPCState
*env
, uint64_t arg
)
839 return do_fri(env
, arg
, float_round_ties_away
);
842 uint64_t helper_friz(CPUPPCState
*env
, uint64_t arg
)
844 return do_fri(env
, arg
, float_round_to_zero
);
847 uint64_t helper_frip(CPUPPCState
*env
, uint64_t arg
)
849 return do_fri(env
, arg
, float_round_up
);
852 uint64_t helper_frim(CPUPPCState
*env
, uint64_t arg
)
854 return do_fri(env
, arg
, float_round_down
);
857 #define FPU_MADDSUB_UPDATE(NAME, TP) \
858 static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \
859 unsigned int madd_flags, uintptr_t retaddr) \
861 if (TP##_is_signaling_nan(arg1, &env->fp_status) || \
862 TP##_is_signaling_nan(arg2, &env->fp_status) || \
863 TP##_is_signaling_nan(arg3, &env->fp_status)) { \
864 /* sNaN operation */ \
865 float_invalid_op_vxsnan(env, retaddr); \
867 if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \
868 (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \
869 /* Multiplication of zero by infinity */ \
870 float_invalid_op_vximz(env, 1, retaddr); \
872 if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \
873 TP##_is_infinity(arg3)) { \
874 uint8_t aSign, bSign, cSign; \
876 aSign = TP##_is_neg(arg1); \
877 bSign = TP##_is_neg(arg2); \
878 cSign = TP##_is_neg(arg3); \
879 if (madd_flags & float_muladd_negate_c) { \
882 if (aSign ^ bSign ^ cSign) { \
883 float_invalid_op_vxisi(env, 1, retaddr); \
887 FPU_MADDSUB_UPDATE(float32_maddsub_update_excp
, float32
)
888 FPU_MADDSUB_UPDATE(float64_maddsub_update_excp
, float64
)
890 #define FPU_FMADD(op, madd_flags) \
891 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
892 uint64_t arg2, uint64_t arg3) \
895 float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \
897 flags = get_float_exception_flags(&env->fp_status); \
899 if (flags & float_flag_invalid) { \
900 float64_maddsub_update_excp(env, arg1, arg2, arg3, \
901 madd_flags, GETPC()); \
903 do_float_check_status(env, GETPC()); \
909 #define MSUB_FLGS float_muladd_negate_c
910 #define NMADD_FLGS float_muladd_negate_result
911 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
913 FPU_FMADD(fmadd
, MADD_FLGS
)
914 FPU_FMADD(fnmadd
, NMADD_FLGS
)
915 FPU_FMADD(fmsub
, MSUB_FLGS
)
916 FPU_FMADD(fnmsub
, NMSUB_FLGS
)
919 uint64_t helper_frsp(CPUPPCState
*env
, uint64_t arg
)
926 if (unlikely(float64_is_signaling_nan(farg
.d
, &env
->fp_status
))) {
927 float_invalid_op_vxsnan(env
, GETPC());
929 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
930 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
936 float64
helper_fsqrt(CPUPPCState
*env
, float64 arg
)
938 float64 ret
= float64_sqrt(arg
, &env
->fp_status
);
939 int status
= get_float_exception_flags(&env
->fp_status
);
941 if (unlikely(status
& float_flag_invalid
)) {
942 if (unlikely(float64_is_any_nan(arg
))) {
943 if (unlikely(float64_is_signaling_nan(arg
, &env
->fp_status
))) {
944 /* sNaN square root */
945 float_invalid_op_vxsnan(env
, GETPC());
948 /* Square root of a negative nonzero number */
949 float_invalid_op_vxsqrt(env
, 1, GETPC());
957 float64
helper_fre(CPUPPCState
*env
, float64 arg
)
959 /* "Estimate" the reciprocal with actual division. */
960 float64 ret
= float64_div(float64_one
, arg
, &env
->fp_status
);
961 int status
= get_float_exception_flags(&env
->fp_status
);
963 if (unlikely(status
)) {
964 if (status
& float_flag_invalid
) {
965 if (float64_is_signaling_nan(arg
, &env
->fp_status
)) {
966 /* sNaN reciprocal */
967 float_invalid_op_vxsnan(env
, GETPC());
970 if (status
& float_flag_divbyzero
) {
971 float_zero_divide_excp(env
, GETPC());
972 /* For FPSCR.ZE == 0, the result is 1/2. */
973 ret
= float64_set_sign(float64_half
, float64_is_neg(arg
));
981 uint64_t helper_fres(CPUPPCState
*env
, uint64_t arg
)
988 if (unlikely(float64_is_signaling_nan(farg
.d
, &env
->fp_status
))) {
989 /* sNaN reciprocal */
990 float_invalid_op_vxsnan(env
, GETPC());
992 farg
.d
= float64_div(float64_one
, farg
.d
, &env
->fp_status
);
993 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
994 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
999 /* frsqrte - frsqrte. */
1000 float64
helper_frsqrte(CPUPPCState
*env
, float64 arg
)
1002 /* "Estimate" the reciprocal with actual division. */
1003 float64 rets
= float64_sqrt(arg
, &env
->fp_status
);
1004 float64 retd
= float64_div(float64_one
, rets
, &env
->fp_status
);
1005 int status
= get_float_exception_flags(&env
->fp_status
);
1007 if (unlikely(status
)) {
1008 if (status
& float_flag_invalid
) {
1009 if (float64_is_signaling_nan(arg
, &env
->fp_status
)) {
1010 /* sNaN reciprocal */
1011 float_invalid_op_vxsnan(env
, GETPC());
1013 /* Square root of a negative nonzero number */
1014 float_invalid_op_vxsqrt(env
, 1, GETPC());
1017 if (status
& float_flag_divbyzero
) {
1018 /* Reciprocal of (square root of) zero. */
1019 float_zero_divide_excp(env
, GETPC());
1027 uint64_t helper_fsel(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
1034 if ((!float64_is_neg(farg1
.d
) || float64_is_zero(farg1
.d
)) &&
1035 !float64_is_any_nan(farg1
.d
)) {
1042 uint32_t helper_ftdiv(uint64_t fra
, uint64_t frb
)
1047 if (unlikely(float64_is_infinity(fra
) ||
1048 float64_is_infinity(frb
) ||
1049 float64_is_zero(frb
))) {
1053 int e_a
= ppc_float64_get_unbiased_exp(fra
);
1054 int e_b
= ppc_float64_get_unbiased_exp(frb
);
1056 if (unlikely(float64_is_any_nan(fra
) ||
1057 float64_is_any_nan(frb
))) {
1059 } else if ((e_b
<= -1022) || (e_b
>= 1021)) {
1061 } else if (!float64_is_zero(fra
) &&
1062 (((e_a
- e_b
) >= 1023) ||
1063 ((e_a
- e_b
) <= -1021) ||
1068 if (unlikely(float64_is_zero_or_denormal(frb
))) {
1069 /* XB is not zero because of the above check and */
1070 /* so must be denormalized. */
1075 return 0x8 | (fg_flag
? 4 : 0) | (fe_flag
? 2 : 0);
1078 uint32_t helper_ftsqrt(uint64_t frb
)
1083 if (unlikely(float64_is_infinity(frb
) || float64_is_zero(frb
))) {
1087 int e_b
= ppc_float64_get_unbiased_exp(frb
);
1089 if (unlikely(float64_is_any_nan(frb
))) {
1091 } else if (unlikely(float64_is_zero(frb
))) {
1093 } else if (unlikely(float64_is_neg(frb
))) {
1095 } else if (!float64_is_zero(frb
) && (e_b
<= (-1022 + 52))) {
1099 if (unlikely(float64_is_zero_or_denormal(frb
))) {
1100 /* XB is not zero because of the above check and */
1101 /* therefore must be denormalized. */
1106 return 0x8 | (fg_flag
? 4 : 0) | (fe_flag
? 2 : 0);
1109 void helper_fcmpu(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
1112 CPU_DoubleU farg1
, farg2
;
1118 if (unlikely(float64_is_any_nan(farg1
.d
) ||
1119 float64_is_any_nan(farg2
.d
))) {
1121 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1123 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1129 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1130 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1131 env
->crf
[crfD
] = ret
;
1132 if (unlikely(ret
== 0x01UL
1133 && (float64_is_signaling_nan(farg1
.d
, &env
->fp_status
) ||
1134 float64_is_signaling_nan(farg2
.d
, &env
->fp_status
)))) {
1135 /* sNaN comparison */
1136 float_invalid_op_vxsnan(env
, GETPC());
1140 void helper_fcmpo(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
1143 CPU_DoubleU farg1
, farg2
;
1149 if (unlikely(float64_is_any_nan(farg1
.d
) ||
1150 float64_is_any_nan(farg2
.d
))) {
1152 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1154 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1160 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1161 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1162 env
->crf
[crfD
] = ret
;
1163 if (unlikely(ret
== 0x01UL
)) {
1164 float_invalid_op_vxvc(env
, 1, GETPC());
1165 if (float64_is_signaling_nan(farg1
.d
, &env
->fp_status
) ||
1166 float64_is_signaling_nan(farg2
.d
, &env
->fp_status
)) {
1167 /* sNaN comparison */
1168 float_invalid_op_vxsnan(env
, GETPC());
1173 /* Single-precision floating-point conversions */
1174 static inline uint32_t efscfsi(CPUPPCState
*env
, uint32_t val
)
1178 u
.f
= int32_to_float32(val
, &env
->vec_status
);
1183 static inline uint32_t efscfui(CPUPPCState
*env
, uint32_t val
)
1187 u
.f
= uint32_to_float32(val
, &env
->vec_status
);
1192 static inline int32_t efsctsi(CPUPPCState
*env
, uint32_t val
)
1197 /* NaN are not treated the same way IEEE 754 does */
1198 if (unlikely(float32_is_quiet_nan(u
.f
, &env
->vec_status
))) {
1202 return float32_to_int32(u
.f
, &env
->vec_status
);
1205 static inline uint32_t efsctui(CPUPPCState
*env
, uint32_t val
)
1210 /* NaN are not treated the same way IEEE 754 does */
1211 if (unlikely(float32_is_quiet_nan(u
.f
, &env
->vec_status
))) {
1215 return float32_to_uint32(u
.f
, &env
->vec_status
);
1218 static inline uint32_t efsctsiz(CPUPPCState
*env
, uint32_t val
)
1223 /* NaN are not treated the same way IEEE 754 does */
1224 if (unlikely(float32_is_quiet_nan(u
.f
, &env
->vec_status
))) {
1228 return float32_to_int32_round_to_zero(u
.f
, &env
->vec_status
);
1231 static inline uint32_t efsctuiz(CPUPPCState
*env
, uint32_t val
)
1236 /* NaN are not treated the same way IEEE 754 does */
1237 if (unlikely(float32_is_quiet_nan(u
.f
, &env
->vec_status
))) {
1241 return float32_to_uint32_round_to_zero(u
.f
, &env
->vec_status
);
1244 static inline uint32_t efscfsf(CPUPPCState
*env
, uint32_t val
)
1249 u
.f
= int32_to_float32(val
, &env
->vec_status
);
1250 tmp
= int64_to_float32(1ULL << 32, &env
->vec_status
);
1251 u
.f
= float32_div(u
.f
, tmp
, &env
->vec_status
);
1256 static inline uint32_t efscfuf(CPUPPCState
*env
, uint32_t val
)
1261 u
.f
= uint32_to_float32(val
, &env
->vec_status
);
1262 tmp
= uint64_to_float32(1ULL << 32, &env
->vec_status
);
1263 u
.f
= float32_div(u
.f
, tmp
, &env
->vec_status
);
1268 static inline uint32_t efsctsf(CPUPPCState
*env
, uint32_t val
)
1274 /* NaN are not treated the same way IEEE 754 does */
1275 if (unlikely(float32_is_quiet_nan(u
.f
, &env
->vec_status
))) {
1278 tmp
= uint64_to_float32(1ULL << 32, &env
->vec_status
);
1279 u
.f
= float32_mul(u
.f
, tmp
, &env
->vec_status
);
1281 return float32_to_int32(u
.f
, &env
->vec_status
);
1284 static inline uint32_t efsctuf(CPUPPCState
*env
, uint32_t val
)
1290 /* NaN are not treated the same way IEEE 754 does */
1291 if (unlikely(float32_is_quiet_nan(u
.f
, &env
->vec_status
))) {
1294 tmp
= uint64_to_float32(1ULL << 32, &env
->vec_status
);
1295 u
.f
= float32_mul(u
.f
, tmp
, &env
->vec_status
);
1297 return float32_to_uint32(u
.f
, &env
->vec_status
);
1300 #define HELPER_SPE_SINGLE_CONV(name) \
1301 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1303 return e##name(env, val); \
1306 HELPER_SPE_SINGLE_CONV(fscfsi
);
1308 HELPER_SPE_SINGLE_CONV(fscfui
);
1310 HELPER_SPE_SINGLE_CONV(fscfuf
);
1312 HELPER_SPE_SINGLE_CONV(fscfsf
);
1314 HELPER_SPE_SINGLE_CONV(fsctsi
);
1316 HELPER_SPE_SINGLE_CONV(fsctui
);
1318 HELPER_SPE_SINGLE_CONV(fsctsiz
);
1320 HELPER_SPE_SINGLE_CONV(fsctuiz
);
1322 HELPER_SPE_SINGLE_CONV(fsctsf
);
1324 HELPER_SPE_SINGLE_CONV(fsctuf
);
1326 #define HELPER_SPE_VECTOR_CONV(name) \
1327 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1329 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1330 (uint64_t)e##name(env, val); \
1333 HELPER_SPE_VECTOR_CONV(fscfsi
);
1335 HELPER_SPE_VECTOR_CONV(fscfui
);
1337 HELPER_SPE_VECTOR_CONV(fscfuf
);
1339 HELPER_SPE_VECTOR_CONV(fscfsf
);
1341 HELPER_SPE_VECTOR_CONV(fsctsi
);
1343 HELPER_SPE_VECTOR_CONV(fsctui
);
1345 HELPER_SPE_VECTOR_CONV(fsctsiz
);
1347 HELPER_SPE_VECTOR_CONV(fsctuiz
);
1349 HELPER_SPE_VECTOR_CONV(fsctsf
);
1351 HELPER_SPE_VECTOR_CONV(fsctuf
);
1353 /* Single-precision floating-point arithmetic */
1354 static inline uint32_t efsadd(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1360 u1
.f
= float32_add(u1
.f
, u2
.f
, &env
->vec_status
);
1364 static inline uint32_t efssub(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1370 u1
.f
= float32_sub(u1
.f
, u2
.f
, &env
->vec_status
);
1374 static inline uint32_t efsmul(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1380 u1
.f
= float32_mul(u1
.f
, u2
.f
, &env
->vec_status
);
1384 static inline uint32_t efsdiv(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1390 u1
.f
= float32_div(u1
.f
, u2
.f
, &env
->vec_status
);
1394 #define HELPER_SPE_SINGLE_ARITH(name) \
1395 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1397 return e##name(env, op1, op2); \
1400 HELPER_SPE_SINGLE_ARITH(fsadd
);
1402 HELPER_SPE_SINGLE_ARITH(fssub
);
1404 HELPER_SPE_SINGLE_ARITH(fsmul
);
1406 HELPER_SPE_SINGLE_ARITH(fsdiv
);
1408 #define HELPER_SPE_VECTOR_ARITH(name) \
1409 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1411 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1412 (uint64_t)e##name(env, op1, op2); \
1415 HELPER_SPE_VECTOR_ARITH(fsadd
);
1417 HELPER_SPE_VECTOR_ARITH(fssub
);
1419 HELPER_SPE_VECTOR_ARITH(fsmul
);
1421 HELPER_SPE_VECTOR_ARITH(fsdiv
);
1423 /* Single-precision floating-point comparisons */
1424 static inline uint32_t efscmplt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1430 return float32_lt(u1
.f
, u2
.f
, &env
->vec_status
) ? 4 : 0;
1433 static inline uint32_t efscmpgt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1439 return float32_le(u1
.f
, u2
.f
, &env
->vec_status
) ? 0 : 4;
1442 static inline uint32_t efscmpeq(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1448 return float32_eq(u1
.f
, u2
.f
, &env
->vec_status
) ? 4 : 0;
1451 static inline uint32_t efststlt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1453 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1454 return efscmplt(env
, op1
, op2
);
1457 static inline uint32_t efststgt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1459 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1460 return efscmpgt(env
, op1
, op2
);
1463 static inline uint32_t efststeq(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1465 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1466 return efscmpeq(env
, op1
, op2
);
1469 #define HELPER_SINGLE_SPE_CMP(name) \
1470 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1472 return e##name(env, op1, op2); \
1475 HELPER_SINGLE_SPE_CMP(fststlt
);
1477 HELPER_SINGLE_SPE_CMP(fststgt
);
1479 HELPER_SINGLE_SPE_CMP(fststeq
);
1481 HELPER_SINGLE_SPE_CMP(fscmplt
);
1483 HELPER_SINGLE_SPE_CMP(fscmpgt
);
1485 HELPER_SINGLE_SPE_CMP(fscmpeq
);
1487 static inline uint32_t evcmp_merge(int t0
, int t1
)
1489 return (t0
<< 3) | (t1
<< 2) | ((t0
| t1
) << 1) | (t0
& t1
);
1492 #define HELPER_VECTOR_SPE_CMP(name) \
1493 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1495 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1496 e##name(env, op1, op2)); \
1499 HELPER_VECTOR_SPE_CMP(fststlt
);
1501 HELPER_VECTOR_SPE_CMP(fststgt
);
1503 HELPER_VECTOR_SPE_CMP(fststeq
);
1505 HELPER_VECTOR_SPE_CMP(fscmplt
);
1507 HELPER_VECTOR_SPE_CMP(fscmpgt
);
1509 HELPER_VECTOR_SPE_CMP(fscmpeq
);
1511 /* Double-precision floating-point conversion */
1512 uint64_t helper_efdcfsi(CPUPPCState
*env
, uint32_t val
)
1516 u
.d
= int32_to_float64(val
, &env
->vec_status
);
1521 uint64_t helper_efdcfsid(CPUPPCState
*env
, uint64_t val
)
1525 u
.d
= int64_to_float64(val
, &env
->vec_status
);
1530 uint64_t helper_efdcfui(CPUPPCState
*env
, uint32_t val
)
1534 u
.d
= uint32_to_float64(val
, &env
->vec_status
);
1539 uint64_t helper_efdcfuid(CPUPPCState
*env
, uint64_t val
)
1543 u
.d
= uint64_to_float64(val
, &env
->vec_status
);
1548 uint32_t helper_efdctsi(CPUPPCState
*env
, uint64_t val
)
1553 /* NaN are not treated the same way IEEE 754 does */
1554 if (unlikely(float64_is_any_nan(u
.d
))) {
1558 return float64_to_int32(u
.d
, &env
->vec_status
);
1561 uint32_t helper_efdctui(CPUPPCState
*env
, uint64_t val
)
1566 /* NaN are not treated the same way IEEE 754 does */
1567 if (unlikely(float64_is_any_nan(u
.d
))) {
1571 return float64_to_uint32(u
.d
, &env
->vec_status
);
1574 uint32_t helper_efdctsiz(CPUPPCState
*env
, uint64_t val
)
1579 /* NaN are not treated the same way IEEE 754 does */
1580 if (unlikely(float64_is_any_nan(u
.d
))) {
1584 return float64_to_int32_round_to_zero(u
.d
, &env
->vec_status
);
1587 uint64_t helper_efdctsidz(CPUPPCState
*env
, uint64_t val
)
1592 /* NaN are not treated the same way IEEE 754 does */
1593 if (unlikely(float64_is_any_nan(u
.d
))) {
1597 return float64_to_int64_round_to_zero(u
.d
, &env
->vec_status
);
1600 uint32_t helper_efdctuiz(CPUPPCState
*env
, uint64_t val
)
1605 /* NaN are not treated the same way IEEE 754 does */
1606 if (unlikely(float64_is_any_nan(u
.d
))) {
1610 return float64_to_uint32_round_to_zero(u
.d
, &env
->vec_status
);
1613 uint64_t helper_efdctuidz(CPUPPCState
*env
, uint64_t val
)
1618 /* NaN are not treated the same way IEEE 754 does */
1619 if (unlikely(float64_is_any_nan(u
.d
))) {
1623 return float64_to_uint64_round_to_zero(u
.d
, &env
->vec_status
);
1626 uint64_t helper_efdcfsf(CPUPPCState
*env
, uint32_t val
)
1631 u
.d
= int32_to_float64(val
, &env
->vec_status
);
1632 tmp
= int64_to_float64(1ULL << 32, &env
->vec_status
);
1633 u
.d
= float64_div(u
.d
, tmp
, &env
->vec_status
);
1638 uint64_t helper_efdcfuf(CPUPPCState
*env
, uint32_t val
)
1643 u
.d
= uint32_to_float64(val
, &env
->vec_status
);
1644 tmp
= int64_to_float64(1ULL << 32, &env
->vec_status
);
1645 u
.d
= float64_div(u
.d
, tmp
, &env
->vec_status
);
1650 uint32_t helper_efdctsf(CPUPPCState
*env
, uint64_t val
)
1656 /* NaN are not treated the same way IEEE 754 does */
1657 if (unlikely(float64_is_any_nan(u
.d
))) {
1660 tmp
= uint64_to_float64(1ULL << 32, &env
->vec_status
);
1661 u
.d
= float64_mul(u
.d
, tmp
, &env
->vec_status
);
1663 return float64_to_int32(u
.d
, &env
->vec_status
);
1666 uint32_t helper_efdctuf(CPUPPCState
*env
, uint64_t val
)
1672 /* NaN are not treated the same way IEEE 754 does */
1673 if (unlikely(float64_is_any_nan(u
.d
))) {
1676 tmp
= uint64_to_float64(1ULL << 32, &env
->vec_status
);
1677 u
.d
= float64_mul(u
.d
, tmp
, &env
->vec_status
);
1679 return float64_to_uint32(u
.d
, &env
->vec_status
);
1682 uint32_t helper_efscfd(CPUPPCState
*env
, uint64_t val
)
1688 u2
.f
= float64_to_float32(u1
.d
, &env
->vec_status
);
1693 uint64_t helper_efdcfs(CPUPPCState
*env
, uint32_t val
)
1699 u2
.d
= float32_to_float64(u1
.f
, &env
->vec_status
);
1704 /* Double precision fixed-point arithmetic */
1705 uint64_t helper_efdadd(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1711 u1
.d
= float64_add(u1
.d
, u2
.d
, &env
->vec_status
);
1715 uint64_t helper_efdsub(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1721 u1
.d
= float64_sub(u1
.d
, u2
.d
, &env
->vec_status
);
1725 uint64_t helper_efdmul(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1731 u1
.d
= float64_mul(u1
.d
, u2
.d
, &env
->vec_status
);
1735 uint64_t helper_efddiv(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1741 u1
.d
= float64_div(u1
.d
, u2
.d
, &env
->vec_status
);
1745 /* Double precision floating point helpers */
1746 uint32_t helper_efdtstlt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1752 return float64_lt(u1
.d
, u2
.d
, &env
->vec_status
) ? 4 : 0;
1755 uint32_t helper_efdtstgt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1761 return float64_le(u1
.d
, u2
.d
, &env
->vec_status
) ? 0 : 4;
1764 uint32_t helper_efdtsteq(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1770 return float64_eq_quiet(u1
.d
, u2
.d
, &env
->vec_status
) ? 4 : 0;
1773 uint32_t helper_efdcmplt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1775 /* XXX: TODO: test special values (NaN, infinites, ...) */
1776 return helper_efdtstlt(env
, op1
, op2
);
1779 uint32_t helper_efdcmpgt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1781 /* XXX: TODO: test special values (NaN, infinites, ...) */
1782 return helper_efdtstgt(env
, op1
, op2
);
1785 uint32_t helper_efdcmpeq(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1787 /* XXX: TODO: test special values (NaN, infinites, ...) */
1788 return helper_efdtsteq(env
, op1
, op2
);
1791 #define float64_to_float64(x, env) x
1795 * VSX_ADD_SUB - VSX floating point add/subract
1796 * name - instruction mnemonic
1797 * op - operation (add or sub)
1798 * nels - number of elements (1, 2 or 4)
1799 * tp - type (float32 or float64)
1800 * fld - vsr_t field (VsrD(*) or VsrW(*))
1803 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1804 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
1805 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1807 ppc_vsr_t t = *xt; \
1810 helper_reset_fpstatus(env); \
1812 for (i = 0; i < nels; i++) { \
1813 float_status tstat = env->fp_status; \
1814 set_float_exception_flags(0, &tstat); \
1815 t.fld = tp##_##op(xa->fld, xb->fld, &tstat); \
1816 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1818 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1819 float_invalid_op_addsub(env, sfprf, GETPC(), \
1820 tp##_classify(xa->fld) | \
1821 tp##_classify(xb->fld)); \
1825 t.fld = helper_frsp(env, t.fld); \
1829 helper_compute_fprf_float64(env, t.fld); \
1833 do_float_check_status(env, GETPC()); \
1836 VSX_ADD_SUB(xsadddp
, add
, 1, float64
, VsrD(0), 1, 0)
1837 VSX_ADD_SUB(xsaddsp
, add
, 1, float64
, VsrD(0), 1, 1)
1838 VSX_ADD_SUB(xvadddp
, add
, 2, float64
, VsrD(i
), 0, 0)
1839 VSX_ADD_SUB(xvaddsp
, add
, 4, float32
, VsrW(i
), 0, 0)
1840 VSX_ADD_SUB(xssubdp
, sub
, 1, float64
, VsrD(0), 1, 0)
1841 VSX_ADD_SUB(xssubsp
, sub
, 1, float64
, VsrD(0), 1, 1)
1842 VSX_ADD_SUB(xvsubdp
, sub
, 2, float64
, VsrD(i
), 0, 0)
1843 VSX_ADD_SUB(xvsubsp
, sub
, 4, float32
, VsrW(i
), 0, 0)
1845 void helper_xsaddqp(CPUPPCState
*env
, uint32_t opcode
)
1847 ppc_vsr_t
*xt
= &env
->vsr
[rD(opcode
) + 32];
1848 ppc_vsr_t
*xa
= &env
->vsr
[rA(opcode
) + 32];
1849 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
1853 helper_reset_fpstatus(env
);
1855 tstat
= env
->fp_status
;
1856 if (unlikely(Rc(opcode
) != 0)) {
1857 tstat
.float_rounding_mode
= float_round_to_odd
;
1860 set_float_exception_flags(0, &tstat
);
1861 t
.f128
= float128_add(xa
->f128
, xb
->f128
, &tstat
);
1862 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
1864 if (unlikely(tstat
.float_exception_flags
& float_flag_invalid
)) {
1865 float_invalid_op_addsub(env
, 1, GETPC(),
1866 float128_classify(xa
->f128
) |
1867 float128_classify(xb
->f128
));
1870 helper_compute_fprf_float128(env
, t
.f128
);
1873 do_float_check_status(env
, GETPC());
1877 * VSX_MUL - VSX floating point multiply
1878 * op - instruction mnemonic
1879 * nels - number of elements (1, 2 or 4)
1880 * tp - type (float32 or float64)
1881 * fld - vsr_t field (VsrD(*) or VsrW(*))
1884 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1885 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1886 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1888 ppc_vsr_t t = *xt; \
1891 helper_reset_fpstatus(env); \
1893 for (i = 0; i < nels; i++) { \
1894 float_status tstat = env->fp_status; \
1895 set_float_exception_flags(0, &tstat); \
1896 t.fld = tp##_mul(xa->fld, xb->fld, &tstat); \
1897 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1899 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1900 float_invalid_op_mul(env, sfprf, GETPC(), \
1901 tp##_classify(xa->fld) | \
1902 tp##_classify(xb->fld)); \
1906 t.fld = helper_frsp(env, t.fld); \
1910 helper_compute_fprf_float64(env, t.fld); \
1915 do_float_check_status(env, GETPC()); \
1918 VSX_MUL(xsmuldp
, 1, float64
, VsrD(0), 1, 0)
1919 VSX_MUL(xsmulsp
, 1, float64
, VsrD(0), 1, 1)
1920 VSX_MUL(xvmuldp
, 2, float64
, VsrD(i
), 0, 0)
1921 VSX_MUL(xvmulsp
, 4, float32
, VsrW(i
), 0, 0)
1923 void helper_xsmulqp(CPUPPCState
*env
, uint32_t opcode
)
1925 ppc_vsr_t
*xt
= &env
->vsr
[rD(opcode
) + 32];
1926 ppc_vsr_t
*xa
= &env
->vsr
[rA(opcode
) + 32];
1927 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
1931 helper_reset_fpstatus(env
);
1932 tstat
= env
->fp_status
;
1933 if (unlikely(Rc(opcode
) != 0)) {
1934 tstat
.float_rounding_mode
= float_round_to_odd
;
1937 set_float_exception_flags(0, &tstat
);
1938 t
.f128
= float128_mul(xa
->f128
, xb
->f128
, &tstat
);
1939 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
1941 if (unlikely(tstat
.float_exception_flags
& float_flag_invalid
)) {
1942 float_invalid_op_mul(env
, 1, GETPC(),
1943 float128_classify(xa
->f128
) |
1944 float128_classify(xb
->f128
));
1946 helper_compute_fprf_float128(env
, t
.f128
);
1949 do_float_check_status(env
, GETPC());
1953 * VSX_DIV - VSX floating point divide
1954 * op - instruction mnemonic
1955 * nels - number of elements (1, 2 or 4)
1956 * tp - type (float32 or float64)
1957 * fld - vsr_t field (VsrD(*) or VsrW(*))
1960 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1961 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1962 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1964 ppc_vsr_t t = *xt; \
1967 helper_reset_fpstatus(env); \
1969 for (i = 0; i < nels; i++) { \
1970 float_status tstat = env->fp_status; \
1971 set_float_exception_flags(0, &tstat); \
1972 t.fld = tp##_div(xa->fld, xb->fld, &tstat); \
1973 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1975 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1976 float_invalid_op_div(env, sfprf, GETPC(), \
1977 tp##_classify(xa->fld) | \
1978 tp##_classify(xb->fld)); \
1980 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1981 float_zero_divide_excp(env, GETPC()); \
1985 t.fld = helper_frsp(env, t.fld); \
1989 helper_compute_fprf_float64(env, t.fld); \
1994 do_float_check_status(env, GETPC()); \
1997 VSX_DIV(xsdivdp
, 1, float64
, VsrD(0), 1, 0)
1998 VSX_DIV(xsdivsp
, 1, float64
, VsrD(0), 1, 1)
1999 VSX_DIV(xvdivdp
, 2, float64
, VsrD(i
), 0, 0)
2000 VSX_DIV(xvdivsp
, 4, float32
, VsrW(i
), 0, 0)
2002 void helper_xsdivqp(CPUPPCState
*env
, uint32_t opcode
)
2004 ppc_vsr_t
*xt
= &env
->vsr
[rD(opcode
) + 32];
2005 ppc_vsr_t
*xa
= &env
->vsr
[rA(opcode
) + 32];
2006 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
2010 helper_reset_fpstatus(env
);
2011 tstat
= env
->fp_status
;
2012 if (unlikely(Rc(opcode
) != 0)) {
2013 tstat
.float_rounding_mode
= float_round_to_odd
;
2016 set_float_exception_flags(0, &tstat
);
2017 t
.f128
= float128_div(xa
->f128
, xb
->f128
, &tstat
);
2018 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
2020 if (unlikely(tstat
.float_exception_flags
& float_flag_invalid
)) {
2021 float_invalid_op_div(env
, 1, GETPC(),
2022 float128_classify(xa
->f128
) |
2023 float128_classify(xb
->f128
));
2025 if (unlikely(tstat
.float_exception_flags
& float_flag_divbyzero
)) {
2026 float_zero_divide_excp(env
, GETPC());
2029 helper_compute_fprf_float128(env
, t
.f128
);
2031 do_float_check_status(env
, GETPC());
2035 * VSX_RE - VSX floating point reciprocal estimate
2036 * op - instruction mnemonic
2037 * nels - number of elements (1, 2 or 4)
2038 * tp - type (float32 or float64)
2039 * fld - vsr_t field (VsrD(*) or VsrW(*))
2042 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
2043 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2045 ppc_vsr_t t = *xt; \
2048 helper_reset_fpstatus(env); \
2050 for (i = 0; i < nels; i++) { \
2051 if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
2052 float_invalid_op_vxsnan(env, GETPC()); \
2054 t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
2057 t.fld = helper_frsp(env, t.fld); \
2061 helper_compute_fprf_float64(env, t.fld); \
2066 do_float_check_status(env, GETPC()); \
2069 VSX_RE(xsredp
, 1, float64
, VsrD(0), 1, 0)
2070 VSX_RE(xsresp
, 1, float64
, VsrD(0), 1, 1)
2071 VSX_RE(xvredp
, 2, float64
, VsrD(i
), 0, 0)
2072 VSX_RE(xvresp
, 4, float32
, VsrW(i
), 0, 0)
2075 * VSX_SQRT - VSX floating point square root
2076 * op - instruction mnemonic
2077 * nels - number of elements (1, 2 or 4)
2078 * tp - type (float32 or float64)
2079 * fld - vsr_t field (VsrD(*) or VsrW(*))
2082 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
2083 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2085 ppc_vsr_t t = *xt; \
2088 helper_reset_fpstatus(env); \
2090 for (i = 0; i < nels; i++) { \
2091 float_status tstat = env->fp_status; \
2092 set_float_exception_flags(0, &tstat); \
2093 t.fld = tp##_sqrt(xb->fld, &tstat); \
2094 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2096 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2097 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
2098 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
2099 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
2100 float_invalid_op_vxsnan(env, GETPC()); \
2105 t.fld = helper_frsp(env, t.fld); \
2109 helper_compute_fprf_float64(env, t.fld); \
2114 do_float_check_status(env, GETPC()); \
2117 VSX_SQRT(xssqrtdp
, 1, float64
, VsrD(0), 1, 0)
2118 VSX_SQRT(xssqrtsp
, 1, float64
, VsrD(0), 1, 1)
2119 VSX_SQRT(xvsqrtdp
, 2, float64
, VsrD(i
), 0, 0)
2120 VSX_SQRT(xvsqrtsp
, 4, float32
, VsrW(i
), 0, 0)
2123 *VSX_RSQRTE - VSX floating point reciprocal square root estimate
2124 * op - instruction mnemonic
2125 * nels - number of elements (1, 2 or 4)
2126 * tp - type (float32 or float64)
2127 * fld - vsr_t field (VsrD(*) or VsrW(*))
2130 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
2131 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2133 ppc_vsr_t t = *xt; \
2136 helper_reset_fpstatus(env); \
2138 for (i = 0; i < nels; i++) { \
2139 float_status tstat = env->fp_status; \
2140 set_float_exception_flags(0, &tstat); \
2141 t.fld = tp##_sqrt(xb->fld, &tstat); \
2142 t.fld = tp##_div(tp##_one, t.fld, &tstat); \
2143 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2145 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2146 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
2147 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
2148 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
2149 float_invalid_op_vxsnan(env, GETPC()); \
2154 t.fld = helper_frsp(env, t.fld); \
2158 helper_compute_fprf_float64(env, t.fld); \
2163 do_float_check_status(env, GETPC()); \
2166 VSX_RSQRTE(xsrsqrtedp
, 1, float64
, VsrD(0), 1, 0)
2167 VSX_RSQRTE(xsrsqrtesp
, 1, float64
, VsrD(0), 1, 1)
2168 VSX_RSQRTE(xvrsqrtedp
, 2, float64
, VsrD(i
), 0, 0)
2169 VSX_RSQRTE(xvrsqrtesp
, 4, float32
, VsrW(i
), 0, 0)
2172 * VSX_TDIV - VSX floating point test for divide
2173 * op - instruction mnemonic
2174 * nels - number of elements (1, 2 or 4)
2175 * tp - type (float32 or float64)
2176 * fld - vsr_t field (VsrD(*) or VsrW(*))
2177 * emin - minimum unbiased exponent
2178 * emax - maximum unbiased exponent
2179 * nbits - number of fraction bits
2181 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
2182 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2183 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2189 for (i = 0; i < nels; i++) { \
2190 if (unlikely(tp##_is_infinity(xa->fld) || \
2191 tp##_is_infinity(xb->fld) || \
2192 tp##_is_zero(xb->fld))) { \
2196 int e_a = ppc_##tp##_get_unbiased_exp(xa->fld); \
2197 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
2199 if (unlikely(tp##_is_any_nan(xa->fld) || \
2200 tp##_is_any_nan(xb->fld))) { \
2202 } else if ((e_b <= emin) || (e_b >= (emax - 2))) { \
2204 } else if (!tp##_is_zero(xa->fld) && \
2205 (((e_a - e_b) >= emax) || \
2206 ((e_a - e_b) <= (emin + 1)) || \
2207 (e_a <= (emin + nbits)))) { \
2211 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2213 * XB is not zero because of the above check and so \
2214 * must be denormalized. \
2221 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2224 VSX_TDIV(xstdivdp
, 1, float64
, VsrD(0), -1022, 1023, 52)
2225 VSX_TDIV(xvtdivdp
, 2, float64
, VsrD(i
), -1022, 1023, 52)
2226 VSX_TDIV(xvtdivsp
, 4, float32
, VsrW(i
), -126, 127, 23)
2229 * VSX_TSQRT - VSX floating point test for square root
2230 * op - instruction mnemonic
2231 * nels - number of elements (1, 2 or 4)
2232 * tp - type (float32 or float64)
2233 * fld - vsr_t field (VsrD(*) or VsrW(*))
2234 * emin - minimum unbiased exponent
2235 * emax - maximum unbiased exponent
2236 * nbits - number of fraction bits
2238 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2239 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2241 ppc_vsr_t *xb = &env->vsr[xB(opcode)]; \
2246 for (i = 0; i < nels; i++) { \
2247 if (unlikely(tp##_is_infinity(xb->fld) || \
2248 tp##_is_zero(xb->fld))) { \
2252 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
2254 if (unlikely(tp##_is_any_nan(xb->fld))) { \
2256 } else if (unlikely(tp##_is_zero(xb->fld))) { \
2258 } else if (unlikely(tp##_is_neg(xb->fld))) { \
2260 } else if (!tp##_is_zero(xb->fld) && \
2261 (e_b <= (emin + nbits))) { \
2265 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2267 * XB is not zero because of the above check and \
2268 * therefore must be denormalized. \
2275 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2278 VSX_TSQRT(xstsqrtdp
, 1, float64
, VsrD(0), -1022, 52)
2279 VSX_TSQRT(xvtsqrtdp
, 2, float64
, VsrD(i
), -1022, 52)
2280 VSX_TSQRT(xvtsqrtsp
, 4, float32
, VsrW(i
), -126, 23)
2283 * VSX_MADD - VSX floating point muliply/add variations
2284 * op - instruction mnemonic
2285 * nels - number of elements (1, 2 or 4)
2286 * tp - type (float32 or float64)
2287 * fld - vsr_t field (VsrD(*) or VsrW(*))
2288 * maddflgs - flags for the float*muladd routine that control the
2289 * various forms (madd, msub, nmadd, nmsub)
2290 * afrm - A form (1=A, 0=M)
2293 #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) \
2294 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2295 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2297 ppc_vsr_t t = *xt, *b, *c; \
2300 if (afrm) { /* AxB + T */ \
2303 } else { /* AxT + B */ \
2308 helper_reset_fpstatus(env); \
2310 for (i = 0; i < nels; i++) { \
2311 float_status tstat = env->fp_status; \
2312 set_float_exception_flags(0, &tstat); \
2313 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2315 * Avoid double rounding errors by rounding the intermediate \
2318 set_float_rounding_mode(float_round_to_zero, &tstat); \
2319 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2320 maddflgs, &tstat); \
2321 t.fld |= (get_float_exception_flags(&tstat) & \
2322 float_flag_inexact) != 0; \
2324 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2325 maddflgs, &tstat); \
2327 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2329 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2330 tp##_maddsub_update_excp(env, xa->fld, b->fld, \
2331 c->fld, maddflgs, GETPC()); \
2335 t.fld = helper_frsp(env, t.fld); \
2339 helper_compute_fprf_float64(env, t.fld); \
2343 do_float_check_status(env, GETPC()); \
2346 VSX_MADD(xsmaddadp
, 1, float64
, VsrD(0), MADD_FLGS
, 1, 1, 0)
2347 VSX_MADD(xsmaddmdp
, 1, float64
, VsrD(0), MADD_FLGS
, 0, 1, 0)
2348 VSX_MADD(xsmsubadp
, 1, float64
, VsrD(0), MSUB_FLGS
, 1, 1, 0)
2349 VSX_MADD(xsmsubmdp
, 1, float64
, VsrD(0), MSUB_FLGS
, 0, 1, 0)
2350 VSX_MADD(xsnmaddadp
, 1, float64
, VsrD(0), NMADD_FLGS
, 1, 1, 0)
2351 VSX_MADD(xsnmaddmdp
, 1, float64
, VsrD(0), NMADD_FLGS
, 0, 1, 0)
2352 VSX_MADD(xsnmsubadp
, 1, float64
, VsrD(0), NMSUB_FLGS
, 1, 1, 0)
2353 VSX_MADD(xsnmsubmdp
, 1, float64
, VsrD(0), NMSUB_FLGS
, 0, 1, 0)
2355 VSX_MADD(xsmaddasp
, 1, float64
, VsrD(0), MADD_FLGS
, 1, 1, 1)
2356 VSX_MADD(xsmaddmsp
, 1, float64
, VsrD(0), MADD_FLGS
, 0, 1, 1)
2357 VSX_MADD(xsmsubasp
, 1, float64
, VsrD(0), MSUB_FLGS
, 1, 1, 1)
2358 VSX_MADD(xsmsubmsp
, 1, float64
, VsrD(0), MSUB_FLGS
, 0, 1, 1)
2359 VSX_MADD(xsnmaddasp
, 1, float64
, VsrD(0), NMADD_FLGS
, 1, 1, 1)
2360 VSX_MADD(xsnmaddmsp
, 1, float64
, VsrD(0), NMADD_FLGS
, 0, 1, 1)
2361 VSX_MADD(xsnmsubasp
, 1, float64
, VsrD(0), NMSUB_FLGS
, 1, 1, 1)
2362 VSX_MADD(xsnmsubmsp
, 1, float64
, VsrD(0), NMSUB_FLGS
, 0, 1, 1)
2364 VSX_MADD(xvmaddadp
, 2, float64
, VsrD(i
), MADD_FLGS
, 1, 0, 0)
2365 VSX_MADD(xvmaddmdp
, 2, float64
, VsrD(i
), MADD_FLGS
, 0, 0, 0)
2366 VSX_MADD(xvmsubadp
, 2, float64
, VsrD(i
), MSUB_FLGS
, 1, 0, 0)
2367 VSX_MADD(xvmsubmdp
, 2, float64
, VsrD(i
), MSUB_FLGS
, 0, 0, 0)
2368 VSX_MADD(xvnmaddadp
, 2, float64
, VsrD(i
), NMADD_FLGS
, 1, 0, 0)
2369 VSX_MADD(xvnmaddmdp
, 2, float64
, VsrD(i
), NMADD_FLGS
, 0, 0, 0)
2370 VSX_MADD(xvnmsubadp
, 2, float64
, VsrD(i
), NMSUB_FLGS
, 1, 0, 0)
2371 VSX_MADD(xvnmsubmdp
, 2, float64
, VsrD(i
), NMSUB_FLGS
, 0, 0, 0)
2373 VSX_MADD(xvmaddasp
, 4, float32
, VsrW(i
), MADD_FLGS
, 1, 0, 0)
2374 VSX_MADD(xvmaddmsp
, 4, float32
, VsrW(i
), MADD_FLGS
, 0, 0, 0)
2375 VSX_MADD(xvmsubasp
, 4, float32
, VsrW(i
), MSUB_FLGS
, 1, 0, 0)
2376 VSX_MADD(xvmsubmsp
, 4, float32
, VsrW(i
), MSUB_FLGS
, 0, 0, 0)
2377 VSX_MADD(xvnmaddasp
, 4, float32
, VsrW(i
), NMADD_FLGS
, 1, 0, 0)
2378 VSX_MADD(xvnmaddmsp
, 4, float32
, VsrW(i
), NMADD_FLGS
, 0, 0, 0)
2379 VSX_MADD(xvnmsubasp
, 4, float32
, VsrW(i
), NMSUB_FLGS
, 1, 0, 0)
2380 VSX_MADD(xvnmsubmsp
, 4, float32
, VsrW(i
), NMSUB_FLGS
, 0, 0, 0)
2383 * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
2384 * op - instruction mnemonic
2385 * cmp - comparison operation
2386 * exp - expected result of comparison
2387 * svxvc - set VXVC bit
2389 #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
2390 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2391 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2393 ppc_vsr_t t = *xt; \
2394 bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
2396 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2397 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2398 vxsnan_flag = true; \
2399 if (fpscr_ve == 0 && svxvc) { \
2402 } else if (svxvc) { \
2403 vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2404 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); \
2406 if (vxsnan_flag) { \
2407 float_invalid_op_vxsnan(env, GETPC()); \
2410 float_invalid_op_vxvc(env, 0, GETPC()); \
2412 vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
2415 if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), \
2416 &env->fp_status) == exp) { \
2425 do_float_check_status(env, GETPC()); \
2428 VSX_SCALAR_CMP_DP(xscmpeqdp
, eq
, 1, 0)
2429 VSX_SCALAR_CMP_DP(xscmpgedp
, le
, 1, 1)
2430 VSX_SCALAR_CMP_DP(xscmpgtdp
, lt
, 1, 1)
2431 VSX_SCALAR_CMP_DP(xscmpnedp
, eq
, 0, 0)
2433 void helper_xscmpexpdp(CPUPPCState
*env
, uint32_t opcode
,
2434 ppc_vsr_t
*xa
, ppc_vsr_t
*xb
)
2436 int64_t exp_a
, exp_b
;
2439 exp_a
= extract64(xa
->VsrD(0), 52, 11);
2440 exp_b
= extract64(xb
->VsrD(0), 52, 11);
2442 if (unlikely(float64_is_any_nan(xa
->VsrD(0)) ||
2443 float64_is_any_nan(xb
->VsrD(0)))) {
2446 if (exp_a
< exp_b
) {
2448 } else if (exp_a
> exp_b
) {
2455 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
2456 env
->fpscr
|= cc
<< FPSCR_FPRF
;
2457 env
->crf
[BF(opcode
)] = cc
;
2459 do_float_check_status(env
, GETPC());
2462 void helper_xscmpexpqp(CPUPPCState
*env
, uint32_t opcode
)
2464 ppc_vsr_t
*xa
= &env
->vsr
[rA(opcode
) + 32];
2465 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
2466 int64_t exp_a
, exp_b
;
2469 exp_a
= extract64(xa
->VsrD(0), 48, 15);
2470 exp_b
= extract64(xb
->VsrD(0), 48, 15);
2472 if (unlikely(float128_is_any_nan(xa
->f128
) ||
2473 float128_is_any_nan(xb
->f128
))) {
2476 if (exp_a
< exp_b
) {
2478 } else if (exp_a
> exp_b
) {
2485 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
2486 env
->fpscr
|= cc
<< FPSCR_FPRF
;
2487 env
->crf
[BF(opcode
)] = cc
;
2489 do_float_check_status(env
, GETPC());
2492 #define VSX_SCALAR_CMP(op, ordered) \
2493 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2494 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2497 bool vxsnan_flag = false, vxvc_flag = false; \
2499 helper_reset_fpstatus(env); \
2501 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2502 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2503 vxsnan_flag = true; \
2505 if (fpscr_ve == 0 && ordered) { \
2508 } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2509 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { \
2515 if (vxsnan_flag) { \
2516 float_invalid_op_vxsnan(env, GETPC()); \
2519 float_invalid_op_vxvc(env, 0, GETPC()); \
2522 if (float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \
2524 } else if (!float64_le(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \
2530 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2531 env->fpscr |= cc << FPSCR_FPRF; \
2532 env->crf[BF(opcode)] = cc; \
2534 do_float_check_status(env, GETPC()); \
2537 VSX_SCALAR_CMP(xscmpodp
, 1)
2538 VSX_SCALAR_CMP(xscmpudp
, 0)
2540 #define VSX_SCALAR_CMPQ(op, ordered) \
2541 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2543 ppc_vsr_t *xa = &env->vsr[rA(opcode) + 32]; \
2544 ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32]; \
2546 bool vxsnan_flag = false, vxvc_flag = false; \
2548 helper_reset_fpstatus(env); \
2550 if (float128_is_signaling_nan(xa->f128, &env->fp_status) || \
2551 float128_is_signaling_nan(xb->f128, &env->fp_status)) { \
2552 vxsnan_flag = true; \
2554 if (fpscr_ve == 0 && ordered) { \
2557 } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) || \
2558 float128_is_quiet_nan(xb->f128, &env->fp_status)) { \
2564 if (vxsnan_flag) { \
2565 float_invalid_op_vxsnan(env, GETPC()); \
2568 float_invalid_op_vxvc(env, 0, GETPC()); \
2571 if (float128_lt(xa->f128, xb->f128, &env->fp_status)) { \
2573 } else if (!float128_le(xa->f128, xb->f128, &env->fp_status)) { \
2579 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2580 env->fpscr |= cc << FPSCR_FPRF; \
2581 env->crf[BF(opcode)] = cc; \
2583 do_float_check_status(env, GETPC()); \
2586 VSX_SCALAR_CMPQ(xscmpoqp
, 1)
2587 VSX_SCALAR_CMPQ(xscmpuqp
, 0)
2590 * VSX_MAX_MIN - VSX floating point maximum/minimum
2591 * name - instruction mnemonic
2592 * op - operation (max or min)
2593 * nels - number of elements (1, 2 or 4)
2594 * tp - type (float32 or float64)
2595 * fld - vsr_t field (VsrD(*) or VsrW(*))
2597 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2598 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
2599 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2601 ppc_vsr_t t = *xt; \
2604 for (i = 0; i < nels; i++) { \
2605 t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status); \
2606 if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2607 tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
2608 float_invalid_op_vxsnan(env, GETPC()); \
2613 do_float_check_status(env, GETPC()); \
2616 VSX_MAX_MIN(xsmaxdp
, maxnum
, 1, float64
, VsrD(0))
2617 VSX_MAX_MIN(xvmaxdp
, maxnum
, 2, float64
, VsrD(i
))
2618 VSX_MAX_MIN(xvmaxsp
, maxnum
, 4, float32
, VsrW(i
))
2619 VSX_MAX_MIN(xsmindp
, minnum
, 1, float64
, VsrD(0))
2620 VSX_MAX_MIN(xvmindp
, minnum
, 2, float64
, VsrD(i
))
2621 VSX_MAX_MIN(xvminsp
, minnum
, 4, float32
, VsrW(i
))
2623 #define VSX_MAX_MINC(name, max) \
2624 void helper_##name(CPUPPCState *env, uint32_t opcode) \
2626 ppc_vsr_t *xt = &env->vsr[rD(opcode) + 32]; \
2627 ppc_vsr_t *xa = &env->vsr[rA(opcode) + 32]; \
2628 ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32]; \
2629 ppc_vsr_t t = *xt; \
2630 bool vxsnan_flag = false, vex_flag = false; \
2632 if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
2633 float64_is_any_nan(xb->VsrD(0)))) { \
2634 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2635 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2636 vxsnan_flag = true; \
2638 t.VsrD(0) = xb->VsrD(0); \
2639 } else if ((max && \
2640 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2642 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2643 t.VsrD(0) = xa->VsrD(0); \
2645 t.VsrD(0) = xb->VsrD(0); \
2648 vex_flag = fpscr_ve & vxsnan_flag; \
2649 if (vxsnan_flag) { \
2650 float_invalid_op_vxsnan(env, GETPC()); \
2657 VSX_MAX_MINC(xsmaxcdp, 1);
2658 VSX_MAX_MINC(xsmincdp
, 0);
2660 #define VSX_MAX_MINJ(name, max) \
2661 void helper_##name(CPUPPCState *env, uint32_t opcode) \
2663 ppc_vsr_t *xt = &env->vsr[rD(opcode) + 32]; \
2664 ppc_vsr_t *xa = &env->vsr[rA(opcode) + 32]; \
2665 ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32]; \
2666 ppc_vsr_t t = *xt; \
2667 bool vxsnan_flag = false, vex_flag = false; \
2669 if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { \
2670 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { \
2671 vxsnan_flag = true; \
2673 t.VsrD(0) = xa->VsrD(0); \
2674 } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { \
2675 if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2676 vxsnan_flag = true; \
2678 t.VsrD(0) = xb->VsrD(0); \
2679 } else if (float64_is_zero(xa->VsrD(0)) && \
2680 float64_is_zero(xb->VsrD(0))) { \
2682 if (!float64_is_neg(xa->VsrD(0)) || \
2683 !float64_is_neg(xb->VsrD(0))) { \
2686 t.VsrD(0) = 0x8000000000000000ULL; \
2689 if (float64_is_neg(xa->VsrD(0)) || \
2690 float64_is_neg(xb->VsrD(0))) { \
2691 t.VsrD(0) = 0x8000000000000000ULL; \
2696 } else if ((max && \
2697 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2699 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2700 t.VsrD(0) = xa->VsrD(0); \
2702 t.VsrD(0) = xb->VsrD(0); \
2705 vex_flag = fpscr_ve & vxsnan_flag; \
2706 if (vxsnan_flag) { \
2707 float_invalid_op_vxsnan(env, GETPC()); \
2714 VSX_MAX_MINJ(xsmaxjdp, 1);
2715 VSX_MAX_MINJ(xsminjdp
, 0);
2718 * VSX_CMP - VSX floating point compare
2719 * op - instruction mnemonic
2720 * nels - number of elements (1, 2 or 4)
2721 * tp - type (float32 or float64)
2722 * fld - vsr_t field (VsrD(*) or VsrW(*))
2723 * cmp - comparison operation
2724 * svxvc - set VXVC bit
2725 * exp - expected result of comparison
2727 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
2728 uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2729 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2731 ppc_vsr_t t = *xt; \
2732 uint32_t crf6 = 0; \
2735 int all_false = 1; \
2737 for (i = 0; i < nels; i++) { \
2738 if (unlikely(tp##_is_any_nan(xa->fld) || \
2739 tp##_is_any_nan(xb->fld))) { \
2740 if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2741 tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \
2742 float_invalid_op_vxsnan(env, GETPC()); \
2745 float_invalid_op_vxvc(env, 0, GETPC()); \
2750 if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) == exp) { \
2761 crf6 = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2765 VSX_CMP(xvcmpeqdp
, 2, float64
, VsrD(i
), eq
, 0, 1)
2766 VSX_CMP(xvcmpgedp
, 2, float64
, VsrD(i
), le
, 1, 1)
2767 VSX_CMP(xvcmpgtdp
, 2, float64
, VsrD(i
), lt
, 1, 1)
2768 VSX_CMP(xvcmpnedp
, 2, float64
, VsrD(i
), eq
, 0, 0)
2769 VSX_CMP(xvcmpeqsp
, 4, float32
, VsrW(i
), eq
, 0, 1)
2770 VSX_CMP(xvcmpgesp
, 4, float32
, VsrW(i
), le
, 1, 1)
2771 VSX_CMP(xvcmpgtsp
, 4, float32
, VsrW(i
), lt
, 1, 1)
2772 VSX_CMP(xvcmpnesp
, 4, float32
, VsrW(i
), eq
, 0, 0)
2775 * VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2776 * op - instruction mnemonic
2777 * nels - number of elements (1, 2 or 4)
2778 * stp - source type (float32 or float64)
2779 * ttp - target type (float32 or float64)
2780 * sfld - source vsr_t field
2781 * tfld - target vsr_t field (f32 or f64)
2784 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2785 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2787 ppc_vsr_t t = *xt; \
2790 for (i = 0; i < nels; i++) { \
2791 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2792 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2793 &env->fp_status))) { \
2794 float_invalid_op_vxsnan(env, GETPC()); \
2795 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2798 helper_compute_fprf_##ttp(env, t.tfld); \
2803 do_float_check_status(env, GETPC()); \
2806 VSX_CVT_FP_TO_FP(xscvdpsp
, 1, float64
, float32
, VsrD(0), VsrW(0), 1)
2807 VSX_CVT_FP_TO_FP(xscvspdp
, 1, float32
, float64
, VsrW(0), VsrD(0), 1)
2808 VSX_CVT_FP_TO_FP(xvcvdpsp
, 2, float64
, float32
, VsrD(i
), VsrW(2 * i
), 0)
2809 VSX_CVT_FP_TO_FP(xvcvspdp
, 2, float32
, float64
, VsrW(2 * i
), VsrD(i
), 0)
2812 * VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2813 * op - instruction mnemonic
2814 * nels - number of elements (1, 2 or 4)
2815 * stp - source type (float32 or float64)
2816 * ttp - target type (float32 or float64)
2817 * sfld - source vsr_t field
2818 * tfld - target vsr_t field (f32 or f64)
2821 #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
2822 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2824 ppc_vsr_t *xt = &env->vsr[rD(opcode) + 32]; \
2825 ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32]; \
2826 ppc_vsr_t t = *xt; \
2829 for (i = 0; i < nels; i++) { \
2830 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2831 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2832 &env->fp_status))) { \
2833 float_invalid_op_vxsnan(env, GETPC()); \
2834 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2837 helper_compute_fprf_##ttp(env, t.tfld); \
2842 do_float_check_status(env, GETPC()); \
2845 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp
, 1, float64
, float128
, VsrD(0), f128
, 1)
2848 * VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2849 * involving one half precision value
2850 * op - instruction mnemonic
2851 * nels - number of elements (1, 2 or 4)
2854 * sfld - source vsr_t field
2855 * tfld - target vsr_t field
2858 #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2859 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2861 ppc_vsr_t t = { }; \
2864 for (i = 0; i < nels; i++) { \
2865 t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
2866 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2867 &env->fp_status))) { \
2868 float_invalid_op_vxsnan(env, GETPC()); \
2869 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2872 helper_compute_fprf_##ttp(env, t.tfld); \
2877 do_float_check_status(env, GETPC()); \
2880 VSX_CVT_FP_TO_FP_HP(xscvdphp
, 1, float64
, float16
, VsrD(0), VsrH(3), 1)
2881 VSX_CVT_FP_TO_FP_HP(xscvhpdp
, 1, float16
, float64
, VsrH(3), VsrD(0), 1)
2882 VSX_CVT_FP_TO_FP_HP(xvcvsphp
, 4, float32
, float16
, VsrW(i
), VsrH(2 * i
+ 1), 0)
2883 VSX_CVT_FP_TO_FP_HP(xvcvhpsp
, 4, float16
, float32
, VsrH(2 * i
+ 1), VsrW(i
), 0)
2886 * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2887 * added to this later.
2889 void helper_xscvqpdp(CPUPPCState
*env
, uint32_t opcode
,
2890 ppc_vsr_t
*xt
, ppc_vsr_t
*xb
)
2895 tstat
= env
->fp_status
;
2896 if (unlikely(Rc(opcode
) != 0)) {
2897 tstat
.float_rounding_mode
= float_round_to_odd
;
2900 t
.VsrD(0) = float128_to_float64(xb
->f128
, &tstat
);
2901 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
2902 if (unlikely(float128_is_signaling_nan(xb
->f128
, &tstat
))) {
2903 float_invalid_op_vxsnan(env
, GETPC());
2904 t
.VsrD(0) = float64_snan_to_qnan(t
.VsrD(0));
2906 helper_compute_fprf_float64(env
, t
.VsrD(0));
2909 do_float_check_status(env
, GETPC());
2912 uint64_t helper_xscvdpspn(CPUPPCState
*env
, uint64_t xb
)
2914 float_status tstat
= env
->fp_status
;
2915 set_float_exception_flags(0, &tstat
);
2917 return (uint64_t)float64_to_float32(xb
, &tstat
) << 32;
2920 uint64_t helper_xscvspdpn(CPUPPCState
*env
, uint64_t xb
)
2922 float_status tstat
= env
->fp_status
;
2923 set_float_exception_flags(0, &tstat
);
2925 return float32_to_float64(xb
>> 32, &tstat
);
2929 * VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2930 * op - instruction mnemonic
2931 * nels - number of elements (1, 2 or 4)
2932 * stp - source type (float32 or float64)
2933 * ttp - target type (int32, uint32, int64 or uint64)
2934 * sfld - source vsr_t field
2935 * tfld - target vsr_t field
2936 * rnan - resulting NaN
2938 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
2939 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2941 int all_flags = env->fp_status.float_exception_flags, flags; \
2942 ppc_vsr_t t = *xt; \
2945 for (i = 0; i < nels; i++) { \
2946 env->fp_status.float_exception_flags = 0; \
2947 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2948 flags = env->fp_status.float_exception_flags; \
2949 if (unlikely(flags & float_flag_invalid)) { \
2950 float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
2953 all_flags |= flags; \
2957 env->fp_status.float_exception_flags = all_flags; \
2958 do_float_check_status(env, GETPC()); \
2961 VSX_CVT_FP_TO_INT(xscvdpsxds
, 1, float64
, int64
, VsrD(0), VsrD(0), \
2962 0x8000000000000000ULL
)
2963 VSX_CVT_FP_TO_INT(xscvdpsxws
, 1, float64
, int32
, VsrD(0), VsrW(1), \
2965 VSX_CVT_FP_TO_INT(xscvdpuxds
, 1, float64
, uint64
, VsrD(0), VsrD(0), 0ULL)
2966 VSX_CVT_FP_TO_INT(xscvdpuxws
, 1, float64
, uint32
, VsrD(0), VsrW(1), 0U)
2967 VSX_CVT_FP_TO_INT(xvcvdpsxds
, 2, float64
, int64
, VsrD(i
), VsrD(i
), \
2968 0x8000000000000000ULL
)
2969 VSX_CVT_FP_TO_INT(xvcvdpsxws
, 2, float64
, int32
, VsrD(i
), VsrW(2 * i
), \
2971 VSX_CVT_FP_TO_INT(xvcvdpuxds
, 2, float64
, uint64
, VsrD(i
), VsrD(i
), 0ULL)
2972 VSX_CVT_FP_TO_INT(xvcvdpuxws
, 2, float64
, uint32
, VsrD(i
), VsrW(2 * i
), 0U)
2973 VSX_CVT_FP_TO_INT(xvcvspsxds
, 2, float32
, int64
, VsrW(2 * i
), VsrD(i
), \
2974 0x8000000000000000ULL
)
2975 VSX_CVT_FP_TO_INT(xvcvspsxws
, 4, float32
, int32
, VsrW(i
), VsrW(i
), 0x80000000U
)
2976 VSX_CVT_FP_TO_INT(xvcvspuxds
, 2, float32
, uint64
, VsrW(2 * i
), VsrD(i
), 0ULL)
2977 VSX_CVT_FP_TO_INT(xvcvspuxws
, 4, float32
, uint32
, VsrW(i
), VsrW(i
), 0U)
2980 * VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
2981 * op - instruction mnemonic
2982 * stp - source type (float32 or float64)
2983 * ttp - target type (int32, uint32, int64 or uint64)
2984 * sfld - source vsr_t field
2985 * tfld - target vsr_t field
2986 * rnan - resulting NaN
2988 #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
2989 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2991 ppc_vsr_t *xt = &env->vsr[rD(opcode) + 32]; \
2992 ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32]; \
2993 ppc_vsr_t t = { }; \
2995 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2996 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2997 float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
3002 do_float_check_status(env, GETPC()); \
3005 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz
, float128
, int64
, f128
, VsrD(0), \
3006 0x8000000000000000ULL
)
3008 VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz
, float128
, int32
, f128
, VsrD(0), \
3009 0xffffffff80000000ULL
)
3010 VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz
, float128
, uint64
, f128
, VsrD(0), 0x0ULL
)
3011 VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz
, float128
, uint32
, f128
, VsrD(0), 0x0ULL
)
3014 * VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
3015 * op - instruction mnemonic
3016 * nels - number of elements (1, 2 or 4)
3017 * stp - source type (int32, uint32, int64 or uint64)
3018 * ttp - target type (float32 or float64)
3019 * sfld - source vsr_t field
3020 * tfld - target vsr_t field
3021 * jdef - definition of the j index (i or 2*i)
3024 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
3025 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
3027 ppc_vsr_t t = *xt; \
3030 for (i = 0; i < nels; i++) { \
3031 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
3033 t.tfld = helper_frsp(env, t.tfld); \
3036 helper_compute_fprf_float64(env, t.tfld); \
3041 do_float_check_status(env, GETPC()); \
3044 VSX_CVT_INT_TO_FP(xscvsxddp
, 1, int64
, float64
, VsrD(0), VsrD(0), 1, 0)
3045 VSX_CVT_INT_TO_FP(xscvuxddp
, 1, uint64
, float64
, VsrD(0), VsrD(0), 1, 0)
3046 VSX_CVT_INT_TO_FP(xscvsxdsp
, 1, int64
, float64
, VsrD(0), VsrD(0), 1, 1)
3047 VSX_CVT_INT_TO_FP(xscvuxdsp
, 1, uint64
, float64
, VsrD(0), VsrD(0), 1, 1)
3048 VSX_CVT_INT_TO_FP(xvcvsxddp
, 2, int64
, float64
, VsrD(i
), VsrD(i
), 0, 0)
3049 VSX_CVT_INT_TO_FP(xvcvuxddp
, 2, uint64
, float64
, VsrD(i
), VsrD(i
), 0, 0)
3050 VSX_CVT_INT_TO_FP(xvcvsxwdp
, 2, int32
, float64
, VsrW(2 * i
), VsrD(i
), 0, 0)
3051 VSX_CVT_INT_TO_FP(xvcvuxwdp
, 2, uint64
, float64
, VsrW(2 * i
), VsrD(i
), 0, 0)
3052 VSX_CVT_INT_TO_FP(xvcvsxdsp
, 2, int64
, float32
, VsrD(i
), VsrW(2 * i
), 0, 0)
3053 VSX_CVT_INT_TO_FP(xvcvuxdsp
, 2, uint64
, float32
, VsrD(i
), VsrW(2 * i
), 0, 0)
3054 VSX_CVT_INT_TO_FP(xvcvsxwsp
, 4, int32
, float32
, VsrW(i
), VsrW(i
), 0, 0)
3055 VSX_CVT_INT_TO_FP(xvcvuxwsp
, 4, uint32
, float32
, VsrW(i
), VsrW(i
), 0, 0)
3058 * VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
3059 * op - instruction mnemonic
3060 * stp - source type (int32, uint32, int64 or uint64)
3061 * ttp - target type (float32 or float64)
3062 * sfld - source vsr_t field
3063 * tfld - target vsr_t field
3065 #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
3066 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3068 ppc_vsr_t *xt = &env->vsr[rD(opcode) + 32]; \
3069 ppc_vsr_t *xb = &env->vsr[rB(opcode) + 32]; \
3070 ppc_vsr_t t = *xt; \
3072 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
3073 helper_compute_fprf_##ttp(env, t.tfld); \
3076 do_float_check_status(env, GETPC()); \
3079 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp
, int64
, float128
, VsrD(0), f128
)
3080 VSX_CVT_INT_TO_FP_VECTOR(xscvudqp
, uint64
, float128
, VsrD(0), f128
)
3083 * For "use current rounding mode", define a value that will not be
3084 * one of the existing rounding model enums.
3086 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
3087 float_round_up + float_round_to_zero)
3090 * VSX_ROUND - VSX floating point round
3091 * op - instruction mnemonic
3092 * nels - number of elements (1, 2 or 4)
3093 * tp - type (float32 or float64)
3094 * fld - vsr_t field (VsrD(*) or VsrW(*))
3095 * rmode - rounding mode
3098 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
3099 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
3101 ppc_vsr_t t = *xt; \
3104 if (rmode != FLOAT_ROUND_CURRENT) { \
3105 set_float_rounding_mode(rmode, &env->fp_status); \
3108 for (i = 0; i < nels; i++) { \
3109 if (unlikely(tp##_is_signaling_nan(xb->fld, \
3110 &env->fp_status))) { \
3111 float_invalid_op_vxsnan(env, GETPC()); \
3112 t.fld = tp##_snan_to_qnan(xb->fld); \
3114 t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
3117 helper_compute_fprf_float64(env, t.fld); \
3122 * If this is not a "use current rounding mode" instruction, \
3123 * then inhibit setting of the XX bit and restore rounding \
3126 if (rmode != FLOAT_ROUND_CURRENT) { \
3127 fpscr_set_rounding_mode(env); \
3128 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
3132 do_float_check_status(env, GETPC()); \
3135 VSX_ROUND(xsrdpi
, 1, float64
, VsrD(0), float_round_ties_away
, 1)
3136 VSX_ROUND(xsrdpic
, 1, float64
, VsrD(0), FLOAT_ROUND_CURRENT
, 1)
3137 VSX_ROUND(xsrdpim
, 1, float64
, VsrD(0), float_round_down
, 1)
3138 VSX_ROUND(xsrdpip
, 1, float64
, VsrD(0), float_round_up
, 1)
3139 VSX_ROUND(xsrdpiz
, 1, float64
, VsrD(0), float_round_to_zero
, 1)
3141 VSX_ROUND(xvrdpi
, 2, float64
, VsrD(i
), float_round_ties_away
, 0)
3142 VSX_ROUND(xvrdpic
, 2, float64
, VsrD(i
), FLOAT_ROUND_CURRENT
, 0)
3143 VSX_ROUND(xvrdpim
, 2, float64
, VsrD(i
), float_round_down
, 0)
3144 VSX_ROUND(xvrdpip
, 2, float64
, VsrD(i
), float_round_up
, 0)
3145 VSX_ROUND(xvrdpiz
, 2, float64
, VsrD(i
), float_round_to_zero
, 0)
3147 VSX_ROUND(xvrspi
, 4, float32
, VsrW(i
), float_round_ties_away
, 0)
3148 VSX_ROUND(xvrspic
, 4, float32
, VsrW(i
), FLOAT_ROUND_CURRENT
, 0)
3149 VSX_ROUND(xvrspim
, 4, float32
, VsrW(i
), float_round_down
, 0)
3150 VSX_ROUND(xvrspip
, 4, float32
, VsrW(i
), float_round_up
, 0)
3151 VSX_ROUND(xvrspiz
, 4, float32
, VsrW(i
), float_round_to_zero
, 0)
3153 uint64_t helper_xsrsp(CPUPPCState
*env
, uint64_t xb
)
3155 helper_reset_fpstatus(env
);
3157 uint64_t xt
= helper_frsp(env
, xb
);
3159 helper_compute_fprf_float64(env
, xt
);
3160 do_float_check_status(env
, GETPC());
3164 #define VSX_XXPERM(op, indexed) \
3165 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
3166 ppc_vsr_t *xa, ppc_vsr_t *pcv) \
3168 ppc_vsr_t t = *xt; \
3171 for (i = 0; i < 16; i++) { \
3172 idx = pcv->VsrB(i) & 0x1F; \
3176 t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \
3177 : xt->VsrB(idx - 16); \
3182 VSX_XXPERM(xxperm
, 0)
3183 VSX_XXPERM(xxpermr
, 1)
3185 void helper_xvxsigsp(CPUPPCState
*env
, ppc_vsr_t
*xt
, ppc_vsr_t
*xb
)
3188 uint32_t exp
, i
, fraction
;
3190 for (i
= 0; i
< 4; i
++) {
3191 exp
= (xb
->VsrW(i
) >> 23) & 0xFF;
3192 fraction
= xb
->VsrW(i
) & 0x7FFFFF;
3193 if (exp
!= 0 && exp
!= 255) {
3194 t
.VsrW(i
) = fraction
| 0x00800000;
3196 t
.VsrW(i
) = fraction
;
3203 * VSX_TEST_DC - VSX floating point test data class
3204 * op - instruction mnemonic
3205 * nels - number of elements (1, 2 or 4)
3206 * xbn - VSR register number
3207 * tp - type (float32 or float64)
3208 * fld - vsr_t field (VsrD(*) or VsrW(*))
3209 * tfld - target vsr_t field (VsrD(*) or VsrW(*))
3210 * fld_max - target field max
3211 * scrf - set result in CR and FPCC
3213 #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
3214 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3216 ppc_vsr_t *xt = &env->vsr[xT(opcode)]; \
3217 ppc_vsr_t *xb = &env->vsr[xbn]; \
3218 ppc_vsr_t t = { }; \
3219 uint32_t i, sign, dcmx; \
3220 uint32_t cc, match = 0; \
3223 dcmx = DCMX_XV(opcode); \
3226 dcmx = DCMX(opcode); \
3229 for (i = 0; i < nels; i++) { \
3230 sign = tp##_is_neg(xb->fld); \
3231 if (tp##_is_any_nan(xb->fld)) { \
3232 match = extract32(dcmx, 6, 1); \
3233 } else if (tp##_is_infinity(xb->fld)) { \
3234 match = extract32(dcmx, 4 + !sign, 1); \
3235 } else if (tp##_is_zero(xb->fld)) { \
3236 match = extract32(dcmx, 2 + !sign, 1); \
3237 } else if (tp##_is_zero_or_denormal(xb->fld)) { \
3238 match = extract32(dcmx, 0 + !sign, 1); \
3242 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
3243 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
3244 env->fpscr |= cc << FPSCR_FPRF; \
3245 env->crf[BF(opcode)] = cc; \
3247 t.tfld = match ? fld_max : 0; \
3256 VSX_TEST_DC(xvtstdcdp
, 2, xB(opcode
), float64
, VsrD(i
), VsrD(i
), UINT64_MAX
, 0)
3257 VSX_TEST_DC(xvtstdcsp
, 4, xB(opcode
), float32
, VsrW(i
), VsrW(i
), UINT32_MAX
, 0)
3258 VSX_TEST_DC(xststdcdp
, 1, xB(opcode
), float64
, VsrD(0), VsrD(0), 0, 1)
3259 VSX_TEST_DC(xststdcqp
, 1, (rB(opcode
) + 32), float128
, f128
, VsrD(0), 0, 1)
3261 void helper_xststdcsp(CPUPPCState
*env
, uint32_t opcode
)
3263 ppc_vsr_t
*xb
= &env
->vsr
[xB(opcode
)];
3264 uint32_t dcmx
, sign
, exp
;
3265 uint32_t cc
, match
= 0, not_sp
= 0;
3267 dcmx
= DCMX(opcode
);
3268 exp
= (xb
->VsrD(0) >> 52) & 0x7FF;
3270 sign
= float64_is_neg(xb
->VsrD(0));
3271 if (float64_is_any_nan(xb
->VsrD(0))) {
3272 match
= extract32(dcmx
, 6, 1);
3273 } else if (float64_is_infinity(xb
->VsrD(0))) {
3274 match
= extract32(dcmx
, 4 + !sign
, 1);
3275 } else if (float64_is_zero(xb
->VsrD(0))) {
3276 match
= extract32(dcmx
, 2 + !sign
, 1);
3277 } else if (float64_is_zero_or_denormal(xb
->VsrD(0)) ||
3278 (exp
> 0 && exp
< 0x381)) {
3279 match
= extract32(dcmx
, 0 + !sign
, 1);
3282 not_sp
= !float64_eq(xb
->VsrD(0),
3284 float64_to_float32(xb
->VsrD(0), &env
->fp_status
),
3285 &env
->fp_status
), &env
->fp_status
);
3287 cc
= sign
<< CRF_LT_BIT
| match
<< CRF_EQ_BIT
| not_sp
<< CRF_SO_BIT
;
3288 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
3289 env
->fpscr
|= cc
<< FPSCR_FPRF
;
3290 env
->crf
[BF(opcode
)] = cc
;
3293 void helper_xsrqpi(CPUPPCState
*env
, uint32_t opcode
)
3295 ppc_vsr_t
*xt
= &env
->vsr
[rD(opcode
) + 32];
3296 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
3298 uint8_t r
= Rrm(opcode
);
3299 uint8_t ex
= Rc(opcode
);
3300 uint8_t rmc
= RMC(opcode
);
3304 helper_reset_fpstatus(env
);
3306 if (r
== 0 && rmc
== 0) {
3307 rmode
= float_round_ties_away
;
3308 } else if (r
== 0 && rmc
== 0x3) {
3310 } else if (r
== 1) {
3313 rmode
= float_round_nearest_even
;
3316 rmode
= float_round_to_zero
;
3319 rmode
= float_round_up
;
3322 rmode
= float_round_down
;
3329 tstat
= env
->fp_status
;
3330 set_float_exception_flags(0, &tstat
);
3331 set_float_rounding_mode(rmode
, &tstat
);
3332 t
.f128
= float128_round_to_int(xb
->f128
, &tstat
);
3333 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
3335 if (unlikely(tstat
.float_exception_flags
& float_flag_invalid
)) {
3336 if (float128_is_signaling_nan(xb
->f128
, &tstat
)) {
3337 float_invalid_op_vxsnan(env
, GETPC());
3338 t
.f128
= float128_snan_to_qnan(t
.f128
);
3342 if (ex
== 0 && (tstat
.float_exception_flags
& float_flag_inexact
)) {
3343 env
->fp_status
.float_exception_flags
&= ~float_flag_inexact
;
3346 helper_compute_fprf_float128(env
, t
.f128
);
3347 do_float_check_status(env
, GETPC());
3351 void helper_xsrqpxp(CPUPPCState
*env
, uint32_t opcode
)
3353 ppc_vsr_t
*xt
= &env
->vsr
[rD(opcode
) + 32];
3354 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
3356 uint8_t r
= Rrm(opcode
);
3357 uint8_t rmc
= RMC(opcode
);
3362 helper_reset_fpstatus(env
);
3364 if (r
== 0 && rmc
== 0) {
3365 rmode
= float_round_ties_away
;
3366 } else if (r
== 0 && rmc
== 0x3) {
3368 } else if (r
== 1) {
3371 rmode
= float_round_nearest_even
;
3374 rmode
= float_round_to_zero
;
3377 rmode
= float_round_up
;
3380 rmode
= float_round_down
;
3387 tstat
= env
->fp_status
;
3388 set_float_exception_flags(0, &tstat
);
3389 set_float_rounding_mode(rmode
, &tstat
);
3390 round_res
= float128_to_floatx80(xb
->f128
, &tstat
);
3391 t
.f128
= floatx80_to_float128(round_res
, &tstat
);
3392 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
3394 if (unlikely(tstat
.float_exception_flags
& float_flag_invalid
)) {
3395 if (float128_is_signaling_nan(xb
->f128
, &tstat
)) {
3396 float_invalid_op_vxsnan(env
, GETPC());
3397 t
.f128
= float128_snan_to_qnan(t
.f128
);
3401 helper_compute_fprf_float128(env
, t
.f128
);
3403 do_float_check_status(env
, GETPC());
3406 void helper_xssqrtqp(CPUPPCState
*env
, uint32_t opcode
)
3408 ppc_vsr_t
*xt
= &env
->vsr
[rD(opcode
) + 32];
3409 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
3413 helper_reset_fpstatus(env
);
3415 tstat
= env
->fp_status
;
3416 if (unlikely(Rc(opcode
) != 0)) {
3417 tstat
.float_rounding_mode
= float_round_to_odd
;
3420 set_float_exception_flags(0, &tstat
);
3421 t
.f128
= float128_sqrt(xb
->f128
, &tstat
);
3422 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
3424 if (unlikely(tstat
.float_exception_flags
& float_flag_invalid
)) {
3425 if (float128_is_signaling_nan(xb
->f128
, &tstat
)) {
3426 float_invalid_op_vxsnan(env
, GETPC());
3427 t
.f128
= float128_snan_to_qnan(xb
->f128
);
3428 } else if (float128_is_quiet_nan(xb
->f128
, &tstat
)) {
3430 } else if (float128_is_neg(xb
->f128
) && !float128_is_zero(xb
->f128
)) {
3431 float_invalid_op_vxsqrt(env
, 1, GETPC());
3432 t
.f128
= float128_default_nan(&env
->fp_status
);
3436 helper_compute_fprf_float128(env
, t
.f128
);
3438 do_float_check_status(env
, GETPC());
3441 void helper_xssubqp(CPUPPCState
*env
, uint32_t opcode
)
3443 ppc_vsr_t
*xt
= &env
->vsr
[rD(opcode
) + 32];
3444 ppc_vsr_t
*xa
= &env
->vsr
[rA(opcode
) + 32];
3445 ppc_vsr_t
*xb
= &env
->vsr
[rB(opcode
) + 32];
3449 helper_reset_fpstatus(env
);
3451 tstat
= env
->fp_status
;
3452 if (unlikely(Rc(opcode
) != 0)) {
3453 tstat
.float_rounding_mode
= float_round_to_odd
;
3456 set_float_exception_flags(0, &tstat
);
3457 t
.f128
= float128_sub(xa
->f128
, xb
->f128
, &tstat
);
3458 env
->fp_status
.float_exception_flags
|= tstat
.float_exception_flags
;
3460 if (unlikely(tstat
.float_exception_flags
& float_flag_invalid
)) {
3461 float_invalid_op_addsub(env
, 1, GETPC(),
3462 float128_classify(xa
->f128
) |
3463 float128_classify(xb
->f128
));
3466 helper_compute_fprf_float128(env
, t
.f128
);
3468 do_float_check_status(env
, GETPC());