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target/ppc: Split out float_invalid_op_mul
[mirror_qemu.git] / target / ppc / fpu_helper.c
1 /*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "internal.h"
24 #include "fpu/softfloat.h"
25
26 static inline float128 float128_snan_to_qnan(float128 x)
27 {
28 float128 r;
29
30 r.high = x.high | 0x0000800000000000;
31 r.low = x.low;
32 return r;
33 }
34
35 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37 #define float16_snan_to_qnan(x) ((x) | 0x0200)
38
39 static inline bool fp_exceptions_enabled(CPUPPCState *env)
40 {
41 #ifdef CONFIG_USER_ONLY
42 return true;
43 #else
44 return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
45 #endif
46 }
47
48 /*****************************************************************************/
49 /* Floating point operations helpers */
50
51 /*
52 * This is the non-arithmatic conversion that happens e.g. on loads.
53 * In the Power ISA pseudocode, this is called DOUBLE.
54 */
55 uint64_t helper_todouble(uint32_t arg)
56 {
57 uint32_t abs_arg = arg & 0x7fffffff;
58 uint64_t ret;
59
60 if (likely(abs_arg >= 0x00800000)) {
61 /* Normalized operand, or Inf, or NaN. */
62 ret = (uint64_t)extract32(arg, 30, 2) << 62;
63 ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
64 ret |= (uint64_t)extract32(arg, 0, 30) << 29;
65 } else {
66 /* Zero or Denormalized operand. */
67 ret = (uint64_t)extract32(arg, 31, 1) << 63;
68 if (unlikely(abs_arg != 0)) {
69 /* Denormalized operand. */
70 int shift = clz32(abs_arg) - 9;
71 int exp = -126 - shift + 1023;
72 ret |= (uint64_t)exp << 52;
73 ret |= abs_arg << (shift + 29);
74 }
75 }
76 return ret;
77 }
78
79 /*
80 * This is the non-arithmatic conversion that happens e.g. on stores.
81 * In the Power ISA pseudocode, this is called SINGLE.
82 */
83 uint32_t helper_tosingle(uint64_t arg)
84 {
85 int exp = extract64(arg, 52, 11);
86 uint32_t ret;
87
88 if (likely(exp > 896)) {
89 /* No denormalization required (includes Inf, NaN). */
90 ret = extract64(arg, 62, 2) << 30;
91 ret |= extract64(arg, 29, 30);
92 } else {
93 /* Zero or Denormal result. If the exponent is in bounds for
94 * a single-precision denormal result, extract the proper bits.
95 * If the input is not zero, and the exponent is out of bounds,
96 * then the result is undefined; this underflows to zero.
97 */
98 ret = extract64(arg, 63, 1) << 31;
99 if (unlikely(exp >= 874)) {
100 /* Denormal result. */
101 ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
102 }
103 }
104 return ret;
105 }
106
107 static inline int ppc_float32_get_unbiased_exp(float32 f)
108 {
109 return ((f >> 23) & 0xFF) - 127;
110 }
111
112 static inline int ppc_float64_get_unbiased_exp(float64 f)
113 {
114 return ((f >> 52) & 0x7FF) - 1023;
115 }
116
117 /* Classify a floating-point number. */
118 enum {
119 is_normal = 1,
120 is_zero = 2,
121 is_denormal = 4,
122 is_inf = 8,
123 is_qnan = 16,
124 is_snan = 32,
125 is_neg = 64,
126 };
127
128 #define COMPUTE_CLASS(tp) \
129 static int tp##_classify(tp arg) \
130 { \
131 int ret = tp##_is_neg(arg) * is_neg; \
132 if (unlikely(tp##_is_any_nan(arg))) { \
133 float_status dummy = { }; /* snan_bit_is_one = 0 */ \
134 ret |= (tp##_is_signaling_nan(arg, &dummy) \
135 ? is_snan : is_qnan); \
136 } else if (unlikely(tp##_is_infinity(arg))) { \
137 ret |= is_inf; \
138 } else if (tp##_is_zero(arg)) { \
139 ret |= is_zero; \
140 } else if (tp##_is_zero_or_denormal(arg)) { \
141 ret |= is_denormal; \
142 } else { \
143 ret |= is_normal; \
144 } \
145 return ret; \
146 }
147
148 COMPUTE_CLASS(float16)
149 COMPUTE_CLASS(float32)
150 COMPUTE_CLASS(float64)
151 COMPUTE_CLASS(float128)
152
153 static void set_fprf_from_class(CPUPPCState *env, int class)
154 {
155 static const uint8_t fprf[6][2] = {
156 { 0x04, 0x08 }, /* normalized */
157 { 0x02, 0x12 }, /* zero */
158 { 0x14, 0x18 }, /* denormalized */
159 { 0x05, 0x09 }, /* infinity */
160 { 0x11, 0x11 }, /* qnan */
161 { 0x00, 0x00 }, /* snan -- flags are undefined */
162 };
163 bool isneg = class & is_neg;
164
165 env->fpscr &= ~(0x1F << FPSCR_FPRF);
166 env->fpscr |= fprf[ctz32(class)][isneg] << FPSCR_FPRF;
167 }
168
169 #define COMPUTE_FPRF(tp) \
170 void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
171 { \
172 set_fprf_from_class(env, tp##_classify(arg)); \
173 }
174
175 COMPUTE_FPRF(float16)
176 COMPUTE_FPRF(float32)
177 COMPUTE_FPRF(float64)
178 COMPUTE_FPRF(float128)
179
180 /* Floating-point invalid operations exception */
181 static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
182 {
183 /* Update the floating-point invalid operation summary */
184 env->fpscr |= 1 << FPSCR_VX;
185 /* Update the floating-point exception summary */
186 env->fpscr |= FP_FX;
187 if (fpscr_ve != 0) {
188 /* Update the floating-point enabled exception summary */
189 env->fpscr |= 1 << FPSCR_FEX;
190 if (fp_exceptions_enabled(env)) {
191 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
192 POWERPC_EXCP_FP | op, retaddr);
193 }
194 }
195 }
196
197 static void finish_invalid_op_arith(CPUPPCState *env, int op,
198 bool set_fpcc, uintptr_t retaddr)
199 {
200 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
201 if (fpscr_ve == 0) {
202 if (set_fpcc) {
203 env->fpscr &= ~(0xF << FPSCR_FPCC);
204 env->fpscr |= 0x11 << FPSCR_FPCC;
205 }
206 }
207 finish_invalid_op_excp(env, op, retaddr);
208 }
209
210 /* Signalling NaN */
211 static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr)
212 {
213 env->fpscr |= 1 << FPSCR_VXSNAN;
214 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr);
215 }
216
217 /* Magnitude subtraction of infinities */
218 static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc,
219 uintptr_t retaddr)
220 {
221 env->fpscr |= 1 << FPSCR_VXISI;
222 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr);
223 }
224
225 /* Division of infinity by infinity */
226 static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc,
227 uintptr_t retaddr)
228 {
229 env->fpscr |= 1 << FPSCR_VXIDI;
230 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr);
231 }
232
233 /* Division of zero by zero */
234 static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc,
235 uintptr_t retaddr)
236 {
237 env->fpscr |= 1 << FPSCR_VXZDZ;
238 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr);
239 }
240
241 /* Multiplication of zero by infinity */
242 static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc,
243 uintptr_t retaddr)
244 {
245 env->fpscr |= 1 << FPSCR_VXIMZ;
246 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr);
247 }
248
249 /* Square root of a negative number */
250 static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc,
251 uintptr_t retaddr)
252 {
253 env->fpscr |= 1 << FPSCR_VXSQRT;
254 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr);
255 }
256
257 /* Ordered comparison of NaN */
258 static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
259 uintptr_t retaddr)
260 {
261 env->fpscr |= 1 << FPSCR_VXVC;
262 if (set_fpcc) {
263 env->fpscr &= ~(0xF << FPSCR_FPCC);
264 env->fpscr |= 0x11 << FPSCR_FPCC;
265 }
266 /* Update the floating-point invalid operation summary */
267 env->fpscr |= 1 << FPSCR_VX;
268 /* Update the floating-point exception summary */
269 env->fpscr |= FP_FX;
270 /* We must update the target FPR before raising the exception */
271 if (fpscr_ve != 0) {
272 CPUState *cs = CPU(ppc_env_get_cpu(env));
273
274 cs->exception_index = POWERPC_EXCP_PROGRAM;
275 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
276 /* Update the floating-point enabled exception summary */
277 env->fpscr |= 1 << FPSCR_FEX;
278 /* Exception is differed */
279 }
280 }
281
282 /* Invalid conversion */
283 static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
284 uintptr_t retaddr)
285 {
286 env->fpscr |= 1 << FPSCR_VXCVI;
287 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
288 if (fpscr_ve == 0) {
289 if (set_fpcc) {
290 env->fpscr &= ~(0xF << FPSCR_FPCC);
291 env->fpscr |= 0x11 << FPSCR_FPCC;
292 }
293 }
294 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr);
295 }
296
297 static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
298 {
299 env->fpscr |= 1 << FPSCR_ZX;
300 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
301 /* Update the floating-point exception summary */
302 env->fpscr |= FP_FX;
303 if (fpscr_ze != 0) {
304 /* Update the floating-point enabled exception summary */
305 env->fpscr |= 1 << FPSCR_FEX;
306 if (fp_exceptions_enabled(env)) {
307 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
308 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
309 raddr);
310 }
311 }
312 }
313
314 static inline void float_overflow_excp(CPUPPCState *env)
315 {
316 CPUState *cs = CPU(ppc_env_get_cpu(env));
317
318 env->fpscr |= 1 << FPSCR_OX;
319 /* Update the floating-point exception summary */
320 env->fpscr |= FP_FX;
321 if (fpscr_oe != 0) {
322 /* XXX: should adjust the result */
323 /* Update the floating-point enabled exception summary */
324 env->fpscr |= 1 << FPSCR_FEX;
325 /* We must update the target FPR before raising the exception */
326 cs->exception_index = POWERPC_EXCP_PROGRAM;
327 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
328 } else {
329 env->fpscr |= 1 << FPSCR_XX;
330 env->fpscr |= 1 << FPSCR_FI;
331 }
332 }
333
334 static inline void float_underflow_excp(CPUPPCState *env)
335 {
336 CPUState *cs = CPU(ppc_env_get_cpu(env));
337
338 env->fpscr |= 1 << FPSCR_UX;
339 /* Update the floating-point exception summary */
340 env->fpscr |= FP_FX;
341 if (fpscr_ue != 0) {
342 /* XXX: should adjust the result */
343 /* Update the floating-point enabled exception summary */
344 env->fpscr |= 1 << FPSCR_FEX;
345 /* We must update the target FPR before raising the exception */
346 cs->exception_index = POWERPC_EXCP_PROGRAM;
347 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
348 }
349 }
350
351 static inline void float_inexact_excp(CPUPPCState *env)
352 {
353 CPUState *cs = CPU(ppc_env_get_cpu(env));
354
355 env->fpscr |= 1 << FPSCR_FI;
356 env->fpscr |= 1 << FPSCR_XX;
357 /* Update the floating-point exception summary */
358 env->fpscr |= FP_FX;
359 if (fpscr_xe != 0) {
360 /* Update the floating-point enabled exception summary */
361 env->fpscr |= 1 << FPSCR_FEX;
362 /* We must update the target FPR before raising the exception */
363 cs->exception_index = POWERPC_EXCP_PROGRAM;
364 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
365 }
366 }
367
368 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
369 {
370 int rnd_type;
371
372 /* Set rounding mode */
373 switch (fpscr_rn) {
374 case 0:
375 /* Best approximation (round to nearest) */
376 rnd_type = float_round_nearest_even;
377 break;
378 case 1:
379 /* Smaller magnitude (round toward zero) */
380 rnd_type = float_round_to_zero;
381 break;
382 case 2:
383 /* Round toward +infinite */
384 rnd_type = float_round_up;
385 break;
386 default:
387 case 3:
388 /* Round toward -infinite */
389 rnd_type = float_round_down;
390 break;
391 }
392 set_float_rounding_mode(rnd_type, &env->fp_status);
393 }
394
395 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
396 {
397 int prev;
398
399 prev = (env->fpscr >> bit) & 1;
400 env->fpscr &= ~(1 << bit);
401 if (prev == 1) {
402 switch (bit) {
403 case FPSCR_RN1:
404 case FPSCR_RN:
405 fpscr_set_rounding_mode(env);
406 break;
407 case FPSCR_VXSNAN:
408 case FPSCR_VXISI:
409 case FPSCR_VXIDI:
410 case FPSCR_VXZDZ:
411 case FPSCR_VXIMZ:
412 case FPSCR_VXVC:
413 case FPSCR_VXSOFT:
414 case FPSCR_VXSQRT:
415 case FPSCR_VXCVI:
416 if (!fpscr_ix) {
417 /* Set VX bit to zero */
418 env->fpscr &= ~(1 << FPSCR_VX);
419 }
420 break;
421 case FPSCR_OX:
422 case FPSCR_UX:
423 case FPSCR_ZX:
424 case FPSCR_XX:
425 case FPSCR_VE:
426 case FPSCR_OE:
427 case FPSCR_UE:
428 case FPSCR_ZE:
429 case FPSCR_XE:
430 if (!fpscr_eex) {
431 /* Set the FEX bit */
432 env->fpscr &= ~(1 << FPSCR_FEX);
433 }
434 break;
435 default:
436 break;
437 }
438 }
439 }
440
441 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
442 {
443 CPUState *cs = CPU(ppc_env_get_cpu(env));
444 int prev;
445
446 prev = (env->fpscr >> bit) & 1;
447 env->fpscr |= 1 << bit;
448 if (prev == 0) {
449 switch (bit) {
450 case FPSCR_VX:
451 env->fpscr |= FP_FX;
452 if (fpscr_ve) {
453 goto raise_ve;
454 }
455 break;
456 case FPSCR_OX:
457 env->fpscr |= FP_FX;
458 if (fpscr_oe) {
459 goto raise_oe;
460 }
461 break;
462 case FPSCR_UX:
463 env->fpscr |= FP_FX;
464 if (fpscr_ue) {
465 goto raise_ue;
466 }
467 break;
468 case FPSCR_ZX:
469 env->fpscr |= FP_FX;
470 if (fpscr_ze) {
471 goto raise_ze;
472 }
473 break;
474 case FPSCR_XX:
475 env->fpscr |= FP_FX;
476 if (fpscr_xe) {
477 goto raise_xe;
478 }
479 break;
480 case FPSCR_VXSNAN:
481 case FPSCR_VXISI:
482 case FPSCR_VXIDI:
483 case FPSCR_VXZDZ:
484 case FPSCR_VXIMZ:
485 case FPSCR_VXVC:
486 case FPSCR_VXSOFT:
487 case FPSCR_VXSQRT:
488 case FPSCR_VXCVI:
489 env->fpscr |= 1 << FPSCR_VX;
490 env->fpscr |= FP_FX;
491 if (fpscr_ve != 0) {
492 goto raise_ve;
493 }
494 break;
495 case FPSCR_VE:
496 if (fpscr_vx != 0) {
497 raise_ve:
498 env->error_code = POWERPC_EXCP_FP;
499 if (fpscr_vxsnan) {
500 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
501 }
502 if (fpscr_vxisi) {
503 env->error_code |= POWERPC_EXCP_FP_VXISI;
504 }
505 if (fpscr_vxidi) {
506 env->error_code |= POWERPC_EXCP_FP_VXIDI;
507 }
508 if (fpscr_vxzdz) {
509 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
510 }
511 if (fpscr_vximz) {
512 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
513 }
514 if (fpscr_vxvc) {
515 env->error_code |= POWERPC_EXCP_FP_VXVC;
516 }
517 if (fpscr_vxsoft) {
518 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
519 }
520 if (fpscr_vxsqrt) {
521 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
522 }
523 if (fpscr_vxcvi) {
524 env->error_code |= POWERPC_EXCP_FP_VXCVI;
525 }
526 goto raise_excp;
527 }
528 break;
529 case FPSCR_OE:
530 if (fpscr_ox != 0) {
531 raise_oe:
532 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
533 goto raise_excp;
534 }
535 break;
536 case FPSCR_UE:
537 if (fpscr_ux != 0) {
538 raise_ue:
539 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
540 goto raise_excp;
541 }
542 break;
543 case FPSCR_ZE:
544 if (fpscr_zx != 0) {
545 raise_ze:
546 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
547 goto raise_excp;
548 }
549 break;
550 case FPSCR_XE:
551 if (fpscr_xx != 0) {
552 raise_xe:
553 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
554 goto raise_excp;
555 }
556 break;
557 case FPSCR_RN1:
558 case FPSCR_RN:
559 fpscr_set_rounding_mode(env);
560 break;
561 default:
562 break;
563 raise_excp:
564 /* Update the floating-point enabled exception summary */
565 env->fpscr |= 1 << FPSCR_FEX;
566 /* We have to update Rc1 before raising the exception */
567 cs->exception_index = POWERPC_EXCP_PROGRAM;
568 break;
569 }
570 }
571 }
572
573 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
574 {
575 CPUState *cs = CPU(ppc_env_get_cpu(env));
576 target_ulong prev, new;
577 int i;
578
579 prev = env->fpscr;
580 new = (target_ulong)arg;
581 new &= ~0x60000000LL;
582 new |= prev & 0x60000000LL;
583 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
584 if (mask & (1 << i)) {
585 env->fpscr &= ~(0xFLL << (4 * i));
586 env->fpscr |= new & (0xFLL << (4 * i));
587 }
588 }
589 /* Update VX and FEX */
590 if (fpscr_ix != 0) {
591 env->fpscr |= 1 << FPSCR_VX;
592 } else {
593 env->fpscr &= ~(1 << FPSCR_VX);
594 }
595 if ((fpscr_ex & fpscr_eex) != 0) {
596 env->fpscr |= 1 << FPSCR_FEX;
597 cs->exception_index = POWERPC_EXCP_PROGRAM;
598 /* XXX: we should compute it properly */
599 env->error_code = POWERPC_EXCP_FP;
600 } else {
601 env->fpscr &= ~(1 << FPSCR_FEX);
602 }
603 fpscr_set_rounding_mode(env);
604 }
605
606 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
607 {
608 helper_store_fpscr(env, arg, mask);
609 }
610
611 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
612 {
613 CPUState *cs = CPU(ppc_env_get_cpu(env));
614 int status = get_float_exception_flags(&env->fp_status);
615 bool inexact_happened = false;
616
617 if (status & float_flag_overflow) {
618 float_overflow_excp(env);
619 } else if (status & float_flag_underflow) {
620 float_underflow_excp(env);
621 } else if (status & float_flag_inexact) {
622 float_inexact_excp(env);
623 inexact_happened = true;
624 }
625
626 /* if the inexact flag was not set */
627 if (inexact_happened == false) {
628 env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
629 }
630
631 if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
632 (env->error_code & POWERPC_EXCP_FP)) {
633 /* Differred floating-point exception after target FPR update */
634 if (fp_exceptions_enabled(env)) {
635 raise_exception_err_ra(env, cs->exception_index,
636 env->error_code, raddr);
637 }
638 }
639 }
640
641 void helper_float_check_status(CPUPPCState *env)
642 {
643 do_float_check_status(env, GETPC());
644 }
645
646 void helper_reset_fpstatus(CPUPPCState *env)
647 {
648 set_float_exception_flags(0, &env->fp_status);
649 }
650
651 static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
652 uintptr_t retaddr, int classes)
653 {
654 if ((classes & ~is_neg) == is_inf) {
655 /* Magnitude subtraction of infinities */
656 float_invalid_op_vxisi(env, set_fpcc, retaddr);
657 } else if (classes & is_snan) {
658 float_invalid_op_vxsnan(env, retaddr);
659 }
660 }
661
662 /* fadd - fadd. */
663 float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
664 {
665 float64 ret = float64_add(arg1, arg2, &env->fp_status);
666 int status = get_float_exception_flags(&env->fp_status);
667
668 if (unlikely(status & float_flag_invalid)) {
669 float_invalid_op_addsub(env, 1, GETPC(),
670 float64_classify(arg1) |
671 float64_classify(arg2));
672 }
673
674 return ret;
675 }
676
677 /* fsub - fsub. */
678 float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
679 {
680 float64 ret = float64_sub(arg1, arg2, &env->fp_status);
681 int status = get_float_exception_flags(&env->fp_status);
682
683 if (unlikely(status & float_flag_invalid)) {
684 float_invalid_op_addsub(env, 1, GETPC(),
685 float64_classify(arg1) |
686 float64_classify(arg2));
687 }
688
689 return ret;
690 }
691
692 static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc,
693 uintptr_t retaddr, int classes)
694 {
695 if ((classes & (is_zero | is_inf)) == (is_zero | is_inf)) {
696 /* Multiplication of zero by infinity */
697 float_invalid_op_vximz(env, set_fprc, retaddr);
698 } else if (classes & is_snan) {
699 float_invalid_op_vxsnan(env, retaddr);
700 }
701 }
702
703 /* fmul - fmul. */
704 float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
705 {
706 float64 ret = float64_mul(arg1, arg2, &env->fp_status);
707 int status = get_float_exception_flags(&env->fp_status);
708
709 if (unlikely(status & float_flag_invalid)) {
710 float_invalid_op_mul(env, 1, GETPC(),
711 float64_classify(arg1) |
712 float64_classify(arg2));
713 }
714
715 return ret;
716 }
717
718 /* fdiv - fdiv. */
719 float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
720 {
721 float64 ret = float64_div(arg1, arg2, &env->fp_status);
722 int status = get_float_exception_flags(&env->fp_status);
723
724 if (unlikely(status)) {
725 if (status & float_flag_invalid) {
726 /* Determine what kind of invalid operation was seen. */
727 if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) {
728 /* Division of infinity by infinity */
729 float_invalid_op_vxidi(env, 1, GETPC());
730 } else if (float64_is_zero(arg1) && float64_is_zero(arg2)) {
731 /* Division of zero by zero */
732 float_invalid_op_vxzdz(env, 1, GETPC());
733 } else if (float64_is_signaling_nan(arg1, &env->fp_status) ||
734 float64_is_signaling_nan(arg2, &env->fp_status)) {
735 /* sNaN division */
736 float_invalid_op_vxsnan(env, GETPC());
737 }
738 }
739 if (status & float_flag_divbyzero) {
740 float_zero_divide_excp(env, GETPC());
741 }
742 }
743
744 return ret;
745 }
746
747
748 #define FPU_FCTI(op, cvt, nanval) \
749 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
750 { \
751 CPU_DoubleU farg; \
752 \
753 farg.ll = arg; \
754 farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
755 \
756 if (unlikely(env->fp_status.float_exception_flags)) { \
757 if (float64_is_any_nan(arg)) { \
758 float_invalid_op_vxcvi(env, 1, GETPC()); \
759 if (float64_is_signaling_nan(arg, &env->fp_status)) { \
760 float_invalid_op_vxsnan(env, GETPC()); \
761 } \
762 farg.ll = nanval; \
763 } else if (env->fp_status.float_exception_flags & \
764 float_flag_invalid) { \
765 float_invalid_op_vxcvi(env, 1, GETPC()); \
766 } \
767 do_float_check_status(env, GETPC()); \
768 } \
769 return farg.ll; \
770 }
771
772 FPU_FCTI(fctiw, int32, 0x80000000U)
773 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
774 FPU_FCTI(fctiwu, uint32, 0x00000000U)
775 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
776 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
777 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
778 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
779 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
780
781 #define FPU_FCFI(op, cvtr, is_single) \
782 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
783 { \
784 CPU_DoubleU farg; \
785 \
786 if (is_single) { \
787 float32 tmp = cvtr(arg, &env->fp_status); \
788 farg.d = float32_to_float64(tmp, &env->fp_status); \
789 } else { \
790 farg.d = cvtr(arg, &env->fp_status); \
791 } \
792 do_float_check_status(env, GETPC()); \
793 return farg.ll; \
794 }
795
796 FPU_FCFI(fcfid, int64_to_float64, 0)
797 FPU_FCFI(fcfids, int64_to_float32, 1)
798 FPU_FCFI(fcfidu, uint64_to_float64, 0)
799 FPU_FCFI(fcfidus, uint64_to_float32, 1)
800
801 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
802 int rounding_mode)
803 {
804 CPU_DoubleU farg;
805
806 farg.ll = arg;
807
808 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
809 /* sNaN round */
810 float_invalid_op_vxsnan(env, GETPC());
811 farg.ll = arg | 0x0008000000000000ULL;
812 } else {
813 int inexact = get_float_exception_flags(&env->fp_status) &
814 float_flag_inexact;
815 set_float_rounding_mode(rounding_mode, &env->fp_status);
816 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
817 /* Restore rounding mode from FPSCR */
818 fpscr_set_rounding_mode(env);
819
820 /* fri* does not set FPSCR[XX] */
821 if (!inexact) {
822 env->fp_status.float_exception_flags &= ~float_flag_inexact;
823 }
824 }
825 do_float_check_status(env, GETPC());
826 return farg.ll;
827 }
828
829 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
830 {
831 return do_fri(env, arg, float_round_ties_away);
832 }
833
834 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
835 {
836 return do_fri(env, arg, float_round_to_zero);
837 }
838
839 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
840 {
841 return do_fri(env, arg, float_round_up);
842 }
843
844 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
845 {
846 return do_fri(env, arg, float_round_down);
847 }
848
849 #define FPU_MADDSUB_UPDATE(NAME, TP) \
850 static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \
851 unsigned int madd_flags, uintptr_t retaddr) \
852 { \
853 if (TP##_is_signaling_nan(arg1, &env->fp_status) || \
854 TP##_is_signaling_nan(arg2, &env->fp_status) || \
855 TP##_is_signaling_nan(arg3, &env->fp_status)) { \
856 /* sNaN operation */ \
857 float_invalid_op_vxsnan(env, retaddr); \
858 } \
859 if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \
860 (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \
861 /* Multiplication of zero by infinity */ \
862 float_invalid_op_vximz(env, 1, retaddr); \
863 } \
864 if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \
865 TP##_is_infinity(arg3)) { \
866 uint8_t aSign, bSign, cSign; \
867 \
868 aSign = TP##_is_neg(arg1); \
869 bSign = TP##_is_neg(arg2); \
870 cSign = TP##_is_neg(arg3); \
871 if (madd_flags & float_muladd_negate_c) { \
872 cSign ^= 1; \
873 } \
874 if (aSign ^ bSign ^ cSign) { \
875 float_invalid_op_vxisi(env, 1, retaddr); \
876 } \
877 } \
878 }
879 FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32)
880 FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64)
881
882 #define FPU_FMADD(op, madd_flags) \
883 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
884 uint64_t arg2, uint64_t arg3) \
885 { \
886 uint32_t flags; \
887 float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \
888 &env->fp_status); \
889 flags = get_float_exception_flags(&env->fp_status); \
890 if (flags) { \
891 if (flags & float_flag_invalid) { \
892 float64_maddsub_update_excp(env, arg1, arg2, arg3, \
893 madd_flags, GETPC()); \
894 } \
895 do_float_check_status(env, GETPC()); \
896 } \
897 return ret; \
898 }
899
900 #define MADD_FLGS 0
901 #define MSUB_FLGS float_muladd_negate_c
902 #define NMADD_FLGS float_muladd_negate_result
903 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
904
905 FPU_FMADD(fmadd, MADD_FLGS)
906 FPU_FMADD(fnmadd, NMADD_FLGS)
907 FPU_FMADD(fmsub, MSUB_FLGS)
908 FPU_FMADD(fnmsub, NMSUB_FLGS)
909
910 /* frsp - frsp. */
911 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
912 {
913 CPU_DoubleU farg;
914 float32 f32;
915
916 farg.ll = arg;
917
918 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
919 float_invalid_op_vxsnan(env, GETPC());
920 }
921 f32 = float64_to_float32(farg.d, &env->fp_status);
922 farg.d = float32_to_float64(f32, &env->fp_status);
923
924 return farg.ll;
925 }
926
927 /* fsqrt - fsqrt. */
928 float64 helper_fsqrt(CPUPPCState *env, float64 arg)
929 {
930 float64 ret = float64_sqrt(arg, &env->fp_status);
931 int status = get_float_exception_flags(&env->fp_status);
932
933 if (unlikely(status & float_flag_invalid)) {
934 if (unlikely(float64_is_any_nan(arg))) {
935 if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) {
936 /* sNaN square root */
937 float_invalid_op_vxsnan(env, GETPC());
938 }
939 } else {
940 /* Square root of a negative nonzero number */
941 float_invalid_op_vxsqrt(env, 1, GETPC());
942 }
943 }
944
945 return ret;
946 }
947
948 /* fre - fre. */
949 float64 helper_fre(CPUPPCState *env, float64 arg)
950 {
951 /* "Estimate" the reciprocal with actual division. */
952 float64 ret = float64_div(float64_one, arg, &env->fp_status);
953 int status = get_float_exception_flags(&env->fp_status);
954
955 if (unlikely(status)) {
956 if (status & float_flag_invalid) {
957 if (float64_is_signaling_nan(arg, &env->fp_status)) {
958 /* sNaN reciprocal */
959 float_invalid_op_vxsnan(env, GETPC());
960 }
961 }
962 if (status & float_flag_divbyzero) {
963 float_zero_divide_excp(env, GETPC());
964 /* For FPSCR.ZE == 0, the result is 1/2. */
965 ret = float64_set_sign(float64_half, float64_is_neg(arg));
966 }
967 }
968
969 return ret;
970 }
971
972 /* fres - fres. */
973 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
974 {
975 CPU_DoubleU farg;
976 float32 f32;
977
978 farg.ll = arg;
979
980 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
981 /* sNaN reciprocal */
982 float_invalid_op_vxsnan(env, GETPC());
983 }
984 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
985 f32 = float64_to_float32(farg.d, &env->fp_status);
986 farg.d = float32_to_float64(f32, &env->fp_status);
987
988 return farg.ll;
989 }
990
991 /* frsqrte - frsqrte. */
992 float64 helper_frsqrte(CPUPPCState *env, float64 arg)
993 {
994 /* "Estimate" the reciprocal with actual division. */
995 float64 rets = float64_sqrt(arg, &env->fp_status);
996 float64 retd = float64_div(float64_one, rets, &env->fp_status);
997 int status = get_float_exception_flags(&env->fp_status);
998
999 if (unlikely(status)) {
1000 if (status & float_flag_invalid) {
1001 if (float64_is_signaling_nan(arg, &env->fp_status)) {
1002 /* sNaN reciprocal */
1003 float_invalid_op_vxsnan(env, GETPC());
1004 } else {
1005 /* Square root of a negative nonzero number */
1006 float_invalid_op_vxsqrt(env, 1, GETPC());
1007 }
1008 }
1009 if (status & float_flag_divbyzero) {
1010 /* Reciprocal of (square root of) zero. */
1011 float_zero_divide_excp(env, GETPC());
1012 }
1013 }
1014
1015 return retd;
1016 }
1017
1018 /* fsel - fsel. */
1019 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1020 uint64_t arg3)
1021 {
1022 CPU_DoubleU farg1;
1023
1024 farg1.ll = arg1;
1025
1026 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
1027 !float64_is_any_nan(farg1.d)) {
1028 return arg2;
1029 } else {
1030 return arg3;
1031 }
1032 }
1033
1034 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
1035 {
1036 int fe_flag = 0;
1037 int fg_flag = 0;
1038
1039 if (unlikely(float64_is_infinity(fra) ||
1040 float64_is_infinity(frb) ||
1041 float64_is_zero(frb))) {
1042 fe_flag = 1;
1043 fg_flag = 1;
1044 } else {
1045 int e_a = ppc_float64_get_unbiased_exp(fra);
1046 int e_b = ppc_float64_get_unbiased_exp(frb);
1047
1048 if (unlikely(float64_is_any_nan(fra) ||
1049 float64_is_any_nan(frb))) {
1050 fe_flag = 1;
1051 } else if ((e_b <= -1022) || (e_b >= 1021)) {
1052 fe_flag = 1;
1053 } else if (!float64_is_zero(fra) &&
1054 (((e_a - e_b) >= 1023) ||
1055 ((e_a - e_b) <= -1021) ||
1056 (e_a <= -970))) {
1057 fe_flag = 1;
1058 }
1059
1060 if (unlikely(float64_is_zero_or_denormal(frb))) {
1061 /* XB is not zero because of the above check and */
1062 /* so must be denormalized. */
1063 fg_flag = 1;
1064 }
1065 }
1066
1067 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1068 }
1069
1070 uint32_t helper_ftsqrt(uint64_t frb)
1071 {
1072 int fe_flag = 0;
1073 int fg_flag = 0;
1074
1075 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
1076 fe_flag = 1;
1077 fg_flag = 1;
1078 } else {
1079 int e_b = ppc_float64_get_unbiased_exp(frb);
1080
1081 if (unlikely(float64_is_any_nan(frb))) {
1082 fe_flag = 1;
1083 } else if (unlikely(float64_is_zero(frb))) {
1084 fe_flag = 1;
1085 } else if (unlikely(float64_is_neg(frb))) {
1086 fe_flag = 1;
1087 } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
1088 fe_flag = 1;
1089 }
1090
1091 if (unlikely(float64_is_zero_or_denormal(frb))) {
1092 /* XB is not zero because of the above check and */
1093 /* therefore must be denormalized. */
1094 fg_flag = 1;
1095 }
1096 }
1097
1098 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1099 }
1100
1101 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1102 uint32_t crfD)
1103 {
1104 CPU_DoubleU farg1, farg2;
1105 uint32_t ret = 0;
1106
1107 farg1.ll = arg1;
1108 farg2.ll = arg2;
1109
1110 if (unlikely(float64_is_any_nan(farg1.d) ||
1111 float64_is_any_nan(farg2.d))) {
1112 ret = 0x01UL;
1113 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1114 ret = 0x08UL;
1115 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1116 ret = 0x04UL;
1117 } else {
1118 ret = 0x02UL;
1119 }
1120
1121 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1122 env->fpscr |= ret << FPSCR_FPRF;
1123 env->crf[crfD] = ret;
1124 if (unlikely(ret == 0x01UL
1125 && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
1126 float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
1127 /* sNaN comparison */
1128 float_invalid_op_vxsnan(env, GETPC());
1129 }
1130 }
1131
1132 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1133 uint32_t crfD)
1134 {
1135 CPU_DoubleU farg1, farg2;
1136 uint32_t ret = 0;
1137
1138 farg1.ll = arg1;
1139 farg2.ll = arg2;
1140
1141 if (unlikely(float64_is_any_nan(farg1.d) ||
1142 float64_is_any_nan(farg2.d))) {
1143 ret = 0x01UL;
1144 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1145 ret = 0x08UL;
1146 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1147 ret = 0x04UL;
1148 } else {
1149 ret = 0x02UL;
1150 }
1151
1152 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1153 env->fpscr |= ret << FPSCR_FPRF;
1154 env->crf[crfD] = ret;
1155 if (unlikely(ret == 0x01UL)) {
1156 float_invalid_op_vxvc(env, 1, GETPC());
1157 if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
1158 float64_is_signaling_nan(farg2.d, &env->fp_status)) {
1159 /* sNaN comparison */
1160 float_invalid_op_vxsnan(env, GETPC());
1161 }
1162 }
1163 }
1164
1165 /* Single-precision floating-point conversions */
1166 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
1167 {
1168 CPU_FloatU u;
1169
1170 u.f = int32_to_float32(val, &env->vec_status);
1171
1172 return u.l;
1173 }
1174
1175 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
1176 {
1177 CPU_FloatU u;
1178
1179 u.f = uint32_to_float32(val, &env->vec_status);
1180
1181 return u.l;
1182 }
1183
1184 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1185 {
1186 CPU_FloatU u;
1187
1188 u.l = val;
1189 /* NaN are not treated the same way IEEE 754 does */
1190 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1191 return 0;
1192 }
1193
1194 return float32_to_int32(u.f, &env->vec_status);
1195 }
1196
1197 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1198 {
1199 CPU_FloatU u;
1200
1201 u.l = val;
1202 /* NaN are not treated the same way IEEE 754 does */
1203 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1204 return 0;
1205 }
1206
1207 return float32_to_uint32(u.f, &env->vec_status);
1208 }
1209
1210 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1211 {
1212 CPU_FloatU u;
1213
1214 u.l = val;
1215 /* NaN are not treated the same way IEEE 754 does */
1216 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1217 return 0;
1218 }
1219
1220 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1221 }
1222
1223 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1224 {
1225 CPU_FloatU u;
1226
1227 u.l = val;
1228 /* NaN are not treated the same way IEEE 754 does */
1229 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1230 return 0;
1231 }
1232
1233 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1234 }
1235
1236 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1237 {
1238 CPU_FloatU u;
1239 float32 tmp;
1240
1241 u.f = int32_to_float32(val, &env->vec_status);
1242 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1243 u.f = float32_div(u.f, tmp, &env->vec_status);
1244
1245 return u.l;
1246 }
1247
1248 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1249 {
1250 CPU_FloatU u;
1251 float32 tmp;
1252
1253 u.f = uint32_to_float32(val, &env->vec_status);
1254 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1255 u.f = float32_div(u.f, tmp, &env->vec_status);
1256
1257 return u.l;
1258 }
1259
1260 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1261 {
1262 CPU_FloatU u;
1263 float32 tmp;
1264
1265 u.l = val;
1266 /* NaN are not treated the same way IEEE 754 does */
1267 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1268 return 0;
1269 }
1270 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1271 u.f = float32_mul(u.f, tmp, &env->vec_status);
1272
1273 return float32_to_int32(u.f, &env->vec_status);
1274 }
1275
1276 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1277 {
1278 CPU_FloatU u;
1279 float32 tmp;
1280
1281 u.l = val;
1282 /* NaN are not treated the same way IEEE 754 does */
1283 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1284 return 0;
1285 }
1286 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1287 u.f = float32_mul(u.f, tmp, &env->vec_status);
1288
1289 return float32_to_uint32(u.f, &env->vec_status);
1290 }
1291
1292 #define HELPER_SPE_SINGLE_CONV(name) \
1293 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1294 { \
1295 return e##name(env, val); \
1296 }
1297 /* efscfsi */
1298 HELPER_SPE_SINGLE_CONV(fscfsi);
1299 /* efscfui */
1300 HELPER_SPE_SINGLE_CONV(fscfui);
1301 /* efscfuf */
1302 HELPER_SPE_SINGLE_CONV(fscfuf);
1303 /* efscfsf */
1304 HELPER_SPE_SINGLE_CONV(fscfsf);
1305 /* efsctsi */
1306 HELPER_SPE_SINGLE_CONV(fsctsi);
1307 /* efsctui */
1308 HELPER_SPE_SINGLE_CONV(fsctui);
1309 /* efsctsiz */
1310 HELPER_SPE_SINGLE_CONV(fsctsiz);
1311 /* efsctuiz */
1312 HELPER_SPE_SINGLE_CONV(fsctuiz);
1313 /* efsctsf */
1314 HELPER_SPE_SINGLE_CONV(fsctsf);
1315 /* efsctuf */
1316 HELPER_SPE_SINGLE_CONV(fsctuf);
1317
1318 #define HELPER_SPE_VECTOR_CONV(name) \
1319 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1320 { \
1321 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1322 (uint64_t)e##name(env, val); \
1323 }
1324 /* evfscfsi */
1325 HELPER_SPE_VECTOR_CONV(fscfsi);
1326 /* evfscfui */
1327 HELPER_SPE_VECTOR_CONV(fscfui);
1328 /* evfscfuf */
1329 HELPER_SPE_VECTOR_CONV(fscfuf);
1330 /* evfscfsf */
1331 HELPER_SPE_VECTOR_CONV(fscfsf);
1332 /* evfsctsi */
1333 HELPER_SPE_VECTOR_CONV(fsctsi);
1334 /* evfsctui */
1335 HELPER_SPE_VECTOR_CONV(fsctui);
1336 /* evfsctsiz */
1337 HELPER_SPE_VECTOR_CONV(fsctsiz);
1338 /* evfsctuiz */
1339 HELPER_SPE_VECTOR_CONV(fsctuiz);
1340 /* evfsctsf */
1341 HELPER_SPE_VECTOR_CONV(fsctsf);
1342 /* evfsctuf */
1343 HELPER_SPE_VECTOR_CONV(fsctuf);
1344
1345 /* Single-precision floating-point arithmetic */
1346 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1347 {
1348 CPU_FloatU u1, u2;
1349
1350 u1.l = op1;
1351 u2.l = op2;
1352 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1353 return u1.l;
1354 }
1355
1356 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1357 {
1358 CPU_FloatU u1, u2;
1359
1360 u1.l = op1;
1361 u2.l = op2;
1362 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1363 return u1.l;
1364 }
1365
1366 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1367 {
1368 CPU_FloatU u1, u2;
1369
1370 u1.l = op1;
1371 u2.l = op2;
1372 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1373 return u1.l;
1374 }
1375
1376 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1377 {
1378 CPU_FloatU u1, u2;
1379
1380 u1.l = op1;
1381 u2.l = op2;
1382 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1383 return u1.l;
1384 }
1385
1386 #define HELPER_SPE_SINGLE_ARITH(name) \
1387 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1388 { \
1389 return e##name(env, op1, op2); \
1390 }
1391 /* efsadd */
1392 HELPER_SPE_SINGLE_ARITH(fsadd);
1393 /* efssub */
1394 HELPER_SPE_SINGLE_ARITH(fssub);
1395 /* efsmul */
1396 HELPER_SPE_SINGLE_ARITH(fsmul);
1397 /* efsdiv */
1398 HELPER_SPE_SINGLE_ARITH(fsdiv);
1399
1400 #define HELPER_SPE_VECTOR_ARITH(name) \
1401 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1402 { \
1403 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1404 (uint64_t)e##name(env, op1, op2); \
1405 }
1406 /* evfsadd */
1407 HELPER_SPE_VECTOR_ARITH(fsadd);
1408 /* evfssub */
1409 HELPER_SPE_VECTOR_ARITH(fssub);
1410 /* evfsmul */
1411 HELPER_SPE_VECTOR_ARITH(fsmul);
1412 /* evfsdiv */
1413 HELPER_SPE_VECTOR_ARITH(fsdiv);
1414
1415 /* Single-precision floating-point comparisons */
1416 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1417 {
1418 CPU_FloatU u1, u2;
1419
1420 u1.l = op1;
1421 u2.l = op2;
1422 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1423 }
1424
1425 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1426 {
1427 CPU_FloatU u1, u2;
1428
1429 u1.l = op1;
1430 u2.l = op2;
1431 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1432 }
1433
1434 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1435 {
1436 CPU_FloatU u1, u2;
1437
1438 u1.l = op1;
1439 u2.l = op2;
1440 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1441 }
1442
1443 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1444 {
1445 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1446 return efscmplt(env, op1, op2);
1447 }
1448
1449 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1450 {
1451 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1452 return efscmpgt(env, op1, op2);
1453 }
1454
1455 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1456 {
1457 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1458 return efscmpeq(env, op1, op2);
1459 }
1460
1461 #define HELPER_SINGLE_SPE_CMP(name) \
1462 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1463 { \
1464 return e##name(env, op1, op2); \
1465 }
1466 /* efststlt */
1467 HELPER_SINGLE_SPE_CMP(fststlt);
1468 /* efststgt */
1469 HELPER_SINGLE_SPE_CMP(fststgt);
1470 /* efststeq */
1471 HELPER_SINGLE_SPE_CMP(fststeq);
1472 /* efscmplt */
1473 HELPER_SINGLE_SPE_CMP(fscmplt);
1474 /* efscmpgt */
1475 HELPER_SINGLE_SPE_CMP(fscmpgt);
1476 /* efscmpeq */
1477 HELPER_SINGLE_SPE_CMP(fscmpeq);
1478
1479 static inline uint32_t evcmp_merge(int t0, int t1)
1480 {
1481 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1482 }
1483
1484 #define HELPER_VECTOR_SPE_CMP(name) \
1485 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1486 { \
1487 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1488 e##name(env, op1, op2)); \
1489 }
1490 /* evfststlt */
1491 HELPER_VECTOR_SPE_CMP(fststlt);
1492 /* evfststgt */
1493 HELPER_VECTOR_SPE_CMP(fststgt);
1494 /* evfststeq */
1495 HELPER_VECTOR_SPE_CMP(fststeq);
1496 /* evfscmplt */
1497 HELPER_VECTOR_SPE_CMP(fscmplt);
1498 /* evfscmpgt */
1499 HELPER_VECTOR_SPE_CMP(fscmpgt);
1500 /* evfscmpeq */
1501 HELPER_VECTOR_SPE_CMP(fscmpeq);
1502
1503 /* Double-precision floating-point conversion */
1504 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1505 {
1506 CPU_DoubleU u;
1507
1508 u.d = int32_to_float64(val, &env->vec_status);
1509
1510 return u.ll;
1511 }
1512
1513 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1514 {
1515 CPU_DoubleU u;
1516
1517 u.d = int64_to_float64(val, &env->vec_status);
1518
1519 return u.ll;
1520 }
1521
1522 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1523 {
1524 CPU_DoubleU u;
1525
1526 u.d = uint32_to_float64(val, &env->vec_status);
1527
1528 return u.ll;
1529 }
1530
1531 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1532 {
1533 CPU_DoubleU u;
1534
1535 u.d = uint64_to_float64(val, &env->vec_status);
1536
1537 return u.ll;
1538 }
1539
1540 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1541 {
1542 CPU_DoubleU u;
1543
1544 u.ll = val;
1545 /* NaN are not treated the same way IEEE 754 does */
1546 if (unlikely(float64_is_any_nan(u.d))) {
1547 return 0;
1548 }
1549
1550 return float64_to_int32(u.d, &env->vec_status);
1551 }
1552
1553 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1554 {
1555 CPU_DoubleU u;
1556
1557 u.ll = val;
1558 /* NaN are not treated the same way IEEE 754 does */
1559 if (unlikely(float64_is_any_nan(u.d))) {
1560 return 0;
1561 }
1562
1563 return float64_to_uint32(u.d, &env->vec_status);
1564 }
1565
1566 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1567 {
1568 CPU_DoubleU u;
1569
1570 u.ll = val;
1571 /* NaN are not treated the same way IEEE 754 does */
1572 if (unlikely(float64_is_any_nan(u.d))) {
1573 return 0;
1574 }
1575
1576 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1577 }
1578
1579 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1580 {
1581 CPU_DoubleU u;
1582
1583 u.ll = val;
1584 /* NaN are not treated the same way IEEE 754 does */
1585 if (unlikely(float64_is_any_nan(u.d))) {
1586 return 0;
1587 }
1588
1589 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1590 }
1591
1592 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1593 {
1594 CPU_DoubleU u;
1595
1596 u.ll = val;
1597 /* NaN are not treated the same way IEEE 754 does */
1598 if (unlikely(float64_is_any_nan(u.d))) {
1599 return 0;
1600 }
1601
1602 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1603 }
1604
1605 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1606 {
1607 CPU_DoubleU u;
1608
1609 u.ll = val;
1610 /* NaN are not treated the same way IEEE 754 does */
1611 if (unlikely(float64_is_any_nan(u.d))) {
1612 return 0;
1613 }
1614
1615 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1616 }
1617
1618 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1619 {
1620 CPU_DoubleU u;
1621 float64 tmp;
1622
1623 u.d = int32_to_float64(val, &env->vec_status);
1624 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1625 u.d = float64_div(u.d, tmp, &env->vec_status);
1626
1627 return u.ll;
1628 }
1629
1630 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1631 {
1632 CPU_DoubleU u;
1633 float64 tmp;
1634
1635 u.d = uint32_to_float64(val, &env->vec_status);
1636 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1637 u.d = float64_div(u.d, tmp, &env->vec_status);
1638
1639 return u.ll;
1640 }
1641
1642 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1643 {
1644 CPU_DoubleU u;
1645 float64 tmp;
1646
1647 u.ll = val;
1648 /* NaN are not treated the same way IEEE 754 does */
1649 if (unlikely(float64_is_any_nan(u.d))) {
1650 return 0;
1651 }
1652 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1653 u.d = float64_mul(u.d, tmp, &env->vec_status);
1654
1655 return float64_to_int32(u.d, &env->vec_status);
1656 }
1657
1658 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1659 {
1660 CPU_DoubleU u;
1661 float64 tmp;
1662
1663 u.ll = val;
1664 /* NaN are not treated the same way IEEE 754 does */
1665 if (unlikely(float64_is_any_nan(u.d))) {
1666 return 0;
1667 }
1668 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1669 u.d = float64_mul(u.d, tmp, &env->vec_status);
1670
1671 return float64_to_uint32(u.d, &env->vec_status);
1672 }
1673
1674 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1675 {
1676 CPU_DoubleU u1;
1677 CPU_FloatU u2;
1678
1679 u1.ll = val;
1680 u2.f = float64_to_float32(u1.d, &env->vec_status);
1681
1682 return u2.l;
1683 }
1684
1685 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1686 {
1687 CPU_DoubleU u2;
1688 CPU_FloatU u1;
1689
1690 u1.l = val;
1691 u2.d = float32_to_float64(u1.f, &env->vec_status);
1692
1693 return u2.ll;
1694 }
1695
1696 /* Double precision fixed-point arithmetic */
1697 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1698 {
1699 CPU_DoubleU u1, u2;
1700
1701 u1.ll = op1;
1702 u2.ll = op2;
1703 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1704 return u1.ll;
1705 }
1706
1707 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1708 {
1709 CPU_DoubleU u1, u2;
1710
1711 u1.ll = op1;
1712 u2.ll = op2;
1713 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1714 return u1.ll;
1715 }
1716
1717 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1718 {
1719 CPU_DoubleU u1, u2;
1720
1721 u1.ll = op1;
1722 u2.ll = op2;
1723 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1724 return u1.ll;
1725 }
1726
1727 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1728 {
1729 CPU_DoubleU u1, u2;
1730
1731 u1.ll = op1;
1732 u2.ll = op2;
1733 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1734 return u1.ll;
1735 }
1736
1737 /* Double precision floating point helpers */
1738 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1739 {
1740 CPU_DoubleU u1, u2;
1741
1742 u1.ll = op1;
1743 u2.ll = op2;
1744 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1745 }
1746
1747 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1748 {
1749 CPU_DoubleU u1, u2;
1750
1751 u1.ll = op1;
1752 u2.ll = op2;
1753 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1754 }
1755
1756 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1757 {
1758 CPU_DoubleU u1, u2;
1759
1760 u1.ll = op1;
1761 u2.ll = op2;
1762 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1763 }
1764
1765 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1766 {
1767 /* XXX: TODO: test special values (NaN, infinites, ...) */
1768 return helper_efdtstlt(env, op1, op2);
1769 }
1770
1771 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1772 {
1773 /* XXX: TODO: test special values (NaN, infinites, ...) */
1774 return helper_efdtstgt(env, op1, op2);
1775 }
1776
1777 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1778 {
1779 /* XXX: TODO: test special values (NaN, infinites, ...) */
1780 return helper_efdtsteq(env, op1, op2);
1781 }
1782
1783 #define float64_to_float64(x, env) x
1784
1785
1786 /* VSX_ADD_SUB - VSX floating point add/subract
1787 * name - instruction mnemonic
1788 * op - operation (add or sub)
1789 * nels - number of elements (1, 2 or 4)
1790 * tp - type (float32 or float64)
1791 * fld - vsr_t field (VsrD(*) or VsrW(*))
1792 * sfprf - set FPRF
1793 */
1794 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1795 void helper_##name(CPUPPCState *env, uint32_t opcode) \
1796 { \
1797 ppc_vsr_t xt, xa, xb; \
1798 int i; \
1799 \
1800 getVSR(xA(opcode), &xa, env); \
1801 getVSR(xB(opcode), &xb, env); \
1802 getVSR(xT(opcode), &xt, env); \
1803 helper_reset_fpstatus(env); \
1804 \
1805 for (i = 0; i < nels; i++) { \
1806 float_status tstat = env->fp_status; \
1807 set_float_exception_flags(0, &tstat); \
1808 xt.fld = tp##_##op(xa.fld, xb.fld, &tstat); \
1809 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1810 \
1811 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1812 float_invalid_op_addsub(env, sfprf, GETPC(), \
1813 tp##_classify(xa.fld) | \
1814 tp##_classify(xb.fld)); \
1815 } \
1816 \
1817 if (r2sp) { \
1818 xt.fld = helper_frsp(env, xt.fld); \
1819 } \
1820 \
1821 if (sfprf) { \
1822 helper_compute_fprf_float64(env, xt.fld); \
1823 } \
1824 } \
1825 putVSR(xT(opcode), &xt, env); \
1826 do_float_check_status(env, GETPC()); \
1827 }
1828
1829 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1830 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1831 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1832 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1833 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1834 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1835 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1836 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1837
1838 void helper_xsaddqp(CPUPPCState *env, uint32_t opcode)
1839 {
1840 ppc_vsr_t xt, xa, xb;
1841 float_status tstat;
1842
1843 getVSR(rA(opcode) + 32, &xa, env);
1844 getVSR(rB(opcode) + 32, &xb, env);
1845 getVSR(rD(opcode) + 32, &xt, env);
1846 helper_reset_fpstatus(env);
1847
1848 tstat = env->fp_status;
1849 if (unlikely(Rc(opcode) != 0)) {
1850 tstat.float_rounding_mode = float_round_to_odd;
1851 }
1852
1853 set_float_exception_flags(0, &tstat);
1854 xt.f128 = float128_add(xa.f128, xb.f128, &tstat);
1855 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1856
1857 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1858 float_invalid_op_addsub(env, 1, GETPC(),
1859 float128_classify(xa.f128) |
1860 float128_classify(xb.f128));
1861 }
1862
1863 helper_compute_fprf_float128(env, xt.f128);
1864
1865 putVSR(rD(opcode) + 32, &xt, env);
1866 do_float_check_status(env, GETPC());
1867 }
1868
1869 /* VSX_MUL - VSX floating point multiply
1870 * op - instruction mnemonic
1871 * nels - number of elements (1, 2 or 4)
1872 * tp - type (float32 or float64)
1873 * fld - vsr_t field (VsrD(*) or VsrW(*))
1874 * sfprf - set FPRF
1875 */
1876 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1877 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1878 { \
1879 ppc_vsr_t xt, xa, xb; \
1880 int i; \
1881 \
1882 getVSR(xA(opcode), &xa, env); \
1883 getVSR(xB(opcode), &xb, env); \
1884 getVSR(xT(opcode), &xt, env); \
1885 helper_reset_fpstatus(env); \
1886 \
1887 for (i = 0; i < nels; i++) { \
1888 float_status tstat = env->fp_status; \
1889 set_float_exception_flags(0, &tstat); \
1890 xt.fld = tp##_mul(xa.fld, xb.fld, &tstat); \
1891 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1892 \
1893 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1894 float_invalid_op_mul(env, sfprf, GETPC(), \
1895 tp##_classify(xa.fld) | \
1896 tp##_classify(xb.fld)); \
1897 } \
1898 \
1899 if (r2sp) { \
1900 xt.fld = helper_frsp(env, xt.fld); \
1901 } \
1902 \
1903 if (sfprf) { \
1904 helper_compute_fprf_float64(env, xt.fld); \
1905 } \
1906 } \
1907 \
1908 putVSR(xT(opcode), &xt, env); \
1909 do_float_check_status(env, GETPC()); \
1910 }
1911
1912 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1913 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1914 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1915 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1916
1917 void helper_xsmulqp(CPUPPCState *env, uint32_t opcode)
1918 {
1919 ppc_vsr_t xt, xa, xb;
1920 float_status tstat;
1921
1922 getVSR(rA(opcode) + 32, &xa, env);
1923 getVSR(rB(opcode) + 32, &xb, env);
1924 getVSR(rD(opcode) + 32, &xt, env);
1925
1926 helper_reset_fpstatus(env);
1927 tstat = env->fp_status;
1928 if (unlikely(Rc(opcode) != 0)) {
1929 tstat.float_rounding_mode = float_round_to_odd;
1930 }
1931
1932 set_float_exception_flags(0, &tstat);
1933 xt.f128 = float128_mul(xa.f128, xb.f128, &tstat);
1934 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1935
1936 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1937 float_invalid_op_mul(env, 1, GETPC(),
1938 float128_classify(xa.f128) |
1939 float128_classify(xb.f128));
1940 }
1941 helper_compute_fprf_float128(env, xt.f128);
1942
1943 putVSR(rD(opcode) + 32, &xt, env);
1944 do_float_check_status(env, GETPC());
1945 }
1946
1947 /* VSX_DIV - VSX floating point divide
1948 * op - instruction mnemonic
1949 * nels - number of elements (1, 2 or 4)
1950 * tp - type (float32 or float64)
1951 * fld - vsr_t field (VsrD(*) or VsrW(*))
1952 * sfprf - set FPRF
1953 */
1954 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1955 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1956 { \
1957 ppc_vsr_t xt, xa, xb; \
1958 int i; \
1959 \
1960 getVSR(xA(opcode), &xa, env); \
1961 getVSR(xB(opcode), &xb, env); \
1962 getVSR(xT(opcode), &xt, env); \
1963 helper_reset_fpstatus(env); \
1964 \
1965 for (i = 0; i < nels; i++) { \
1966 float_status tstat = env->fp_status; \
1967 set_float_exception_flags(0, &tstat); \
1968 xt.fld = tp##_div(xa.fld, xb.fld, &tstat); \
1969 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1970 \
1971 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1972 if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \
1973 float_invalid_op_vxidi(env, sfprf, GETPC()); \
1974 } else if (tp##_is_zero(xa.fld) && tp##_is_zero(xb.fld)) { \
1975 float_invalid_op_vxzdz(env, sfprf, GETPC()); \
1976 } else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
1977 tp##_is_signaling_nan(xb.fld, &tstat)) { \
1978 float_invalid_op_vxsnan(env, GETPC()); \
1979 } \
1980 } \
1981 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1982 float_zero_divide_excp(env, GETPC()); \
1983 } \
1984 \
1985 if (r2sp) { \
1986 xt.fld = helper_frsp(env, xt.fld); \
1987 } \
1988 \
1989 if (sfprf) { \
1990 helper_compute_fprf_float64(env, xt.fld); \
1991 } \
1992 } \
1993 \
1994 putVSR(xT(opcode), &xt, env); \
1995 do_float_check_status(env, GETPC()); \
1996 }
1997
1998 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1999 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
2000 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
2001 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
2002
2003 void helper_xsdivqp(CPUPPCState *env, uint32_t opcode)
2004 {
2005 ppc_vsr_t xt, xa, xb;
2006 float_status tstat;
2007
2008 getVSR(rA(opcode) + 32, &xa, env);
2009 getVSR(rB(opcode) + 32, &xb, env);
2010 getVSR(rD(opcode) + 32, &xt, env);
2011
2012 helper_reset_fpstatus(env);
2013 tstat = env->fp_status;
2014 if (unlikely(Rc(opcode) != 0)) {
2015 tstat.float_rounding_mode = float_round_to_odd;
2016 }
2017
2018 set_float_exception_flags(0, &tstat);
2019 xt.f128 = float128_div(xa.f128, xb.f128, &tstat);
2020 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2021
2022 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
2023 if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
2024 float_invalid_op_vxidi(env, 1, GETPC());
2025 } else if (float128_is_zero(xa.f128) && float128_is_zero(xb.f128)) {
2026 float_invalid_op_vxzdz(env, 1, GETPC());
2027 } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
2028 float128_is_signaling_nan(xb.f128, &tstat)) {
2029 float_invalid_op_vxsnan(env, GETPC());
2030 }
2031 }
2032 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
2033 float_zero_divide_excp(env, GETPC());
2034 }
2035
2036 helper_compute_fprf_float128(env, xt.f128);
2037 putVSR(rD(opcode) + 32, &xt, env);
2038 do_float_check_status(env, GETPC());
2039 }
2040
2041 /* VSX_RE - VSX floating point reciprocal estimate
2042 * op - instruction mnemonic
2043 * nels - number of elements (1, 2 or 4)
2044 * tp - type (float32 or float64)
2045 * fld - vsr_t field (VsrD(*) or VsrW(*))
2046 * sfprf - set FPRF
2047 */
2048 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
2049 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2050 { \
2051 ppc_vsr_t xt, xb; \
2052 int i; \
2053 \
2054 getVSR(xB(opcode), &xb, env); \
2055 getVSR(xT(opcode), &xt, env); \
2056 helper_reset_fpstatus(env); \
2057 \
2058 for (i = 0; i < nels; i++) { \
2059 if (unlikely(tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \
2060 float_invalid_op_vxsnan(env, GETPC()); \
2061 } \
2062 xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status); \
2063 \
2064 if (r2sp) { \
2065 xt.fld = helper_frsp(env, xt.fld); \
2066 } \
2067 \
2068 if (sfprf) { \
2069 helper_compute_fprf_float64(env, xt.fld); \
2070 } \
2071 } \
2072 \
2073 putVSR(xT(opcode), &xt, env); \
2074 do_float_check_status(env, GETPC()); \
2075 }
2076
2077 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
2078 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
2079 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
2080 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
2081
2082 /* VSX_SQRT - VSX floating point square root
2083 * op - instruction mnemonic
2084 * nels - number of elements (1, 2 or 4)
2085 * tp - type (float32 or float64)
2086 * fld - vsr_t field (VsrD(*) or VsrW(*))
2087 * sfprf - set FPRF
2088 */
2089 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
2090 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2091 { \
2092 ppc_vsr_t xt, xb; \
2093 int i; \
2094 \
2095 getVSR(xB(opcode), &xb, env); \
2096 getVSR(xT(opcode), &xt, env); \
2097 helper_reset_fpstatus(env); \
2098 \
2099 for (i = 0; i < nels; i++) { \
2100 float_status tstat = env->fp_status; \
2101 set_float_exception_flags(0, &tstat); \
2102 xt.fld = tp##_sqrt(xb.fld, &tstat); \
2103 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2104 \
2105 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2106 if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
2107 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
2108 } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \
2109 float_invalid_op_vxsnan(env, GETPC()); \
2110 } \
2111 } \
2112 \
2113 if (r2sp) { \
2114 xt.fld = helper_frsp(env, xt.fld); \
2115 } \
2116 \
2117 if (sfprf) { \
2118 helper_compute_fprf_float64(env, xt.fld); \
2119 } \
2120 } \
2121 \
2122 putVSR(xT(opcode), &xt, env); \
2123 do_float_check_status(env, GETPC()); \
2124 }
2125
2126 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
2127 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
2128 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
2129 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
2130
2131 /* VSX_RSQRTE - VSX floating point reciprocal square root estimate
2132 * op - instruction mnemonic
2133 * nels - number of elements (1, 2 or 4)
2134 * tp - type (float32 or float64)
2135 * fld - vsr_t field (VsrD(*) or VsrW(*))
2136 * sfprf - set FPRF
2137 */
2138 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
2139 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2140 { \
2141 ppc_vsr_t xt, xb; \
2142 int i; \
2143 \
2144 getVSR(xB(opcode), &xb, env); \
2145 getVSR(xT(opcode), &xt, env); \
2146 helper_reset_fpstatus(env); \
2147 \
2148 for (i = 0; i < nels; i++) { \
2149 float_status tstat = env->fp_status; \
2150 set_float_exception_flags(0, &tstat); \
2151 xt.fld = tp##_sqrt(xb.fld, &tstat); \
2152 xt.fld = tp##_div(tp##_one, xt.fld, &tstat); \
2153 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2154 \
2155 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2156 if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
2157 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
2158 } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \
2159 float_invalid_op_vxsnan(env, GETPC()); \
2160 } \
2161 } \
2162 \
2163 if (r2sp) { \
2164 xt.fld = helper_frsp(env, xt.fld); \
2165 } \
2166 \
2167 if (sfprf) { \
2168 helper_compute_fprf_float64(env, xt.fld); \
2169 } \
2170 } \
2171 \
2172 putVSR(xT(opcode), &xt, env); \
2173 do_float_check_status(env, GETPC()); \
2174 }
2175
2176 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
2177 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
2178 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
2179 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
2180
2181 /* VSX_TDIV - VSX floating point test for divide
2182 * op - instruction mnemonic
2183 * nels - number of elements (1, 2 or 4)
2184 * tp - type (float32 or float64)
2185 * fld - vsr_t field (VsrD(*) or VsrW(*))
2186 * emin - minimum unbiased exponent
2187 * emax - maximum unbiased exponent
2188 * nbits - number of fraction bits
2189 */
2190 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
2191 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2192 { \
2193 ppc_vsr_t xa, xb; \
2194 int i; \
2195 int fe_flag = 0; \
2196 int fg_flag = 0; \
2197 \
2198 getVSR(xA(opcode), &xa, env); \
2199 getVSR(xB(opcode), &xb, env); \
2200 \
2201 for (i = 0; i < nels; i++) { \
2202 if (unlikely(tp##_is_infinity(xa.fld) || \
2203 tp##_is_infinity(xb.fld) || \
2204 tp##_is_zero(xb.fld))) { \
2205 fe_flag = 1; \
2206 fg_flag = 1; \
2207 } else { \
2208 int e_a = ppc_##tp##_get_unbiased_exp(xa.fld); \
2209 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld); \
2210 \
2211 if (unlikely(tp##_is_any_nan(xa.fld) || \
2212 tp##_is_any_nan(xb.fld))) { \
2213 fe_flag = 1; \
2214 } else if ((e_b <= emin) || (e_b >= (emax-2))) { \
2215 fe_flag = 1; \
2216 } else if (!tp##_is_zero(xa.fld) && \
2217 (((e_a - e_b) >= emax) || \
2218 ((e_a - e_b) <= (emin+1)) || \
2219 (e_a <= (emin+nbits)))) { \
2220 fe_flag = 1; \
2221 } \
2222 \
2223 if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \
2224 /* XB is not zero because of the above check and */ \
2225 /* so must be denormalized. */ \
2226 fg_flag = 1; \
2227 } \
2228 } \
2229 } \
2230 \
2231 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2232 }
2233
2234 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2235 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2236 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2237
2238 /* VSX_TSQRT - VSX floating point test for square root
2239 * op - instruction mnemonic
2240 * nels - number of elements (1, 2 or 4)
2241 * tp - type (float32 or float64)
2242 * fld - vsr_t field (VsrD(*) or VsrW(*))
2243 * emin - minimum unbiased exponent
2244 * emax - maximum unbiased exponent
2245 * nbits - number of fraction bits
2246 */
2247 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2248 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2249 { \
2250 ppc_vsr_t xa, xb; \
2251 int i; \
2252 int fe_flag = 0; \
2253 int fg_flag = 0; \
2254 \
2255 getVSR(xA(opcode), &xa, env); \
2256 getVSR(xB(opcode), &xb, env); \
2257 \
2258 for (i = 0; i < nels; i++) { \
2259 if (unlikely(tp##_is_infinity(xb.fld) || \
2260 tp##_is_zero(xb.fld))) { \
2261 fe_flag = 1; \
2262 fg_flag = 1; \
2263 } else { \
2264 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld); \
2265 \
2266 if (unlikely(tp##_is_any_nan(xb.fld))) { \
2267 fe_flag = 1; \
2268 } else if (unlikely(tp##_is_zero(xb.fld))) { \
2269 fe_flag = 1; \
2270 } else if (unlikely(tp##_is_neg(xb.fld))) { \
2271 fe_flag = 1; \
2272 } else if (!tp##_is_zero(xb.fld) && \
2273 (e_b <= (emin+nbits))) { \
2274 fe_flag = 1; \
2275 } \
2276 \
2277 if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \
2278 /* XB is not zero because of the above check and */ \
2279 /* therefore must be denormalized. */ \
2280 fg_flag = 1; \
2281 } \
2282 } \
2283 } \
2284 \
2285 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2286 }
2287
2288 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2289 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2290 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2291
2292 /* VSX_MADD - VSX floating point muliply/add variations
2293 * op - instruction mnemonic
2294 * nels - number of elements (1, 2 or 4)
2295 * tp - type (float32 or float64)
2296 * fld - vsr_t field (VsrD(*) or VsrW(*))
2297 * maddflgs - flags for the float*muladd routine that control the
2298 * various forms (madd, msub, nmadd, nmsub)
2299 * afrm - A form (1=A, 0=M)
2300 * sfprf - set FPRF
2301 */
2302 #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) \
2303 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2304 { \
2305 ppc_vsr_t xt_in, xa, xb, xt_out; \
2306 ppc_vsr_t *b, *c; \
2307 int i; \
2308 \
2309 if (afrm) { /* AxB + T */ \
2310 b = &xb; \
2311 c = &xt_in; \
2312 } else { /* AxT + B */ \
2313 b = &xt_in; \
2314 c = &xb; \
2315 } \
2316 \
2317 getVSR(xA(opcode), &xa, env); \
2318 getVSR(xB(opcode), &xb, env); \
2319 getVSR(xT(opcode), &xt_in, env); \
2320 \
2321 xt_out = xt_in; \
2322 \
2323 helper_reset_fpstatus(env); \
2324 \
2325 for (i = 0; i < nels; i++) { \
2326 float_status tstat = env->fp_status; \
2327 set_float_exception_flags(0, &tstat); \
2328 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2329 /* Avoid double rounding errors by rounding the intermediate */ \
2330 /* result to odd. */ \
2331 set_float_rounding_mode(float_round_to_zero, &tstat); \
2332 xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld, \
2333 maddflgs, &tstat); \
2334 xt_out.fld |= (get_float_exception_flags(&tstat) & \
2335 float_flag_inexact) != 0; \
2336 } else { \
2337 xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld, \
2338 maddflgs, &tstat); \
2339 } \
2340 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2341 \
2342 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2343 tp##_maddsub_update_excp(env, xa.fld, b->fld, \
2344 c->fld, maddflgs, GETPC()); \
2345 } \
2346 \
2347 if (r2sp) { \
2348 xt_out.fld = helper_frsp(env, xt_out.fld); \
2349 } \
2350 \
2351 if (sfprf) { \
2352 helper_compute_fprf_float64(env, xt_out.fld); \
2353 } \
2354 } \
2355 putVSR(xT(opcode), &xt_out, env); \
2356 do_float_check_status(env, GETPC()); \
2357 }
2358
2359 VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
2360 VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
2361 VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0)
2362 VSX_MADD(xsmsubmdp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 0)
2363 VSX_MADD(xsnmaddadp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 0)
2364 VSX_MADD(xsnmaddmdp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 0)
2365 VSX_MADD(xsnmsubadp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 0)
2366 VSX_MADD(xsnmsubmdp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 0)
2367
2368 VSX_MADD(xsmaddasp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 1)
2369 VSX_MADD(xsmaddmsp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 1)
2370 VSX_MADD(xsmsubasp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 1)
2371 VSX_MADD(xsmsubmsp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 1)
2372 VSX_MADD(xsnmaddasp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 1)
2373 VSX_MADD(xsnmaddmsp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 1)
2374 VSX_MADD(xsnmsubasp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 1)
2375 VSX_MADD(xsnmsubmsp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 1)
2376
2377 VSX_MADD(xvmaddadp, 2, float64, VsrD(i), MADD_FLGS, 1, 0, 0)
2378 VSX_MADD(xvmaddmdp, 2, float64, VsrD(i), MADD_FLGS, 0, 0, 0)
2379 VSX_MADD(xvmsubadp, 2, float64, VsrD(i), MSUB_FLGS, 1, 0, 0)
2380 VSX_MADD(xvmsubmdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0, 0)
2381 VSX_MADD(xvnmaddadp, 2, float64, VsrD(i), NMADD_FLGS, 1, 0, 0)
2382 VSX_MADD(xvnmaddmdp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0, 0)
2383 VSX_MADD(xvnmsubadp, 2, float64, VsrD(i), NMSUB_FLGS, 1, 0, 0)
2384 VSX_MADD(xvnmsubmdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0, 0)
2385
2386 VSX_MADD(xvmaddasp, 4, float32, VsrW(i), MADD_FLGS, 1, 0, 0)
2387 VSX_MADD(xvmaddmsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0, 0)
2388 VSX_MADD(xvmsubasp, 4, float32, VsrW(i), MSUB_FLGS, 1, 0, 0)
2389 VSX_MADD(xvmsubmsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0, 0)
2390 VSX_MADD(xvnmaddasp, 4, float32, VsrW(i), NMADD_FLGS, 1, 0, 0)
2391 VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0)
2392 VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0)
2393 VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0)
2394
2395 /* VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
2396 * op - instruction mnemonic
2397 * cmp - comparison operation
2398 * exp - expected result of comparison
2399 * svxvc - set VXVC bit
2400 */
2401 #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
2402 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2403 { \
2404 ppc_vsr_t xt, xa, xb; \
2405 bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
2406 \
2407 getVSR(xA(opcode), &xa, env); \
2408 getVSR(xB(opcode), &xb, env); \
2409 getVSR(xT(opcode), &xt, env); \
2410 \
2411 if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
2412 float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
2413 vxsnan_flag = true; \
2414 if (fpscr_ve == 0 && svxvc) { \
2415 vxvc_flag = true; \
2416 } \
2417 } else if (svxvc) { \
2418 vxvc_flag = float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) || \
2419 float64_is_quiet_nan(xb.VsrD(0), &env->fp_status); \
2420 } \
2421 if (vxsnan_flag) { \
2422 float_invalid_op_vxsnan(env, GETPC()); \
2423 } \
2424 if (vxvc_flag) { \
2425 float_invalid_op_vxvc(env, 0, GETPC()); \
2426 } \
2427 vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
2428 \
2429 if (!vex_flag) { \
2430 if (float64_##cmp(xb.VsrD(0), xa.VsrD(0), &env->fp_status) == exp) { \
2431 xt.VsrD(0) = -1; \
2432 xt.VsrD(1) = 0; \
2433 } else { \
2434 xt.VsrD(0) = 0; \
2435 xt.VsrD(1) = 0; \
2436 } \
2437 } \
2438 putVSR(xT(opcode), &xt, env); \
2439 do_float_check_status(env, GETPC()); \
2440 }
2441
2442 VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
2443 VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
2444 VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
2445 VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
2446
2447 void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode)
2448 {
2449 ppc_vsr_t xa, xb;
2450 int64_t exp_a, exp_b;
2451 uint32_t cc;
2452
2453 getVSR(xA(opcode), &xa, env);
2454 getVSR(xB(opcode), &xb, env);
2455
2456 exp_a = extract64(xa.VsrD(0), 52, 11);
2457 exp_b = extract64(xb.VsrD(0), 52, 11);
2458
2459 if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||
2460 float64_is_any_nan(xb.VsrD(0)))) {
2461 cc = CRF_SO;
2462 } else {
2463 if (exp_a < exp_b) {
2464 cc = CRF_LT;
2465 } else if (exp_a > exp_b) {
2466 cc = CRF_GT;
2467 } else {
2468 cc = CRF_EQ;
2469 }
2470 }
2471
2472 env->fpscr &= ~(0x0F << FPSCR_FPRF);
2473 env->fpscr |= cc << FPSCR_FPRF;
2474 env->crf[BF(opcode)] = cc;
2475
2476 do_float_check_status(env, GETPC());
2477 }
2478
2479 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode)
2480 {
2481 ppc_vsr_t xa, xb;
2482 int64_t exp_a, exp_b;
2483 uint32_t cc;
2484
2485 getVSR(rA(opcode) + 32, &xa, env);
2486 getVSR(rB(opcode) + 32, &xb, env);
2487
2488 exp_a = extract64(xa.VsrD(0), 48, 15);
2489 exp_b = extract64(xb.VsrD(0), 48, 15);
2490
2491 if (unlikely(float128_is_any_nan(xa.f128) ||
2492 float128_is_any_nan(xb.f128))) {
2493 cc = CRF_SO;
2494 } else {
2495 if (exp_a < exp_b) {
2496 cc = CRF_LT;
2497 } else if (exp_a > exp_b) {
2498 cc = CRF_GT;
2499 } else {
2500 cc = CRF_EQ;
2501 }
2502 }
2503
2504 env->fpscr &= ~(0x0F << FPSCR_FPRF);
2505 env->fpscr |= cc << FPSCR_FPRF;
2506 env->crf[BF(opcode)] = cc;
2507
2508 do_float_check_status(env, GETPC());
2509 }
2510
2511 #define VSX_SCALAR_CMP(op, ordered) \
2512 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2513 { \
2514 ppc_vsr_t xa, xb; \
2515 uint32_t cc = 0; \
2516 bool vxsnan_flag = false, vxvc_flag = false; \
2517 \
2518 helper_reset_fpstatus(env); \
2519 getVSR(xA(opcode), &xa, env); \
2520 getVSR(xB(opcode), &xb, env); \
2521 \
2522 if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
2523 float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
2524 vxsnan_flag = true; \
2525 cc = CRF_SO; \
2526 if (fpscr_ve == 0 && ordered) { \
2527 vxvc_flag = true; \
2528 } \
2529 } else if (float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) || \
2530 float64_is_quiet_nan(xb.VsrD(0), &env->fp_status)) { \
2531 cc = CRF_SO; \
2532 if (ordered) { \
2533 vxvc_flag = true; \
2534 } \
2535 } \
2536 if (vxsnan_flag) { \
2537 float_invalid_op_vxsnan(env, GETPC()); \
2538 } \
2539 if (vxvc_flag) { \
2540 float_invalid_op_vxvc(env, 0, GETPC()); \
2541 } \
2542 \
2543 if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \
2544 cc |= CRF_LT; \
2545 } else if (!float64_le(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \
2546 cc |= CRF_GT; \
2547 } else { \
2548 cc |= CRF_EQ; \
2549 } \
2550 \
2551 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2552 env->fpscr |= cc << FPSCR_FPRF; \
2553 env->crf[BF(opcode)] = cc; \
2554 \
2555 do_float_check_status(env, GETPC()); \
2556 }
2557
2558 VSX_SCALAR_CMP(xscmpodp, 1)
2559 VSX_SCALAR_CMP(xscmpudp, 0)
2560
2561 #define VSX_SCALAR_CMPQ(op, ordered) \
2562 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2563 { \
2564 ppc_vsr_t xa, xb; \
2565 uint32_t cc = 0; \
2566 bool vxsnan_flag = false, vxvc_flag = false; \
2567 \
2568 helper_reset_fpstatus(env); \
2569 getVSR(rA(opcode) + 32, &xa, env); \
2570 getVSR(rB(opcode) + 32, &xb, env); \
2571 \
2572 if (float128_is_signaling_nan(xa.f128, &env->fp_status) || \
2573 float128_is_signaling_nan(xb.f128, &env->fp_status)) { \
2574 vxsnan_flag = true; \
2575 cc = CRF_SO; \
2576 if (fpscr_ve == 0 && ordered) { \
2577 vxvc_flag = true; \
2578 } \
2579 } else if (float128_is_quiet_nan(xa.f128, &env->fp_status) || \
2580 float128_is_quiet_nan(xb.f128, &env->fp_status)) { \
2581 cc = CRF_SO; \
2582 if (ordered) { \
2583 vxvc_flag = true; \
2584 } \
2585 } \
2586 if (vxsnan_flag) { \
2587 float_invalid_op_vxsnan(env, GETPC()); \
2588 } \
2589 if (vxvc_flag) { \
2590 float_invalid_op_vxvc(env, 0, GETPC()); \
2591 } \
2592 \
2593 if (float128_lt(xa.f128, xb.f128, &env->fp_status)) { \
2594 cc |= CRF_LT; \
2595 } else if (!float128_le(xa.f128, xb.f128, &env->fp_status)) { \
2596 cc |= CRF_GT; \
2597 } else { \
2598 cc |= CRF_EQ; \
2599 } \
2600 \
2601 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2602 env->fpscr |= cc << FPSCR_FPRF; \
2603 env->crf[BF(opcode)] = cc; \
2604 \
2605 do_float_check_status(env, GETPC()); \
2606 }
2607
2608 VSX_SCALAR_CMPQ(xscmpoqp, 1)
2609 VSX_SCALAR_CMPQ(xscmpuqp, 0)
2610
2611 /* VSX_MAX_MIN - VSX floating point maximum/minimum
2612 * name - instruction mnemonic
2613 * op - operation (max or min)
2614 * nels - number of elements (1, 2 or 4)
2615 * tp - type (float32 or float64)
2616 * fld - vsr_t field (VsrD(*) or VsrW(*))
2617 */
2618 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2619 void helper_##name(CPUPPCState *env, uint32_t opcode) \
2620 { \
2621 ppc_vsr_t xt, xa, xb; \
2622 int i; \
2623 \
2624 getVSR(xA(opcode), &xa, env); \
2625 getVSR(xB(opcode), &xb, env); \
2626 getVSR(xT(opcode), &xt, env); \
2627 \
2628 for (i = 0; i < nels; i++) { \
2629 xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status); \
2630 if (unlikely(tp##_is_signaling_nan(xa.fld, &env->fp_status) || \
2631 tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \
2632 float_invalid_op_vxsnan(env, GETPC()); \
2633 } \
2634 } \
2635 \
2636 putVSR(xT(opcode), &xt, env); \
2637 do_float_check_status(env, GETPC()); \
2638 }
2639
2640 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2641 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2642 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2643 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2644 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2645 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2646
2647 #define VSX_MAX_MINC(name, max) \
2648 void helper_##name(CPUPPCState *env, uint32_t opcode) \
2649 { \
2650 ppc_vsr_t xt, xa, xb; \
2651 bool vxsnan_flag = false, vex_flag = false; \
2652 \
2653 getVSR(rA(opcode) + 32, &xa, env); \
2654 getVSR(rB(opcode) + 32, &xb, env); \
2655 getVSR(rD(opcode) + 32, &xt, env); \
2656 \
2657 if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
2658 float64_is_any_nan(xb.VsrD(0)))) { \
2659 if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
2660 float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
2661 vxsnan_flag = true; \
2662 } \
2663 xt.VsrD(0) = xb.VsrD(0); \
2664 } else if ((max && \
2665 !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || \
2666 (!max && \
2667 float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { \
2668 xt.VsrD(0) = xa.VsrD(0); \
2669 } else { \
2670 xt.VsrD(0) = xb.VsrD(0); \
2671 } \
2672 \
2673 vex_flag = fpscr_ve & vxsnan_flag; \
2674 if (vxsnan_flag) { \
2675 float_invalid_op_vxsnan(env, GETPC()); \
2676 } \
2677 if (!vex_flag) { \
2678 putVSR(rD(opcode) + 32, &xt, env); \
2679 } \
2680 } \
2681
2682 VSX_MAX_MINC(xsmaxcdp, 1);
2683 VSX_MAX_MINC(xsmincdp, 0);
2684
2685 #define VSX_MAX_MINJ(name, max) \
2686 void helper_##name(CPUPPCState *env, uint32_t opcode) \
2687 { \
2688 ppc_vsr_t xt, xa, xb; \
2689 bool vxsnan_flag = false, vex_flag = false; \
2690 \
2691 getVSR(rA(opcode) + 32, &xa, env); \
2692 getVSR(rB(opcode) + 32, &xb, env); \
2693 getVSR(rD(opcode) + 32, &xt, env); \
2694 \
2695 if (unlikely(float64_is_any_nan(xa.VsrD(0)))) { \
2696 if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status)) { \
2697 vxsnan_flag = true; \
2698 } \
2699 xt.VsrD(0) = xa.VsrD(0); \
2700 } else if (unlikely(float64_is_any_nan(xb.VsrD(0)))) { \
2701 if (float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
2702 vxsnan_flag = true; \
2703 } \
2704 xt.VsrD(0) = xb.VsrD(0); \
2705 } else if (float64_is_zero(xa.VsrD(0)) && float64_is_zero(xb.VsrD(0))) { \
2706 if (max) { \
2707 if (!float64_is_neg(xa.VsrD(0)) || !float64_is_neg(xb.VsrD(0))) { \
2708 xt.VsrD(0) = 0ULL; \
2709 } else { \
2710 xt.VsrD(0) = 0x8000000000000000ULL; \
2711 } \
2712 } else { \
2713 if (float64_is_neg(xa.VsrD(0)) || float64_is_neg(xb.VsrD(0))) { \
2714 xt.VsrD(0) = 0x8000000000000000ULL; \
2715 } else { \
2716 xt.VsrD(0) = 0ULL; \
2717 } \
2718 } \
2719 } else if ((max && \
2720 !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || \
2721 (!max && \
2722 float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { \
2723 xt.VsrD(0) = xa.VsrD(0); \
2724 } else { \
2725 xt.VsrD(0) = xb.VsrD(0); \
2726 } \
2727 \
2728 vex_flag = fpscr_ve & vxsnan_flag; \
2729 if (vxsnan_flag) { \
2730 float_invalid_op_vxsnan(env, GETPC()); \
2731 } \
2732 if (!vex_flag) { \
2733 putVSR(rD(opcode) + 32, &xt, env); \
2734 } \
2735 } \
2736
2737 VSX_MAX_MINJ(xsmaxjdp, 1);
2738 VSX_MAX_MINJ(xsminjdp, 0);
2739
2740 /* VSX_CMP - VSX floating point compare
2741 * op - instruction mnemonic
2742 * nels - number of elements (1, 2 or 4)
2743 * tp - type (float32 or float64)
2744 * fld - vsr_t field (VsrD(*) or VsrW(*))
2745 * cmp - comparison operation
2746 * svxvc - set VXVC bit
2747 * exp - expected result of comparison
2748 */
2749 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
2750 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2751 { \
2752 ppc_vsr_t xt, xa, xb; \
2753 int i; \
2754 int all_true = 1; \
2755 int all_false = 1; \
2756 \
2757 getVSR(xA(opcode), &xa, env); \
2758 getVSR(xB(opcode), &xb, env); \
2759 getVSR(xT(opcode), &xt, env); \
2760 \
2761 for (i = 0; i < nels; i++) { \
2762 if (unlikely(tp##_is_any_nan(xa.fld) || \
2763 tp##_is_any_nan(xb.fld))) { \
2764 if (tp##_is_signaling_nan(xa.fld, &env->fp_status) || \
2765 tp##_is_signaling_nan(xb.fld, &env->fp_status)) { \
2766 float_invalid_op_vxsnan(env, GETPC()); \
2767 } \
2768 if (svxvc) { \
2769 float_invalid_op_vxvc(env, 0, GETPC()); \
2770 } \
2771 xt.fld = 0; \
2772 all_true = 0; \
2773 } else { \
2774 if (tp##_##cmp(xb.fld, xa.fld, &env->fp_status) == exp) { \
2775 xt.fld = -1; \
2776 all_false = 0; \
2777 } else { \
2778 xt.fld = 0; \
2779 all_true = 0; \
2780 } \
2781 } \
2782 } \
2783 \
2784 putVSR(xT(opcode), &xt, env); \
2785 if ((opcode >> (31-21)) & 1) { \
2786 env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2787 } \
2788 do_float_check_status(env, GETPC()); \
2789 }
2790
2791 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1)
2792 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1)
2793 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1, 1)
2794 VSX_CMP(xvcmpnedp, 2, float64, VsrD(i), eq, 0, 0)
2795 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0, 1)
2796 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1, 1)
2797 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1, 1)
2798 VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
2799
2800 /* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2801 * op - instruction mnemonic
2802 * nels - number of elements (1, 2 or 4)
2803 * stp - source type (float32 or float64)
2804 * ttp - target type (float32 or float64)
2805 * sfld - source vsr_t field
2806 * tfld - target vsr_t field (f32 or f64)
2807 * sfprf - set FPRF
2808 */
2809 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2810 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2811 { \
2812 ppc_vsr_t xt, xb; \
2813 int i; \
2814 \
2815 getVSR(xB(opcode), &xb, env); \
2816 getVSR(xT(opcode), &xt, env); \
2817 \
2818 for (i = 0; i < nels; i++) { \
2819 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2820 if (unlikely(stp##_is_signaling_nan(xb.sfld, \
2821 &env->fp_status))) { \
2822 float_invalid_op_vxsnan(env, GETPC()); \
2823 xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
2824 } \
2825 if (sfprf) { \
2826 helper_compute_fprf_##ttp(env, xt.tfld); \
2827 } \
2828 } \
2829 \
2830 putVSR(xT(opcode), &xt, env); \
2831 do_float_check_status(env, GETPC()); \
2832 }
2833
2834 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2835 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2836 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
2837 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
2838
2839 /* VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2840 * op - instruction mnemonic
2841 * nels - number of elements (1, 2 or 4)
2842 * stp - source type (float32 or float64)
2843 * ttp - target type (float32 or float64)
2844 * sfld - source vsr_t field
2845 * tfld - target vsr_t field (f32 or f64)
2846 * sfprf - set FPRF
2847 */
2848 #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
2849 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2850 { \
2851 ppc_vsr_t xt, xb; \
2852 int i; \
2853 \
2854 getVSR(rB(opcode) + 32, &xb, env); \
2855 getVSR(rD(opcode) + 32, &xt, env); \
2856 \
2857 for (i = 0; i < nels; i++) { \
2858 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2859 if (unlikely(stp##_is_signaling_nan(xb.sfld, \
2860 &env->fp_status))) { \
2861 float_invalid_op_vxsnan(env, GETPC()); \
2862 xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
2863 } \
2864 if (sfprf) { \
2865 helper_compute_fprf_##ttp(env, xt.tfld); \
2866 } \
2867 } \
2868 \
2869 putVSR(rD(opcode) + 32, &xt, env); \
2870 do_float_check_status(env, GETPC()); \
2871 }
2872
2873 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2874
2875 /* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2876 * involving one half precision value
2877 * op - instruction mnemonic
2878 * nels - number of elements (1, 2 or 4)
2879 * stp - source type
2880 * ttp - target type
2881 * sfld - source vsr_t field
2882 * tfld - target vsr_t field
2883 * sfprf - set FPRF
2884 */
2885 #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2886 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2887 { \
2888 ppc_vsr_t xt, xb; \
2889 int i; \
2890 \
2891 getVSR(xB(opcode), &xb, env); \
2892 memset(&xt, 0, sizeof(xt)); \
2893 \
2894 for (i = 0; i < nels; i++) { \
2895 xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \
2896 if (unlikely(stp##_is_signaling_nan(xb.sfld, \
2897 &env->fp_status))) { \
2898 float_invalid_op_vxsnan(env, GETPC()); \
2899 xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
2900 } \
2901 if (sfprf) { \
2902 helper_compute_fprf_##ttp(env, xt.tfld); \
2903 } \
2904 } \
2905 \
2906 putVSR(xT(opcode), &xt, env); \
2907 do_float_check_status(env, GETPC()); \
2908 }
2909
2910 VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
2911 VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
2912 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
2913 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
2914
2915 /*
2916 * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2917 * added to this later.
2918 */
2919 void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode)
2920 {
2921 ppc_vsr_t xt, xb;
2922 float_status tstat;
2923
2924 getVSR(rB(opcode) + 32, &xb, env);
2925 memset(&xt, 0, sizeof(xt));
2926
2927 tstat = env->fp_status;
2928 if (unlikely(Rc(opcode) != 0)) {
2929 tstat.float_rounding_mode = float_round_to_odd;
2930 }
2931
2932 xt.VsrD(0) = float128_to_float64(xb.f128, &tstat);
2933 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2934 if (unlikely(float128_is_signaling_nan(xb.f128, &tstat))) {
2935 float_invalid_op_vxsnan(env, GETPC());
2936 xt.VsrD(0) = float64_snan_to_qnan(xt.VsrD(0));
2937 }
2938 helper_compute_fprf_float64(env, xt.VsrD(0));
2939
2940 putVSR(rD(opcode) + 32, &xt, env);
2941 do_float_check_status(env, GETPC());
2942 }
2943
2944 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2945 {
2946 float_status tstat = env->fp_status;
2947 set_float_exception_flags(0, &tstat);
2948
2949 return (uint64_t)float64_to_float32(xb, &tstat) << 32;
2950 }
2951
2952 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2953 {
2954 float_status tstat = env->fp_status;
2955 set_float_exception_flags(0, &tstat);
2956
2957 return float32_to_float64(xb >> 32, &tstat);
2958 }
2959
2960 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2961 * op - instruction mnemonic
2962 * nels - number of elements (1, 2 or 4)
2963 * stp - source type (float32 or float64)
2964 * ttp - target type (int32, uint32, int64 or uint64)
2965 * sfld - source vsr_t field
2966 * tfld - target vsr_t field
2967 * rnan - resulting NaN
2968 */
2969 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
2970 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2971 { \
2972 ppc_vsr_t xt, xb; \
2973 int i; \
2974 \
2975 getVSR(xB(opcode), &xb, env); \
2976 getVSR(xT(opcode), &xt, env); \
2977 \
2978 for (i = 0; i < nels; i++) { \
2979 if (unlikely(stp##_is_any_nan(xb.sfld))) { \
2980 if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \
2981 float_invalid_op_vxsnan(env, GETPC()); \
2982 } \
2983 float_invalid_op_vxcvi(env, 0, GETPC()); \
2984 xt.tfld = rnan; \
2985 } else { \
2986 xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \
2987 &env->fp_status); \
2988 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2989 float_invalid_op_vxcvi(env, 0, GETPC()); \
2990 } \
2991 } \
2992 } \
2993 \
2994 putVSR(xT(opcode), &xt, env); \
2995 do_float_check_status(env, GETPC()); \
2996 }
2997
2998 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2999 0x8000000000000000ULL)
3000 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
3001 0x80000000U)
3002 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
3003 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
3004 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
3005 0x8000000000000000ULL)
3006 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2*i), \
3007 0x80000000U)
3008 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
3009 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2*i), 0U)
3010 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2*i), VsrD(i), \
3011 0x8000000000000000ULL)
3012 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
3013 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL)
3014 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
3015
3016 /* VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
3017 * op - instruction mnemonic
3018 * stp - source type (float32 or float64)
3019 * ttp - target type (int32, uint32, int64 or uint64)
3020 * sfld - source vsr_t field
3021 * tfld - target vsr_t field
3022 * rnan - resulting NaN
3023 */
3024 #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
3025 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3026 { \
3027 ppc_vsr_t xt, xb; \
3028 \
3029 getVSR(rB(opcode) + 32, &xb, env); \
3030 memset(&xt, 0, sizeof(xt)); \
3031 \
3032 if (unlikely(stp##_is_any_nan(xb.sfld))) { \
3033 if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \
3034 float_invalid_op_vxsnan(env, GETPC()); \
3035 } \
3036 float_invalid_op_vxcvi(env, 0, GETPC()); \
3037 xt.tfld = rnan; \
3038 } else { \
3039 xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \
3040 &env->fp_status); \
3041 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
3042 float_invalid_op_vxcvi(env, 0, GETPC()); \
3043 } \
3044 } \
3045 \
3046 putVSR(rD(opcode) + 32, &xt, env); \
3047 do_float_check_status(env, GETPC()); \
3048 }
3049
3050 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
3051 0x8000000000000000ULL)
3052
3053 VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
3054 0xffffffff80000000ULL)
3055 VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
3056 VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
3057
3058 /* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
3059 * op - instruction mnemonic
3060 * nels - number of elements (1, 2 or 4)
3061 * stp - source type (int32, uint32, int64 or uint64)
3062 * ttp - target type (float32 or float64)
3063 * sfld - source vsr_t field
3064 * tfld - target vsr_t field
3065 * jdef - definition of the j index (i or 2*i)
3066 * sfprf - set FPRF
3067 */
3068 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
3069 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3070 { \
3071 ppc_vsr_t xt, xb; \
3072 int i; \
3073 \
3074 getVSR(xB(opcode), &xb, env); \
3075 getVSR(xT(opcode), &xt, env); \
3076 \
3077 for (i = 0; i < nels; i++) { \
3078 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
3079 if (r2sp) { \
3080 xt.tfld = helper_frsp(env, xt.tfld); \
3081 } \
3082 if (sfprf) { \
3083 helper_compute_fprf_float64(env, xt.tfld); \
3084 } \
3085 } \
3086 \
3087 putVSR(xT(opcode), &xt, env); \
3088 do_float_check_status(env, GETPC()); \
3089 }
3090
3091 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
3092 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
3093 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
3094 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
3095 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
3096 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
3097 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2*i), VsrD(i), 0, 0)
3098 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2*i), VsrD(i), 0, 0)
3099 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2*i), 0, 0)
3100 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0)
3101 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
3102 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
3103
3104 /* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
3105 * op - instruction mnemonic
3106 * stp - source type (int32, uint32, int64 or uint64)
3107 * ttp - target type (float32 or float64)
3108 * sfld - source vsr_t field
3109 * tfld - target vsr_t field
3110 */
3111 #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
3112 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3113 { \
3114 ppc_vsr_t xt, xb; \
3115 \
3116 getVSR(rB(opcode) + 32, &xb, env); \
3117 getVSR(rD(opcode) + 32, &xt, env); \
3118 \
3119 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
3120 helper_compute_fprf_##ttp(env, xt.tfld); \
3121 \
3122 putVSR(xT(opcode) + 32, &xt, env); \
3123 do_float_check_status(env, GETPC()); \
3124 }
3125
3126 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
3127 VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
3128
3129 /* For "use current rounding mode", define a value that will not be one of
3130 * the existing rounding model enums.
3131 */
3132 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
3133 float_round_up + float_round_to_zero)
3134
3135 /* VSX_ROUND - VSX floating point round
3136 * op - instruction mnemonic
3137 * nels - number of elements (1, 2 or 4)
3138 * tp - type (float32 or float64)
3139 * fld - vsr_t field (VsrD(*) or VsrW(*))
3140 * rmode - rounding mode
3141 * sfprf - set FPRF
3142 */
3143 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
3144 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3145 { \
3146 ppc_vsr_t xt, xb; \
3147 int i; \
3148 getVSR(xB(opcode), &xb, env); \
3149 getVSR(xT(opcode), &xt, env); \
3150 \
3151 if (rmode != FLOAT_ROUND_CURRENT) { \
3152 set_float_rounding_mode(rmode, &env->fp_status); \
3153 } \
3154 \
3155 for (i = 0; i < nels; i++) { \
3156 if (unlikely(tp##_is_signaling_nan(xb.fld, \
3157 &env->fp_status))) { \
3158 float_invalid_op_vxsnan(env, GETPC()); \
3159 xt.fld = tp##_snan_to_qnan(xb.fld); \
3160 } else { \
3161 xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \
3162 } \
3163 if (sfprf) { \
3164 helper_compute_fprf_float64(env, xt.fld); \
3165 } \
3166 } \
3167 \
3168 /* If this is not a "use current rounding mode" instruction, \
3169 * then inhibit setting of the XX bit and restore rounding \
3170 * mode from FPSCR */ \
3171 if (rmode != FLOAT_ROUND_CURRENT) { \
3172 fpscr_set_rounding_mode(env); \
3173 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
3174 } \
3175 \
3176 putVSR(xT(opcode), &xt, env); \
3177 do_float_check_status(env, GETPC()); \
3178 }
3179
3180 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
3181 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
3182 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
3183 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
3184 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
3185
3186 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
3187 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
3188 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
3189 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
3190 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
3191
3192 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
3193 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
3194 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
3195 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
3196 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
3197
3198 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
3199 {
3200 helper_reset_fpstatus(env);
3201
3202 uint64_t xt = helper_frsp(env, xb);
3203
3204 helper_compute_fprf_float64(env, xt);
3205 do_float_check_status(env, GETPC());
3206 return xt;
3207 }
3208
3209 #define VSX_XXPERM(op, indexed) \
3210 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3211 { \
3212 ppc_vsr_t xt, xa, pcv, xto; \
3213 int i, idx; \
3214 \
3215 getVSR(xA(opcode), &xa, env); \
3216 getVSR(xT(opcode), &xt, env); \
3217 getVSR(xB(opcode), &pcv, env); \
3218 \
3219 for (i = 0; i < 16; i++) { \
3220 idx = pcv.VsrB(i) & 0x1F; \
3221 if (indexed) { \
3222 idx = 31 - idx; \
3223 } \
3224 xto.VsrB(i) = (idx <= 15) ? xa.VsrB(idx) : xt.VsrB(idx - 16); \
3225 } \
3226 putVSR(xT(opcode), &xto, env); \
3227 }
3228
3229 VSX_XXPERM(xxperm, 0)
3230 VSX_XXPERM(xxpermr, 1)
3231
3232 void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
3233 {
3234 ppc_vsr_t xt, xb;
3235 uint32_t exp, i, fraction;
3236
3237 getVSR(xB(opcode), &xb, env);
3238 memset(&xt, 0, sizeof(xt));
3239
3240 for (i = 0; i < 4; i++) {
3241 exp = (xb.VsrW(i) >> 23) & 0xFF;
3242 fraction = xb.VsrW(i) & 0x7FFFFF;
3243 if (exp != 0 && exp != 255) {
3244 xt.VsrW(i) = fraction | 0x00800000;
3245 } else {
3246 xt.VsrW(i) = fraction;
3247 }
3248 }
3249 putVSR(xT(opcode), &xt, env);
3250 }
3251
3252 /* VSX_TEST_DC - VSX floating point test data class
3253 * op - instruction mnemonic
3254 * nels - number of elements (1, 2 or 4)
3255 * xbn - VSR register number
3256 * tp - type (float32 or float64)
3257 * fld - vsr_t field (VsrD(*) or VsrW(*))
3258 * tfld - target vsr_t field (VsrD(*) or VsrW(*))
3259 * fld_max - target field max
3260 * scrf - set result in CR and FPCC
3261 */
3262 #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
3263 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3264 { \
3265 ppc_vsr_t xt, xb; \
3266 uint32_t i, sign, dcmx; \
3267 uint32_t cc, match = 0; \
3268 \
3269 getVSR(xbn, &xb, env); \
3270 if (!scrf) { \
3271 memset(&xt, 0, sizeof(xt)); \
3272 dcmx = DCMX_XV(opcode); \
3273 } else { \
3274 dcmx = DCMX(opcode); \
3275 } \
3276 \
3277 for (i = 0; i < nels; i++) { \
3278 sign = tp##_is_neg(xb.fld); \
3279 if (tp##_is_any_nan(xb.fld)) { \
3280 match = extract32(dcmx, 6, 1); \
3281 } else if (tp##_is_infinity(xb.fld)) { \
3282 match = extract32(dcmx, 4 + !sign, 1); \
3283 } else if (tp##_is_zero(xb.fld)) { \
3284 match = extract32(dcmx, 2 + !sign, 1); \
3285 } else if (tp##_is_zero_or_denormal(xb.fld)) { \
3286 match = extract32(dcmx, 0 + !sign, 1); \
3287 } \
3288 \
3289 if (scrf) { \
3290 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
3291 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
3292 env->fpscr |= cc << FPSCR_FPRF; \
3293 env->crf[BF(opcode)] = cc; \
3294 } else { \
3295 xt.tfld = match ? fld_max : 0; \
3296 } \
3297 match = 0; \
3298 } \
3299 if (!scrf) { \
3300 putVSR(xT(opcode), &xt, env); \
3301 } \
3302 }
3303
3304 VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
3305 VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
3306 VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
3307 VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
3308
3309 void helper_xststdcsp(CPUPPCState *env, uint32_t opcode)
3310 {
3311 ppc_vsr_t xb;
3312 uint32_t dcmx, sign, exp;
3313 uint32_t cc, match = 0, not_sp = 0;
3314
3315 getVSR(xB(opcode), &xb, env);
3316 dcmx = DCMX(opcode);
3317 exp = (xb.VsrD(0) >> 52) & 0x7FF;
3318
3319 sign = float64_is_neg(xb.VsrD(0));
3320 if (float64_is_any_nan(xb.VsrD(0))) {
3321 match = extract32(dcmx, 6, 1);
3322 } else if (float64_is_infinity(xb.VsrD(0))) {
3323 match = extract32(dcmx, 4 + !sign, 1);
3324 } else if (float64_is_zero(xb.VsrD(0))) {
3325 match = extract32(dcmx, 2 + !sign, 1);
3326 } else if (float64_is_zero_or_denormal(xb.VsrD(0)) ||
3327 (exp > 0 && exp < 0x381)) {
3328 match = extract32(dcmx, 0 + !sign, 1);
3329 }
3330
3331 not_sp = !float64_eq(xb.VsrD(0),
3332 float32_to_float64(
3333 float64_to_float32(xb.VsrD(0), &env->fp_status),
3334 &env->fp_status), &env->fp_status);
3335
3336 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
3337 env->fpscr &= ~(0x0F << FPSCR_FPRF);
3338 env->fpscr |= cc << FPSCR_FPRF;
3339 env->crf[BF(opcode)] = cc;
3340 }
3341
3342 void helper_xsrqpi(CPUPPCState *env, uint32_t opcode)
3343 {
3344 ppc_vsr_t xb;
3345 ppc_vsr_t xt;
3346 uint8_t r = Rrm(opcode);
3347 uint8_t ex = Rc(opcode);
3348 uint8_t rmc = RMC(opcode);
3349 uint8_t rmode = 0;
3350 float_status tstat;
3351
3352 getVSR(rB(opcode) + 32, &xb, env);
3353 memset(&xt, 0, sizeof(xt));
3354 helper_reset_fpstatus(env);
3355
3356 if (r == 0 && rmc == 0) {
3357 rmode = float_round_ties_away;
3358 } else if (r == 0 && rmc == 0x3) {
3359 rmode = fpscr_rn;
3360 } else if (r == 1) {
3361 switch (rmc) {
3362 case 0:
3363 rmode = float_round_nearest_even;
3364 break;
3365 case 1:
3366 rmode = float_round_to_zero;
3367 break;
3368 case 2:
3369 rmode = float_round_up;
3370 break;
3371 case 3:
3372 rmode = float_round_down;
3373 break;
3374 default:
3375 abort();
3376 }
3377 }
3378
3379 tstat = env->fp_status;
3380 set_float_exception_flags(0, &tstat);
3381 set_float_rounding_mode(rmode, &tstat);
3382 xt.f128 = float128_round_to_int(xb.f128, &tstat);
3383 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3384
3385 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3386 if (float128_is_signaling_nan(xb.f128, &tstat)) {
3387 float_invalid_op_vxsnan(env, GETPC());
3388 xt.f128 = float128_snan_to_qnan(xt.f128);
3389 }
3390 }
3391
3392 if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3393 env->fp_status.float_exception_flags &= ~float_flag_inexact;
3394 }
3395
3396 helper_compute_fprf_float128(env, xt.f128);
3397 do_float_check_status(env, GETPC());
3398 putVSR(rD(opcode) + 32, &xt, env);
3399 }
3400
3401 void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode)
3402 {
3403 ppc_vsr_t xb;
3404 ppc_vsr_t xt;
3405 uint8_t r = Rrm(opcode);
3406 uint8_t rmc = RMC(opcode);
3407 uint8_t rmode = 0;
3408 floatx80 round_res;
3409 float_status tstat;
3410
3411 getVSR(rB(opcode) + 32, &xb, env);
3412 memset(&xt, 0, sizeof(xt));
3413 helper_reset_fpstatus(env);
3414
3415 if (r == 0 && rmc == 0) {
3416 rmode = float_round_ties_away;
3417 } else if (r == 0 && rmc == 0x3) {
3418 rmode = fpscr_rn;
3419 } else if (r == 1) {
3420 switch (rmc) {
3421 case 0:
3422 rmode = float_round_nearest_even;
3423 break;
3424 case 1:
3425 rmode = float_round_to_zero;
3426 break;
3427 case 2:
3428 rmode = float_round_up;
3429 break;
3430 case 3:
3431 rmode = float_round_down;
3432 break;
3433 default:
3434 abort();
3435 }
3436 }
3437
3438 tstat = env->fp_status;
3439 set_float_exception_flags(0, &tstat);
3440 set_float_rounding_mode(rmode, &tstat);
3441 round_res = float128_to_floatx80(xb.f128, &tstat);
3442 xt.f128 = floatx80_to_float128(round_res, &tstat);
3443 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3444
3445 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3446 if (float128_is_signaling_nan(xb.f128, &tstat)) {
3447 float_invalid_op_vxsnan(env, GETPC());
3448 xt.f128 = float128_snan_to_qnan(xt.f128);
3449 }
3450 }
3451
3452 helper_compute_fprf_float128(env, xt.f128);
3453 putVSR(rD(opcode) + 32, &xt, env);
3454 do_float_check_status(env, GETPC());
3455 }
3456
3457 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode)
3458 {
3459 ppc_vsr_t xb;
3460 ppc_vsr_t xt;
3461 float_status tstat;
3462
3463 getVSR(rB(opcode) + 32, &xb, env);
3464 memset(&xt, 0, sizeof(xt));
3465 helper_reset_fpstatus(env);
3466
3467 tstat = env->fp_status;
3468 if (unlikely(Rc(opcode) != 0)) {
3469 tstat.float_rounding_mode = float_round_to_odd;
3470 }
3471
3472 set_float_exception_flags(0, &tstat);
3473 xt.f128 = float128_sqrt(xb.f128, &tstat);
3474 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3475
3476 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3477 if (float128_is_signaling_nan(xb.f128, &tstat)) {
3478 float_invalid_op_vxsnan(env, GETPC());
3479 xt.f128 = float128_snan_to_qnan(xb.f128);
3480 } else if (float128_is_quiet_nan(xb.f128, &tstat)) {
3481 xt.f128 = xb.f128;
3482 } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) {
3483 float_invalid_op_vxsqrt(env, 1, GETPC());
3484 xt.f128 = float128_default_nan(&env->fp_status);
3485 }
3486 }
3487
3488 helper_compute_fprf_float128(env, xt.f128);
3489 putVSR(rD(opcode) + 32, &xt, env);
3490 do_float_check_status(env, GETPC());
3491 }
3492
3493 void helper_xssubqp(CPUPPCState *env, uint32_t opcode)
3494 {
3495 ppc_vsr_t xt, xa, xb;
3496 float_status tstat;
3497
3498 getVSR(rA(opcode) + 32, &xa, env);
3499 getVSR(rB(opcode) + 32, &xb, env);
3500 getVSR(rD(opcode) + 32, &xt, env);
3501 helper_reset_fpstatus(env);
3502
3503 tstat = env->fp_status;
3504 if (unlikely(Rc(opcode) != 0)) {
3505 tstat.float_rounding_mode = float_round_to_odd;
3506 }
3507
3508 set_float_exception_flags(0, &tstat);
3509 xt.f128 = float128_sub(xa.f128, xb.f128, &tstat);
3510 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3511
3512 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3513 float_invalid_op_addsub(env, 1, GETPC(),
3514 float128_classify(xa.f128) |
3515 float128_classify(xb.f128));
3516 }
3517
3518 helper_compute_fprf_float128(env, xt.f128);
3519 putVSR(rD(opcode) + 32, &xt, env);
3520 do_float_check_status(env, GETPC());
3521 }
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