]> git.proxmox.com Git - mirror_qemu.git/blob - target/ppc/kvm.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into...
[mirror_qemu.git] / target / ppc / kvm.c
1 /*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
17 #include "qemu/osdep.h"
18 #include <dirent.h>
19 #include <sys/ioctl.h>
20 #include <sys/vfs.h>
21
22 #include <linux/kvm.h>
23
24 #include "qemu-common.h"
25 #include "qapi/error.h"
26 #include "qemu/error-report.h"
27 #include "cpu.h"
28 #include "cpu-models.h"
29 #include "qemu/timer.h"
30 #include "sysemu/hw_accel.h"
31 #include "kvm_ppc.h"
32 #include "sysemu/cpus.h"
33 #include "sysemu/device_tree.h"
34 #include "mmu-hash64.h"
35
36 #include "hw/sysbus.h"
37 #include "hw/ppc/spapr.h"
38 #include "hw/ppc/spapr_cpu_core.h"
39 #include "hw/hw.h"
40 #include "hw/ppc/ppc.h"
41 #include "migration/qemu-file-types.h"
42 #include "sysemu/watchdog.h"
43 #include "trace.h"
44 #include "exec/gdbstub.h"
45 #include "exec/memattrs.h"
46 #include "exec/ram_addr.h"
47 #include "sysemu/hostmem.h"
48 #include "qemu/cutils.h"
49 #include "qemu/main-loop.h"
50 #include "qemu/mmap-alloc.h"
51 #include "elf.h"
52 #include "sysemu/kvm_int.h"
53
54 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
55
56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
57 KVM_CAP_LAST_INFO
58 };
59
60 static int cap_interrupt_unset;
61 static int cap_segstate;
62 static int cap_booke_sregs;
63 static int cap_ppc_smt;
64 static int cap_ppc_smt_possible;
65 static int cap_spapr_tce;
66 static int cap_spapr_tce_64;
67 static int cap_spapr_multitce;
68 static int cap_spapr_vfio;
69 static int cap_hior;
70 static int cap_one_reg;
71 static int cap_epr;
72 static int cap_ppc_watchdog;
73 static int cap_papr;
74 static int cap_htab_fd;
75 static int cap_fixup_hcalls;
76 static int cap_htm; /* Hardware transactional memory support */
77 static int cap_mmu_radix;
78 static int cap_mmu_hash_v3;
79 static int cap_xive;
80 static int cap_resize_hpt;
81 static int cap_ppc_pvr_compat;
82 static int cap_ppc_safe_cache;
83 static int cap_ppc_safe_bounds_check;
84 static int cap_ppc_safe_indirect_branch;
85 static int cap_ppc_count_cache_flush_assist;
86 static int cap_ppc_nested_kvm_hv;
87 static int cap_large_decr;
88
89 static uint32_t debug_inst_opcode;
90
91 /*
92 * Check whether we are running with KVM-PR (instead of KVM-HV). This
93 * should only be used for fallback tests - generally we should use
94 * explicit capabilities for the features we want, rather than
95 * assuming what is/isn't available depending on the KVM variant.
96 */
97 static bool kvmppc_is_pr(KVMState *ks)
98 {
99 /* Assume KVM-PR if the GET_PVINFO capability is available */
100 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
101 }
102
103 static int kvm_ppc_register_host_cpu_type(MachineState *ms);
104 static void kvmppc_get_cpu_characteristics(KVMState *s);
105 static int kvmppc_get_dec_bits(void);
106
107 int kvm_arch_init(MachineState *ms, KVMState *s)
108 {
109 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
110 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
111 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
112 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
113 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
114 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
115 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
116 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
117 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
118 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
119 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
120 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
121 /*
122 * Note: we don't set cap_papr here, because this capability is
123 * only activated after this by kvmppc_set_papr()
124 */
125 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
126 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
127 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
128 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
129 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
130 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
131 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
132 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
133 kvmppc_get_cpu_characteristics(s);
134 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
135 cap_large_decr = kvmppc_get_dec_bits();
136 /*
137 * Note: setting it to false because there is not such capability
138 * in KVM at this moment.
139 *
140 * TODO: call kvm_vm_check_extension() with the right capability
141 * after the kernel starts implementing it.
142 */
143 cap_ppc_pvr_compat = false;
144
145 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
146 error_report("KVM: Host kernel doesn't have level irq capability");
147 exit(1);
148 }
149
150 kvm_ppc_register_host_cpu_type(ms);
151
152 return 0;
153 }
154
155 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
156 {
157 return 0;
158 }
159
160 static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
161 {
162 CPUPPCState *cenv = &cpu->env;
163 CPUState *cs = CPU(cpu);
164 struct kvm_sregs sregs;
165 int ret;
166
167 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
168 /*
169 * What we're really trying to say is "if we're on BookE, we
170 * use the native PVR for now". This is the only sane way to
171 * check it though, so we potentially confuse users that they
172 * can run BookE guests on BookS. Let's hope nobody dares
173 * enough :)
174 */
175 return 0;
176 } else {
177 if (!cap_segstate) {
178 fprintf(stderr, "kvm error: missing PVR setting capability\n");
179 return -ENOSYS;
180 }
181 }
182
183 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
184 if (ret) {
185 return ret;
186 }
187
188 sregs.pvr = cenv->spr[SPR_PVR];
189 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
190 }
191
192 /* Set up a shared TLB array with KVM */
193 static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
194 {
195 CPUPPCState *env = &cpu->env;
196 CPUState *cs = CPU(cpu);
197 struct kvm_book3e_206_tlb_params params = {};
198 struct kvm_config_tlb cfg = {};
199 unsigned int entries = 0;
200 int ret, i;
201
202 if (!kvm_enabled() ||
203 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
204 return 0;
205 }
206
207 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
208
209 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
210 params.tlb_sizes[i] = booke206_tlb_size(env, i);
211 params.tlb_ways[i] = booke206_tlb_ways(env, i);
212 entries += params.tlb_sizes[i];
213 }
214
215 assert(entries == env->nb_tlb);
216 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
217
218 env->tlb_dirty = true;
219
220 cfg.array = (uintptr_t)env->tlb.tlbm;
221 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
222 cfg.params = (uintptr_t)&params;
223 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
224
225 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
226 if (ret < 0) {
227 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
228 __func__, strerror(-ret));
229 return ret;
230 }
231
232 env->kvm_sw_tlb = true;
233 return 0;
234 }
235
236
237 #if defined(TARGET_PPC64)
238 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
239 {
240 int ret;
241
242 assert(kvm_state != NULL);
243
244 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
245 error_setg(errp, "KVM doesn't expose the MMU features it supports");
246 error_append_hint(errp, "Consider switching to a newer KVM\n");
247 return;
248 }
249
250 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
251 if (ret == 0) {
252 return;
253 }
254
255 error_setg_errno(errp, -ret,
256 "KVM failed to provide the MMU features it supports");
257 }
258
259 struct ppc_radix_page_info *kvm_get_radix_page_info(void)
260 {
261 KVMState *s = KVM_STATE(current_machine->accelerator);
262 struct ppc_radix_page_info *radix_page_info;
263 struct kvm_ppc_rmmu_info rmmu_info;
264 int i;
265
266 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
267 return NULL;
268 }
269 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
270 return NULL;
271 }
272 radix_page_info = g_malloc0(sizeof(*radix_page_info));
273 radix_page_info->count = 0;
274 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
275 if (rmmu_info.ap_encodings[i]) {
276 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
277 radix_page_info->count++;
278 }
279 }
280 return radix_page_info;
281 }
282
283 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
284 bool radix, bool gtse,
285 uint64_t proc_tbl)
286 {
287 CPUState *cs = CPU(cpu);
288 int ret;
289 uint64_t flags = 0;
290 struct kvm_ppc_mmuv3_cfg cfg = {
291 .process_table = proc_tbl,
292 };
293
294 if (radix) {
295 flags |= KVM_PPC_MMUV3_RADIX;
296 }
297 if (gtse) {
298 flags |= KVM_PPC_MMUV3_GTSE;
299 }
300 cfg.flags = flags;
301 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
302 switch (ret) {
303 case 0:
304 return H_SUCCESS;
305 case -EINVAL:
306 return H_PARAMETER;
307 case -ENODEV:
308 return H_NOT_AVAILABLE;
309 default:
310 return H_HARDWARE;
311 }
312 }
313
314 bool kvmppc_hpt_needs_host_contiguous_pages(void)
315 {
316 static struct kvm_ppc_smmu_info smmu_info;
317
318 if (!kvm_enabled()) {
319 return false;
320 }
321
322 kvm_get_smmu_info(&smmu_info, &error_fatal);
323 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
324 }
325
326 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
327 {
328 struct kvm_ppc_smmu_info smmu_info;
329 int iq, ik, jq, jk;
330 Error *local_err = NULL;
331
332 /* For now, we only have anything to check on hash64 MMUs */
333 if (!cpu->hash64_opts || !kvm_enabled()) {
334 return;
335 }
336
337 kvm_get_smmu_info(&smmu_info, &local_err);
338 if (local_err) {
339 error_propagate(errp, local_err);
340 return;
341 }
342
343 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
344 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
345 error_setg(errp,
346 "KVM does not support 1TiB segments which guest expects");
347 return;
348 }
349
350 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
351 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
352 smmu_info.slb_size, cpu->hash64_opts->slb_size);
353 return;
354 }
355
356 /*
357 * Verify that every pagesize supported by the cpu model is
358 * supported by KVM with the same encodings
359 */
360 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
361 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
362 struct kvm_ppc_one_seg_page_size *ksps;
363
364 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
365 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
366 break;
367 }
368 }
369 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
370 error_setg(errp, "KVM doesn't support for base page shift %u",
371 qsps->page_shift);
372 return;
373 }
374
375 ksps = &smmu_info.sps[ik];
376 if (ksps->slb_enc != qsps->slb_enc) {
377 error_setg(errp,
378 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
379 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
380 return;
381 }
382
383 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
384 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
385 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
386 break;
387 }
388 }
389
390 if (jk >= ARRAY_SIZE(ksps->enc)) {
391 error_setg(errp, "KVM doesn't support page shift %u/%u",
392 qsps->enc[jq].page_shift, qsps->page_shift);
393 return;
394 }
395 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
396 error_setg(errp,
397 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
398 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
399 qsps->page_shift, qsps->enc[jq].pte_enc);
400 return;
401 }
402 }
403 }
404
405 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
406 /*
407 * Mostly what guest pagesizes we can use are related to the
408 * host pages used to map guest RAM, which is handled in the
409 * platform code. Cache-Inhibited largepages (64k) however are
410 * used for I/O, so if they're mapped to the host at all it
411 * will be a normal mapping, not a special hugepage one used
412 * for RAM.
413 */
414 if (getpagesize() < 0x10000) {
415 error_setg(errp,
416 "KVM can't supply 64kiB CI pages, which guest expects");
417 }
418 }
419 }
420 #endif /* !defined (TARGET_PPC64) */
421
422 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
423 {
424 return POWERPC_CPU(cpu)->vcpu_id;
425 }
426
427 /*
428 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
429 * only 1 watchpoint, so array size of 4 is sufficient for now.
430 */
431 #define MAX_HW_BKPTS 4
432
433 static struct HWBreakpoint {
434 target_ulong addr;
435 int type;
436 } hw_debug_points[MAX_HW_BKPTS];
437
438 static CPUWatchpoint hw_watchpoint;
439
440 /* Default there is no breakpoint and watchpoint supported */
441 static int max_hw_breakpoint;
442 static int max_hw_watchpoint;
443 static int nb_hw_breakpoint;
444 static int nb_hw_watchpoint;
445
446 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
447 {
448 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
449 max_hw_breakpoint = 2;
450 max_hw_watchpoint = 2;
451 }
452
453 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
454 fprintf(stderr, "Error initializing h/w breakpoints\n");
455 return;
456 }
457 }
458
459 int kvm_arch_init_vcpu(CPUState *cs)
460 {
461 PowerPCCPU *cpu = POWERPC_CPU(cs);
462 CPUPPCState *cenv = &cpu->env;
463 int ret;
464
465 /* Synchronize sregs with kvm */
466 ret = kvm_arch_sync_sregs(cpu);
467 if (ret) {
468 if (ret == -EINVAL) {
469 error_report("Register sync failed... If you're using kvm-hv.ko,"
470 " only \"-cpu host\" is possible");
471 }
472 return ret;
473 }
474
475 switch (cenv->mmu_model) {
476 case POWERPC_MMU_BOOKE206:
477 /* This target supports access to KVM's guest TLB */
478 ret = kvm_booke206_tlb_init(cpu);
479 break;
480 case POWERPC_MMU_2_07:
481 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
482 /*
483 * KVM-HV has transactional memory on POWER8 also without
484 * the KVM_CAP_PPC_HTM extension, so enable it here
485 * instead as long as it's availble to userspace on the
486 * host.
487 */
488 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
489 cap_htm = true;
490 }
491 }
492 break;
493 default:
494 break;
495 }
496
497 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
498 kvmppc_hw_debug_points_init(cenv);
499
500 return ret;
501 }
502
503 int kvm_arch_destroy_vcpu(CPUState *cs)
504 {
505 return 0;
506 }
507
508 static void kvm_sw_tlb_put(PowerPCCPU *cpu)
509 {
510 CPUPPCState *env = &cpu->env;
511 CPUState *cs = CPU(cpu);
512 struct kvm_dirty_tlb dirty_tlb;
513 unsigned char *bitmap;
514 int ret;
515
516 if (!env->kvm_sw_tlb) {
517 return;
518 }
519
520 bitmap = g_malloc((env->nb_tlb + 7) / 8);
521 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
522
523 dirty_tlb.bitmap = (uintptr_t)bitmap;
524 dirty_tlb.num_dirty = env->nb_tlb;
525
526 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
527 if (ret) {
528 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
529 __func__, strerror(-ret));
530 }
531
532 g_free(bitmap);
533 }
534
535 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
536 {
537 PowerPCCPU *cpu = POWERPC_CPU(cs);
538 CPUPPCState *env = &cpu->env;
539 union {
540 uint32_t u32;
541 uint64_t u64;
542 } val;
543 struct kvm_one_reg reg = {
544 .id = id,
545 .addr = (uintptr_t) &val,
546 };
547 int ret;
548
549 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
550 if (ret != 0) {
551 trace_kvm_failed_spr_get(spr, strerror(errno));
552 } else {
553 switch (id & KVM_REG_SIZE_MASK) {
554 case KVM_REG_SIZE_U32:
555 env->spr[spr] = val.u32;
556 break;
557
558 case KVM_REG_SIZE_U64:
559 env->spr[spr] = val.u64;
560 break;
561
562 default:
563 /* Don't handle this size yet */
564 abort();
565 }
566 }
567 }
568
569 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
570 {
571 PowerPCCPU *cpu = POWERPC_CPU(cs);
572 CPUPPCState *env = &cpu->env;
573 union {
574 uint32_t u32;
575 uint64_t u64;
576 } val;
577 struct kvm_one_reg reg = {
578 .id = id,
579 .addr = (uintptr_t) &val,
580 };
581 int ret;
582
583 switch (id & KVM_REG_SIZE_MASK) {
584 case KVM_REG_SIZE_U32:
585 val.u32 = env->spr[spr];
586 break;
587
588 case KVM_REG_SIZE_U64:
589 val.u64 = env->spr[spr];
590 break;
591
592 default:
593 /* Don't handle this size yet */
594 abort();
595 }
596
597 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
598 if (ret != 0) {
599 trace_kvm_failed_spr_set(spr, strerror(errno));
600 }
601 }
602
603 static int kvm_put_fp(CPUState *cs)
604 {
605 PowerPCCPU *cpu = POWERPC_CPU(cs);
606 CPUPPCState *env = &cpu->env;
607 struct kvm_one_reg reg;
608 int i;
609 int ret;
610
611 if (env->insns_flags & PPC_FLOAT) {
612 uint64_t fpscr = env->fpscr;
613 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
614
615 reg.id = KVM_REG_PPC_FPSCR;
616 reg.addr = (uintptr_t)&fpscr;
617 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
618 if (ret < 0) {
619 trace_kvm_failed_fpscr_set(strerror(errno));
620 return ret;
621 }
622
623 for (i = 0; i < 32; i++) {
624 uint64_t vsr[2];
625 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
626 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
627
628 #ifdef HOST_WORDS_BIGENDIAN
629 vsr[0] = float64_val(*fpr);
630 vsr[1] = *vsrl;
631 #else
632 vsr[0] = *vsrl;
633 vsr[1] = float64_val(*fpr);
634 #endif
635 reg.addr = (uintptr_t) &vsr;
636 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
637
638 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
639 if (ret < 0) {
640 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
641 strerror(errno));
642 return ret;
643 }
644 }
645 }
646
647 if (env->insns_flags & PPC_ALTIVEC) {
648 reg.id = KVM_REG_PPC_VSCR;
649 reg.addr = (uintptr_t)&env->vscr;
650 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
651 if (ret < 0) {
652 trace_kvm_failed_vscr_set(strerror(errno));
653 return ret;
654 }
655
656 for (i = 0; i < 32; i++) {
657 reg.id = KVM_REG_PPC_VR(i);
658 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
659 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
660 if (ret < 0) {
661 trace_kvm_failed_vr_set(i, strerror(errno));
662 return ret;
663 }
664 }
665 }
666
667 return 0;
668 }
669
670 static int kvm_get_fp(CPUState *cs)
671 {
672 PowerPCCPU *cpu = POWERPC_CPU(cs);
673 CPUPPCState *env = &cpu->env;
674 struct kvm_one_reg reg;
675 int i;
676 int ret;
677
678 if (env->insns_flags & PPC_FLOAT) {
679 uint64_t fpscr;
680 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
681
682 reg.id = KVM_REG_PPC_FPSCR;
683 reg.addr = (uintptr_t)&fpscr;
684 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
685 if (ret < 0) {
686 trace_kvm_failed_fpscr_get(strerror(errno));
687 return ret;
688 } else {
689 env->fpscr = fpscr;
690 }
691
692 for (i = 0; i < 32; i++) {
693 uint64_t vsr[2];
694 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
695 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
696
697 reg.addr = (uintptr_t) &vsr;
698 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
699
700 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
701 if (ret < 0) {
702 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
703 strerror(errno));
704 return ret;
705 } else {
706 #ifdef HOST_WORDS_BIGENDIAN
707 *fpr = vsr[0];
708 if (vsx) {
709 *vsrl = vsr[1];
710 }
711 #else
712 *fpr = vsr[1];
713 if (vsx) {
714 *vsrl = vsr[0];
715 }
716 #endif
717 }
718 }
719 }
720
721 if (env->insns_flags & PPC_ALTIVEC) {
722 reg.id = KVM_REG_PPC_VSCR;
723 reg.addr = (uintptr_t)&env->vscr;
724 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
725 if (ret < 0) {
726 trace_kvm_failed_vscr_get(strerror(errno));
727 return ret;
728 }
729
730 for (i = 0; i < 32; i++) {
731 reg.id = KVM_REG_PPC_VR(i);
732 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
733 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
734 if (ret < 0) {
735 trace_kvm_failed_vr_get(i, strerror(errno));
736 return ret;
737 }
738 }
739 }
740
741 return 0;
742 }
743
744 #if defined(TARGET_PPC64)
745 static int kvm_get_vpa(CPUState *cs)
746 {
747 PowerPCCPU *cpu = POWERPC_CPU(cs);
748 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
749 struct kvm_one_reg reg;
750 int ret;
751
752 reg.id = KVM_REG_PPC_VPA_ADDR;
753 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
754 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
755 if (ret < 0) {
756 trace_kvm_failed_vpa_addr_get(strerror(errno));
757 return ret;
758 }
759
760 assert((uintptr_t)&spapr_cpu->slb_shadow_size
761 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
762 reg.id = KVM_REG_PPC_VPA_SLB;
763 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
764 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
765 if (ret < 0) {
766 trace_kvm_failed_slb_get(strerror(errno));
767 return ret;
768 }
769
770 assert((uintptr_t)&spapr_cpu->dtl_size
771 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
772 reg.id = KVM_REG_PPC_VPA_DTL;
773 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
774 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
775 if (ret < 0) {
776 trace_kvm_failed_dtl_get(strerror(errno));
777 return ret;
778 }
779
780 return 0;
781 }
782
783 static int kvm_put_vpa(CPUState *cs)
784 {
785 PowerPCCPU *cpu = POWERPC_CPU(cs);
786 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
787 struct kvm_one_reg reg;
788 int ret;
789
790 /*
791 * SLB shadow or DTL can't be registered unless a master VPA is
792 * registered. That means when restoring state, if a VPA *is*
793 * registered, we need to set that up first. If not, we need to
794 * deregister the others before deregistering the master VPA
795 */
796 assert(spapr_cpu->vpa_addr
797 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
798
799 if (spapr_cpu->vpa_addr) {
800 reg.id = KVM_REG_PPC_VPA_ADDR;
801 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
802 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
803 if (ret < 0) {
804 trace_kvm_failed_vpa_addr_set(strerror(errno));
805 return ret;
806 }
807 }
808
809 assert((uintptr_t)&spapr_cpu->slb_shadow_size
810 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
811 reg.id = KVM_REG_PPC_VPA_SLB;
812 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
813 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
814 if (ret < 0) {
815 trace_kvm_failed_slb_set(strerror(errno));
816 return ret;
817 }
818
819 assert((uintptr_t)&spapr_cpu->dtl_size
820 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
821 reg.id = KVM_REG_PPC_VPA_DTL;
822 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
823 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
824 if (ret < 0) {
825 trace_kvm_failed_dtl_set(strerror(errno));
826 return ret;
827 }
828
829 if (!spapr_cpu->vpa_addr) {
830 reg.id = KVM_REG_PPC_VPA_ADDR;
831 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
832 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
833 if (ret < 0) {
834 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
835 return ret;
836 }
837 }
838
839 return 0;
840 }
841 #endif /* TARGET_PPC64 */
842
843 int kvmppc_put_books_sregs(PowerPCCPU *cpu)
844 {
845 CPUPPCState *env = &cpu->env;
846 struct kvm_sregs sregs;
847 int i;
848
849 sregs.pvr = env->spr[SPR_PVR];
850
851 if (cpu->vhyp) {
852 PPCVirtualHypervisorClass *vhc =
853 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
854 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
855 } else {
856 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
857 }
858
859 /* Sync SLB */
860 #ifdef TARGET_PPC64
861 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
862 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
863 if (env->slb[i].esid & SLB_ESID_V) {
864 sregs.u.s.ppc64.slb[i].slbe |= i;
865 }
866 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
867 }
868 #endif
869
870 /* Sync SRs */
871 for (i = 0; i < 16; i++) {
872 sregs.u.s.ppc32.sr[i] = env->sr[i];
873 }
874
875 /* Sync BATs */
876 for (i = 0; i < 8; i++) {
877 /* Beware. We have to swap upper and lower bits here */
878 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
879 | env->DBAT[1][i];
880 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
881 | env->IBAT[1][i];
882 }
883
884 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
885 }
886
887 int kvm_arch_put_registers(CPUState *cs, int level)
888 {
889 PowerPCCPU *cpu = POWERPC_CPU(cs);
890 CPUPPCState *env = &cpu->env;
891 struct kvm_regs regs;
892 int ret;
893 int i;
894
895 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
896 if (ret < 0) {
897 return ret;
898 }
899
900 regs.ctr = env->ctr;
901 regs.lr = env->lr;
902 regs.xer = cpu_read_xer(env);
903 regs.msr = env->msr;
904 regs.pc = env->nip;
905
906 regs.srr0 = env->spr[SPR_SRR0];
907 regs.srr1 = env->spr[SPR_SRR1];
908
909 regs.sprg0 = env->spr[SPR_SPRG0];
910 regs.sprg1 = env->spr[SPR_SPRG1];
911 regs.sprg2 = env->spr[SPR_SPRG2];
912 regs.sprg3 = env->spr[SPR_SPRG3];
913 regs.sprg4 = env->spr[SPR_SPRG4];
914 regs.sprg5 = env->spr[SPR_SPRG5];
915 regs.sprg6 = env->spr[SPR_SPRG6];
916 regs.sprg7 = env->spr[SPR_SPRG7];
917
918 regs.pid = env->spr[SPR_BOOKE_PID];
919
920 for (i = 0; i < 32; i++) {
921 regs.gpr[i] = env->gpr[i];
922 }
923
924 regs.cr = 0;
925 for (i = 0; i < 8; i++) {
926 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
927 }
928
929 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
930 if (ret < 0) {
931 return ret;
932 }
933
934 kvm_put_fp(cs);
935
936 if (env->tlb_dirty) {
937 kvm_sw_tlb_put(cpu);
938 env->tlb_dirty = false;
939 }
940
941 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
942 ret = kvmppc_put_books_sregs(cpu);
943 if (ret < 0) {
944 return ret;
945 }
946 }
947
948 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
949 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
950 }
951
952 if (cap_one_reg) {
953 int i;
954
955 /*
956 * We deliberately ignore errors here, for kernels which have
957 * the ONE_REG calls, but don't support the specific
958 * registers, there's a reasonable chance things will still
959 * work, at least until we try to migrate.
960 */
961 for (i = 0; i < 1024; i++) {
962 uint64_t id = env->spr_cb[i].one_reg_id;
963
964 if (id != 0) {
965 kvm_put_one_spr(cs, id, i);
966 }
967 }
968
969 #ifdef TARGET_PPC64
970 if (msr_ts) {
971 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
972 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
973 }
974 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
975 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
976 }
977 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
979 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
987 }
988
989 if (cap_papr) {
990 if (kvm_put_vpa(cs) < 0) {
991 trace_kvm_failed_put_vpa();
992 }
993 }
994
995 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
996 #endif /* TARGET_PPC64 */
997 }
998
999 return ret;
1000 }
1001
1002 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1003 {
1004 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1005 }
1006
1007 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1008 {
1009 CPUPPCState *env = &cpu->env;
1010 struct kvm_sregs sregs;
1011 int ret;
1012
1013 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1014 if (ret < 0) {
1015 return ret;
1016 }
1017
1018 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1019 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1020 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1021 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1022 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1023 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1024 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1025 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1026 env->spr[SPR_DECR] = sregs.u.e.dec;
1027 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1028 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1029 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1030 }
1031
1032 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1033 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1034 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1035 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1036 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1037 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1038 }
1039
1040 if (sregs.u.e.features & KVM_SREGS_E_64) {
1041 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1042 }
1043
1044 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1045 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1046 }
1047
1048 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1049 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1050 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1051 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1052 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1053 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1054 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1055 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1056 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1057 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1058 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1059 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1060 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1061 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1062 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1063 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1064 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1065 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1066 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1067 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1068 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1069 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1070 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1071 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1072 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1073 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1074 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1075 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1076 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1077 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1078 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1079 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1080 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1081
1082 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1083 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1084 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1085 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1086 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1087 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1088 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1089 }
1090
1091 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1092 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1093 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1094 }
1095
1096 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1097 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1098 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1099 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1100 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1101 }
1102 }
1103
1104 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1105 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1106 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1107 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1108 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1109 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1110 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1111 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1112 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1113 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1114 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1115 }
1116
1117 if (sregs.u.e.features & KVM_SREGS_EXP) {
1118 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1119 }
1120
1121 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1122 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1123 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1124 }
1125
1126 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1127 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1128 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1129 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1130
1131 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1132 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1133 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1134 }
1135 }
1136
1137 return 0;
1138 }
1139
1140 static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1141 {
1142 CPUPPCState *env = &cpu->env;
1143 struct kvm_sregs sregs;
1144 int ret;
1145 int i;
1146
1147 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1148 if (ret < 0) {
1149 return ret;
1150 }
1151
1152 if (!cpu->vhyp) {
1153 ppc_store_sdr1(env, sregs.u.s.sdr1);
1154 }
1155
1156 /* Sync SLB */
1157 #ifdef TARGET_PPC64
1158 /*
1159 * The packed SLB array we get from KVM_GET_SREGS only contains
1160 * information about valid entries. So we flush our internal copy
1161 * to get rid of stale ones, then put all valid SLB entries back
1162 * in.
1163 */
1164 memset(env->slb, 0, sizeof(env->slb));
1165 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1166 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1167 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1168 /*
1169 * Only restore valid entries
1170 */
1171 if (rb & SLB_ESID_V) {
1172 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1173 }
1174 }
1175 #endif
1176
1177 /* Sync SRs */
1178 for (i = 0; i < 16; i++) {
1179 env->sr[i] = sregs.u.s.ppc32.sr[i];
1180 }
1181
1182 /* Sync BATs */
1183 for (i = 0; i < 8; i++) {
1184 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1185 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1186 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1187 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1188 }
1189
1190 return 0;
1191 }
1192
1193 int kvm_arch_get_registers(CPUState *cs)
1194 {
1195 PowerPCCPU *cpu = POWERPC_CPU(cs);
1196 CPUPPCState *env = &cpu->env;
1197 struct kvm_regs regs;
1198 uint32_t cr;
1199 int i, ret;
1200
1201 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
1202 if (ret < 0) {
1203 return ret;
1204 }
1205
1206 cr = regs.cr;
1207 for (i = 7; i >= 0; i--) {
1208 env->crf[i] = cr & 15;
1209 cr >>= 4;
1210 }
1211
1212 env->ctr = regs.ctr;
1213 env->lr = regs.lr;
1214 cpu_write_xer(env, regs.xer);
1215 env->msr = regs.msr;
1216 env->nip = regs.pc;
1217
1218 env->spr[SPR_SRR0] = regs.srr0;
1219 env->spr[SPR_SRR1] = regs.srr1;
1220
1221 env->spr[SPR_SPRG0] = regs.sprg0;
1222 env->spr[SPR_SPRG1] = regs.sprg1;
1223 env->spr[SPR_SPRG2] = regs.sprg2;
1224 env->spr[SPR_SPRG3] = regs.sprg3;
1225 env->spr[SPR_SPRG4] = regs.sprg4;
1226 env->spr[SPR_SPRG5] = regs.sprg5;
1227 env->spr[SPR_SPRG6] = regs.sprg6;
1228 env->spr[SPR_SPRG7] = regs.sprg7;
1229
1230 env->spr[SPR_BOOKE_PID] = regs.pid;
1231
1232 for (i = 0; i < 32; i++) {
1233 env->gpr[i] = regs.gpr[i];
1234 }
1235
1236 kvm_get_fp(cs);
1237
1238 if (cap_booke_sregs) {
1239 ret = kvmppc_get_booke_sregs(cpu);
1240 if (ret < 0) {
1241 return ret;
1242 }
1243 }
1244
1245 if (cap_segstate) {
1246 ret = kvmppc_get_books_sregs(cpu);
1247 if (ret < 0) {
1248 return ret;
1249 }
1250 }
1251
1252 if (cap_hior) {
1253 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1254 }
1255
1256 if (cap_one_reg) {
1257 int i;
1258
1259 /*
1260 * We deliberately ignore errors here, for kernels which have
1261 * the ONE_REG calls, but don't support the specific
1262 * registers, there's a reasonable chance things will still
1263 * work, at least until we try to migrate.
1264 */
1265 for (i = 0; i < 1024; i++) {
1266 uint64_t id = env->spr_cb[i].one_reg_id;
1267
1268 if (id != 0) {
1269 kvm_get_one_spr(cs, id, i);
1270 }
1271 }
1272
1273 #ifdef TARGET_PPC64
1274 if (msr_ts) {
1275 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1276 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1277 }
1278 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1279 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1280 }
1281 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1282 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1284 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1291 }
1292
1293 if (cap_papr) {
1294 if (kvm_get_vpa(cs) < 0) {
1295 trace_kvm_failed_get_vpa();
1296 }
1297 }
1298
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1300 #endif
1301 }
1302
1303 return 0;
1304 }
1305
1306 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
1307 {
1308 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1309
1310 if (irq != PPC_INTERRUPT_EXT) {
1311 return 0;
1312 }
1313
1314 if (!kvm_enabled() || !cap_interrupt_unset) {
1315 return 0;
1316 }
1317
1318 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
1319
1320 return 0;
1321 }
1322
1323 #if defined(TARGET_PPC64)
1324 #define PPC_INPUT_INT PPC970_INPUT_INT
1325 #else
1326 #define PPC_INPUT_INT PPC6xx_INPUT_INT
1327 #endif
1328
1329 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
1330 {
1331 return;
1332 }
1333
1334 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
1335 {
1336 return MEMTXATTRS_UNSPECIFIED;
1337 }
1338
1339 int kvm_arch_process_async_events(CPUState *cs)
1340 {
1341 return cs->halted;
1342 }
1343
1344 static int kvmppc_handle_halt(PowerPCCPU *cpu)
1345 {
1346 CPUState *cs = CPU(cpu);
1347 CPUPPCState *env = &cpu->env;
1348
1349 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1350 cs->halted = 1;
1351 cs->exception_index = EXCP_HLT;
1352 }
1353
1354 return 0;
1355 }
1356
1357 /* map dcr access to existing qemu dcr emulation */
1358 static int kvmppc_handle_dcr_read(CPUPPCState *env,
1359 uint32_t dcrn, uint32_t *data)
1360 {
1361 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
1362 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1363 }
1364
1365 return 0;
1366 }
1367
1368 static int kvmppc_handle_dcr_write(CPUPPCState *env,
1369 uint32_t dcrn, uint32_t data)
1370 {
1371 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
1372 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1373 }
1374
1375 return 0;
1376 }
1377
1378 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1379 {
1380 /* Mixed endian case is not handled */
1381 uint32_t sc = debug_inst_opcode;
1382
1383 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1384 sizeof(sc), 0) ||
1385 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1386 return -EINVAL;
1387 }
1388
1389 return 0;
1390 }
1391
1392 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1393 {
1394 uint32_t sc;
1395
1396 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1397 sc != debug_inst_opcode ||
1398 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1399 sizeof(sc), 1)) {
1400 return -EINVAL;
1401 }
1402
1403 return 0;
1404 }
1405
1406 static int find_hw_breakpoint(target_ulong addr, int type)
1407 {
1408 int n;
1409
1410 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1411 <= ARRAY_SIZE(hw_debug_points));
1412
1413 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1414 if (hw_debug_points[n].addr == addr &&
1415 hw_debug_points[n].type == type) {
1416 return n;
1417 }
1418 }
1419
1420 return -1;
1421 }
1422
1423 static int find_hw_watchpoint(target_ulong addr, int *flag)
1424 {
1425 int n;
1426
1427 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1428 if (n >= 0) {
1429 *flag = BP_MEM_ACCESS;
1430 return n;
1431 }
1432
1433 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1434 if (n >= 0) {
1435 *flag = BP_MEM_WRITE;
1436 return n;
1437 }
1438
1439 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1440 if (n >= 0) {
1441 *flag = BP_MEM_READ;
1442 return n;
1443 }
1444
1445 return -1;
1446 }
1447
1448 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1449 target_ulong len, int type)
1450 {
1451 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1452 return -ENOBUFS;
1453 }
1454
1455 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1456 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1457
1458 switch (type) {
1459 case GDB_BREAKPOINT_HW:
1460 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1461 return -ENOBUFS;
1462 }
1463
1464 if (find_hw_breakpoint(addr, type) >= 0) {
1465 return -EEXIST;
1466 }
1467
1468 nb_hw_breakpoint++;
1469 break;
1470
1471 case GDB_WATCHPOINT_WRITE:
1472 case GDB_WATCHPOINT_READ:
1473 case GDB_WATCHPOINT_ACCESS:
1474 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1475 return -ENOBUFS;
1476 }
1477
1478 if (find_hw_breakpoint(addr, type) >= 0) {
1479 return -EEXIST;
1480 }
1481
1482 nb_hw_watchpoint++;
1483 break;
1484
1485 default:
1486 return -ENOSYS;
1487 }
1488
1489 return 0;
1490 }
1491
1492 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1493 target_ulong len, int type)
1494 {
1495 int n;
1496
1497 n = find_hw_breakpoint(addr, type);
1498 if (n < 0) {
1499 return -ENOENT;
1500 }
1501
1502 switch (type) {
1503 case GDB_BREAKPOINT_HW:
1504 nb_hw_breakpoint--;
1505 break;
1506
1507 case GDB_WATCHPOINT_WRITE:
1508 case GDB_WATCHPOINT_READ:
1509 case GDB_WATCHPOINT_ACCESS:
1510 nb_hw_watchpoint--;
1511 break;
1512
1513 default:
1514 return -ENOSYS;
1515 }
1516 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1517
1518 return 0;
1519 }
1520
1521 void kvm_arch_remove_all_hw_breakpoints(void)
1522 {
1523 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1524 }
1525
1526 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1527 {
1528 int n;
1529
1530 /* Software Breakpoint updates */
1531 if (kvm_sw_breakpoints_active(cs)) {
1532 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1533 }
1534
1535 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1536 <= ARRAY_SIZE(hw_debug_points));
1537 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1538
1539 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1540 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1541 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1542 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1543 switch (hw_debug_points[n].type) {
1544 case GDB_BREAKPOINT_HW:
1545 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1546 break;
1547 case GDB_WATCHPOINT_WRITE:
1548 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1549 break;
1550 case GDB_WATCHPOINT_READ:
1551 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1552 break;
1553 case GDB_WATCHPOINT_ACCESS:
1554 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1555 KVMPPC_DEBUG_WATCH_READ;
1556 break;
1557 default:
1558 cpu_abort(cs, "Unsupported breakpoint type\n");
1559 }
1560 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1561 }
1562 }
1563 }
1564
1565 static int kvm_handle_hw_breakpoint(CPUState *cs,
1566 struct kvm_debug_exit_arch *arch_info)
1567 {
1568 int handle = 0;
1569 int n;
1570 int flag = 0;
1571
1572 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1573 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1574 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1575 if (n >= 0) {
1576 handle = 1;
1577 }
1578 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1579 KVMPPC_DEBUG_WATCH_WRITE)) {
1580 n = find_hw_watchpoint(arch_info->address, &flag);
1581 if (n >= 0) {
1582 handle = 1;
1583 cs->watchpoint_hit = &hw_watchpoint;
1584 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1585 hw_watchpoint.flags = flag;
1586 }
1587 }
1588 }
1589 return handle;
1590 }
1591
1592 static int kvm_handle_singlestep(void)
1593 {
1594 return 1;
1595 }
1596
1597 static int kvm_handle_sw_breakpoint(void)
1598 {
1599 return 1;
1600 }
1601
1602 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1603 {
1604 CPUState *cs = CPU(cpu);
1605 CPUPPCState *env = &cpu->env;
1606 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1607
1608 if (cs->singlestep_enabled) {
1609 return kvm_handle_singlestep();
1610 }
1611
1612 if (arch_info->status) {
1613 return kvm_handle_hw_breakpoint(cs, arch_info);
1614 }
1615
1616 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1617 return kvm_handle_sw_breakpoint();
1618 }
1619
1620 /*
1621 * QEMU is not able to handle debug exception, so inject
1622 * program exception to guest;
1623 * Yes program exception NOT debug exception !!
1624 * When QEMU is using debug resources then debug exception must
1625 * be always set. To achieve this we set MSR_DE and also set
1626 * MSRP_DEP so guest cannot change MSR_DE.
1627 * When emulating debug resource for guest we want guest
1628 * to control MSR_DE (enable/disable debug interrupt on need).
1629 * Supporting both configurations are NOT possible.
1630 * So the result is that we cannot share debug resources
1631 * between QEMU and Guest on BOOKE architecture.
1632 * In the current design QEMU gets the priority over guest,
1633 * this means that if QEMU is using debug resources then guest
1634 * cannot use them;
1635 * For software breakpoint QEMU uses a privileged instruction;
1636 * So there cannot be any reason that we are here for guest
1637 * set debug exception, only possibility is guest executed a
1638 * privileged / illegal instruction and that's why we are
1639 * injecting a program interrupt.
1640 */
1641 cpu_synchronize_state(cs);
1642 /*
1643 * env->nip is PC, so increment this by 4 to use
1644 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1645 */
1646 env->nip += 4;
1647 cs->exception_index = POWERPC_EXCP_PROGRAM;
1648 env->error_code = POWERPC_EXCP_INVAL;
1649 ppc_cpu_do_interrupt(cs);
1650
1651 return 0;
1652 }
1653
1654 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
1655 {
1656 PowerPCCPU *cpu = POWERPC_CPU(cs);
1657 CPUPPCState *env = &cpu->env;
1658 int ret;
1659
1660 qemu_mutex_lock_iothread();
1661
1662 switch (run->exit_reason) {
1663 case KVM_EXIT_DCR:
1664 if (run->dcr.is_write) {
1665 trace_kvm_handle_dcr_write();
1666 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1667 } else {
1668 trace_kvm_handle_dcr_read();
1669 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1670 }
1671 break;
1672 case KVM_EXIT_HLT:
1673 trace_kvm_handle_halt();
1674 ret = kvmppc_handle_halt(cpu);
1675 break;
1676 #if defined(TARGET_PPC64)
1677 case KVM_EXIT_PAPR_HCALL:
1678 trace_kvm_handle_papr_hcall();
1679 run->papr_hcall.ret = spapr_hypercall(cpu,
1680 run->papr_hcall.nr,
1681 run->papr_hcall.args);
1682 ret = 0;
1683 break;
1684 #endif
1685 case KVM_EXIT_EPR:
1686 trace_kvm_handle_epr();
1687 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
1688 ret = 0;
1689 break;
1690 case KVM_EXIT_WATCHDOG:
1691 trace_kvm_handle_watchdog_expiry();
1692 watchdog_perform_action();
1693 ret = 0;
1694 break;
1695
1696 case KVM_EXIT_DEBUG:
1697 trace_kvm_handle_debug_exception();
1698 if (kvm_handle_debug(cpu, run)) {
1699 ret = EXCP_DEBUG;
1700 break;
1701 }
1702 /* re-enter, this exception was guest-internal */
1703 ret = 0;
1704 break;
1705
1706 default:
1707 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1708 ret = -1;
1709 break;
1710 }
1711
1712 qemu_mutex_unlock_iothread();
1713 return ret;
1714 }
1715
1716 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1717 {
1718 CPUState *cs = CPU(cpu);
1719 uint32_t bits = tsr_bits;
1720 struct kvm_one_reg reg = {
1721 .id = KVM_REG_PPC_OR_TSR,
1722 .addr = (uintptr_t) &bits,
1723 };
1724
1725 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1726 }
1727
1728 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1729 {
1730
1731 CPUState *cs = CPU(cpu);
1732 uint32_t bits = tsr_bits;
1733 struct kvm_one_reg reg = {
1734 .id = KVM_REG_PPC_CLEAR_TSR,
1735 .addr = (uintptr_t) &bits,
1736 };
1737
1738 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1739 }
1740
1741 int kvmppc_set_tcr(PowerPCCPU *cpu)
1742 {
1743 CPUState *cs = CPU(cpu);
1744 CPUPPCState *env = &cpu->env;
1745 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1746
1747 struct kvm_one_reg reg = {
1748 .id = KVM_REG_PPC_TCR,
1749 .addr = (uintptr_t) &tcr,
1750 };
1751
1752 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1753 }
1754
1755 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1756 {
1757 CPUState *cs = CPU(cpu);
1758 int ret;
1759
1760 if (!kvm_enabled()) {
1761 return -1;
1762 }
1763
1764 if (!cap_ppc_watchdog) {
1765 printf("warning: KVM does not support watchdog");
1766 return -1;
1767 }
1768
1769 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
1770 if (ret < 0) {
1771 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1772 __func__, strerror(-ret));
1773 return ret;
1774 }
1775
1776 return ret;
1777 }
1778
1779 static int read_cpuinfo(const char *field, char *value, int len)
1780 {
1781 FILE *f;
1782 int ret = -1;
1783 int field_len = strlen(field);
1784 char line[512];
1785
1786 f = fopen("/proc/cpuinfo", "r");
1787 if (!f) {
1788 return -1;
1789 }
1790
1791 do {
1792 if (!fgets(line, sizeof(line), f)) {
1793 break;
1794 }
1795 if (!strncmp(line, field, field_len)) {
1796 pstrcpy(value, len, line);
1797 ret = 0;
1798 break;
1799 }
1800 } while (*line);
1801
1802 fclose(f);
1803
1804 return ret;
1805 }
1806
1807 uint32_t kvmppc_get_tbfreq(void)
1808 {
1809 char line[512];
1810 char *ns;
1811 uint32_t retval = NANOSECONDS_PER_SECOND;
1812
1813 if (read_cpuinfo("timebase", line, sizeof(line))) {
1814 return retval;
1815 }
1816
1817 ns = strchr(line, ':');
1818 if (!ns) {
1819 return retval;
1820 }
1821
1822 ns++;
1823
1824 return atoi(ns);
1825 }
1826
1827 bool kvmppc_get_host_serial(char **value)
1828 {
1829 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1830 NULL);
1831 }
1832
1833 bool kvmppc_get_host_model(char **value)
1834 {
1835 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1836 }
1837
1838 /* Try to find a device tree node for a CPU with clock-frequency property */
1839 static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1840 {
1841 struct dirent *dirp;
1842 DIR *dp;
1843
1844 dp = opendir(PROC_DEVTREE_CPU);
1845 if (!dp) {
1846 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1847 return -1;
1848 }
1849
1850 buf[0] = '\0';
1851 while ((dirp = readdir(dp)) != NULL) {
1852 FILE *f;
1853 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1854 dirp->d_name);
1855 f = fopen(buf, "r");
1856 if (f) {
1857 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1858 fclose(f);
1859 break;
1860 }
1861 buf[0] = '\0';
1862 }
1863 closedir(dp);
1864 if (buf[0] == '\0') {
1865 printf("Unknown host!\n");
1866 return -1;
1867 }
1868
1869 return 0;
1870 }
1871
1872 static uint64_t kvmppc_read_int_dt(const char *filename)
1873 {
1874 union {
1875 uint32_t v32;
1876 uint64_t v64;
1877 } u;
1878 FILE *f;
1879 int len;
1880
1881 f = fopen(filename, "rb");
1882 if (!f) {
1883 return -1;
1884 }
1885
1886 len = fread(&u, 1, sizeof(u), f);
1887 fclose(f);
1888 switch (len) {
1889 case 4:
1890 /* property is a 32-bit quantity */
1891 return be32_to_cpu(u.v32);
1892 case 8:
1893 return be64_to_cpu(u.v64);
1894 }
1895
1896 return 0;
1897 }
1898
1899 /*
1900 * Read a CPU node property from the host device tree that's a single
1901 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1902 * (can't find or open the property, or doesn't understand the format)
1903 */
1904 static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1905 {
1906 char buf[PATH_MAX], *tmp;
1907 uint64_t val;
1908
1909 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1910 return -1;
1911 }
1912
1913 tmp = g_strdup_printf("%s/%s", buf, propname);
1914 val = kvmppc_read_int_dt(tmp);
1915 g_free(tmp);
1916
1917 return val;
1918 }
1919
1920 uint64_t kvmppc_get_clockfreq(void)
1921 {
1922 return kvmppc_read_int_cpu_dt("clock-frequency");
1923 }
1924
1925 static int kvmppc_get_dec_bits(void)
1926 {
1927 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1928
1929 if (nr_bits > 0) {
1930 return nr_bits;
1931 }
1932 return 0;
1933 }
1934
1935 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
1936 {
1937 CPUState *cs = env_cpu(env);
1938
1939 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1940 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1941 return 0;
1942 }
1943
1944 return 1;
1945 }
1946
1947 int kvmppc_get_hasidle(CPUPPCState *env)
1948 {
1949 struct kvm_ppc_pvinfo pvinfo;
1950
1951 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1952 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1953 return 1;
1954 }
1955
1956 return 0;
1957 }
1958
1959 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
1960 {
1961 uint32_t *hc = (uint32_t *)buf;
1962 struct kvm_ppc_pvinfo pvinfo;
1963
1964 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
1965 memcpy(buf, pvinfo.hcall, buf_len);
1966 return 0;
1967 }
1968
1969 /*
1970 * Fallback to always fail hypercalls regardless of endianness:
1971 *
1972 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
1973 * li r3, -1
1974 * b .+8 (becomes nop in wrong endian)
1975 * bswap32(li r3, -1)
1976 */
1977
1978 hc[0] = cpu_to_be32(0x08000048);
1979 hc[1] = cpu_to_be32(0x3860ffff);
1980 hc[2] = cpu_to_be32(0x48000008);
1981 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
1982
1983 return 1;
1984 }
1985
1986 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
1987 {
1988 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
1989 }
1990
1991 void kvmppc_enable_logical_ci_hcalls(void)
1992 {
1993 /*
1994 * FIXME: it would be nice if we could detect the cases where
1995 * we're using a device which requires the in kernel
1996 * implementation of these hcalls, but the kernel lacks them and
1997 * produce a warning.
1998 */
1999 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2000 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2001 }
2002
2003 void kvmppc_enable_set_mode_hcall(void)
2004 {
2005 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2006 }
2007
2008 void kvmppc_enable_clear_ref_mod_hcalls(void)
2009 {
2010 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2011 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2012 }
2013
2014 void kvmppc_enable_h_page_init(void)
2015 {
2016 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2017 }
2018
2019 void kvmppc_set_papr(PowerPCCPU *cpu)
2020 {
2021 CPUState *cs = CPU(cpu);
2022 int ret;
2023
2024 if (!kvm_enabled()) {
2025 return;
2026 }
2027
2028 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
2029 if (ret) {
2030 error_report("This vCPU type or KVM version does not support PAPR");
2031 exit(1);
2032 }
2033
2034 /*
2035 * Update the capability flag so we sync the right information
2036 * with kvm
2037 */
2038 cap_papr = 1;
2039 }
2040
2041 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
2042 {
2043 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
2044 }
2045
2046 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2047 {
2048 CPUState *cs = CPU(cpu);
2049 int ret;
2050
2051 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
2052 if (ret && mpic_proxy) {
2053 error_report("This KVM version does not support EPR");
2054 exit(1);
2055 }
2056 }
2057
2058 int kvmppc_smt_threads(void)
2059 {
2060 return cap_ppc_smt ? cap_ppc_smt : 1;
2061 }
2062
2063 int kvmppc_set_smt_threads(int smt)
2064 {
2065 int ret;
2066
2067 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2068 if (!ret) {
2069 cap_ppc_smt = smt;
2070 }
2071 return ret;
2072 }
2073
2074 void kvmppc_hint_smt_possible(Error **errp)
2075 {
2076 int i;
2077 GString *g;
2078 char *s;
2079
2080 assert(kvm_enabled());
2081 if (cap_ppc_smt_possible) {
2082 g = g_string_new("Available VSMT modes:");
2083 for (i = 63; i >= 0; i--) {
2084 if ((1UL << i) & cap_ppc_smt_possible) {
2085 g_string_append_printf(g, " %lu", (1UL << i));
2086 }
2087 }
2088 s = g_string_free(g, false);
2089 error_append_hint(errp, "%s.\n", s);
2090 g_free(s);
2091 } else {
2092 error_append_hint(errp,
2093 "This KVM seems to be too old to support VSMT.\n");
2094 }
2095 }
2096
2097
2098 #ifdef TARGET_PPC64
2099 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2100 {
2101 struct kvm_ppc_smmu_info info;
2102 long rampagesize, best_page_shift;
2103 int i;
2104
2105 /*
2106 * Find the largest hardware supported page size that's less than
2107 * or equal to the (logical) backing page size of guest RAM
2108 */
2109 kvm_get_smmu_info(&info, &error_fatal);
2110 rampagesize = qemu_minrampagesize();
2111 best_page_shift = 0;
2112
2113 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2114 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2115
2116 if (!sps->page_shift) {
2117 continue;
2118 }
2119
2120 if ((sps->page_shift > best_page_shift)
2121 && ((1UL << sps->page_shift) <= rampagesize)) {
2122 best_page_shift = sps->page_shift;
2123 }
2124 }
2125
2126 return MIN(current_size,
2127 1ULL << (best_page_shift + hash_shift - 7));
2128 }
2129 #endif
2130
2131 bool kvmppc_spapr_use_multitce(void)
2132 {
2133 return cap_spapr_multitce;
2134 }
2135
2136 int kvmppc_spapr_enable_inkernel_multitce(void)
2137 {
2138 int ret;
2139
2140 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2141 H_PUT_TCE_INDIRECT, 1);
2142 if (!ret) {
2143 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2144 H_STUFF_TCE, 1);
2145 }
2146
2147 return ret;
2148 }
2149
2150 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2151 uint64_t bus_offset, uint32_t nb_table,
2152 int *pfd, bool need_vfio)
2153 {
2154 long len;
2155 int fd;
2156 void *table;
2157
2158 /*
2159 * Must set fd to -1 so we don't try to munmap when called for
2160 * destroying the table, which the upper layers -will- do
2161 */
2162 *pfd = -1;
2163 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
2164 return NULL;
2165 }
2166
2167 if (cap_spapr_tce_64) {
2168 struct kvm_create_spapr_tce_64 args = {
2169 .liobn = liobn,
2170 .page_shift = page_shift,
2171 .offset = bus_offset >> page_shift,
2172 .size = nb_table,
2173 .flags = 0
2174 };
2175 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2176 if (fd < 0) {
2177 fprintf(stderr,
2178 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2179 liobn);
2180 return NULL;
2181 }
2182 } else if (cap_spapr_tce) {
2183 uint64_t window_size = (uint64_t) nb_table << page_shift;
2184 struct kvm_create_spapr_tce args = {
2185 .liobn = liobn,
2186 .window_size = window_size,
2187 };
2188 if ((window_size != args.window_size) || bus_offset) {
2189 return NULL;
2190 }
2191 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2192 if (fd < 0) {
2193 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2194 liobn);
2195 return NULL;
2196 }
2197 } else {
2198 return NULL;
2199 }
2200
2201 len = nb_table * sizeof(uint64_t);
2202 /* FIXME: round this up to page size */
2203
2204 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
2205 if (table == MAP_FAILED) {
2206 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2207 liobn);
2208 close(fd);
2209 return NULL;
2210 }
2211
2212 *pfd = fd;
2213 return table;
2214 }
2215
2216 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
2217 {
2218 long len;
2219
2220 if (fd < 0) {
2221 return -1;
2222 }
2223
2224 len = nb_table * sizeof(uint64_t);
2225 if ((munmap(table, len) < 0) ||
2226 (close(fd) < 0)) {
2227 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2228 strerror(errno));
2229 /* Leak the table */
2230 }
2231
2232 return 0;
2233 }
2234
2235 int kvmppc_reset_htab(int shift_hint)
2236 {
2237 uint32_t shift = shift_hint;
2238
2239 if (!kvm_enabled()) {
2240 /* Full emulation, tell caller to allocate htab itself */
2241 return 0;
2242 }
2243 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
2244 int ret;
2245 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
2246 if (ret == -ENOTTY) {
2247 /*
2248 * At least some versions of PR KVM advertise the
2249 * capability, but don't implement the ioctl(). Oops.
2250 * Return 0 so that we allocate the htab in qemu, as is
2251 * correct for PR.
2252 */
2253 return 0;
2254 } else if (ret < 0) {
2255 return ret;
2256 }
2257 return shift;
2258 }
2259
2260 /*
2261 * We have a kernel that predates the htab reset calls. For PR
2262 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2263 * this era, it has allocated a 16MB fixed size hash table
2264 * already.
2265 */
2266 if (kvmppc_is_pr(kvm_state)) {
2267 /* PR - tell caller to allocate htab */
2268 return 0;
2269 } else {
2270 /* HV - assume 16MB kernel allocated htab */
2271 return 24;
2272 }
2273 }
2274
2275 static inline uint32_t mfpvr(void)
2276 {
2277 uint32_t pvr;
2278
2279 asm ("mfpvr %0"
2280 : "=r"(pvr));
2281 return pvr;
2282 }
2283
2284 static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2285 {
2286 if (on) {
2287 *word |= flags;
2288 } else {
2289 *word &= ~flags;
2290 }
2291 }
2292
2293 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2294 {
2295 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2296 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2297 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
2298
2299 /* Now fix up the class with information we can query from the host */
2300 pcc->pvr = mfpvr();
2301
2302 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2303 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2304 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2305 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2306 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2307 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
2308
2309 if (dcache_size != -1) {
2310 pcc->l1_dcache_size = dcache_size;
2311 }
2312
2313 if (icache_size != -1) {
2314 pcc->l1_icache_size = icache_size;
2315 }
2316
2317 #if defined(TARGET_PPC64)
2318 pcc->radix_page_info = kvm_get_radix_page_info();
2319
2320 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2321 /*
2322 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2323 * compliant. More importantly, advertising ISA 3.00
2324 * architected mode may prevent guests from activating
2325 * necessary DD1 workarounds.
2326 */
2327 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2328 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2329 }
2330 #endif /* defined(TARGET_PPC64) */
2331 }
2332
2333 bool kvmppc_has_cap_epr(void)
2334 {
2335 return cap_epr;
2336 }
2337
2338 bool kvmppc_has_cap_fixup_hcalls(void)
2339 {
2340 return cap_fixup_hcalls;
2341 }
2342
2343 bool kvmppc_has_cap_htm(void)
2344 {
2345 return cap_htm;
2346 }
2347
2348 bool kvmppc_has_cap_mmu_radix(void)
2349 {
2350 return cap_mmu_radix;
2351 }
2352
2353 bool kvmppc_has_cap_mmu_hash_v3(void)
2354 {
2355 return cap_mmu_hash_v3;
2356 }
2357
2358 static bool kvmppc_power8_host(void)
2359 {
2360 bool ret = false;
2361 #ifdef TARGET_PPC64
2362 {
2363 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2364 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2365 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2366 (base_pvr == CPU_POWERPC_POWER8_BASE);
2367 }
2368 #endif /* TARGET_PPC64 */
2369 return ret;
2370 }
2371
2372 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2373 {
2374 bool l1d_thread_priv_req = !kvmppc_power8_host();
2375
2376 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2377 return 2;
2378 } else if ((!l1d_thread_priv_req ||
2379 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
2380 (c.character & c.character_mask
2381 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2382 return 1;
2383 }
2384
2385 return 0;
2386 }
2387
2388 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2389 {
2390 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2391 return 2;
2392 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2393 return 1;
2394 }
2395
2396 return 0;
2397 }
2398
2399 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2400 {
2401 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2402 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2403 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2404 return SPAPR_CAP_FIXED_NA;
2405 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2406 return SPAPR_CAP_WORKAROUND;
2407 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2408 return SPAPR_CAP_FIXED_CCD;
2409 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2410 return SPAPR_CAP_FIXED_IBS;
2411 }
2412
2413 return 0;
2414 }
2415
2416 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2417 {
2418 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2419 return 1;
2420 }
2421 return 0;
2422 }
2423
2424 bool kvmppc_has_cap_xive(void)
2425 {
2426 return cap_xive;
2427 }
2428
2429 static void kvmppc_get_cpu_characteristics(KVMState *s)
2430 {
2431 struct kvm_ppc_cpu_char c;
2432 int ret;
2433
2434 /* Assume broken */
2435 cap_ppc_safe_cache = 0;
2436 cap_ppc_safe_bounds_check = 0;
2437 cap_ppc_safe_indirect_branch = 0;
2438
2439 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2440 if (!ret) {
2441 return;
2442 }
2443 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2444 if (ret < 0) {
2445 return;
2446 }
2447
2448 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2449 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2450 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
2451 cap_ppc_count_cache_flush_assist =
2452 parse_cap_ppc_count_cache_flush_assist(c);
2453 }
2454
2455 int kvmppc_get_cap_safe_cache(void)
2456 {
2457 return cap_ppc_safe_cache;
2458 }
2459
2460 int kvmppc_get_cap_safe_bounds_check(void)
2461 {
2462 return cap_ppc_safe_bounds_check;
2463 }
2464
2465 int kvmppc_get_cap_safe_indirect_branch(void)
2466 {
2467 return cap_ppc_safe_indirect_branch;
2468 }
2469
2470 int kvmppc_get_cap_count_cache_flush_assist(void)
2471 {
2472 return cap_ppc_count_cache_flush_assist;
2473 }
2474
2475 bool kvmppc_has_cap_nested_kvm_hv(void)
2476 {
2477 return !!cap_ppc_nested_kvm_hv;
2478 }
2479
2480 int kvmppc_set_cap_nested_kvm_hv(int enable)
2481 {
2482 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2483 }
2484
2485 bool kvmppc_has_cap_spapr_vfio(void)
2486 {
2487 return cap_spapr_vfio;
2488 }
2489
2490 int kvmppc_get_cap_large_decr(void)
2491 {
2492 return cap_large_decr;
2493 }
2494
2495 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2496 {
2497 CPUState *cs = CPU(cpu);
2498 uint64_t lpcr;
2499
2500 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2501 /* Do we need to modify the LPCR? */
2502 if (!!(lpcr & LPCR_LD) != !!enable) {
2503 if (enable) {
2504 lpcr |= LPCR_LD;
2505 } else {
2506 lpcr &= ~LPCR_LD;
2507 }
2508 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2509 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2510
2511 if (!!(lpcr & LPCR_LD) != !!enable) {
2512 return -1;
2513 }
2514 }
2515
2516 return 0;
2517 }
2518
2519 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2520 {
2521 uint32_t host_pvr = mfpvr();
2522 PowerPCCPUClass *pvr_pcc;
2523
2524 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2525 if (pvr_pcc == NULL) {
2526 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2527 }
2528
2529 return pvr_pcc;
2530 }
2531
2532 static int kvm_ppc_register_host_cpu_type(MachineState *ms)
2533 {
2534 TypeInfo type_info = {
2535 .name = TYPE_HOST_POWERPC_CPU,
2536 .class_init = kvmppc_host_cpu_class_init,
2537 };
2538 MachineClass *mc = MACHINE_GET_CLASS(ms);
2539 PowerPCCPUClass *pvr_pcc;
2540 ObjectClass *oc;
2541 DeviceClass *dc;
2542 int i;
2543
2544 pvr_pcc = kvm_ppc_get_host_cpu_class();
2545 if (pvr_pcc == NULL) {
2546 return -1;
2547 }
2548 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2549 type_register(&type_info);
2550 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) {
2551 /* override TCG default cpu type with 'host' cpu model */
2552 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2553 }
2554
2555 oc = object_class_by_name(type_info.name);
2556 g_assert(oc);
2557
2558 /*
2559 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2560 * we want "POWER8" to be a "family" alias that points to the current
2561 * host CPU type, too)
2562 */
2563 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2564 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
2565 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
2566 char *suffix;
2567
2568 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
2569 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
2570 if (suffix) {
2571 *suffix = 0;
2572 }
2573 break;
2574 }
2575 }
2576
2577 return 0;
2578 }
2579
2580 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2581 {
2582 struct kvm_rtas_token_args args = {
2583 .token = token,
2584 };
2585
2586 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2587 return -ENOENT;
2588 }
2589
2590 strncpy(args.name, function, sizeof(args.name) - 1);
2591
2592 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2593 }
2594
2595 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
2596 {
2597 struct kvm_get_htab_fd s = {
2598 .flags = write ? KVM_GET_HTAB_WRITE : 0,
2599 .start_index = index,
2600 };
2601 int ret;
2602
2603 if (!cap_htab_fd) {
2604 error_setg(errp, "KVM version doesn't support %s the HPT",
2605 write ? "writing" : "reading");
2606 return -ENOTSUP;
2607 }
2608
2609 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2610 if (ret < 0) {
2611 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2612 write ? "writing" : "reading", write ? "to" : "from",
2613 strerror(errno));
2614 return -errno;
2615 }
2616
2617 return ret;
2618 }
2619
2620 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2621 {
2622 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2623 uint8_t buf[bufsize];
2624 ssize_t rc;
2625
2626 do {
2627 rc = read(fd, buf, bufsize);
2628 if (rc < 0) {
2629 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2630 strerror(errno));
2631 return rc;
2632 } else if (rc) {
2633 uint8_t *buffer = buf;
2634 ssize_t n = rc;
2635 while (n) {
2636 struct kvm_get_htab_header *head =
2637 (struct kvm_get_htab_header *) buffer;
2638 size_t chunksize = sizeof(*head) +
2639 HASH_PTE_SIZE_64 * head->n_valid;
2640
2641 qemu_put_be32(f, head->index);
2642 qemu_put_be16(f, head->n_valid);
2643 qemu_put_be16(f, head->n_invalid);
2644 qemu_put_buffer(f, (void *)(head + 1),
2645 HASH_PTE_SIZE_64 * head->n_valid);
2646
2647 buffer += chunksize;
2648 n -= chunksize;
2649 }
2650 }
2651 } while ((rc != 0)
2652 && ((max_ns < 0) ||
2653 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
2654
2655 return (rc == 0) ? 1 : 0;
2656 }
2657
2658 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2659 uint16_t n_valid, uint16_t n_invalid)
2660 {
2661 struct kvm_get_htab_header *buf;
2662 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
2663 ssize_t rc;
2664
2665 buf = alloca(chunksize);
2666 buf->index = index;
2667 buf->n_valid = n_valid;
2668 buf->n_invalid = n_invalid;
2669
2670 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
2671
2672 rc = write(fd, buf, chunksize);
2673 if (rc < 0) {
2674 fprintf(stderr, "Error writing KVM hash table: %s\n",
2675 strerror(errno));
2676 return rc;
2677 }
2678 if (rc != chunksize) {
2679 /* We should never get a short write on a single chunk */
2680 fprintf(stderr, "Short write, restoring KVM hash table\n");
2681 return -1;
2682 }
2683 return 0;
2684 }
2685
2686 bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
2687 {
2688 return true;
2689 }
2690
2691 void kvm_arch_init_irq_routing(KVMState *s)
2692 {
2693 }
2694
2695 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
2696 {
2697 int fd, rc;
2698 int i;
2699
2700 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
2701
2702 i = 0;
2703 while (i < n) {
2704 struct kvm_get_htab_header *hdr;
2705 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2706 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
2707
2708 rc = read(fd, buf, sizeof(buf));
2709 if (rc < 0) {
2710 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2711 }
2712
2713 hdr = (struct kvm_get_htab_header *)buf;
2714 while ((i < n) && ((char *)hdr < (buf + rc))) {
2715 int invalid = hdr->n_invalid, valid = hdr->n_valid;
2716
2717 if (hdr->index != (ptex + i)) {
2718 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2719 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2720 }
2721
2722 if (n - i < valid) {
2723 valid = n - i;
2724 }
2725 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2726 i += valid;
2727
2728 if ((n - i) < invalid) {
2729 invalid = n - i;
2730 }
2731 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
2732 i += invalid;
2733
2734 hdr = (struct kvm_get_htab_header *)
2735 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2736 }
2737 }
2738
2739 close(fd);
2740 }
2741
2742 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
2743 {
2744 int fd, rc;
2745 struct {
2746 struct kvm_get_htab_header hdr;
2747 uint64_t pte0;
2748 uint64_t pte1;
2749 } buf;
2750
2751 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
2752
2753 buf.hdr.n_valid = 1;
2754 buf.hdr.n_invalid = 0;
2755 buf.hdr.index = ptex;
2756 buf.pte0 = cpu_to_be64(pte0);
2757 buf.pte1 = cpu_to_be64(pte1);
2758
2759 rc = write(fd, &buf, sizeof(buf));
2760 if (rc != sizeof(buf)) {
2761 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2762 }
2763 close(fd);
2764 }
2765
2766 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2767 uint64_t address, uint32_t data, PCIDevice *dev)
2768 {
2769 return 0;
2770 }
2771
2772 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2773 int vector, PCIDevice *dev)
2774 {
2775 return 0;
2776 }
2777
2778 int kvm_arch_release_virq_post(int virq)
2779 {
2780 return 0;
2781 }
2782
2783 int kvm_arch_msi_data_to_gsi(uint32_t data)
2784 {
2785 return data & 0xffff;
2786 }
2787
2788 int kvmppc_enable_hwrng(void)
2789 {
2790 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2791 return -1;
2792 }
2793
2794 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2795 }
2796
2797 void kvmppc_check_papr_resize_hpt(Error **errp)
2798 {
2799 if (!kvm_enabled()) {
2800 return; /* No KVM, we're good */
2801 }
2802
2803 if (cap_resize_hpt) {
2804 return; /* Kernel has explicit support, we're good */
2805 }
2806
2807 /* Otherwise fallback on looking for PR KVM */
2808 if (kvmppc_is_pr(kvm_state)) {
2809 return;
2810 }
2811
2812 error_setg(errp,
2813 "Hash page table resizing not available with this KVM version");
2814 }
2815
2816 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2817 {
2818 CPUState *cs = CPU(cpu);
2819 struct kvm_ppc_resize_hpt rhpt = {
2820 .flags = flags,
2821 .shift = shift,
2822 };
2823
2824 if (!cap_resize_hpt) {
2825 return -ENOSYS;
2826 }
2827
2828 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2829 }
2830
2831 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2832 {
2833 CPUState *cs = CPU(cpu);
2834 struct kvm_ppc_resize_hpt rhpt = {
2835 .flags = flags,
2836 .shift = shift,
2837 };
2838
2839 if (!cap_resize_hpt) {
2840 return -ENOSYS;
2841 }
2842
2843 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2844 }
2845
2846 /*
2847 * This is a helper function to detect a post migration scenario
2848 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2849 * the guest kernel can't handle a PVR value other than the actual host
2850 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2851 *
2852 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2853 * (so, we're HV), return true. The workaround itself is done in
2854 * cpu_post_load.
2855 *
2856 * The order here is important: we'll only check for KVM PR as a
2857 * fallback if the guest kernel can't handle the situation itself.
2858 * We need to avoid as much as possible querying the running KVM type
2859 * in QEMU level.
2860 */
2861 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2862 {
2863 CPUState *cs = CPU(cpu);
2864
2865 if (!kvm_enabled()) {
2866 return false;
2867 }
2868
2869 if (cap_ppc_pvr_compat) {
2870 return false;
2871 }
2872
2873 return !kvmppc_is_pr(cs->kvm_state);
2874 }
2875
2876 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2877 {
2878 CPUState *cs = CPU(cpu);
2879
2880 if (kvm_enabled()) {
2881 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2882 }
2883 }
2884
2885 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2886 {
2887 CPUState *cs = CPU(cpu);
2888
2889 if (kvm_enabled()) {
2890 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2891 }
2892 }
QEMU mirror