target/ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "exec/exec-all.h"
   4 #include "sysemu/kvm.h"
   5 #include "helper_regs.h"
   6 #include "mmu-hash64.h"
   7 #include "migration/cpu.h"
   8 #include "qapi/error.h"
   9 #include "qemu/main-loop.h"
  10 #include "kvm_ppc.h"
  11 #include "power8-pmu.h"
  12
  13 static void post_load_update_msr(CPUPPCState *env)
  14 {
  15     target_ulong msr = env->msr;
  16
  17     /*
  18      * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
  19      * before restoring.  Note that this recomputes hflags.
  20      */
  21     env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
  22     ppc_store_msr(env, msr);
  23     pmu_update_summaries(env);
  24 }
  25
  26 static int get_avr(QEMUFile *f, void *pv, size_t size,
  27                    const VMStateField *field)
  28 {
  29     ppc_avr_t *v = pv;
  30
  31     v->u64[0] = qemu_get_be64(f);
  32     v->u64[1] = qemu_get_be64(f);
  33
  34     return 0;
  35 }
  36
  37 static int put_avr(QEMUFile *f, void *pv, size_t size,
  38                    const VMStateField *field, JSONWriter *vmdesc)
  39 {
  40     ppc_avr_t *v = pv;
  41
  42     qemu_put_be64(f, v->u64[0]);
  43     qemu_put_be64(f, v->u64[1]);
  44     return 0;
  45 }
  46
  47 static const VMStateInfo vmstate_info_avr = {
  48     .name = "avr",
  49     .get  = get_avr,
  50     .put  = put_avr,
  51 };
  52
  53 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
  54     VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t)
  55
  56 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
  57     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
  58
  59 static int get_fpr(QEMUFile *f, void *pv, size_t size,
  60                    const VMStateField *field)
  61 {
  62     ppc_vsr_t *v = pv;
  63
  64     v->VsrD(0) = qemu_get_be64(f);
  65
  66     return 0;
  67 }
  68
  69 static int put_fpr(QEMUFile *f, void *pv, size_t size,
  70                    const VMStateField *field, JSONWriter *vmdesc)
  71 {
  72     ppc_vsr_t *v = pv;
  73
  74     qemu_put_be64(f, v->VsrD(0));
  75     return 0;
  76 }
  77
  78 static const VMStateInfo vmstate_info_fpr = {
  79     .name = "fpr",
  80     .get  = get_fpr,
  81     .put  = put_fpr,
  82 };
  83
  84 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                       \
  85     VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t)
  86
  87 #define VMSTATE_FPR_ARRAY(_f, _s, _n)                             \
  88     VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
  89
  90 static int get_vsr(QEMUFile *f, void *pv, size_t size,
  91                    const VMStateField *field)
  92 {
  93     ppc_vsr_t *v = pv;
  94
  95     v->VsrD(1) = qemu_get_be64(f);
  96
  97     return 0;
  98 }
  99
 100 static int put_vsr(QEMUFile *f, void *pv, size_t size,
 101                    const VMStateField *field, JSONWriter *vmdesc)
 102 {
 103     ppc_vsr_t *v = pv;
 104
 105     qemu_put_be64(f, v->VsrD(1));
 106     return 0;
 107 }
 108
 109 static const VMStateInfo vmstate_info_vsr = {
 110     .name = "vsr",
 111     .get  = get_vsr,
 112     .put  = put_vsr,
 113 };
 114
 115 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v)                       \
 116     VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t)
 117
 118 #define VMSTATE_VSR_ARRAY(_f, _s, _n)                             \
 119     VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
 120
 121 static bool cpu_pre_2_8_migration(void *opaque, int version_id)
 122 {
 123     PowerPCCPU *cpu = opaque;
 124
 125     return cpu->pre_2_8_migration;
 126 }
 127
 128 #if defined(TARGET_PPC64)
 129 static bool cpu_pre_3_0_migration(void *opaque, int version_id)
 130 {
 131     PowerPCCPU *cpu = opaque;
 132
 133     return cpu->pre_3_0_migration;
 134 }
 135 #endif
 136
 137 static int cpu_pre_save(void *opaque)
 138 {
 139     PowerPCCPU *cpu = opaque;
 140     CPUPPCState *env = &cpu->env;
 141     int i;
 142     uint64_t insns_compat_mask =
 143         PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
 144         | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
 145         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
 146         | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
 147         | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
 148         | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
 149         | PPC_64B | PPC_64BX | PPC_ALTIVEC
 150         | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
 151     uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
 152         | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
 153         | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
 154         | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
 155         | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
 156         | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM;
 157
 158     env->spr[SPR_LR] = env->lr;
 159     env->spr[SPR_CTR] = env->ctr;
 160     env->spr[SPR_XER] = cpu_read_xer(env);
 161 #if defined(TARGET_PPC64)
 162     env->spr[SPR_CFAR] = env->cfar;
 163 #endif
 164     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 165
 166     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 167         env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i];
 168         env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i];
 169         env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i];
 170         env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i];
 171     }
 172     for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) {
 173         env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4];
 174         env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4];
 175         env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4];
 176         env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4];
 177     }
 178
 179     /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
 180     if (cpu->pre_2_8_migration) {
 181         /*
 182          * Mask out bits that got added to msr_mask since the versions
 183          * which stupidly included it in the migration stream.
 184          */
 185         target_ulong metamask = 0
 186 #if defined(TARGET_PPC64)
 187             | (1ULL << MSR_TS0)
 188             | (1ULL << MSR_TS1)
 189 #endif
 190             ;
 191         cpu->mig_msr_mask = env->msr_mask & ~metamask;
 192         cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
 193         /*
 194          * CPU models supported by old machines all have
 195          * PPC_MEM_TLBIE, so we set it unconditionally to allow
 196          * backward migration from a POWER9 host to a POWER8 host.
 197          */
 198         cpu->mig_insns_flags |= PPC_MEM_TLBIE;
 199         cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
 200         cpu->mig_nb_BATs = env->nb_BATs;
 201     }
 202     if (cpu->pre_3_0_migration) {
 203         if (cpu->hash64_opts) {
 204             cpu->mig_slb_nr = cpu->hash64_opts->slb_size;
 205         }
 206     }
 207
 208     /* Retain migration compatibility for pre 6.0 for 601 machines. */
 209     env->hflags_compat_nmsr = (env->flags & POWERPC_FLAG_HID0_LE
 210                                ? env->hflags & MSR_LE : 0);
 211
 212     return 0;
 213 }
 214
 215 /*
 216  * Determine if a given PVR is a "close enough" match to the CPU
 217  * object.  For TCG and KVM PR it would probably be sufficient to
 218  * require an exact PVR match.  However for KVM HV the user is
 219  * restricted to a PVR exactly matching the host CPU.  The correct way
 220  * to handle this is to put the guest into an architected
 221  * compatibility mode.  However, to allow a more forgiving transition
 222  * and migration from before this was widely done, we allow migration
 223  * between sufficiently similar PVRs, as determined by the CPU class's
 224  * pvr_match() hook.
 225  */
 226 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr)
 227 {
 228     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 229
 230     if (pvr == pcc->pvr) {
 231         return true;
 232     }
 233     return pcc->pvr_match(pcc, pvr);
 234 }
 235
 236 static int cpu_post_load(void *opaque, int version_id)
 237 {
 238     PowerPCCPU *cpu = opaque;
 239     CPUPPCState *env = &cpu->env;
 240     int i;
 241
 242     /*
 243      * If we're operating in compat mode, we should be ok as long as
 244      * the destination supports the same compatibility mode.
 245      *
 246      * Otherwise, however, we require that the destination has exactly
 247      * the same CPU model as the source.
 248      */
 249
 250 #if defined(TARGET_PPC64)
 251     if (cpu->compat_pvr) {
 252         uint32_t compat_pvr = cpu->compat_pvr;
 253         Error *local_err = NULL;
 254         int ret;
 255
 256         cpu->compat_pvr = 0;
 257         ret = ppc_set_compat(cpu, compat_pvr, &local_err);
 258         if (ret < 0) {
 259             error_report_err(local_err);
 260             return ret;
 261         }
 262     } else
 263 #endif
 264     {
 265         if (!pvr_match(cpu, env->spr[SPR_PVR])) {
 266             return -EINVAL;
 267         }
 268     }
 269
 270     /*
 271      * If we're running with KVM HV, there is a chance that the guest
 272      * is running with KVM HV and its kernel does not have the
 273      * capability of dealing with a different PVR other than this
 274      * exact host PVR in KVM_SET_SREGS. If that happens, the
 275      * guest freezes after migration.
 276      *
 277      * The function kvmppc_pvr_workaround_required does this verification
 278      * by first checking if the kernel has the cap, returning true immediately
 279      * if that is the case. Otherwise, it checks if we're running in KVM PR.
 280      * If the guest kernel does not have the cap and we're not running KVM-PR
 281      * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
 282      * receive the PVR it expects as a workaround.
 283      *
 284      */
 285     if (kvmppc_pvr_workaround_required(cpu)) {
 286         env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 287     }
 288
 289     env->lr = env->spr[SPR_LR];
 290     env->ctr = env->spr[SPR_CTR];
 291     cpu_write_xer(env, env->spr[SPR_XER]);
 292 #if defined(TARGET_PPC64)
 293     env->cfar = env->spr[SPR_CFAR];
 294 #endif
 295     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 296
 297     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 298         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i];
 299         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1];
 300         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i];
 301         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1];
 302     }
 303     for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) {
 304         env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i];
 305         env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1];
 306         env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i];
 307         env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1];
 308     }
 309
 310     if (!cpu->vhyp) {
 311         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 312     }
 313
 314     post_load_update_msr(env);
 315
 316     return 0;
 317 }
 318
 319 static bool fpu_needed(void *opaque)
 320 {
 321     PowerPCCPU *cpu = opaque;
 322
 323     return cpu->env.insns_flags & PPC_FLOAT;
 324 }
 325
 326 static const VMStateDescription vmstate_fpu = {
 327     .name = "cpu/fpu",
 328     .version_id = 1,
 329     .minimum_version_id = 1,
 330     .needed = fpu_needed,
 331     .fields = (VMStateField[]) {
 332         VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32),
 333         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 334         VMSTATE_END_OF_LIST()
 335     },
 336 };
 337
 338 static bool altivec_needed(void *opaque)
 339 {
 340     PowerPCCPU *cpu = opaque;
 341
 342     return cpu->env.insns_flags & PPC_ALTIVEC;
 343 }
 344
 345 static int get_vscr(QEMUFile *f, void *opaque, size_t size,
 346                     const VMStateField *field)
 347 {
 348     PowerPCCPU *cpu = opaque;
 349     ppc_store_vscr(&cpu->env, qemu_get_be32(f));
 350     return 0;
 351 }
 352
 353 static int put_vscr(QEMUFile *f, void *opaque, size_t size,
 354                     const VMStateField *field, JSONWriter *vmdesc)
 355 {
 356     PowerPCCPU *cpu = opaque;
 357     qemu_put_be32(f, ppc_get_vscr(&cpu->env));
 358     return 0;
 359 }
 360
 361 static const VMStateInfo vmstate_vscr = {
 362     .name = "cpu/altivec/vscr",
 363     .get = get_vscr,
 364     .put = put_vscr,
 365 };
 366
 367 static const VMStateDescription vmstate_altivec = {
 368     .name = "cpu/altivec",
 369     .version_id = 1,
 370     .minimum_version_id = 1,
 371     .needed = altivec_needed,
 372     .fields = (VMStateField[]) {
 373         VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32),
 374         /*
 375          * Save the architecture value of the vscr, not the internally
 376          * expanded version.  Since this architecture value does not
 377          * exist in memory to be stored, this requires a but of hoop
 378          * jumping.  We want OFFSET=0 so that we effectively pass CPU
 379          * to the helper functions.
 380          */
 381         {
 382             .name = "vscr",
 383             .version_id = 0,
 384             .size = sizeof(uint32_t),
 385             .info = &vmstate_vscr,
 386             .flags = VMS_SINGLE,
 387             .offset = 0
 388         },
 389         VMSTATE_END_OF_LIST()
 390     },
 391 };
 392
 393 static bool vsx_needed(void *opaque)
 394 {
 395     PowerPCCPU *cpu = opaque;
 396
 397     return cpu->env.insns_flags2 & PPC2_VSX;
 398 }
 399
 400 static const VMStateDescription vmstate_vsx = {
 401     .name = "cpu/vsx",
 402     .version_id = 1,
 403     .minimum_version_id = 1,
 404     .needed = vsx_needed,
 405     .fields = (VMStateField[]) {
 406         VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32),
 407         VMSTATE_END_OF_LIST()
 408     },
 409 };
 410
 411 #ifdef TARGET_PPC64
 412 /* Transactional memory state */
 413 static bool tm_needed(void *opaque)
 414 {
 415     PowerPCCPU *cpu = opaque;
 416     CPUPPCState *env = &cpu->env;
 417     return msr_ts;
 418 }
 419
 420 static const VMStateDescription vmstate_tm = {
 421     .name = "cpu/tm",
 422     .version_id = 1,
 423     .minimum_version_id = 1,
 424     .needed = tm_needed,
 425     .fields      = (VMStateField []) {
 426         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 427         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 428         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 429         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 430         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 431         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 432         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 433         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 434         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 435         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 436         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 437         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 438         VMSTATE_END_OF_LIST()
 439     },
 440 };
 441 #endif
 442
 443 static bool sr_needed(void *opaque)
 444 {
 445 #ifdef TARGET_PPC64
 446     PowerPCCPU *cpu = opaque;
 447
 448     return !mmu_is_64bit(cpu->env.mmu_model);
 449 #else
 450     return true;
 451 #endif
 452 }
 453
 454 static const VMStateDescription vmstate_sr = {
 455     .name = "cpu/sr",
 456     .version_id = 1,
 457     .minimum_version_id = 1,
 458     .needed = sr_needed,
 459     .fields = (VMStateField[]) {
 460         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 461         VMSTATE_END_OF_LIST()
 462     },
 463 };
 464
 465 #ifdef TARGET_PPC64
 466 static int get_slbe(QEMUFile *f, void *pv, size_t size,
 467                     const VMStateField *field)
 468 {
 469     ppc_slb_t *v = pv;
 470
 471     v->esid = qemu_get_be64(f);
 472     v->vsid = qemu_get_be64(f);
 473
 474     return 0;
 475 }
 476
 477 static int put_slbe(QEMUFile *f, void *pv, size_t size,
 478                     const VMStateField *field, JSONWriter *vmdesc)
 479 {
 480     ppc_slb_t *v = pv;
 481
 482     qemu_put_be64(f, v->esid);
 483     qemu_put_be64(f, v->vsid);
 484     return 0;
 485 }
 486
 487 static const VMStateInfo vmstate_info_slbe = {
 488     .name = "slbe",
 489     .get  = get_slbe,
 490     .put  = put_slbe,
 491 };
 492
 493 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 494     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 495
 496 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 497     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 498
 499 static bool slb_needed(void *opaque)
 500 {
 501     PowerPCCPU *cpu = opaque;
 502
 503     /* We don't support any of the old segment table based 64-bit CPUs */
 504     return mmu_is_64bit(cpu->env.mmu_model);
 505 }
 506
 507 static int slb_post_load(void *opaque, int version_id)
 508 {
 509     PowerPCCPU *cpu = opaque;
 510     CPUPPCState *env = &cpu->env;
 511     int i;
 512
 513     /*
 514      * We've pulled in the raw esid and vsid values from the migration
 515      * stream, but we need to recompute the page size pointers
 516      */
 517     for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
 518         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 519             /* Migration source had bad values in its SLB */
 520             return -1;
 521         }
 522     }
 523
 524     return 0;
 525 }
 526
 527 static const VMStateDescription vmstate_slb = {
 528     .name = "cpu/slb",
 529     .version_id = 1,
 530     .minimum_version_id = 1,
 531     .needed = slb_needed,
 532     .post_load = slb_post_load,
 533     .fields = (VMStateField[]) {
 534         VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration),
 535         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 536         VMSTATE_END_OF_LIST()
 537     }
 538 };
 539 #endif /* TARGET_PPC64 */
 540
 541 static const VMStateDescription vmstate_tlb6xx_entry = {
 542     .name = "cpu/tlb6xx_entry",
 543     .version_id = 1,
 544     .minimum_version_id = 1,
 545     .fields = (VMStateField[]) {
 546         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 547         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 548         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 549         VMSTATE_END_OF_LIST()
 550     },
 551 };
 552
 553 static bool tlb6xx_needed(void *opaque)
 554 {
 555     PowerPCCPU *cpu = opaque;
 556     CPUPPCState *env = &cpu->env;
 557
 558     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 559 }
 560
 561 static const VMStateDescription vmstate_tlb6xx = {
 562     .name = "cpu/tlb6xx",
 563     .version_id = 1,
 564     .minimum_version_id = 1,
 565     .needed = tlb6xx_needed,
 566     .fields = (VMStateField[]) {
 567         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 568         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 569                                             env.nb_tlb,
 570                                             vmstate_tlb6xx_entry,
 571                                             ppc6xx_tlb_t),
 572         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 573         VMSTATE_END_OF_LIST()
 574     }
 575 };
 576
 577 static const VMStateDescription vmstate_tlbemb_entry = {
 578     .name = "cpu/tlbemb_entry",
 579     .version_id = 1,
 580     .minimum_version_id = 1,
 581     .fields = (VMStateField[]) {
 582         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 583         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 584         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 585         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 586         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 587         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 588         VMSTATE_END_OF_LIST()
 589     },
 590 };
 591
 592 static bool tlbemb_needed(void *opaque)
 593 {
 594     PowerPCCPU *cpu = opaque;
 595     CPUPPCState *env = &cpu->env;
 596
 597     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 598 }
 599
 600 static const VMStateDescription vmstate_tlbemb = {
 601     .name = "cpu/tlb6xx",
 602     .version_id = 1,
 603     .minimum_version_id = 1,
 604     .needed = tlbemb_needed,
 605     .fields = (VMStateField[]) {
 606         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 607         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 608                                             env.nb_tlb,
 609                                             vmstate_tlbemb_entry,
 610                                             ppcemb_tlb_t),
 611         VMSTATE_END_OF_LIST()
 612     },
 613 };
 614
 615 static const VMStateDescription vmstate_tlbmas_entry = {
 616     .name = "cpu/tlbmas_entry",
 617     .version_id = 1,
 618     .minimum_version_id = 1,
 619     .fields = (VMStateField[]) {
 620         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 621         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 622         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 623         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 624         VMSTATE_END_OF_LIST()
 625     },
 626 };
 627
 628 static bool tlbmas_needed(void *opaque)
 629 {
 630     PowerPCCPU *cpu = opaque;
 631     CPUPPCState *env = &cpu->env;
 632
 633     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 634 }
 635
 636 static const VMStateDescription vmstate_tlbmas = {
 637     .name = "cpu/tlbmas",
 638     .version_id = 1,
 639     .minimum_version_id = 1,
 640     .needed = tlbmas_needed,
 641     .fields = (VMStateField[]) {
 642         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 643         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 644                                             env.nb_tlb,
 645                                             vmstate_tlbmas_entry,
 646                                             ppcmas_tlb_t),
 647         VMSTATE_END_OF_LIST()
 648     }
 649 };
 650
 651 static bool compat_needed(void *opaque)
 652 {
 653     PowerPCCPU *cpu = opaque;
 654
 655     assert(!(cpu->compat_pvr && !cpu->vhyp));
 656     return !cpu->pre_2_10_migration && cpu->compat_pvr != 0;
 657 }
 658
 659 static const VMStateDescription vmstate_compat = {
 660     .name = "cpu/compat",
 661     .version_id = 1,
 662     .minimum_version_id = 1,
 663     .needed = compat_needed,
 664     .fields = (VMStateField[]) {
 665         VMSTATE_UINT32(compat_pvr, PowerPCCPU),
 666         VMSTATE_END_OF_LIST()
 667     }
 668 };
 669
 670 const VMStateDescription vmstate_ppc_cpu = {
 671     .name = "cpu",
 672     .version_id = 5,
 673     .minimum_version_id = 5,
 674     .pre_save = cpu_pre_save,
 675     .post_load = cpu_post_load,
 676     .fields = (VMStateField[]) {
 677         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 678
 679         /* User mode architected state */
 680         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 681 #if !defined(TARGET_PPC64)
 682         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 683 #endif
 684         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 685         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 686
 687         /* SPRs */
 688         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 689         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 690
 691         /* Reservation */
 692         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 693
 694         /* Supervisor mode architected state */
 695         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 696
 697         /* Backward compatible internal state */
 698         VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU),
 699
 700         /* Sanity checking */
 701         VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
 702         VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
 703         VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
 704                             cpu_pre_2_8_migration),
 705         VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
 706         VMSTATE_END_OF_LIST()
 707     },
 708     .subsections = (const VMStateDescription*[]) {
 709         &vmstate_fpu,
 710         &vmstate_altivec,
 711         &vmstate_vsx,
 712         &vmstate_sr,
 713 #ifdef TARGET_PPC64
 714         &vmstate_tm,
 715         &vmstate_slb,
 716 #endif /* TARGET_PPC64 */
 717         &vmstate_tlb6xx,
 718         &vmstate_tlbemb,
 719         &vmstate_tlbmas,
 720         &vmstate_compat,
 721         NULL
 722     }
 723 };