target/ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "exec/exec-all.h"
   5 #include "hw/hw.h"
   6 #include "hw/boards.h"
   7 #include "sysemu/kvm.h"
   8 #include "helper_regs.h"
   9 #include "mmu-hash64.h"
  10 #include "migration/cpu.h"
  11 #include "qapi/error.h"
  12 #include "kvm_ppc.h"
  13
  14 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
  15 {
  16     PowerPCCPU *cpu = opaque;
  17     CPUPPCState *env = &cpu->env;
  18     unsigned int i, j;
  19     target_ulong sdr1;
  20     uint32_t fpscr;
  21 #if defined(TARGET_PPC64)
  22     int32_t slb_nr;
  23 #endif
  24     target_ulong xer;
  25
  26     for (i = 0; i < 32; i++)
  27         qemu_get_betls(f, &env->gpr[i]);
  28 #if !defined(TARGET_PPC64)
  29     for (i = 0; i < 32; i++)
  30         qemu_get_betls(f, &env->gprh[i]);
  31 #endif
  32     qemu_get_betls(f, &env->lr);
  33     qemu_get_betls(f, &env->ctr);
  34     for (i = 0; i < 8; i++)
  35         qemu_get_be32s(f, &env->crf[i]);
  36     qemu_get_betls(f, &xer);
  37     cpu_write_xer(env, xer);
  38     qemu_get_betls(f, &env->reserve_addr);
  39     qemu_get_betls(f, &env->msr);
  40     for (i = 0; i < 4; i++)
  41         qemu_get_betls(f, &env->tgpr[i]);
  42     for (i = 0; i < 32; i++) {
  43         union {
  44             float64 d;
  45             uint64_t l;
  46         } u;
  47         u.l = qemu_get_be64(f);
  48         env->fpr[i] = u.d;
  49     }
  50     qemu_get_be32s(f, &fpscr);
  51     env->fpscr = fpscr;
  52     qemu_get_sbe32s(f, &env->access_type);
  53 #if defined(TARGET_PPC64)
  54     qemu_get_betls(f, &env->spr[SPR_ASR]);
  55     qemu_get_sbe32s(f, &slb_nr);
  56 #endif
  57     qemu_get_betls(f, &sdr1);
  58     for (i = 0; i < 32; i++)
  59         qemu_get_betls(f, &env->sr[i]);
  60     for (i = 0; i < 2; i++)
  61         for (j = 0; j < 8; j++)
  62             qemu_get_betls(f, &env->DBAT[i][j]);
  63     for (i = 0; i < 2; i++)
  64         for (j = 0; j < 8; j++)
  65             qemu_get_betls(f, &env->IBAT[i][j]);
  66     qemu_get_sbe32s(f, &env->nb_tlb);
  67     qemu_get_sbe32s(f, &env->tlb_per_way);
  68     qemu_get_sbe32s(f, &env->nb_ways);
  69     qemu_get_sbe32s(f, &env->last_way);
  70     qemu_get_sbe32s(f, &env->id_tlbs);
  71     qemu_get_sbe32s(f, &env->nb_pids);
  72     if (env->tlb.tlb6) {
  73         // XXX assumes 6xx
  74         for (i = 0; i < env->nb_tlb; i++) {
  75             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  76             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  77             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  78         }
  79     }
  80     for (i = 0; i < 4; i++)
  81         qemu_get_betls(f, &env->pb[i]);
  82     for (i = 0; i < 1024; i++)
  83         qemu_get_betls(f, &env->spr[i]);
  84     if (!cpu->vhyp) {
  85         ppc_store_sdr1(env, sdr1);
  86     }
  87     qemu_get_be32s(f, &env->vscr);
  88     qemu_get_be64s(f, &env->spe_acc);
  89     qemu_get_be32s(f, &env->spe_fscr);
  90     qemu_get_betls(f, &env->msr_mask);
  91     qemu_get_be32s(f, &env->flags);
  92     qemu_get_sbe32s(f, &env->error_code);
  93     qemu_get_be32s(f, &env->pending_interrupts);
  94     qemu_get_be32s(f, &env->irq_input_state);
  95     for (i = 0; i < POWERPC_EXCP_NB; i++)
  96         qemu_get_betls(f, &env->excp_vectors[i]);
  97     qemu_get_betls(f, &env->excp_prefix);
  98     qemu_get_betls(f, &env->ivor_mask);
  99     qemu_get_betls(f, &env->ivpr_mask);
 100     qemu_get_betls(f, &env->hreset_vector);
 101     qemu_get_betls(f, &env->nip);
 102     qemu_get_betls(f, &env->hflags);
 103     qemu_get_betls(f, &env->hflags_nmsr);
 104     qemu_get_sbe32(f); /* Discard unused mmu_idx */
 105     qemu_get_sbe32(f); /* Discard unused power_mode */
 106
 107     /* Recompute mmu indices */
 108     hreg_compute_mem_idx(env);
 109
 110     return 0;
 111 }
 112
 113 static int get_avr(QEMUFile *f, void *pv, size_t size,
 114                    const VMStateField *field)
 115 {
 116     ppc_avr_t *v = pv;
 117
 118     v->u64[0] = qemu_get_be64(f);
 119     v->u64[1] = qemu_get_be64(f);
 120
 121     return 0;
 122 }
 123
 124 static int put_avr(QEMUFile *f, void *pv, size_t size,
 125                    const VMStateField *field, QJSON *vmdesc)
 126 {
 127     ppc_avr_t *v = pv;
 128
 129     qemu_put_be64(f, v->u64[0]);
 130     qemu_put_be64(f, v->u64[1]);
 131     return 0;
 132 }
 133
 134 static const VMStateInfo vmstate_info_avr = {
 135     .name = "avr",
 136     .get  = get_avr,
 137     .put  = put_avr,
 138 };
 139
 140 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 141     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 142
 143 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 144     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 145
 146 static bool cpu_pre_2_8_migration(void *opaque, int version_id)
 147 {
 148     PowerPCCPU *cpu = opaque;
 149
 150     return cpu->pre_2_8_migration;
 151 }
 152
 153 #if defined(TARGET_PPC64)
 154 static bool cpu_pre_3_0_migration(void *opaque, int version_id)
 155 {
 156     PowerPCCPU *cpu = opaque;
 157
 158     return cpu->pre_3_0_migration;
 159 }
 160 #endif
 161
 162 static int cpu_pre_save(void *opaque)
 163 {
 164     PowerPCCPU *cpu = opaque;
 165     CPUPPCState *env = &cpu->env;
 166     int i;
 167     uint64_t insns_compat_mask =
 168         PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
 169         | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
 170         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
 171         | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
 172         | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
 173         | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
 174         | PPC_64B | PPC_64BX | PPC_ALTIVEC
 175         | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
 176     uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
 177         | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
 178         | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
 179         | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
 180         | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
 181         | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM;
 182
 183     env->spr[SPR_LR] = env->lr;
 184     env->spr[SPR_CTR] = env->ctr;
 185     env->spr[SPR_XER] = cpu_read_xer(env);
 186 #if defined(TARGET_PPC64)
 187     env->spr[SPR_CFAR] = env->cfar;
 188 #endif
 189     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 190
 191     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 192         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 193         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 194         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 195         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 196     }
 197     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 198         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 199         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 200         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 201         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 202     }
 203
 204     /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
 205     if (cpu->pre_2_8_migration) {
 206         /* Mask out bits that got added to msr_mask since the versions
 207          * which stupidly included it in the migration stream. */
 208         target_ulong metamask = 0
 209 #if defined(TARGET_PPC64)
 210             | (1ULL << MSR_TS0)
 211             | (1ULL << MSR_TS1)
 212 #endif
 213             ;
 214         cpu->mig_msr_mask = env->msr_mask & ~metamask;
 215         cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
 216         /* CPU models supported by old machines all have PPC_MEM_TLBIE,
 217          * so we set it unconditionally to allow backward migration from
 218          * a POWER9 host to a POWER8 host.
 219          */
 220         cpu->mig_insns_flags |= PPC_MEM_TLBIE;
 221         cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
 222         cpu->mig_nb_BATs = env->nb_BATs;
 223     }
 224     if (cpu->pre_3_0_migration) {
 225         if (cpu->hash64_opts) {
 226             cpu->mig_slb_nr = cpu->hash64_opts->slb_size;
 227         }
 228     }
 229
 230     return 0;
 231 }
 232
 233 /*
 234  * Determine if a given PVR is a "close enough" match to the CPU
 235  * object.  For TCG and KVM PR it would probably be sufficient to
 236  * require an exact PVR match.  However for KVM HV the user is
 237  * restricted to a PVR exactly matching the host CPU.  The correct way
 238  * to handle this is to put the guest into an architected
 239  * compatibility mode.  However, to allow a more forgiving transition
 240  * and migration from before this was widely done, we allow migration
 241  * between sufficiently similar PVRs, as determined by the CPU class's
 242  * pvr_match() hook.
 243  */
 244 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr)
 245 {
 246     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 247
 248     if (pvr == pcc->pvr) {
 249         return true;
 250     }
 251     return pcc->pvr_match(pcc, pvr);
 252 }
 253
 254 static int cpu_post_load(void *opaque, int version_id)
 255 {
 256     PowerPCCPU *cpu = opaque;
 257     CPUPPCState *env = &cpu->env;
 258     int i;
 259     target_ulong msr;
 260
 261     /*
 262      * If we're operating in compat mode, we should be ok as long as
 263      * the destination supports the same compatiblity mode.
 264      *
 265      * Otherwise, however, we require that the destination has exactly
 266      * the same CPU model as the source.
 267      */
 268
 269 #if defined(TARGET_PPC64)
 270     if (cpu->compat_pvr) {
 271         uint32_t compat_pvr = cpu->compat_pvr;
 272         Error *local_err = NULL;
 273
 274         cpu->compat_pvr = 0;
 275         ppc_set_compat(cpu, compat_pvr, &local_err);
 276         if (local_err) {
 277             error_report_err(local_err);
 278             return -1;
 279         }
 280     } else
 281 #endif
 282     {
 283         if (!pvr_match(cpu, env->spr[SPR_PVR])) {
 284             return -1;
 285         }
 286     }
 287
 288     /*
 289      * If we're running with KVM HV, there is a chance that the guest
 290      * is running with KVM HV and its kernel does not have the
 291      * capability of dealing with a different PVR other than this
 292      * exact host PVR in KVM_SET_SREGS. If that happens, the
 293      * guest freezes after migration.
 294      *
 295      * The function kvmppc_pvr_workaround_required does this verification
 296      * by first checking if the kernel has the cap, returning true immediately
 297      * if that is the case. Otherwise, it checks if we're running in KVM PR.
 298      * If the guest kernel does not have the cap and we're not running KVM-PR
 299      * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
 300      * receive the PVR it expects as a workaround.
 301      *
 302      */
 303 #if defined(CONFIG_KVM)
 304     if (kvmppc_pvr_workaround_required(cpu)) {
 305         env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 306     }
 307 #endif
 308
 309     env->lr = env->spr[SPR_LR];
 310     env->ctr = env->spr[SPR_CTR];
 311     cpu_write_xer(env, env->spr[SPR_XER]);
 312 #if defined(TARGET_PPC64)
 313     env->cfar = env->spr[SPR_CFAR];
 314 #endif
 315     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 316
 317     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 318         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 319         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 320         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 321         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 322     }
 323     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 324         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 325         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 326         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 327         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 328     }
 329
 330     if (!cpu->vhyp) {
 331         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 332     }
 333
 334     /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */
 335     msr = env->msr;
 336     env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
 337     ppc_store_msr(env, msr);
 338
 339     hreg_compute_mem_idx(env);
 340
 341     return 0;
 342 }
 343
 344 static bool fpu_needed(void *opaque)
 345 {
 346     PowerPCCPU *cpu = opaque;
 347
 348     return (cpu->env.insns_flags & PPC_FLOAT);
 349 }
 350
 351 static const VMStateDescription vmstate_fpu = {
 352     .name = "cpu/fpu",
 353     .version_id = 1,
 354     .minimum_version_id = 1,
 355     .needed = fpu_needed,
 356     .fields = (VMStateField[]) {
 357         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 358         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 359         VMSTATE_END_OF_LIST()
 360     },
 361 };
 362
 363 static bool altivec_needed(void *opaque)
 364 {
 365     PowerPCCPU *cpu = opaque;
 366
 367     return (cpu->env.insns_flags & PPC_ALTIVEC);
 368 }
 369
 370 static const VMStateDescription vmstate_altivec = {
 371     .name = "cpu/altivec",
 372     .version_id = 1,
 373     .minimum_version_id = 1,
 374     .needed = altivec_needed,
 375     .fields = (VMStateField[]) {
 376         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 377         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 378         VMSTATE_END_OF_LIST()
 379     },
 380 };
 381
 382 static bool vsx_needed(void *opaque)
 383 {
 384     PowerPCCPU *cpu = opaque;
 385
 386     return (cpu->env.insns_flags2 & PPC2_VSX);
 387 }
 388
 389 static const VMStateDescription vmstate_vsx = {
 390     .name = "cpu/vsx",
 391     .version_id = 1,
 392     .minimum_version_id = 1,
 393     .needed = vsx_needed,
 394     .fields = (VMStateField[]) {
 395         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 396         VMSTATE_END_OF_LIST()
 397     },
 398 };
 399
 400 #ifdef TARGET_PPC64
 401 /* Transactional memory state */
 402 static bool tm_needed(void *opaque)
 403 {
 404     PowerPCCPU *cpu = opaque;
 405     CPUPPCState *env = &cpu->env;
 406     return msr_ts;
 407 }
 408
 409 static const VMStateDescription vmstate_tm = {
 410     .name = "cpu/tm",
 411     .version_id = 1,
 412     .minimum_version_id = 1,
 413     .minimum_version_id_old = 1,
 414     .needed = tm_needed,
 415     .fields      = (VMStateField []) {
 416         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 417         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 418         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 419         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 420         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 421         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 422         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 423         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 424         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 425         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 426         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 427         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 428         VMSTATE_END_OF_LIST()
 429     },
 430 };
 431 #endif
 432
 433 static bool sr_needed(void *opaque)
 434 {
 435 #ifdef TARGET_PPC64
 436     PowerPCCPU *cpu = opaque;
 437
 438     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 439 #else
 440     return true;
 441 #endif
 442 }
 443
 444 static const VMStateDescription vmstate_sr = {
 445     .name = "cpu/sr",
 446     .version_id = 1,
 447     .minimum_version_id = 1,
 448     .needed = sr_needed,
 449     .fields = (VMStateField[]) {
 450         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 451         VMSTATE_END_OF_LIST()
 452     },
 453 };
 454
 455 #ifdef TARGET_PPC64
 456 static int get_slbe(QEMUFile *f, void *pv, size_t size,
 457                     const VMStateField *field)
 458 {
 459     ppc_slb_t *v = pv;
 460
 461     v->esid = qemu_get_be64(f);
 462     v->vsid = qemu_get_be64(f);
 463
 464     return 0;
 465 }
 466
 467 static int put_slbe(QEMUFile *f, void *pv, size_t size,
 468                     const VMStateField *field, QJSON *vmdesc)
 469 {
 470     ppc_slb_t *v = pv;
 471
 472     qemu_put_be64(f, v->esid);
 473     qemu_put_be64(f, v->vsid);
 474     return 0;
 475 }
 476
 477 static const VMStateInfo vmstate_info_slbe = {
 478     .name = "slbe",
 479     .get  = get_slbe,
 480     .put  = put_slbe,
 481 };
 482
 483 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 484     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 485
 486 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 487     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 488
 489 static bool slb_needed(void *opaque)
 490 {
 491     PowerPCCPU *cpu = opaque;
 492
 493     /* We don't support any of the old segment table based 64-bit CPUs */
 494     return (cpu->env.mmu_model & POWERPC_MMU_64);
 495 }
 496
 497 static int slb_post_load(void *opaque, int version_id)
 498 {
 499     PowerPCCPU *cpu = opaque;
 500     CPUPPCState *env = &cpu->env;
 501     int i;
 502
 503     /* We've pulled in the raw esid and vsid values from the migration
 504      * stream, but we need to recompute the page size pointers */
 505     for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
 506         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 507             /* Migration source had bad values in its SLB */
 508             return -1;
 509         }
 510     }
 511
 512     return 0;
 513 }
 514
 515 static const VMStateDescription vmstate_slb = {
 516     .name = "cpu/slb",
 517     .version_id = 1,
 518     .minimum_version_id = 1,
 519     .needed = slb_needed,
 520     .post_load = slb_post_load,
 521     .fields = (VMStateField[]) {
 522         VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration),
 523         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 524         VMSTATE_END_OF_LIST()
 525     }
 526 };
 527 #endif /* TARGET_PPC64 */
 528
 529 static const VMStateDescription vmstate_tlb6xx_entry = {
 530     .name = "cpu/tlb6xx_entry",
 531     .version_id = 1,
 532     .minimum_version_id = 1,
 533     .fields = (VMStateField[]) {
 534         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 535         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 536         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 537         VMSTATE_END_OF_LIST()
 538     },
 539 };
 540
 541 static bool tlb6xx_needed(void *opaque)
 542 {
 543     PowerPCCPU *cpu = opaque;
 544     CPUPPCState *env = &cpu->env;
 545
 546     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 547 }
 548
 549 static const VMStateDescription vmstate_tlb6xx = {
 550     .name = "cpu/tlb6xx",
 551     .version_id = 1,
 552     .minimum_version_id = 1,
 553     .needed = tlb6xx_needed,
 554     .fields = (VMStateField[]) {
 555         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 556         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 557                                             env.nb_tlb,
 558                                             vmstate_tlb6xx_entry,
 559                                             ppc6xx_tlb_t),
 560         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 561         VMSTATE_END_OF_LIST()
 562     }
 563 };
 564
 565 static const VMStateDescription vmstate_tlbemb_entry = {
 566     .name = "cpu/tlbemb_entry",
 567     .version_id = 1,
 568     .minimum_version_id = 1,
 569     .fields = (VMStateField[]) {
 570         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 571         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 572         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 573         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 574         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 575         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 576         VMSTATE_END_OF_LIST()
 577     },
 578 };
 579
 580 static bool tlbemb_needed(void *opaque)
 581 {
 582     PowerPCCPU *cpu = opaque;
 583     CPUPPCState *env = &cpu->env;
 584
 585     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 586 }
 587
 588 static bool pbr403_needed(void *opaque)
 589 {
 590     PowerPCCPU *cpu = opaque;
 591     uint32_t pvr = cpu->env.spr[SPR_PVR];
 592
 593     return (pvr & 0xffff0000) == 0x00200000;
 594 }
 595
 596 static const VMStateDescription vmstate_pbr403 = {
 597     .name = "cpu/pbr403",
 598     .version_id = 1,
 599     .minimum_version_id = 1,
 600     .needed = pbr403_needed,
 601     .fields = (VMStateField[]) {
 602         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 603         VMSTATE_END_OF_LIST()
 604     },
 605 };
 606
 607 static const VMStateDescription vmstate_tlbemb = {
 608     .name = "cpu/tlb6xx",
 609     .version_id = 1,
 610     .minimum_version_id = 1,
 611     .needed = tlbemb_needed,
 612     .fields = (VMStateField[]) {
 613         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 614         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 615                                             env.nb_tlb,
 616                                             vmstate_tlbemb_entry,
 617                                             ppcemb_tlb_t),
 618         /* 403 protection registers */
 619         VMSTATE_END_OF_LIST()
 620     },
 621     .subsections = (const VMStateDescription*[]) {
 622         &vmstate_pbr403,
 623         NULL
 624     }
 625 };
 626
 627 static const VMStateDescription vmstate_tlbmas_entry = {
 628     .name = "cpu/tlbmas_entry",
 629     .version_id = 1,
 630     .minimum_version_id = 1,
 631     .fields = (VMStateField[]) {
 632         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 633         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 634         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 635         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 636         VMSTATE_END_OF_LIST()
 637     },
 638 };
 639
 640 static bool tlbmas_needed(void *opaque)
 641 {
 642     PowerPCCPU *cpu = opaque;
 643     CPUPPCState *env = &cpu->env;
 644
 645     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 646 }
 647
 648 static const VMStateDescription vmstate_tlbmas = {
 649     .name = "cpu/tlbmas",
 650     .version_id = 1,
 651     .minimum_version_id = 1,
 652     .needed = tlbmas_needed,
 653     .fields = (VMStateField[]) {
 654         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 655         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 656                                             env.nb_tlb,
 657                                             vmstate_tlbmas_entry,
 658                                             ppcmas_tlb_t),
 659         VMSTATE_END_OF_LIST()
 660     }
 661 };
 662
 663 static bool compat_needed(void *opaque)
 664 {
 665     PowerPCCPU *cpu = opaque;
 666
 667     assert(!(cpu->compat_pvr && !cpu->vhyp));
 668     return !cpu->pre_2_10_migration && cpu->compat_pvr != 0;
 669 }
 670
 671 static const VMStateDescription vmstate_compat = {
 672     .name = "cpu/compat",
 673     .version_id = 1,
 674     .minimum_version_id = 1,
 675     .needed = compat_needed,
 676     .fields = (VMStateField[]) {
 677         VMSTATE_UINT32(compat_pvr, PowerPCCPU),
 678         VMSTATE_END_OF_LIST()
 679     }
 680 };
 681
 682 const VMStateDescription vmstate_ppc_cpu = {
 683     .name = "cpu",
 684     .version_id = 5,
 685     .minimum_version_id = 5,
 686     .minimum_version_id_old = 4,
 687     .load_state_old = cpu_load_old,
 688     .pre_save = cpu_pre_save,
 689     .post_load = cpu_post_load,
 690     .fields = (VMStateField[]) {
 691         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 692
 693         /* User mode architected state */
 694         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 695 #if !defined(TARGET_PPC64)
 696         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 697 #endif
 698         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 699         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 700
 701         /* SPRs */
 702         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 703         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 704
 705         /* Reservation */
 706         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 707
 708         /* Supervisor mode architected state */
 709         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 710
 711         /* Internal state */
 712         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 713         /* FIXME: access_type? */
 714
 715         /* Sanity checking */
 716         VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
 717         VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
 718         VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
 719                             cpu_pre_2_8_migration),
 720         VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
 721         VMSTATE_END_OF_LIST()
 722     },
 723     .subsections = (const VMStateDescription*[]) {
 724         &vmstate_fpu,
 725         &vmstate_altivec,
 726         &vmstate_vsx,
 727         &vmstate_sr,
 728 #ifdef TARGET_PPC64
 729         &vmstate_tm,
 730         &vmstate_slb,
 731 #endif /* TARGET_PPC64 */
 732         &vmstate_tlb6xx,
 733         &vmstate_tlbemb,
 734         &vmstate_tlbmas,
 735         &vmstate_compat,
 736         NULL
 737     }
 738 };