target/ppc/misc_helper.c

   1 /*
   2  * Miscellaneous PowerPC emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/exec-all.h"
  22 #include "exec/helper-proto.h"
  23
  24 #include "helper_regs.h"
  25
  26 /*****************************************************************************/
  27 /* SPR accesses */
  28 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  29 {
  30     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  31              env->spr[sprn]);
  32 }
  33
  34 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  35 {
  36     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  37              env->spr[sprn]);
  38 }
  39
  40 #ifdef TARGET_PPC64
  41 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
  42                                uint32_t sprn, uint32_t cause,
  43                                uintptr_t raddr)
  44 {
  45     qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
  46
  47     env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
  48     cause &= FSCR_IC_MASK;
  49     env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
  50
  51     raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
  52 }
  53 #endif
  54
  55 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
  56                                 uint32_t sprn, uint32_t cause)
  57 {
  58 #ifdef TARGET_PPC64
  59     if (env->spr[SPR_FSCR] & (1ULL << bit)) {
  60         /* Facility is enabled, continue */
  61         return;
  62     }
  63     raise_fu_exception(env, bit, sprn, cause, GETPC());
  64 #endif
  65 }
  66
  67 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
  68                                uint32_t sprn, uint32_t cause)
  69 {
  70 #ifdef TARGET_PPC64
  71     if (env->msr & (1ULL << bit)) {
  72         /* Facility is enabled, continue */
  73         return;
  74     }
  75     raise_fu_exception(env, bit, sprn, cause, GETPC());
  76 #endif
  77 }
  78
  79 #if !defined(CONFIG_USER_ONLY)
  80
  81 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  82 {
  83     PowerPCCPU *cpu = ppc_env_get_cpu(env);
  84
  85     if (env->spr[SPR_SDR1] != val) {
  86         ppc_store_sdr1(env, val);
  87         tlb_flush(CPU(cpu));
  88     }
  89 }
  90
  91 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
  92 {
  93     target_ulong hid0;
  94
  95     hid0 = env->spr[SPR_HID0];
  96     if ((val ^ hid0) & 0x00000008) {
  97         /* Change current endianness */
  98         env->hflags &= ~(1 << MSR_LE);
  99         env->hflags_nmsr &= ~(1 << MSR_LE);
 100         env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
 101         env->hflags |= env->hflags_nmsr;
 102         qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
 103                  val & 0x8 ? 'l' : 'b', env->hflags);
 104     }
 105     env->spr[SPR_HID0] = (uint32_t)val;
 106 }
 107
 108 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
 109 {
 110     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 111
 112     if (likely(env->pb[num] != value)) {
 113         env->pb[num] = value;
 114         /* Should be optimized */
 115         tlb_flush(CPU(cpu));
 116     }
 117 }
 118
 119 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
 120 {
 121     store_40x_dbcr0(env, val);
 122 }
 123
 124 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
 125 {
 126     store_40x_sler(env, val);
 127 }
 128 #endif
 129 /*****************************************************************************/
 130 /* PowerPC 601 specific instructions (POWER bridge) */
 131
 132 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
 133 {
 134     switch (arg) {
 135     case 0x0CUL:
 136         /* Instruction cache line size */
 137         return env->icache_line_size;
 138         break;
 139     case 0x0DUL:
 140         /* Data cache line size */
 141         return env->dcache_line_size;
 142         break;
 143     case 0x0EUL:
 144         /* Minimum cache line size */
 145         return (env->icache_line_size < env->dcache_line_size) ?
 146             env->icache_line_size : env->dcache_line_size;
 147         break;
 148     case 0x0FUL:
 149         /* Maximum cache line size */
 150         return (env->icache_line_size > env->dcache_line_size) ?
 151             env->icache_line_size : env->dcache_line_size;
 152         break;
 153     default:
 154         /* Undefined */
 155         return 0;
 156         break;
 157     }
 158 }
 159
 160 /*****************************************************************************/
 161 /* Special registers manipulation */
 162
 163 /* GDBstub can read and write MSR... */
 164 void ppc_store_msr(CPUPPCState *env, target_ulong value)
 165 {
 166     hreg_store_msr(env, value, 0);
 167 }
 168
 169 /* This code is lifted from MacOnLinux. It is called whenever
 170  * THRM1,2 or 3 is read an fixes up the values in such a way
 171  * that will make MacOS not hang. These registers exist on some
 172  * 75x and 74xx processors.
 173  */
 174 void helper_fixup_thrm(CPUPPCState *env)
 175 {
 176     target_ulong v, t;
 177     int i;
 178
 179 #define THRM1_TIN       (1 << 31)
 180 #define THRM1_TIV       (1 << 30)
 181 #define THRM1_THRES(x)  (((x) & 0x7f) << 23)
 182 #define THRM1_TID       (1 << 2)
 183 #define THRM1_TIE       (1 << 1)
 184 #define THRM1_V         (1 << 0)
 185 #define THRM3_E         (1 << 0)
 186
 187     if (!(env->spr[SPR_THRM3] & THRM3_E)) {
 188         return;
 189     }
 190
 191     /* Note: Thermal interrupts are unimplemented */
 192     for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
 193         v = env->spr[i];
 194         if (!(v & THRM1_V)) {
 195             continue;
 196         }
 197         v |= THRM1_TIV;
 198         v &= ~THRM1_TIN;
 199         t = v & THRM1_THRES(127);
 200         if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
 201             v |= THRM1_TIN;
 202         }
 203         if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
 204             v |= THRM1_TIN;
 205         }
 206         env->spr[i] = v;
 207     }
 208 }