2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "qemu/error-report.h"
26 #include "qemu/qemu-print.h"
27 #include "sysemu/hw_accel.h"
29 #include "mmu-hash64.h"
33 #include "mmu-book3s-v3.h"
34 #include "helper_regs.h"
36 /* #define DEBUG_SLB */
39 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
41 # define LOG_SLB(...) do { } while (0)
48 static ppc_slb_t
*slb_lookup(PowerPCCPU
*cpu
, target_ulong eaddr
)
50 CPUPPCState
*env
= &cpu
->env
;
51 uint64_t esid_256M
, esid_1T
;
54 LOG_SLB("%s: eaddr " TARGET_FMT_lx
"\n", __func__
, eaddr
);
56 esid_256M
= (eaddr
& SEGMENT_MASK_256M
) | SLB_ESID_V
;
57 esid_1T
= (eaddr
& SEGMENT_MASK_1T
) | SLB_ESID_V
;
59 for (n
= 0; n
< cpu
->hash64_opts
->slb_size
; n
++) {
60 ppc_slb_t
*slb
= &env
->slb
[n
];
62 LOG_SLB("%s: slot %d %016" PRIx64
" %016"
63 PRIx64
"\n", __func__
, n
, slb
->esid
, slb
->vsid
);
65 * We check for 1T matches on all MMUs here - if the MMU
66 * doesn't have 1T segment support, we will have prevented 1T
67 * entries from being inserted in the slbmte code.
69 if (((slb
->esid
== esid_256M
) &&
70 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_256M
))
71 || ((slb
->esid
== esid_1T
) &&
72 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_1T
))) {
80 void dump_slb(PowerPCCPU
*cpu
)
82 CPUPPCState
*env
= &cpu
->env
;
86 cpu_synchronize_state(CPU(cpu
));
88 qemu_printf("SLB\tESID\t\t\tVSID\n");
89 for (i
= 0; i
< cpu
->hash64_opts
->slb_size
; i
++) {
90 slbe
= env
->slb
[i
].esid
;
91 slbv
= env
->slb
[i
].vsid
;
92 if (slbe
== 0 && slbv
== 0) {
95 qemu_printf("%d\t0x%016" PRIx64
"\t0x%016" PRIx64
"\n",
100 void helper_slbia(CPUPPCState
*env
, uint32_t ih
)
102 PowerPCCPU
*cpu
= env_archcpu(env
);
107 * slbia must always flush all TLB (which is equivalent to ERAT in ppc
108 * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
109 * can overwrite a valid SLB without flushing its lookaside information.
111 * It would be possible to keep the TLB in synch with the SLB by flushing
112 * when a valid entry is overwritten by slbmte, and therefore slbia would
113 * not have to flush unless it evicts a valid SLB entry. However it is
114 * expected that slbmte is more common than slbia, and slbia is usually
115 * going to evict valid SLB entries, so that tradeoff is unlikely to be a
118 * ISA v2.05 introduced IH field with values 0,1,2,6. These all invalidate
119 * the same SLB entries (everything but entry 0), but differ in what
120 * "lookaside information" is invalidated. TCG can ignore this and flush
123 * ISA v3.0 introduced additional values 3,4,7, which change what SLBs are
127 env
->tlb_need_flush
|= TLB_NEED_LOCAL_FLUSH
;
129 starting_entry
= 1; /* default for IH=0,1,2,6 */
131 if (env
->mmu_model
== POWERPC_MMU_3_00
) {
134 /* invalidate no SLBs, but all lookaside information */
139 /* also considers SLB entry 0 */
144 /* treat undefined values as ih==0, and warn */
145 qemu_log_mask(LOG_GUEST_ERROR
,
146 "slbia undefined IH field %u.\n", ih
);
155 for (n
= starting_entry
; n
< cpu
->hash64_opts
->slb_size
; n
++) {
156 ppc_slb_t
*slb
= &env
->slb
[n
];
158 if (!(slb
->esid
& SLB_ESID_V
)) {
161 if (env
->mmu_model
== POWERPC_MMU_3_00
) {
162 if (ih
== 0x3 && (slb
->vsid
& SLB_VSID_C
) == 0) {
163 /* preserves entries with a class value of 0 */
168 slb
->esid
&= ~SLB_ESID_V
;
172 static void __helper_slbie(CPUPPCState
*env
, target_ulong addr
,
175 PowerPCCPU
*cpu
= env_archcpu(env
);
178 slb
= slb_lookup(cpu
, addr
);
183 if (slb
->esid
& SLB_ESID_V
) {
184 slb
->esid
&= ~SLB_ESID_V
;
187 * XXX: given the fact that segment size is 256 MB or 1TB,
188 * and we still don't have a tlb_flush_mask(env, n, mask)
189 * in QEMU, we just invalidate all TLBs
191 env
->tlb_need_flush
|=
192 (global
== false ? TLB_NEED_LOCAL_FLUSH
: TLB_NEED_GLOBAL_FLUSH
);
196 void helper_slbie(CPUPPCState
*env
, target_ulong addr
)
198 __helper_slbie(env
, addr
, false);
201 void helper_slbieg(CPUPPCState
*env
, target_ulong addr
)
203 __helper_slbie(env
, addr
, true);
206 int ppc_store_slb(PowerPCCPU
*cpu
, target_ulong slot
,
207 target_ulong esid
, target_ulong vsid
)
209 CPUPPCState
*env
= &cpu
->env
;
210 ppc_slb_t
*slb
= &env
->slb
[slot
];
211 const PPCHash64SegmentPageSizes
*sps
= NULL
;
214 if (slot
>= cpu
->hash64_opts
->slb_size
) {
215 return -1; /* Bad slot number */
217 if (esid
& ~(SLB_ESID_ESID
| SLB_ESID_V
)) {
218 return -1; /* Reserved bits set */
220 if (vsid
& (SLB_VSID_B
& ~SLB_VSID_B_1T
)) {
221 return -1; /* Bad segment size */
223 if ((vsid
& SLB_VSID_B
) && !(ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
))) {
224 return -1; /* 1T segment on MMU that doesn't support it */
227 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
228 const PPCHash64SegmentPageSizes
*sps1
= &cpu
->hash64_opts
->sps
[i
];
230 if (!sps1
->page_shift
) {
234 if ((vsid
& SLB_VSID_LLP_MASK
) == sps1
->slb_enc
) {
241 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
242 " esid 0x"TARGET_FMT_lx
" vsid 0x"TARGET_FMT_lx
,
251 LOG_SLB("%s: " TARGET_FMT_lu
" " TARGET_FMT_lx
" - " TARGET_FMT_lx
252 " => %016" PRIx64
" %016" PRIx64
"\n", __func__
, slot
, esid
, vsid
,
253 slb
->esid
, slb
->vsid
);
258 static int ppc_load_slb_esid(PowerPCCPU
*cpu
, target_ulong rb
,
261 CPUPPCState
*env
= &cpu
->env
;
262 int slot
= rb
& 0xfff;
263 ppc_slb_t
*slb
= &env
->slb
[slot
];
265 if (slot
>= cpu
->hash64_opts
->slb_size
) {
273 static int ppc_load_slb_vsid(PowerPCCPU
*cpu
, target_ulong rb
,
276 CPUPPCState
*env
= &cpu
->env
;
277 int slot
= rb
& 0xfff;
278 ppc_slb_t
*slb
= &env
->slb
[slot
];
280 if (slot
>= cpu
->hash64_opts
->slb_size
) {
288 static int ppc_find_slb_vsid(PowerPCCPU
*cpu
, target_ulong rb
,
291 CPUPPCState
*env
= &cpu
->env
;
294 if (!msr_is_64bit(env
, env
->msr
)) {
297 slb
= slb_lookup(cpu
, rb
);
299 *rt
= (target_ulong
)-1ul;
306 void helper_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
308 PowerPCCPU
*cpu
= env_archcpu(env
);
310 if (ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
) < 0) {
311 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
312 POWERPC_EXCP_INVAL
, GETPC());
316 target_ulong
helper_load_slb_esid(CPUPPCState
*env
, target_ulong rb
)
318 PowerPCCPU
*cpu
= env_archcpu(env
);
321 if (ppc_load_slb_esid(cpu
, rb
, &rt
) < 0) {
322 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
323 POWERPC_EXCP_INVAL
, GETPC());
328 target_ulong
helper_find_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
330 PowerPCCPU
*cpu
= env_archcpu(env
);
333 if (ppc_find_slb_vsid(cpu
, rb
, &rt
) < 0) {
334 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
335 POWERPC_EXCP_INVAL
, GETPC());
340 target_ulong
helper_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
342 PowerPCCPU
*cpu
= env_archcpu(env
);
345 if (ppc_load_slb_vsid(cpu
, rb
, &rt
) < 0) {
346 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
347 POWERPC_EXCP_INVAL
, GETPC());
352 /* Check No-Execute or Guarded Storage */
353 static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU
*cpu
,
354 ppc_hash_pte64_t pte
)
356 /* Exec permissions CANNOT take away read or write permissions */
357 return (pte
.pte1
& HPTE64_R_N
) || (pte
.pte1
& HPTE64_R_G
) ?
358 PAGE_READ
| PAGE_WRITE
: PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
361 /* Check Basic Storage Protection */
362 static int ppc_hash64_pte_prot(PowerPCCPU
*cpu
,
363 ppc_slb_t
*slb
, ppc_hash_pte64_t pte
)
365 CPUPPCState
*env
= &cpu
->env
;
368 * Some pp bit combinations have undefined behaviour, so default
369 * to no access in those cases
373 key
= !!(msr_pr
? (slb
->vsid
& SLB_VSID_KP
)
374 : (slb
->vsid
& SLB_VSID_KS
));
375 pp
= (pte
.pte1
& HPTE64_R_PP
) | ((pte
.pte1
& HPTE64_R_PP0
) >> 61);
382 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
387 prot
= PAGE_READ
| PAGE_EXEC
;
398 prot
= PAGE_READ
| PAGE_EXEC
;
402 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
410 /* Check the instruction access permissions specified in the IAMR */
411 static int ppc_hash64_iamr_prot(PowerPCCPU
*cpu
, int key
)
413 CPUPPCState
*env
= &cpu
->env
;
414 int iamr_bits
= (env
->spr
[SPR_IAMR
] >> 2 * (31 - key
)) & 0x3;
417 * An instruction fetch is permitted if the IAMR bit is 0.
418 * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit
419 * can only take away EXEC permissions not READ or WRITE permissions.
420 * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since
421 * EXEC permissions are allowed.
423 return (iamr_bits
& 0x1) ? PAGE_READ
| PAGE_WRITE
:
424 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
427 static int ppc_hash64_amr_prot(PowerPCCPU
*cpu
, ppc_hash_pte64_t pte
)
429 CPUPPCState
*env
= &cpu
->env
;
431 int prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
433 /* Only recent MMUs implement Virtual Page Class Key Protection */
434 if (!ppc_hash64_has(cpu
, PPC_HASH64_AMR
)) {
438 key
= HPTE64_R_KEY(pte
.pte1
);
439 amrbits
= (env
->spr
[SPR_AMR
] >> 2 * (31 - key
)) & 0x3;
441 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
442 /* env->spr[SPR_AMR]); */
445 * A store is permitted if the AMR bit is 0. Remove write
446 * protection if it is set.
452 * A load is permitted if the AMR bit is 0. Remove read
453 * protection if it is set.
459 switch (env
->mmu_model
) {
461 * MMU version 2.07 and later support IAMR
462 * Check if the IAMR allows the instruction access - it will return
463 * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0
464 * if it does (and prot will be unchanged indicating execution support).
466 case POWERPC_MMU_2_07
:
467 case POWERPC_MMU_3_00
:
468 prot
&= ppc_hash64_iamr_prot(cpu
, key
);
477 const ppc_hash_pte64_t
*ppc_hash64_map_hptes(PowerPCCPU
*cpu
,
480 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
482 hwaddr plen
= n
* HASH_PTE_SIZE_64
;
483 const ppc_hash_pte64_t
*hptes
;
486 PPCVirtualHypervisorClass
*vhc
=
487 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
488 return vhc
->map_hptes(cpu
->vhyp
, ptex
, n
);
490 base
= ppc_hash64_hpt_base(cpu
);
496 hptes
= address_space_map(CPU(cpu
)->as
, base
+ pte_offset
, &plen
, false,
497 MEMTXATTRS_UNSPECIFIED
);
498 if (plen
< (n
* HASH_PTE_SIZE_64
)) {
499 hw_error("%s: Unable to map all requested HPTEs\n", __func__
);
504 void ppc_hash64_unmap_hptes(PowerPCCPU
*cpu
, const ppc_hash_pte64_t
*hptes
,
508 PPCVirtualHypervisorClass
*vhc
=
509 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
510 vhc
->unmap_hptes(cpu
->vhyp
, hptes
, ptex
, n
);
514 address_space_unmap(CPU(cpu
)->as
, (void *)hptes
, n
* HASH_PTE_SIZE_64
,
515 false, n
* HASH_PTE_SIZE_64
);
518 static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes
*sps
,
519 uint64_t pte0
, uint64_t pte1
)
523 if (!(pte0
& HPTE64_V_LARGE
)) {
524 if (sps
->page_shift
!= 12) {
525 /* 4kiB page in a non 4kiB segment */
528 /* Normal 4kiB page */
532 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
533 const PPCHash64PageSize
*ps
= &sps
->enc
[i
];
536 if (!ps
->page_shift
) {
540 if (ps
->page_shift
== 12) {
541 /* L bit is set so this can't be a 4kiB page */
545 mask
= ((1ULL << ps
->page_shift
) - 1) & HPTE64_R_RPN
;
547 if ((pte1
& mask
) == ((uint64_t)ps
->pte_enc
<< HPTE64_R_RPN_SHIFT
)) {
548 return ps
->page_shift
;
552 return 0; /* Bad page size encoding */
555 static void ppc64_v3_new_to_old_hpte(target_ulong
*pte0
, target_ulong
*pte1
)
557 /* Insert B into pte0 */
558 *pte0
= (*pte0
& HPTE64_V_COMMON_BITS
) |
559 ((*pte1
& HPTE64_R_3_0_SSIZE_MASK
) <<
560 (HPTE64_V_SSIZE_SHIFT
- HPTE64_R_3_0_SSIZE_SHIFT
));
562 /* Remove B from pte1 */
563 *pte1
= *pte1
& ~HPTE64_R_3_0_SSIZE_MASK
;
567 static hwaddr
ppc_hash64_pteg_search(PowerPCCPU
*cpu
, hwaddr hash
,
568 const PPCHash64SegmentPageSizes
*sps
,
570 ppc_hash_pte64_t
*pte
, unsigned *pshift
)
573 const ppc_hash_pte64_t
*pteg
;
574 target_ulong pte0
, pte1
;
577 ptex
= (hash
& ppc_hash64_hpt_mask(cpu
)) * HPTES_PER_GROUP
;
578 pteg
= ppc_hash64_map_hptes(cpu
, ptex
, HPTES_PER_GROUP
);
582 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
583 pte0
= ppc_hash64_hpte0(cpu
, pteg
, i
);
585 * pte0 contains the valid bit and must be read before pte1,
586 * otherwise we might see an old pte1 with a new valid bit and
587 * thus an inconsistent hpte value
590 pte1
= ppc_hash64_hpte1(cpu
, pteg
, i
);
592 /* Convert format if necessary */
593 if (cpu
->env
.mmu_model
== POWERPC_MMU_3_00
&& !cpu
->vhyp
) {
594 ppc64_v3_new_to_old_hpte(&pte0
, &pte1
);
597 /* This compares V, B, H (secondary) and the AVPN */
598 if (HPTE64_V_COMPARE(pte0
, ptem
)) {
599 *pshift
= hpte_page_shift(sps
, pte0
, pte1
);
601 * If there is no match, ignore the PTE, it could simply
602 * be for a different segment size encoding and the
603 * architecture specifies we should not match. Linux will
604 * potentially leave behind PTEs for the wrong base page
605 * size when demoting segments.
611 * We don't do anything with pshift yet as qemu TLB only
612 * deals with 4K pages anyway
616 ppc_hash64_unmap_hptes(cpu
, pteg
, ptex
, HPTES_PER_GROUP
);
620 ppc_hash64_unmap_hptes(cpu
, pteg
, ptex
, HPTES_PER_GROUP
);
622 * We didn't find a valid entry.
627 static hwaddr
ppc_hash64_htab_lookup(PowerPCCPU
*cpu
,
628 ppc_slb_t
*slb
, target_ulong eaddr
,
629 ppc_hash_pte64_t
*pte
, unsigned *pshift
)
631 CPUPPCState
*env
= &cpu
->env
;
633 uint64_t vsid
, epnmask
, epn
, ptem
;
634 const PPCHash64SegmentPageSizes
*sps
= slb
->sps
;
637 * The SLB store path should prevent any bad page size encodings
638 * getting in there, so:
642 /* If ISL is set in LPCR we need to clamp the page size to 4K */
643 if (env
->spr
[SPR_LPCR
] & LPCR_ISL
) {
644 /* We assume that when using TCG, 4k is first entry of SPS */
645 sps
= &cpu
->hash64_opts
->sps
[0];
646 assert(sps
->page_shift
== 12);
649 epnmask
= ~((1ULL << sps
->page_shift
) - 1);
651 if (slb
->vsid
& SLB_VSID_B
) {
653 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT_1T
;
654 epn
= (eaddr
& ~SEGMENT_MASK_1T
) & epnmask
;
655 hash
= vsid
^ (vsid
<< 25) ^ (epn
>> sps
->page_shift
);
658 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT
;
659 epn
= (eaddr
& ~SEGMENT_MASK_256M
) & epnmask
;
660 hash
= vsid
^ (epn
>> sps
->page_shift
);
662 ptem
= (slb
->vsid
& SLB_VSID_PTEM
) | ((epn
>> 16) & HPTE64_V_AVPN
);
663 ptem
|= HPTE64_V_VALID
;
665 /* Page address translation */
666 qemu_log_mask(CPU_LOG_MMU
,
667 "htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
668 " hash " TARGET_FMT_plx
"\n",
669 ppc_hash64_hpt_base(cpu
), ppc_hash64_hpt_mask(cpu
), hash
);
671 /* Primary PTEG lookup */
672 qemu_log_mask(CPU_LOG_MMU
,
673 "0 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
674 " vsid=" TARGET_FMT_lx
" ptem=" TARGET_FMT_lx
675 " hash=" TARGET_FMT_plx
"\n",
676 ppc_hash64_hpt_base(cpu
), ppc_hash64_hpt_mask(cpu
),
678 ptex
= ppc_hash64_pteg_search(cpu
, hash
, sps
, ptem
, pte
, pshift
);
681 /* Secondary PTEG lookup */
682 ptem
|= HPTE64_V_SECONDARY
;
683 qemu_log_mask(CPU_LOG_MMU
,
684 "1 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
685 " vsid=" TARGET_FMT_lx
" api=" TARGET_FMT_lx
686 " hash=" TARGET_FMT_plx
"\n", ppc_hash64_hpt_base(cpu
),
687 ppc_hash64_hpt_mask(cpu
), vsid
, ptem
, ~hash
);
689 ptex
= ppc_hash64_pteg_search(cpu
, ~hash
, sps
, ptem
, pte
, pshift
);
695 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU
*cpu
,
696 uint64_t pte0
, uint64_t pte1
)
700 if (!(pte0
& HPTE64_V_LARGE
)) {
705 * The encodings in env->sps need to be carefully chosen so that
706 * this gives an unambiguous result.
708 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
709 const PPCHash64SegmentPageSizes
*sps
= &cpu
->hash64_opts
->sps
[i
];
712 if (!sps
->page_shift
) {
716 shift
= hpte_page_shift(sps
, pte0
, pte1
);
725 static bool ppc_hash64_use_vrma(CPUPPCState
*env
)
727 switch (env
->mmu_model
) {
728 case POWERPC_MMU_3_00
:
730 * ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR
731 * register no longer exist
736 return !!(env
->spr
[SPR_LPCR
] & LPCR_VPM0
);
740 static void ppc_hash64_set_isi(CPUState
*cs
, uint64_t error_code
)
742 CPUPPCState
*env
= &POWERPC_CPU(cs
)->env
;
746 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM1
);
748 vpm
= ppc_hash64_use_vrma(env
);
750 if (vpm
&& !msr_hv
) {
751 cs
->exception_index
= POWERPC_EXCP_HISI
;
753 cs
->exception_index
= POWERPC_EXCP_ISI
;
755 env
->error_code
= error_code
;
758 static void ppc_hash64_set_dsi(CPUState
*cs
, uint64_t dar
, uint64_t dsisr
)
760 CPUPPCState
*env
= &POWERPC_CPU(cs
)->env
;
764 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM1
);
766 vpm
= ppc_hash64_use_vrma(env
);
768 if (vpm
&& !msr_hv
) {
769 cs
->exception_index
= POWERPC_EXCP_HDSI
;
770 env
->spr
[SPR_HDAR
] = dar
;
771 env
->spr
[SPR_HDSISR
] = dsisr
;
773 cs
->exception_index
= POWERPC_EXCP_DSI
;
774 env
->spr
[SPR_DAR
] = dar
;
775 env
->spr
[SPR_DSISR
] = dsisr
;
781 static void ppc_hash64_set_r(PowerPCCPU
*cpu
, hwaddr ptex
, uint64_t pte1
)
783 hwaddr base
, offset
= ptex
* HASH_PTE_SIZE_64
+ 16;
786 PPCVirtualHypervisorClass
*vhc
=
787 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
788 vhc
->hpte_set_r(cpu
->vhyp
, ptex
, pte1
);
791 base
= ppc_hash64_hpt_base(cpu
);
794 /* The HW performs a non-atomic byte update */
795 stb_phys(CPU(cpu
)->as
, base
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
798 static void ppc_hash64_set_c(PowerPCCPU
*cpu
, hwaddr ptex
, uint64_t pte1
)
800 hwaddr base
, offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
803 PPCVirtualHypervisorClass
*vhc
=
804 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
805 vhc
->hpte_set_c(cpu
->vhyp
, ptex
, pte1
);
808 base
= ppc_hash64_hpt_base(cpu
);
810 /* The HW performs a non-atomic byte update */
811 stb_phys(CPU(cpu
)->as
, base
+ offset
, (pte1
& 0xff) | 0x80);
814 static target_ulong
rmls_limit(PowerPCCPU
*cpu
)
816 CPUPPCState
*env
= &cpu
->env
;
818 * In theory the meanings of RMLS values are implementation
819 * dependent. In practice, this seems to have been the set from
820 * POWER4+..POWER8, and RMLS is no longer supported in POWER9.
822 * Unsupported values mean the OS has shot itself in the
823 * foot. Return a 0-sized RMA in this case, which we expect
824 * to trigger an immediate DSI or ISI
826 static const target_ulong rma_sizes
[16] = {
835 target_ulong rmls
= (env
->spr
[SPR_LPCR
] & LPCR_RMLS
) >> LPCR_RMLS_SHIFT
;
837 return rma_sizes
[rmls
];
840 static int build_vrma_slbe(PowerPCCPU
*cpu
, ppc_slb_t
*slb
)
842 CPUPPCState
*env
= &cpu
->env
;
843 target_ulong lpcr
= env
->spr
[SPR_LPCR
];
844 uint32_t vrmasd
= (lpcr
& LPCR_VRMASD
) >> LPCR_VRMASD_SHIFT
;
845 target_ulong vsid
= SLB_VSID_VRMA
| ((vrmasd
<< 4) & SLB_VSID_LLP_MASK
);
848 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
849 const PPCHash64SegmentPageSizes
*sps
= &cpu
->hash64_opts
->sps
[i
];
851 if (!sps
->page_shift
) {
855 if ((vsid
& SLB_VSID_LLP_MASK
) == sps
->slb_enc
) {
856 slb
->esid
= SLB_ESID_V
;
863 error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
864 TARGET_FMT_lx
, lpcr
);
869 int ppc_hash64_handle_mmu_fault(PowerPCCPU
*cpu
, vaddr eaddr
,
870 int rwx
, int mmu_idx
)
872 CPUState
*cs
= CPU(cpu
);
873 CPUPPCState
*env
= &cpu
->env
;
878 ppc_hash_pte64_t pte
;
879 int exec_prot
, pp_prot
, amr_prot
, prot
;
880 MMUAccessType access_type
;
884 assert((rwx
== 0) || (rwx
== 1) || (rwx
== 2));
888 * Note on LPCR usage: 970 uses HID4, but our special variant of
889 * store_spr copies relevant fields into env->spr[SPR_LPCR].
890 * Similarly we filter unimplemented bits when storing into LPCR
891 * depending on the MMU version. This code can thus just use the
895 /* 1. Handle real mode accesses */
896 if (access_type
== MMU_INST_FETCH
? !msr_ir
: !msr_dr
) {
898 * Translation is supposedly "off", but in real mode the top 4
899 * effective address bits are (mostly) ignored
901 raddr
= eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
905 * In virtual hypervisor mode, there's nothing to do:
906 * EA == GPA == qemu guest address
908 } else if (msr_hv
|| !env
->has_hv_mode
) {
909 /* In HV mode, add HRMOR if top EA bit is clear */
910 if (!(eaddr
>> 63)) {
911 raddr
|= env
->spr
[SPR_HRMOR
];
913 } else if (ppc_hash64_use_vrma(env
)) {
914 /* Emulated VRMA mode */
916 if (build_vrma_slbe(cpu
, slb
) != 0) {
917 /* Invalid VRMA setup, machine check */
918 cs
->exception_index
= POWERPC_EXCP_MCHECK
;
923 goto skip_slb_search
;
925 target_ulong limit
= rmls_limit(cpu
);
927 /* Emulated old-style RMO mode, bounds check against RMLS */
928 if (raddr
>= limit
) {
929 switch (access_type
) {
931 ppc_hash64_set_isi(cs
, SRR1_PROTFAULT
);
934 ppc_hash64_set_dsi(cs
, eaddr
, DSISR_PROTFAULT
);
937 ppc_hash64_set_dsi(cs
, eaddr
,
938 DSISR_PROTFAULT
| DSISR_ISSTORE
);
941 g_assert_not_reached();
946 raddr
|= env
->spr
[SPR_RMOR
];
948 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
949 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
, mmu_idx
,
954 /* 2. Translation is on, so look up the SLB */
955 slb
= slb_lookup(cpu
, eaddr
);
957 /* No entry found, check if in-memory segment tables are in use */
958 if (ppc64_use_proc_tbl(cpu
)) {
959 /* TODO - Unsupported */
960 error_report("Segment Table Support Unimplemented");
963 /* Segment still not found, generate the appropriate interrupt */
964 switch (access_type
) {
966 cs
->exception_index
= POWERPC_EXCP_ISEG
;
971 cs
->exception_index
= POWERPC_EXCP_DSEG
;
973 env
->spr
[SPR_DAR
] = eaddr
;
976 g_assert_not_reached();
983 /* 3. Check for segment level no-execute violation */
984 if (access_type
== MMU_INST_FETCH
&& (slb
->vsid
& SLB_VSID_N
)) {
985 ppc_hash64_set_isi(cs
, SRR1_NOEXEC_GUARD
);
989 /* 4. Locate the PTE in the hash table */
990 ptex
= ppc_hash64_htab_lookup(cpu
, slb
, eaddr
, &pte
, &apshift
);
992 switch (access_type
) {
994 ppc_hash64_set_isi(cs
, SRR1_NOPTE
);
997 ppc_hash64_set_dsi(cs
, eaddr
, DSISR_NOPTE
);
1000 ppc_hash64_set_dsi(cs
, eaddr
, DSISR_NOPTE
| DSISR_ISSTORE
);
1003 g_assert_not_reached();
1007 qemu_log_mask(CPU_LOG_MMU
,
1008 "found PTE at index %08" HWADDR_PRIx
"\n", ptex
);
1010 /* 5. Check access permissions */
1012 exec_prot
= ppc_hash64_pte_noexec_guard(cpu
, pte
);
1013 pp_prot
= ppc_hash64_pte_prot(cpu
, slb
, pte
);
1014 amr_prot
= ppc_hash64_amr_prot(cpu
, pte
);
1015 prot
= exec_prot
& pp_prot
& amr_prot
;
1017 need_prot
= prot_for_access_type(access_type
);
1018 if (need_prot
& ~prot
) {
1019 /* Access right violation */
1020 qemu_log_mask(CPU_LOG_MMU
, "PTE access rejected\n");
1021 if (access_type
== MMU_INST_FETCH
) {
1023 if (PAGE_EXEC
& ~exec_prot
) {
1024 srr1
|= SRR1_NOEXEC_GUARD
; /* Access violates noexec or guard */
1025 } else if (PAGE_EXEC
& ~pp_prot
) {
1026 srr1
|= SRR1_PROTFAULT
; /* Access violates access authority */
1028 if (PAGE_EXEC
& ~amr_prot
) {
1029 srr1
|= SRR1_IAMR
; /* Access violates virt pg class key prot */
1031 ppc_hash64_set_isi(cs
, srr1
);
1034 if (need_prot
& ~pp_prot
) {
1035 dsisr
|= DSISR_PROTFAULT
;
1037 if (access_type
== MMU_DATA_STORE
) {
1038 dsisr
|= DSISR_ISSTORE
;
1040 if (need_prot
& ~amr_prot
) {
1043 ppc_hash64_set_dsi(cs
, eaddr
, dsisr
);
1048 qemu_log_mask(CPU_LOG_MMU
, "PTE access granted !\n");
1050 /* 6. Update PTE referenced and changed bits if necessary */
1052 if (!(pte
.pte1
& HPTE64_R_R
)) {
1053 ppc_hash64_set_r(cpu
, ptex
, pte
.pte1
);
1055 if (!(pte
.pte1
& HPTE64_R_C
)) {
1056 if (access_type
== MMU_DATA_STORE
) {
1057 ppc_hash64_set_c(cpu
, ptex
, pte
.pte1
);
1060 * Treat the page as read-only for now, so that a later write
1061 * will pass through this function again to set the C bit
1063 prot
&= ~PAGE_WRITE
;
1067 /* 7. Determine the real address from the PTE */
1069 raddr
= deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, eaddr
);
1071 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
1072 prot
, mmu_idx
, 1ULL << apshift
);
1077 hwaddr
ppc_hash64_get_phys_page_debug(PowerPCCPU
*cpu
, target_ulong addr
)
1079 CPUPPCState
*env
= &cpu
->env
;
1080 ppc_slb_t vrma_slbe
;
1083 ppc_hash_pte64_t pte
;
1086 /* Handle real mode */
1088 /* In real mode the top 4 effective address bits are ignored */
1089 raddr
= addr
& 0x0FFFFFFFFFFFFFFFULL
;
1093 * In virtual hypervisor mode, there's nothing to do:
1094 * EA == GPA == qemu guest address
1097 } else if ((msr_hv
|| !env
->has_hv_mode
) && !(addr
>> 63)) {
1098 /* In HV mode, add HRMOR if top EA bit is clear */
1099 return raddr
| env
->spr
[SPR_HRMOR
];
1100 } else if (ppc_hash64_use_vrma(env
)) {
1101 /* Emulated VRMA mode */
1103 if (build_vrma_slbe(cpu
, slb
) != 0) {
1107 target_ulong limit
= rmls_limit(cpu
);
1109 /* Emulated old-style RMO mode, bounds check against RMLS */
1110 if (raddr
>= limit
) {
1113 return raddr
| env
->spr
[SPR_RMOR
];
1116 slb
= slb_lookup(cpu
, addr
);
1122 ptex
= ppc_hash64_htab_lookup(cpu
, slb
, addr
, &pte
, &apshift
);
1127 return deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, addr
)
1131 void ppc_hash64_tlb_flush_hpte(PowerPCCPU
*cpu
, target_ulong ptex
,
1132 target_ulong pte0
, target_ulong pte1
)
1135 * XXX: given the fact that there are too many segments to
1136 * invalidate, and we still don't have a tlb_flush_mask(env, n,
1137 * mask) in QEMU, we just invalidate all TLBs
1139 cpu
->env
.tlb_need_flush
= TLB_NEED_GLOBAL_FLUSH
| TLB_NEED_LOCAL_FLUSH
;
1142 void helper_store_lpcr(CPUPPCState
*env
, target_ulong val
)
1144 PowerPCCPU
*cpu
= env_archcpu(env
);
1146 ppc_store_lpcr(cpu
, val
);
1149 void ppc_hash64_init(PowerPCCPU
*cpu
)
1151 CPUPPCState
*env
= &cpu
->env
;
1152 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
1154 if (!pcc
->hash64_opts
) {
1155 assert(!mmu_is_64bit(env
->mmu_model
));
1159 cpu
->hash64_opts
= g_memdup(pcc
->hash64_opts
, sizeof(*cpu
->hash64_opts
));
1162 void ppc_hash64_finalize(PowerPCCPU
*cpu
)
1164 g_free(cpu
->hash64_opts
);
1167 const PPCHash64Options ppc_hash64_opts_basic
= {
1171 { .page_shift
= 12, /* 4K */
1173 .enc
= { { .page_shift
= 12, .pte_enc
= 0 } }
1175 { .page_shift
= 24, /* 16M */
1177 .enc
= { { .page_shift
= 24, .pte_enc
= 0 } }
1182 const PPCHash64Options ppc_hash64_opts_POWER7
= {
1183 .flags
= PPC_HASH64_1TSEG
| PPC_HASH64_AMR
| PPC_HASH64_CI_LARGEPAGE
,
1187 .page_shift
= 12, /* 4K */
1189 .enc
= { { .page_shift
= 12, .pte_enc
= 0 },
1190 { .page_shift
= 16, .pte_enc
= 0x7 },
1191 { .page_shift
= 24, .pte_enc
= 0x38 }, },
1194 .page_shift
= 16, /* 64K */
1195 .slb_enc
= SLB_VSID_64K
,
1196 .enc
= { { .page_shift
= 16, .pte_enc
= 0x1 },
1197 { .page_shift
= 24, .pte_enc
= 0x8 }, },
1200 .page_shift
= 24, /* 16M */
1201 .slb_enc
= SLB_VSID_16M
,
1202 .enc
= { { .page_shift
= 24, .pte_enc
= 0 }, },
1205 .page_shift
= 34, /* 16G */
1206 .slb_enc
= SLB_VSID_16G
,
1207 .enc
= { { .page_shift
= 34, .pte_enc
= 0x3 }, },