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[mirror_qemu.git] / target / ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_env cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87 static int done_init = 0;
88
89 if (done_init)
90 return;
91
92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
93 tcg_ctx.tcg_env = cpu_env;
94
95 p = cpu_reg_names;
96 cpu_reg_names_size = sizeof(cpu_reg_names);
97
98 for (i = 0; i < 8; i++) {
99 snprintf(p, cpu_reg_names_size, "crf%d", i);
100 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
101 offsetof(CPUPPCState, crf[i]), p);
102 p += 5;
103 cpu_reg_names_size -= 5;
104 }
105
106 for (i = 0; i < 32; i++) {
107 snprintf(p, cpu_reg_names_size, "r%d", i);
108 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
109 offsetof(CPUPPCState, gpr[i]), p);
110 p += (i < 10) ? 3 : 4;
111 cpu_reg_names_size -= (i < 10) ? 3 : 4;
112 snprintf(p, cpu_reg_names_size, "r%dH", i);
113 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
114 offsetof(CPUPPCState, gprh[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "fp%d", i);
119 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, fpr[i]), p);
121 p += (i < 10) ? 4 : 5;
122 cpu_reg_names_size -= (i < 10) ? 4 : 5;
123
124 snprintf(p, cpu_reg_names_size, "avr%dH", i);
125 #ifdef HOST_WORDS_BIGENDIAN
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[0]), p);
128 #else
129 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
130 offsetof(CPUPPCState, avr[i].u64[1]), p);
131 #endif
132 p += (i < 10) ? 6 : 7;
133 cpu_reg_names_size -= (i < 10) ? 6 : 7;
134
135 snprintf(p, cpu_reg_names_size, "avr%dL", i);
136 #ifdef HOST_WORDS_BIGENDIAN
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[1]), p);
139 #else
140 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
141 offsetof(CPUPPCState, avr[i].u64[0]), p);
142 #endif
143 p += (i < 10) ? 6 : 7;
144 cpu_reg_names_size -= (i < 10) ? 6 : 7;
145 snprintf(p, cpu_reg_names_size, "vsr%d", i);
146 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
147 offsetof(CPUPPCState, vsr[i]), p);
148 p += (i < 10) ? 5 : 6;
149 cpu_reg_names_size -= (i < 10) ? 5 : 6;
150 }
151
152 cpu_nip = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, nip), "nip");
154
155 cpu_msr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, msr), "msr");
157
158 cpu_ctr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, ctr), "ctr");
160
161 cpu_lr = tcg_global_mem_new(cpu_env,
162 offsetof(CPUPPCState, lr), "lr");
163
164 #if defined(TARGET_PPC64)
165 cpu_cfar = tcg_global_mem_new(cpu_env,
166 offsetof(CPUPPCState, cfar), "cfar");
167 #endif
168
169 cpu_xer = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, xer), "xer");
171 cpu_so = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, so), "SO");
173 cpu_ov = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ov), "OV");
175 cpu_ca = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, ca), "CA");
177 cpu_ov32 = tcg_global_mem_new(cpu_env,
178 offsetof(CPUPPCState, ov32), "OV32");
179 cpu_ca32 = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, ca32), "CA32");
181
182 cpu_reserve = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, reserve_addr),
184 "reserve_addr");
185 cpu_reserve_val = tcg_global_mem_new(cpu_env,
186 offsetof(CPUPPCState, reserve_val),
187 "reserve_val");
188
189 cpu_fpscr = tcg_global_mem_new(cpu_env,
190 offsetof(CPUPPCState, fpscr), "fpscr");
191
192 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
193 offsetof(CPUPPCState, access_type), "access_type");
194
195 done_init = 1;
196 }
197
198 /* internal defines */
199 struct DisasContext {
200 struct TranslationBlock *tb;
201 target_ulong nip;
202 uint32_t opcode;
203 uint32_t exception;
204 /* Routine used to access memory */
205 bool pr, hv, dr, le_mode;
206 bool lazy_tlb_flush;
207 bool need_access_type;
208 int mem_idx;
209 int access_type;
210 /* Translation flags */
211 TCGMemOp default_tcg_memop_mask;
212 #if defined(TARGET_PPC64)
213 bool sf_mode;
214 bool has_cfar;
215 #endif
216 bool fpu_enabled;
217 bool altivec_enabled;
218 bool vsx_enabled;
219 bool spe_enabled;
220 bool tm_enabled;
221 bool gtse;
222 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
223 int singlestep_enabled;
224 uint64_t insns_flags;
225 uint64_t insns_flags2;
226 };
227
228 /* Return true iff byteswap is needed in a scalar memop */
229 static inline bool need_byteswap(const DisasContext *ctx)
230 {
231 #if defined(TARGET_WORDS_BIGENDIAN)
232 return ctx->le_mode;
233 #else
234 return !ctx->le_mode;
235 #endif
236 }
237
238 /* True when active word size < size of target_long. */
239 #ifdef TARGET_PPC64
240 # define NARROW_MODE(C) (!(C)->sf_mode)
241 #else
242 # define NARROW_MODE(C) 0
243 #endif
244
245 struct opc_handler_t {
246 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
247 uint32_t inval1;
248 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
249 uint32_t inval2;
250 /* instruction type */
251 uint64_t type;
252 /* extended instruction type */
253 uint64_t type2;
254 /* handler */
255 void (*handler)(DisasContext *ctx);
256 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
257 const char *oname;
258 #endif
259 #if defined(DO_PPC_STATISTICS)
260 uint64_t count;
261 #endif
262 };
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->need_access_type && ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
281 {
282 TCGv_i32 t0, t1;
283
284 /* These are all synchronous exceptions, we set the PC back to
285 * the faulting instruction
286 */
287 if (ctx->exception == POWERPC_EXCP_NONE) {
288 gen_update_nip(ctx, ctx->nip - 4);
289 }
290 t0 = tcg_const_i32(excp);
291 t1 = tcg_const_i32(error);
292 gen_helper_raise_exception_err(cpu_env, t0, t1);
293 tcg_temp_free_i32(t0);
294 tcg_temp_free_i32(t1);
295 ctx->exception = (excp);
296 }
297
298 static void gen_exception(DisasContext *ctx, uint32_t excp)
299 {
300 TCGv_i32 t0;
301
302 /* These are all synchronous exceptions, we set the PC back to
303 * the faulting instruction
304 */
305 if (ctx->exception == POWERPC_EXCP_NONE) {
306 gen_update_nip(ctx, ctx->nip - 4);
307 }
308 t0 = tcg_const_i32(excp);
309 gen_helper_raise_exception(cpu_env, t0);
310 tcg_temp_free_i32(t0);
311 ctx->exception = (excp);
312 }
313
314 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
315 target_ulong nip)
316 {
317 TCGv_i32 t0;
318
319 gen_update_nip(ctx, nip);
320 t0 = tcg_const_i32(excp);
321 gen_helper_raise_exception(cpu_env, t0);
322 tcg_temp_free_i32(t0);
323 ctx->exception = (excp);
324 }
325
326 static void gen_debug_exception(DisasContext *ctx)
327 {
328 TCGv_i32 t0;
329
330 /* These are all synchronous exceptions, we set the PC back to
331 * the faulting instruction
332 */
333 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
334 (ctx->exception != POWERPC_EXCP_SYNC)) {
335 gen_update_nip(ctx, ctx->nip);
336 }
337 t0 = tcg_const_i32(EXCP_DEBUG);
338 gen_helper_raise_exception(cpu_env, t0);
339 tcg_temp_free_i32(t0);
340 }
341
342 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
343 {
344 /* Will be converted to program check if needed */
345 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
346 }
347
348 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
349 {
350 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
351 }
352
353 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
354 {
355 /* Will be converted to program check if needed */
356 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
357 }
358
359 /* Stop translation */
360 static inline void gen_stop_exception(DisasContext *ctx)
361 {
362 gen_update_nip(ctx, ctx->nip);
363 ctx->exception = POWERPC_EXCP_STOP;
364 }
365
366 #ifndef CONFIG_USER_ONLY
367 /* No need to update nip here, as execution flow will change */
368 static inline void gen_sync_exception(DisasContext *ctx)
369 {
370 ctx->exception = POWERPC_EXCP_SYNC;
371 }
372 #endif
373
374 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
375 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
376
377 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
378 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
379
380 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
381 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
382
383 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
384 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
385
386 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
387 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
388
389 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
390 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
391
392 typedef struct opcode_t {
393 unsigned char opc1, opc2, opc3, opc4;
394 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
395 unsigned char pad[4];
396 #endif
397 opc_handler_t handler;
398 const char *oname;
399 } opcode_t;
400
401 /* Helpers for priv. check */
402 #define GEN_PRIV \
403 do { \
404 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
405 } while (0)
406
407 #if defined(CONFIG_USER_ONLY)
408 #define CHK_HV GEN_PRIV
409 #define CHK_SV GEN_PRIV
410 #define CHK_HVRM GEN_PRIV
411 #else
412 #define CHK_HV \
413 do { \
414 if (unlikely(ctx->pr || !ctx->hv)) { \
415 GEN_PRIV; \
416 } \
417 } while (0)
418 #define CHK_SV \
419 do { \
420 if (unlikely(ctx->pr)) { \
421 GEN_PRIV; \
422 } \
423 } while (0)
424 #define CHK_HVRM \
425 do { \
426 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
427 GEN_PRIV; \
428 } \
429 } while (0)
430 #endif
431
432 #define CHK_NONE
433
434 /*****************************************************************************/
435 /* PowerPC instructions table */
436
437 #if defined(DO_PPC_STATISTICS)
438 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
439 { \
440 .opc1 = op1, \
441 .opc2 = op2, \
442 .opc3 = op3, \
443 .opc4 = 0xff, \
444 .handler = { \
445 .inval1 = invl, \
446 .type = _typ, \
447 .type2 = _typ2, \
448 .handler = &gen_##name, \
449 .oname = stringify(name), \
450 }, \
451 .oname = stringify(name), \
452 }
453 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
454 { \
455 .opc1 = op1, \
456 .opc2 = op2, \
457 .opc3 = op3, \
458 .opc4 = 0xff, \
459 .handler = { \
460 .inval1 = invl1, \
461 .inval2 = invl2, \
462 .type = _typ, \
463 .type2 = _typ2, \
464 .handler = &gen_##name, \
465 .oname = stringify(name), \
466 }, \
467 .oname = stringify(name), \
468 }
469 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
470 { \
471 .opc1 = op1, \
472 .opc2 = op2, \
473 .opc3 = op3, \
474 .opc4 = 0xff, \
475 .handler = { \
476 .inval1 = invl, \
477 .type = _typ, \
478 .type2 = _typ2, \
479 .handler = &gen_##name, \
480 .oname = onam, \
481 }, \
482 .oname = onam, \
483 }
484 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
485 { \
486 .opc1 = op1, \
487 .opc2 = op2, \
488 .opc3 = op3, \
489 .opc4 = op4, \
490 .handler = { \
491 .inval1 = invl, \
492 .type = _typ, \
493 .type2 = _typ2, \
494 .handler = &gen_##name, \
495 .oname = stringify(name), \
496 }, \
497 .oname = stringify(name), \
498 }
499 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
500 { \
501 .opc1 = op1, \
502 .opc2 = op2, \
503 .opc3 = op3, \
504 .opc4 = op4, \
505 .handler = { \
506 .inval1 = invl, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = onam, \
511 }, \
512 .oname = onam, \
513 }
514 #else
515 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
516 { \
517 .opc1 = op1, \
518 .opc2 = op2, \
519 .opc3 = op3, \
520 .opc4 = 0xff, \
521 .handler = { \
522 .inval1 = invl, \
523 .type = _typ, \
524 .type2 = _typ2, \
525 .handler = &gen_##name, \
526 }, \
527 .oname = stringify(name), \
528 }
529 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
530 { \
531 .opc1 = op1, \
532 .opc2 = op2, \
533 .opc3 = op3, \
534 .opc4 = 0xff, \
535 .handler = { \
536 .inval1 = invl1, \
537 .inval2 = invl2, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .opc4 = 0xff, \
550 .handler = { \
551 .inval1 = invl, \
552 .type = _typ, \
553 .type2 = _typ2, \
554 .handler = &gen_##name, \
555 }, \
556 .oname = onam, \
557 }
558 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
559 { \
560 .opc1 = op1, \
561 .opc2 = op2, \
562 .opc3 = op3, \
563 .opc4 = op4, \
564 .handler = { \
565 .inval1 = invl, \
566 .type = _typ, \
567 .type2 = _typ2, \
568 .handler = &gen_##name, \
569 }, \
570 .oname = stringify(name), \
571 }
572 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
573 { \
574 .opc1 = op1, \
575 .opc2 = op2, \
576 .opc3 = op3, \
577 .opc4 = op4, \
578 .handler = { \
579 .inval1 = invl, \
580 .type = _typ, \
581 .type2 = _typ2, \
582 .handler = &gen_##name, \
583 }, \
584 .oname = onam, \
585 }
586 #endif
587
588 /* SPR load/store helpers */
589 static inline void gen_load_spr(TCGv t, int reg)
590 {
591 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
592 }
593
594 static inline void gen_store_spr(int reg, TCGv t)
595 {
596 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
597 }
598
599 /* Invalid instruction */
600 static void gen_invalid(DisasContext *ctx)
601 {
602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
603 }
604
605 static opc_handler_t invalid_handler = {
606 .inval1 = 0xFFFFFFFF,
607 .inval2 = 0xFFFFFFFF,
608 .type = PPC_NONE,
609 .type2 = PPC_NONE,
610 .handler = gen_invalid,
611 };
612
613 /*** Integer comparison ***/
614
615 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
616 {
617 TCGv t0 = tcg_temp_new();
618 TCGv_i32 t1 = tcg_temp_new_i32();
619
620 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
621
622 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
623 tcg_gen_trunc_tl_i32(t1, t0);
624 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
625 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
626
627 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
628 tcg_gen_trunc_tl_i32(t1, t0);
629 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
630 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
631
632 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
633 tcg_gen_trunc_tl_i32(t1, t0);
634 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
635 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
636
637 tcg_temp_free(t0);
638 tcg_temp_free_i32(t1);
639 }
640
641 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
642 {
643 TCGv t0 = tcg_const_tl(arg1);
644 gen_op_cmp(arg0, t0, s, crf);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
649 {
650 TCGv t0, t1;
651 t0 = tcg_temp_new();
652 t1 = tcg_temp_new();
653 if (s) {
654 tcg_gen_ext32s_tl(t0, arg0);
655 tcg_gen_ext32s_tl(t1, arg1);
656 } else {
657 tcg_gen_ext32u_tl(t0, arg0);
658 tcg_gen_ext32u_tl(t1, arg1);
659 }
660 gen_op_cmp(t0, t1, s, crf);
661 tcg_temp_free(t1);
662 tcg_temp_free(t0);
663 }
664
665 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
666 {
667 TCGv t0 = tcg_const_tl(arg1);
668 gen_op_cmp32(arg0, t0, s, crf);
669 tcg_temp_free(t0);
670 }
671
672 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
673 {
674 if (NARROW_MODE(ctx)) {
675 gen_op_cmpi32(reg, 0, 1, 0);
676 } else {
677 gen_op_cmpi(reg, 0, 1, 0);
678 }
679 }
680
681 /* cmp */
682 static void gen_cmp(DisasContext *ctx)
683 {
684 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
685 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
686 1, crfD(ctx->opcode));
687 } else {
688 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
689 1, crfD(ctx->opcode));
690 }
691 }
692
693 /* cmpi */
694 static void gen_cmpi(DisasContext *ctx)
695 {
696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
697 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
698 1, crfD(ctx->opcode));
699 } else {
700 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
701 1, crfD(ctx->opcode));
702 }
703 }
704
705 /* cmpl */
706 static void gen_cmpl(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
710 0, crfD(ctx->opcode));
711 } else {
712 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 0, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpli */
718 static void gen_cmpli(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
722 0, crfD(ctx->opcode));
723 } else {
724 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
725 0, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmprb - range comparison: isupper, isaplha, islower*/
730 static void gen_cmprb(DisasContext *ctx)
731 {
732 TCGv_i32 src1 = tcg_temp_new_i32();
733 TCGv_i32 src2 = tcg_temp_new_i32();
734 TCGv_i32 src2lo = tcg_temp_new_i32();
735 TCGv_i32 src2hi = tcg_temp_new_i32();
736 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
737
738 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
739 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
740
741 tcg_gen_andi_i32(src1, src1, 0xFF);
742 tcg_gen_ext8u_i32(src2lo, src2);
743 tcg_gen_shri_i32(src2, src2, 8);
744 tcg_gen_ext8u_i32(src2hi, src2);
745
746 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
747 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
748 tcg_gen_and_i32(crf, src2lo, src2hi);
749
750 if (ctx->opcode & 0x00200000) {
751 tcg_gen_shri_i32(src2, src2, 8);
752 tcg_gen_ext8u_i32(src2lo, src2);
753 tcg_gen_shri_i32(src2, src2, 8);
754 tcg_gen_ext8u_i32(src2hi, src2);
755 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
756 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
757 tcg_gen_and_i32(src2lo, src2lo, src2hi);
758 tcg_gen_or_i32(crf, crf, src2lo);
759 }
760 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
761 tcg_temp_free_i32(src1);
762 tcg_temp_free_i32(src2);
763 tcg_temp_free_i32(src2lo);
764 tcg_temp_free_i32(src2hi);
765 }
766
767 #if defined(TARGET_PPC64)
768 /* cmpeqb */
769 static void gen_cmpeqb(DisasContext *ctx)
770 {
771 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
772 cpu_gpr[rB(ctx->opcode)]);
773 }
774 #endif
775
776 /* isel (PowerPC 2.03 specification) */
777 static void gen_isel(DisasContext *ctx)
778 {
779 uint32_t bi = rC(ctx->opcode);
780 uint32_t mask = 0x08 >> (bi & 0x03);
781 TCGv t0 = tcg_temp_new();
782 TCGv zr;
783
784 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
785 tcg_gen_andi_tl(t0, t0, mask);
786
787 zr = tcg_const_tl(0);
788 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
789 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
790 cpu_gpr[rB(ctx->opcode)]);
791 tcg_temp_free(zr);
792 tcg_temp_free(t0);
793 }
794
795 /* cmpb: PowerPC 2.05 specification */
796 static void gen_cmpb(DisasContext *ctx)
797 {
798 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
799 cpu_gpr[rB(ctx->opcode)]);
800 }
801
802 /*** Integer arithmetic ***/
803
804 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
805 TCGv arg1, TCGv arg2, int sub)
806 {
807 TCGv t0 = tcg_temp_new();
808
809 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
810 tcg_gen_xor_tl(t0, arg1, arg2);
811 if (sub) {
812 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
813 } else {
814 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
815 }
816 tcg_temp_free(t0);
817 if (NARROW_MODE(ctx)) {
818 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
819 if (is_isa300(ctx)) {
820 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
821 }
822 } else {
823 if (is_isa300(ctx)) {
824 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
825 }
826 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
827 }
828 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
829 }
830
831 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
832 TCGv res, TCGv arg0, TCGv arg1,
833 int sub)
834 {
835 TCGv t0;
836
837 if (!is_isa300(ctx)) {
838 return;
839 }
840
841 t0 = tcg_temp_new();
842 if (sub) {
843 tcg_gen_eqv_tl(t0, arg0, arg1);
844 } else {
845 tcg_gen_xor_tl(t0, arg0, arg1);
846 }
847 tcg_gen_xor_tl(t0, t0, res);
848 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
849 tcg_temp_free(t0);
850 }
851
852 /* Common add function */
853 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
854 TCGv arg2, bool add_ca, bool compute_ca,
855 bool compute_ov, bool compute_rc0)
856 {
857 TCGv t0 = ret;
858
859 if (compute_ca || compute_ov) {
860 t0 = tcg_temp_new();
861 }
862
863 if (compute_ca) {
864 if (NARROW_MODE(ctx)) {
865 /* Caution: a non-obvious corner case of the spec is that we
866 must produce the *entire* 64-bit addition, but produce the
867 carry into bit 32. */
868 TCGv t1 = tcg_temp_new();
869 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
870 tcg_gen_add_tl(t0, arg1, arg2);
871 if (add_ca) {
872 tcg_gen_add_tl(t0, t0, cpu_ca);
873 }
874 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
875 tcg_temp_free(t1);
876 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
877 if (is_isa300(ctx)) {
878 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
879 }
880 } else {
881 TCGv zero = tcg_const_tl(0);
882 if (add_ca) {
883 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
884 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
885 } else {
886 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
887 }
888 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
889 tcg_temp_free(zero);
890 }
891 } else {
892 tcg_gen_add_tl(t0, arg1, arg2);
893 if (add_ca) {
894 tcg_gen_add_tl(t0, t0, cpu_ca);
895 }
896 }
897
898 if (compute_ov) {
899 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
900 }
901 if (unlikely(compute_rc0)) {
902 gen_set_Rc0(ctx, t0);
903 }
904
905 if (!TCGV_EQUAL(t0, ret)) {
906 tcg_gen_mov_tl(ret, t0);
907 tcg_temp_free(t0);
908 }
909 }
910 /* Add functions with two operands */
911 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
912 static void glue(gen_, name)(DisasContext *ctx) \
913 { \
914 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
915 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
917 }
918 /* Add functions with one operand and one immediate */
919 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
920 add_ca, compute_ca, compute_ov) \
921 static void glue(gen_, name)(DisasContext *ctx) \
922 { \
923 TCGv t0 = tcg_const_tl(const_val); \
924 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
925 cpu_gpr[rA(ctx->opcode)], t0, \
926 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
927 tcg_temp_free(t0); \
928 }
929
930 /* add add. addo addo. */
931 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
932 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
933 /* addc addc. addco addco. */
934 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
935 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
936 /* adde adde. addeo addeo. */
937 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
938 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
939 /* addme addme. addmeo addmeo. */
940 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
941 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
942 /* addze addze. addzeo addzeo.*/
943 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
944 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
945 /* addi */
946 static void gen_addi(DisasContext *ctx)
947 {
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* li case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
955 cpu_gpr[rA(ctx->opcode)], simm);
956 }
957 }
958 /* addic addic.*/
959 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
960 {
961 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
962 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
963 c, 0, 1, 0, compute_rc0);
964 tcg_temp_free(c);
965 }
966
967 static void gen_addic(DisasContext *ctx)
968 {
969 gen_op_addic(ctx, 0);
970 }
971
972 static void gen_addic_(DisasContext *ctx)
973 {
974 gen_op_addic(ctx, 1);
975 }
976
977 /* addis */
978 static void gen_addis(DisasContext *ctx)
979 {
980 target_long simm = SIMM(ctx->opcode);
981
982 if (rA(ctx->opcode) == 0) {
983 /* lis case */
984 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
985 } else {
986 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
987 cpu_gpr[rA(ctx->opcode)], simm << 16);
988 }
989 }
990
991 /* addpcis */
992 static void gen_addpcis(DisasContext *ctx)
993 {
994 target_long d = DX(ctx->opcode);
995
996 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
997 }
998
999 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1000 TCGv arg2, int sign, int compute_ov)
1001 {
1002 TCGv_i32 t0 = tcg_temp_new_i32();
1003 TCGv_i32 t1 = tcg_temp_new_i32();
1004 TCGv_i32 t2 = tcg_temp_new_i32();
1005 TCGv_i32 t3 = tcg_temp_new_i32();
1006
1007 tcg_gen_trunc_tl_i32(t0, arg1);
1008 tcg_gen_trunc_tl_i32(t1, arg2);
1009 if (sign) {
1010 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1012 tcg_gen_and_i32(t2, t2, t3);
1013 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1014 tcg_gen_or_i32(t2, t2, t3);
1015 tcg_gen_movi_i32(t3, 0);
1016 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1017 tcg_gen_div_i32(t3, t0, t1);
1018 tcg_gen_extu_i32_tl(ret, t3);
1019 } else {
1020 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1021 tcg_gen_movi_i32(t3, 0);
1022 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1023 tcg_gen_divu_i32(t3, t0, t1);
1024 tcg_gen_extu_i32_tl(ret, t3);
1025 }
1026 if (compute_ov) {
1027 tcg_gen_extu_i32_tl(cpu_ov, t2);
1028 if (is_isa300(ctx)) {
1029 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1030 }
1031 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1032 }
1033 tcg_temp_free_i32(t0);
1034 tcg_temp_free_i32(t1);
1035 tcg_temp_free_i32(t2);
1036 tcg_temp_free_i32(t3);
1037
1038 if (unlikely(Rc(ctx->opcode) != 0))
1039 gen_set_Rc0(ctx, ret);
1040 }
1041 /* Div functions */
1042 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1043 static void glue(gen_, name)(DisasContext *ctx) \
1044 { \
1045 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1046 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1047 sign, compute_ov); \
1048 }
1049 /* divwu divwu. divwuo divwuo. */
1050 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1051 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1052 /* divw divw. divwo divwo. */
1053 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1054 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1055
1056 /* div[wd]eu[o][.] */
1057 #define GEN_DIVE(name, hlpr, compute_ov) \
1058 static void gen_##name(DisasContext *ctx) \
1059 { \
1060 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1061 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1062 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1063 tcg_temp_free_i32(t0); \
1064 if (unlikely(Rc(ctx->opcode) != 0)) { \
1065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1066 } \
1067 }
1068
1069 GEN_DIVE(divweu, divweu, 0);
1070 GEN_DIVE(divweuo, divweu, 1);
1071 GEN_DIVE(divwe, divwe, 0);
1072 GEN_DIVE(divweo, divwe, 1);
1073
1074 #if defined(TARGET_PPC64)
1075 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1076 TCGv arg2, int sign, int compute_ov)
1077 {
1078 TCGv_i64 t0 = tcg_temp_new_i64();
1079 TCGv_i64 t1 = tcg_temp_new_i64();
1080 TCGv_i64 t2 = tcg_temp_new_i64();
1081 TCGv_i64 t3 = tcg_temp_new_i64();
1082
1083 tcg_gen_mov_i64(t0, arg1);
1084 tcg_gen_mov_i64(t1, arg2);
1085 if (sign) {
1086 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1088 tcg_gen_and_i64(t2, t2, t3);
1089 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1090 tcg_gen_or_i64(t2, t2, t3);
1091 tcg_gen_movi_i64(t3, 0);
1092 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1093 tcg_gen_div_i64(ret, t0, t1);
1094 } else {
1095 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1096 tcg_gen_movi_i64(t3, 0);
1097 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1098 tcg_gen_divu_i64(ret, t0, t1);
1099 }
1100 if (compute_ov) {
1101 tcg_gen_mov_tl(cpu_ov, t2);
1102 if (is_isa300(ctx)) {
1103 tcg_gen_mov_tl(cpu_ov32, t2);
1104 }
1105 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1106 }
1107 tcg_temp_free_i64(t0);
1108 tcg_temp_free_i64(t1);
1109 tcg_temp_free_i64(t2);
1110 tcg_temp_free_i64(t3);
1111
1112 if (unlikely(Rc(ctx->opcode) != 0))
1113 gen_set_Rc0(ctx, ret);
1114 }
1115
1116 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1117 static void glue(gen_, name)(DisasContext *ctx) \
1118 { \
1119 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1121 sign, compute_ov); \
1122 }
1123 /* divdu divdu. divduo divduo. */
1124 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1125 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1126 /* divd divd. divdo divdo. */
1127 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1128 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1129
1130 GEN_DIVE(divdeu, divdeu, 0);
1131 GEN_DIVE(divdeuo, divdeu, 1);
1132 GEN_DIVE(divde, divde, 0);
1133 GEN_DIVE(divdeo, divde, 1);
1134 #endif
1135
1136 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1137 TCGv arg2, int sign)
1138 {
1139 TCGv_i32 t0 = tcg_temp_new_i32();
1140 TCGv_i32 t1 = tcg_temp_new_i32();
1141
1142 tcg_gen_trunc_tl_i32(t0, arg1);
1143 tcg_gen_trunc_tl_i32(t1, arg2);
1144 if (sign) {
1145 TCGv_i32 t2 = tcg_temp_new_i32();
1146 TCGv_i32 t3 = tcg_temp_new_i32();
1147 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1148 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1149 tcg_gen_and_i32(t2, t2, t3);
1150 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1151 tcg_gen_or_i32(t2, t2, t3);
1152 tcg_gen_movi_i32(t3, 0);
1153 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1154 tcg_gen_rem_i32(t3, t0, t1);
1155 tcg_gen_ext_i32_tl(ret, t3);
1156 tcg_temp_free_i32(t2);
1157 tcg_temp_free_i32(t3);
1158 } else {
1159 TCGv_i32 t2 = tcg_const_i32(1);
1160 TCGv_i32 t3 = tcg_const_i32(0);
1161 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1162 tcg_gen_remu_i32(t3, t0, t1);
1163 tcg_gen_extu_i32_tl(ret, t3);
1164 tcg_temp_free_i32(t2);
1165 tcg_temp_free_i32(t3);
1166 }
1167 tcg_temp_free_i32(t0);
1168 tcg_temp_free_i32(t1);
1169 }
1170
1171 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1172 static void glue(gen_, name)(DisasContext *ctx) \
1173 { \
1174 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1175 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1176 sign); \
1177 }
1178
1179 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1180 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1181
1182 #if defined(TARGET_PPC64)
1183 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1184 TCGv arg2, int sign)
1185 {
1186 TCGv_i64 t0 = tcg_temp_new_i64();
1187 TCGv_i64 t1 = tcg_temp_new_i64();
1188
1189 tcg_gen_mov_i64(t0, arg1);
1190 tcg_gen_mov_i64(t1, arg2);
1191 if (sign) {
1192 TCGv_i64 t2 = tcg_temp_new_i64();
1193 TCGv_i64 t3 = tcg_temp_new_i64();
1194 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1195 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1196 tcg_gen_and_i64(t2, t2, t3);
1197 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1198 tcg_gen_or_i64(t2, t2, t3);
1199 tcg_gen_movi_i64(t3, 0);
1200 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1201 tcg_gen_rem_i64(ret, t0, t1);
1202 tcg_temp_free_i64(t2);
1203 tcg_temp_free_i64(t3);
1204 } else {
1205 TCGv_i64 t2 = tcg_const_i64(1);
1206 TCGv_i64 t3 = tcg_const_i64(0);
1207 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1208 tcg_gen_remu_i64(ret, t0, t1);
1209 tcg_temp_free_i64(t2);
1210 tcg_temp_free_i64(t3);
1211 }
1212 tcg_temp_free_i64(t0);
1213 tcg_temp_free_i64(t1);
1214 }
1215
1216 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1217 static void glue(gen_, name)(DisasContext *ctx) \
1218 { \
1219 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1220 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1221 sign); \
1222 }
1223
1224 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1225 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1226 #endif
1227
1228 /* mulhw mulhw. */
1229 static void gen_mulhw(DisasContext *ctx)
1230 {
1231 TCGv_i32 t0 = tcg_temp_new_i32();
1232 TCGv_i32 t1 = tcg_temp_new_i32();
1233
1234 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1235 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1236 tcg_gen_muls2_i32(t0, t1, t0, t1);
1237 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1238 tcg_temp_free_i32(t0);
1239 tcg_temp_free_i32(t1);
1240 if (unlikely(Rc(ctx->opcode) != 0))
1241 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1242 }
1243
1244 /* mulhwu mulhwu. */
1245 static void gen_mulhwu(DisasContext *ctx)
1246 {
1247 TCGv_i32 t0 = tcg_temp_new_i32();
1248 TCGv_i32 t1 = tcg_temp_new_i32();
1249
1250 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1251 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1252 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1253 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1254 tcg_temp_free_i32(t0);
1255 tcg_temp_free_i32(t1);
1256 if (unlikely(Rc(ctx->opcode) != 0))
1257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1258 }
1259
1260 /* mullw mullw. */
1261 static void gen_mullw(DisasContext *ctx)
1262 {
1263 #if defined(TARGET_PPC64)
1264 TCGv_i64 t0, t1;
1265 t0 = tcg_temp_new_i64();
1266 t1 = tcg_temp_new_i64();
1267 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1268 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1269 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1270 tcg_temp_free(t0);
1271 tcg_temp_free(t1);
1272 #else
1273 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1274 cpu_gpr[rB(ctx->opcode)]);
1275 #endif
1276 if (unlikely(Rc(ctx->opcode) != 0))
1277 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1278 }
1279
1280 /* mullwo mullwo. */
1281 static void gen_mullwo(DisasContext *ctx)
1282 {
1283 TCGv_i32 t0 = tcg_temp_new_i32();
1284 TCGv_i32 t1 = tcg_temp_new_i32();
1285
1286 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1287 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1288 tcg_gen_muls2_i32(t0, t1, t0, t1);
1289 #if defined(TARGET_PPC64)
1290 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1291 #else
1292 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1293 #endif
1294
1295 tcg_gen_sari_i32(t0, t0, 31);
1296 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1297 tcg_gen_extu_i32_tl(cpu_ov, t0);
1298 if (is_isa300(ctx)) {
1299 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1300 }
1301 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1302
1303 tcg_temp_free_i32(t0);
1304 tcg_temp_free_i32(t1);
1305 if (unlikely(Rc(ctx->opcode) != 0))
1306 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1307 }
1308
1309 /* mulli */
1310 static void gen_mulli(DisasContext *ctx)
1311 {
1312 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1313 SIMM(ctx->opcode));
1314 }
1315
1316 #if defined(TARGET_PPC64)
1317 /* mulhd mulhd. */
1318 static void gen_mulhd(DisasContext *ctx)
1319 {
1320 TCGv lo = tcg_temp_new();
1321 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1322 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1323 tcg_temp_free(lo);
1324 if (unlikely(Rc(ctx->opcode) != 0)) {
1325 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1326 }
1327 }
1328
1329 /* mulhdu mulhdu. */
1330 static void gen_mulhdu(DisasContext *ctx)
1331 {
1332 TCGv lo = tcg_temp_new();
1333 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1334 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1335 tcg_temp_free(lo);
1336 if (unlikely(Rc(ctx->opcode) != 0)) {
1337 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1338 }
1339 }
1340
1341 /* mulld mulld. */
1342 static void gen_mulld(DisasContext *ctx)
1343 {
1344 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1345 cpu_gpr[rB(ctx->opcode)]);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1348 }
1349
1350 /* mulldo mulldo. */
1351 static void gen_mulldo(DisasContext *ctx)
1352 {
1353 TCGv_i64 t0 = tcg_temp_new_i64();
1354 TCGv_i64 t1 = tcg_temp_new_i64();
1355
1356 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1357 cpu_gpr[rB(ctx->opcode)]);
1358 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1359
1360 tcg_gen_sari_i64(t0, t0, 63);
1361 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1362 if (is_isa300(ctx)) {
1363 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1364 }
1365 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1366
1367 tcg_temp_free_i64(t0);
1368 tcg_temp_free_i64(t1);
1369
1370 if (unlikely(Rc(ctx->opcode) != 0)) {
1371 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1372 }
1373 }
1374 #endif
1375
1376 /* Common subf function */
1377 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1378 TCGv arg2, bool add_ca, bool compute_ca,
1379 bool compute_ov, bool compute_rc0)
1380 {
1381 TCGv t0 = ret;
1382
1383 if (compute_ca || compute_ov) {
1384 t0 = tcg_temp_new();
1385 }
1386
1387 if (compute_ca) {
1388 /* dest = ~arg1 + arg2 [+ ca]. */
1389 if (NARROW_MODE(ctx)) {
1390 /* Caution: a non-obvious corner case of the spec is that we
1391 must produce the *entire* 64-bit addition, but produce the
1392 carry into bit 32. */
1393 TCGv inv1 = tcg_temp_new();
1394 TCGv t1 = tcg_temp_new();
1395 tcg_gen_not_tl(inv1, arg1);
1396 if (add_ca) {
1397 tcg_gen_add_tl(t0, arg2, cpu_ca);
1398 } else {
1399 tcg_gen_addi_tl(t0, arg2, 1);
1400 }
1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1402 tcg_gen_add_tl(t0, t0, inv1);
1403 tcg_temp_free(inv1);
1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1405 tcg_temp_free(t1);
1406 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1407 if (is_isa300(ctx)) {
1408 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1409 }
1410 } else if (add_ca) {
1411 TCGv zero, inv1 = tcg_temp_new();
1412 tcg_gen_not_tl(inv1, arg1);
1413 zero = tcg_const_tl(0);
1414 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1415 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1416 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1417 tcg_temp_free(zero);
1418 tcg_temp_free(inv1);
1419 } else {
1420 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1421 tcg_gen_sub_tl(t0, arg2, arg1);
1422 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1423 }
1424 } else if (add_ca) {
1425 /* Since we're ignoring carry-out, we can simplify the
1426 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1427 tcg_gen_sub_tl(t0, arg2, arg1);
1428 tcg_gen_add_tl(t0, t0, cpu_ca);
1429 tcg_gen_subi_tl(t0, t0, 1);
1430 } else {
1431 tcg_gen_sub_tl(t0, arg2, arg1);
1432 }
1433
1434 if (compute_ov) {
1435 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1436 }
1437 if (unlikely(compute_rc0)) {
1438 gen_set_Rc0(ctx, t0);
1439 }
1440
1441 if (!TCGV_EQUAL(t0, ret)) {
1442 tcg_gen_mov_tl(ret, t0);
1443 tcg_temp_free(t0);
1444 }
1445 }
1446 /* Sub functions with Two operands functions */
1447 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1448 static void glue(gen_, name)(DisasContext *ctx) \
1449 { \
1450 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1451 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1452 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1453 }
1454 /* Sub functions with one operand and one immediate */
1455 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1456 add_ca, compute_ca, compute_ov) \
1457 static void glue(gen_, name)(DisasContext *ctx) \
1458 { \
1459 TCGv t0 = tcg_const_tl(const_val); \
1460 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1461 cpu_gpr[rA(ctx->opcode)], t0, \
1462 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1463 tcg_temp_free(t0); \
1464 }
1465 /* subf subf. subfo subfo. */
1466 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1467 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1468 /* subfc subfc. subfco subfco. */
1469 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1470 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1471 /* subfe subfe. subfeo subfo. */
1472 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1473 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1474 /* subfme subfme. subfmeo subfmeo. */
1475 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1476 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1477 /* subfze subfze. subfzeo subfzeo.*/
1478 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1479 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1480
1481 /* subfic */
1482 static void gen_subfic(DisasContext *ctx)
1483 {
1484 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1485 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1486 c, 0, 1, 0, 0);
1487 tcg_temp_free(c);
1488 }
1489
1490 /* neg neg. nego nego. */
1491 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1492 {
1493 TCGv zero = tcg_const_tl(0);
1494 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1495 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1496 tcg_temp_free(zero);
1497 }
1498
1499 static void gen_neg(DisasContext *ctx)
1500 {
1501 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1502 if (unlikely(Rc(ctx->opcode))) {
1503 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1504 }
1505 }
1506
1507 static void gen_nego(DisasContext *ctx)
1508 {
1509 gen_op_arith_neg(ctx, 1);
1510 }
1511
1512 /*** Integer logical ***/
1513 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1514 static void glue(gen_, name)(DisasContext *ctx) \
1515 { \
1516 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1517 cpu_gpr[rB(ctx->opcode)]); \
1518 if (unlikely(Rc(ctx->opcode) != 0)) \
1519 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1520 }
1521
1522 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1523 static void glue(gen_, name)(DisasContext *ctx) \
1524 { \
1525 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1526 if (unlikely(Rc(ctx->opcode) != 0)) \
1527 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1528 }
1529
1530 /* and & and. */
1531 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1532 /* andc & andc. */
1533 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1534
1535 /* andi. */
1536 static void gen_andi_(DisasContext *ctx)
1537 {
1538 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1539 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1540 }
1541
1542 /* andis. */
1543 static void gen_andis_(DisasContext *ctx)
1544 {
1545 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1546 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1547 }
1548
1549 /* cntlzw */
1550 static void gen_cntlzw(DisasContext *ctx)
1551 {
1552 TCGv_i32 t = tcg_temp_new_i32();
1553
1554 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1555 tcg_gen_clzi_i32(t, t, 32);
1556 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1557 tcg_temp_free_i32(t);
1558
1559 if (unlikely(Rc(ctx->opcode) != 0))
1560 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1561 }
1562
1563 /* cnttzw */
1564 static void gen_cnttzw(DisasContext *ctx)
1565 {
1566 TCGv_i32 t = tcg_temp_new_i32();
1567
1568 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1569 tcg_gen_ctzi_i32(t, t, 32);
1570 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1571 tcg_temp_free_i32(t);
1572
1573 if (unlikely(Rc(ctx->opcode) != 0)) {
1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1575 }
1576 }
1577
1578 /* eqv & eqv. */
1579 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1580 /* extsb & extsb. */
1581 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1582 /* extsh & extsh. */
1583 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1584 /* nand & nand. */
1585 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1586 /* nor & nor. */
1587 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1588
1589 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1590 static void gen_pause(DisasContext *ctx)
1591 {
1592 TCGv_i32 t0 = tcg_const_i32(0);
1593 tcg_gen_st_i32(t0, cpu_env,
1594 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1595 tcg_temp_free_i32(t0);
1596
1597 /* Stop translation, this gives other CPUs a chance to run */
1598 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1599 }
1600 #endif /* defined(TARGET_PPC64) */
1601
1602 /* or & or. */
1603 static void gen_or(DisasContext *ctx)
1604 {
1605 int rs, ra, rb;
1606
1607 rs = rS(ctx->opcode);
1608 ra = rA(ctx->opcode);
1609 rb = rB(ctx->opcode);
1610 /* Optimisation for mr. ri case */
1611 if (rs != ra || rs != rb) {
1612 if (rs != rb)
1613 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1614 else
1615 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1616 if (unlikely(Rc(ctx->opcode) != 0))
1617 gen_set_Rc0(ctx, cpu_gpr[ra]);
1618 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1619 gen_set_Rc0(ctx, cpu_gpr[rs]);
1620 #if defined(TARGET_PPC64)
1621 } else if (rs != 0) { /* 0 is nop */
1622 int prio = 0;
1623
1624 switch (rs) {
1625 case 1:
1626 /* Set process priority to low */
1627 prio = 2;
1628 break;
1629 case 6:
1630 /* Set process priority to medium-low */
1631 prio = 3;
1632 break;
1633 case 2:
1634 /* Set process priority to normal */
1635 prio = 4;
1636 break;
1637 #if !defined(CONFIG_USER_ONLY)
1638 case 31:
1639 if (!ctx->pr) {
1640 /* Set process priority to very low */
1641 prio = 1;
1642 }
1643 break;
1644 case 5:
1645 if (!ctx->pr) {
1646 /* Set process priority to medium-hight */
1647 prio = 5;
1648 }
1649 break;
1650 case 3:
1651 if (!ctx->pr) {
1652 /* Set process priority to high */
1653 prio = 6;
1654 }
1655 break;
1656 case 7:
1657 if (ctx->hv && !ctx->pr) {
1658 /* Set process priority to very high */
1659 prio = 7;
1660 }
1661 break;
1662 #endif
1663 default:
1664 break;
1665 }
1666 if (prio) {
1667 TCGv t0 = tcg_temp_new();
1668 gen_load_spr(t0, SPR_PPR);
1669 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1670 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1671 gen_store_spr(SPR_PPR, t0);
1672 tcg_temp_free(t0);
1673 }
1674 #if !defined(CONFIG_USER_ONLY)
1675 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1676 * CPU and the kernel hangs. This applies to all encodings other
1677 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1678 * and all currently undefined.
1679 */
1680 gen_pause(ctx);
1681 #endif
1682 #endif
1683 }
1684 }
1685 /* orc & orc. */
1686 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1687
1688 /* xor & xor. */
1689 static void gen_xor(DisasContext *ctx)
1690 {
1691 /* Optimisation for "set to zero" case */
1692 if (rS(ctx->opcode) != rB(ctx->opcode))
1693 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1694 else
1695 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1696 if (unlikely(Rc(ctx->opcode) != 0))
1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1698 }
1699
1700 /* ori */
1701 static void gen_ori(DisasContext *ctx)
1702 {
1703 target_ulong uimm = UIMM(ctx->opcode);
1704
1705 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1706 return;
1707 }
1708 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1709 }
1710
1711 /* oris */
1712 static void gen_oris(DisasContext *ctx)
1713 {
1714 target_ulong uimm = UIMM(ctx->opcode);
1715
1716 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1717 /* NOP */
1718 return;
1719 }
1720 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1721 }
1722
1723 /* xori */
1724 static void gen_xori(DisasContext *ctx)
1725 {
1726 target_ulong uimm = UIMM(ctx->opcode);
1727
1728 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1729 /* NOP */
1730 return;
1731 }
1732 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1733 }
1734
1735 /* xoris */
1736 static void gen_xoris(DisasContext *ctx)
1737 {
1738 target_ulong uimm = UIMM(ctx->opcode);
1739
1740 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1741 /* NOP */
1742 return;
1743 }
1744 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1745 }
1746
1747 /* popcntb : PowerPC 2.03 specification */
1748 static void gen_popcntb(DisasContext *ctx)
1749 {
1750 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1751 }
1752
1753 static void gen_popcntw(DisasContext *ctx)
1754 {
1755 #if defined(TARGET_PPC64)
1756 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1757 #else
1758 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1759 #endif
1760 }
1761
1762 #if defined(TARGET_PPC64)
1763 /* popcntd: PowerPC 2.06 specification */
1764 static void gen_popcntd(DisasContext *ctx)
1765 {
1766 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1767 }
1768 #endif
1769
1770 /* prtyw: PowerPC 2.05 specification */
1771 static void gen_prtyw(DisasContext *ctx)
1772 {
1773 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1774 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1775 TCGv t0 = tcg_temp_new();
1776 tcg_gen_shri_tl(t0, rs, 16);
1777 tcg_gen_xor_tl(ra, rs, t0);
1778 tcg_gen_shri_tl(t0, ra, 8);
1779 tcg_gen_xor_tl(ra, ra, t0);
1780 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1781 tcg_temp_free(t0);
1782 }
1783
1784 #if defined(TARGET_PPC64)
1785 /* prtyd: PowerPC 2.05 specification */
1786 static void gen_prtyd(DisasContext *ctx)
1787 {
1788 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1789 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1790 TCGv t0 = tcg_temp_new();
1791 tcg_gen_shri_tl(t0, rs, 32);
1792 tcg_gen_xor_tl(ra, rs, t0);
1793 tcg_gen_shri_tl(t0, ra, 16);
1794 tcg_gen_xor_tl(ra, ra, t0);
1795 tcg_gen_shri_tl(t0, ra, 8);
1796 tcg_gen_xor_tl(ra, ra, t0);
1797 tcg_gen_andi_tl(ra, ra, 1);
1798 tcg_temp_free(t0);
1799 }
1800 #endif
1801
1802 #if defined(TARGET_PPC64)
1803 /* bpermd */
1804 static void gen_bpermd(DisasContext *ctx)
1805 {
1806 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1807 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1808 }
1809 #endif
1810
1811 #if defined(TARGET_PPC64)
1812 /* extsw & extsw. */
1813 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1814
1815 /* cntlzd */
1816 static void gen_cntlzd(DisasContext *ctx)
1817 {
1818 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1819 if (unlikely(Rc(ctx->opcode) != 0))
1820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1821 }
1822
1823 /* cnttzd */
1824 static void gen_cnttzd(DisasContext *ctx)
1825 {
1826 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1827 if (unlikely(Rc(ctx->opcode) != 0)) {
1828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1829 }
1830 }
1831
1832 /* darn */
1833 static void gen_darn(DisasContext *ctx)
1834 {
1835 int l = L(ctx->opcode);
1836
1837 if (l == 0) {
1838 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1839 } else if (l <= 2) {
1840 /* Return 64-bit random for both CRN and RRN */
1841 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1842 } else {
1843 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1844 }
1845 }
1846 #endif
1847
1848 /*** Integer rotate ***/
1849
1850 /* rlwimi & rlwimi. */
1851 static void gen_rlwimi(DisasContext *ctx)
1852 {
1853 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1854 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1855 uint32_t sh = SH(ctx->opcode);
1856 uint32_t mb = MB(ctx->opcode);
1857 uint32_t me = ME(ctx->opcode);
1858
1859 if (sh == (31-me) && mb <= me) {
1860 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1861 } else {
1862 target_ulong mask;
1863 TCGv t1;
1864
1865 #if defined(TARGET_PPC64)
1866 mb += 32;
1867 me += 32;
1868 #endif
1869 mask = MASK(mb, me);
1870
1871 t1 = tcg_temp_new();
1872 if (mask <= 0xffffffffu) {
1873 TCGv_i32 t0 = tcg_temp_new_i32();
1874 tcg_gen_trunc_tl_i32(t0, t_rs);
1875 tcg_gen_rotli_i32(t0, t0, sh);
1876 tcg_gen_extu_i32_tl(t1, t0);
1877 tcg_temp_free_i32(t0);
1878 } else {
1879 #if defined(TARGET_PPC64)
1880 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1881 tcg_gen_rotli_i64(t1, t1, sh);
1882 #else
1883 g_assert_not_reached();
1884 #endif
1885 }
1886
1887 tcg_gen_andi_tl(t1, t1, mask);
1888 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1889 tcg_gen_or_tl(t_ra, t_ra, t1);
1890 tcg_temp_free(t1);
1891 }
1892 if (unlikely(Rc(ctx->opcode) != 0)) {
1893 gen_set_Rc0(ctx, t_ra);
1894 }
1895 }
1896
1897 /* rlwinm & rlwinm. */
1898 static void gen_rlwinm(DisasContext *ctx)
1899 {
1900 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1901 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1902 int sh = SH(ctx->opcode);
1903 int mb = MB(ctx->opcode);
1904 int me = ME(ctx->opcode);
1905 int len = me - mb + 1;
1906 int rsh = (32 - sh) & 31;
1907
1908 if (sh != 0 && len > 0 && me == (31 - sh)) {
1909 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1910 } else if (me == 31 && rsh + len <= 32) {
1911 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1912 } else {
1913 target_ulong mask;
1914 #if defined(TARGET_PPC64)
1915 mb += 32;
1916 me += 32;
1917 #endif
1918 mask = MASK(mb, me);
1919 if (sh == 0) {
1920 tcg_gen_andi_tl(t_ra, t_rs, mask);
1921 } else if (mask <= 0xffffffffu) {
1922 TCGv_i32 t0 = tcg_temp_new_i32();
1923 tcg_gen_trunc_tl_i32(t0, t_rs);
1924 tcg_gen_rotli_i32(t0, t0, sh);
1925 tcg_gen_andi_i32(t0, t0, mask);
1926 tcg_gen_extu_i32_tl(t_ra, t0);
1927 tcg_temp_free_i32(t0);
1928 } else {
1929 #if defined(TARGET_PPC64)
1930 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1931 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1932 tcg_gen_andi_i64(t_ra, t_ra, mask);
1933 #else
1934 g_assert_not_reached();
1935 #endif
1936 }
1937 }
1938 if (unlikely(Rc(ctx->opcode) != 0)) {
1939 gen_set_Rc0(ctx, t_ra);
1940 }
1941 }
1942
1943 /* rlwnm & rlwnm. */
1944 static void gen_rlwnm(DisasContext *ctx)
1945 {
1946 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1947 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1948 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1949 uint32_t mb = MB(ctx->opcode);
1950 uint32_t me = ME(ctx->opcode);
1951 target_ulong mask;
1952
1953 #if defined(TARGET_PPC64)
1954 mb += 32;
1955 me += 32;
1956 #endif
1957 mask = MASK(mb, me);
1958
1959 if (mask <= 0xffffffffu) {
1960 TCGv_i32 t0 = tcg_temp_new_i32();
1961 TCGv_i32 t1 = tcg_temp_new_i32();
1962 tcg_gen_trunc_tl_i32(t0, t_rb);
1963 tcg_gen_trunc_tl_i32(t1, t_rs);
1964 tcg_gen_andi_i32(t0, t0, 0x1f);
1965 tcg_gen_rotl_i32(t1, t1, t0);
1966 tcg_gen_extu_i32_tl(t_ra, t1);
1967 tcg_temp_free_i32(t0);
1968 tcg_temp_free_i32(t1);
1969 } else {
1970 #if defined(TARGET_PPC64)
1971 TCGv_i64 t0 = tcg_temp_new_i64();
1972 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1973 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1974 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1975 tcg_temp_free_i64(t0);
1976 #else
1977 g_assert_not_reached();
1978 #endif
1979 }
1980
1981 tcg_gen_andi_tl(t_ra, t_ra, mask);
1982
1983 if (unlikely(Rc(ctx->opcode) != 0)) {
1984 gen_set_Rc0(ctx, t_ra);
1985 }
1986 }
1987
1988 #if defined(TARGET_PPC64)
1989 #define GEN_PPC64_R2(name, opc1, opc2) \
1990 static void glue(gen_, name##0)(DisasContext *ctx) \
1991 { \
1992 gen_##name(ctx, 0); \
1993 } \
1994 \
1995 static void glue(gen_, name##1)(DisasContext *ctx) \
1996 { \
1997 gen_##name(ctx, 1); \
1998 }
1999 #define GEN_PPC64_R4(name, opc1, opc2) \
2000 static void glue(gen_, name##0)(DisasContext *ctx) \
2001 { \
2002 gen_##name(ctx, 0, 0); \
2003 } \
2004 \
2005 static void glue(gen_, name##1)(DisasContext *ctx) \
2006 { \
2007 gen_##name(ctx, 0, 1); \
2008 } \
2009 \
2010 static void glue(gen_, name##2)(DisasContext *ctx) \
2011 { \
2012 gen_##name(ctx, 1, 0); \
2013 } \
2014 \
2015 static void glue(gen_, name##3)(DisasContext *ctx) \
2016 { \
2017 gen_##name(ctx, 1, 1); \
2018 }
2019
2020 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2021 {
2022 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2023 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2024 int len = me - mb + 1;
2025 int rsh = (64 - sh) & 63;
2026
2027 if (sh != 0 && len > 0 && me == (63 - sh)) {
2028 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2029 } else if (me == 63 && rsh + len <= 64) {
2030 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2031 } else {
2032 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2033 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2034 }
2035 if (unlikely(Rc(ctx->opcode) != 0)) {
2036 gen_set_Rc0(ctx, t_ra);
2037 }
2038 }
2039
2040 /* rldicl - rldicl. */
2041 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2042 {
2043 uint32_t sh, mb;
2044
2045 sh = SH(ctx->opcode) | (shn << 5);
2046 mb = MB(ctx->opcode) | (mbn << 5);
2047 gen_rldinm(ctx, mb, 63, sh);
2048 }
2049 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2050
2051 /* rldicr - rldicr. */
2052 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2053 {
2054 uint32_t sh, me;
2055
2056 sh = SH(ctx->opcode) | (shn << 5);
2057 me = MB(ctx->opcode) | (men << 5);
2058 gen_rldinm(ctx, 0, me, sh);
2059 }
2060 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2061
2062 /* rldic - rldic. */
2063 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2064 {
2065 uint32_t sh, mb;
2066
2067 sh = SH(ctx->opcode) | (shn << 5);
2068 mb = MB(ctx->opcode) | (mbn << 5);
2069 gen_rldinm(ctx, mb, 63 - sh, sh);
2070 }
2071 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2072
2073 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2074 {
2075 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2076 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2077 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2078 TCGv t0;
2079
2080 t0 = tcg_temp_new();
2081 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2082 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2083 tcg_temp_free(t0);
2084
2085 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2086 if (unlikely(Rc(ctx->opcode) != 0)) {
2087 gen_set_Rc0(ctx, t_ra);
2088 }
2089 }
2090
2091 /* rldcl - rldcl. */
2092 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2093 {
2094 uint32_t mb;
2095
2096 mb = MB(ctx->opcode) | (mbn << 5);
2097 gen_rldnm(ctx, mb, 63);
2098 }
2099 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2100
2101 /* rldcr - rldcr. */
2102 static inline void gen_rldcr(DisasContext *ctx, int men)
2103 {
2104 uint32_t me;
2105
2106 me = MB(ctx->opcode) | (men << 5);
2107 gen_rldnm(ctx, 0, me);
2108 }
2109 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2110
2111 /* rldimi - rldimi. */
2112 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2113 {
2114 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2115 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2116 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2117 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2118 uint32_t me = 63 - sh;
2119
2120 if (mb <= me) {
2121 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2122 } else {
2123 target_ulong mask = MASK(mb, me);
2124 TCGv t1 = tcg_temp_new();
2125
2126 tcg_gen_rotli_tl(t1, t_rs, sh);
2127 tcg_gen_andi_tl(t1, t1, mask);
2128 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2129 tcg_gen_or_tl(t_ra, t_ra, t1);
2130 tcg_temp_free(t1);
2131 }
2132 if (unlikely(Rc(ctx->opcode) != 0)) {
2133 gen_set_Rc0(ctx, t_ra);
2134 }
2135 }
2136 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2137 #endif
2138
2139 /*** Integer shift ***/
2140
2141 /* slw & slw. */
2142 static void gen_slw(DisasContext *ctx)
2143 {
2144 TCGv t0, t1;
2145
2146 t0 = tcg_temp_new();
2147 /* AND rS with a mask that is 0 when rB >= 0x20 */
2148 #if defined(TARGET_PPC64)
2149 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2150 tcg_gen_sari_tl(t0, t0, 0x3f);
2151 #else
2152 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2153 tcg_gen_sari_tl(t0, t0, 0x1f);
2154 #endif
2155 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2156 t1 = tcg_temp_new();
2157 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2158 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2159 tcg_temp_free(t1);
2160 tcg_temp_free(t0);
2161 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2162 if (unlikely(Rc(ctx->opcode) != 0))
2163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2164 }
2165
2166 /* sraw & sraw. */
2167 static void gen_sraw(DisasContext *ctx)
2168 {
2169 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2170 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2171 if (unlikely(Rc(ctx->opcode) != 0))
2172 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2173 }
2174
2175 /* srawi & srawi. */
2176 static void gen_srawi(DisasContext *ctx)
2177 {
2178 int sh = SH(ctx->opcode);
2179 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2180 TCGv src = cpu_gpr[rS(ctx->opcode)];
2181 if (sh == 0) {
2182 tcg_gen_ext32s_tl(dst, src);
2183 tcg_gen_movi_tl(cpu_ca, 0);
2184 if (is_isa300(ctx)) {
2185 tcg_gen_movi_tl(cpu_ca32, 0);
2186 }
2187 } else {
2188 TCGv t0;
2189 tcg_gen_ext32s_tl(dst, src);
2190 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2191 t0 = tcg_temp_new();
2192 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2193 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2194 tcg_temp_free(t0);
2195 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2196 if (is_isa300(ctx)) {
2197 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2198 }
2199 tcg_gen_sari_tl(dst, dst, sh);
2200 }
2201 if (unlikely(Rc(ctx->opcode) != 0)) {
2202 gen_set_Rc0(ctx, dst);
2203 }
2204 }
2205
2206 /* srw & srw. */
2207 static void gen_srw(DisasContext *ctx)
2208 {
2209 TCGv t0, t1;
2210
2211 t0 = tcg_temp_new();
2212 /* AND rS with a mask that is 0 when rB >= 0x20 */
2213 #if defined(TARGET_PPC64)
2214 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2215 tcg_gen_sari_tl(t0, t0, 0x3f);
2216 #else
2217 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2218 tcg_gen_sari_tl(t0, t0, 0x1f);
2219 #endif
2220 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2221 tcg_gen_ext32u_tl(t0, t0);
2222 t1 = tcg_temp_new();
2223 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2224 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2225 tcg_temp_free(t1);
2226 tcg_temp_free(t0);
2227 if (unlikely(Rc(ctx->opcode) != 0))
2228 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2229 }
2230
2231 #if defined(TARGET_PPC64)
2232 /* sld & sld. */
2233 static void gen_sld(DisasContext *ctx)
2234 {
2235 TCGv t0, t1;
2236
2237 t0 = tcg_temp_new();
2238 /* AND rS with a mask that is 0 when rB >= 0x40 */
2239 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2240 tcg_gen_sari_tl(t0, t0, 0x3f);
2241 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2242 t1 = tcg_temp_new();
2243 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2244 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2245 tcg_temp_free(t1);
2246 tcg_temp_free(t0);
2247 if (unlikely(Rc(ctx->opcode) != 0))
2248 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2249 }
2250
2251 /* srad & srad. */
2252 static void gen_srad(DisasContext *ctx)
2253 {
2254 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2255 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2256 if (unlikely(Rc(ctx->opcode) != 0))
2257 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2258 }
2259 /* sradi & sradi. */
2260 static inline void gen_sradi(DisasContext *ctx, int n)
2261 {
2262 int sh = SH(ctx->opcode) + (n << 5);
2263 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2264 TCGv src = cpu_gpr[rS(ctx->opcode)];
2265 if (sh == 0) {
2266 tcg_gen_mov_tl(dst, src);
2267 tcg_gen_movi_tl(cpu_ca, 0);
2268 if (is_isa300(ctx)) {
2269 tcg_gen_movi_tl(cpu_ca32, 0);
2270 }
2271 } else {
2272 TCGv t0;
2273 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2274 t0 = tcg_temp_new();
2275 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2276 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2277 tcg_temp_free(t0);
2278 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2279 if (is_isa300(ctx)) {
2280 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2281 }
2282 tcg_gen_sari_tl(dst, src, sh);
2283 }
2284 if (unlikely(Rc(ctx->opcode) != 0)) {
2285 gen_set_Rc0(ctx, dst);
2286 }
2287 }
2288
2289 static void gen_sradi0(DisasContext *ctx)
2290 {
2291 gen_sradi(ctx, 0);
2292 }
2293
2294 static void gen_sradi1(DisasContext *ctx)
2295 {
2296 gen_sradi(ctx, 1);
2297 }
2298
2299 /* extswsli & extswsli. */
2300 static inline void gen_extswsli(DisasContext *ctx, int n)
2301 {
2302 int sh = SH(ctx->opcode) + (n << 5);
2303 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2304 TCGv src = cpu_gpr[rS(ctx->opcode)];
2305
2306 tcg_gen_ext32s_tl(dst, src);
2307 tcg_gen_shli_tl(dst, dst, sh);
2308 if (unlikely(Rc(ctx->opcode) != 0)) {
2309 gen_set_Rc0(ctx, dst);
2310 }
2311 }
2312
2313 static void gen_extswsli0(DisasContext *ctx)
2314 {
2315 gen_extswsli(ctx, 0);
2316 }
2317
2318 static void gen_extswsli1(DisasContext *ctx)
2319 {
2320 gen_extswsli(ctx, 1);
2321 }
2322
2323 /* srd & srd. */
2324 static void gen_srd(DisasContext *ctx)
2325 {
2326 TCGv t0, t1;
2327
2328 t0 = tcg_temp_new();
2329 /* AND rS with a mask that is 0 when rB >= 0x40 */
2330 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2331 tcg_gen_sari_tl(t0, t0, 0x3f);
2332 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2333 t1 = tcg_temp_new();
2334 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2335 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2336 tcg_temp_free(t1);
2337 tcg_temp_free(t0);
2338 if (unlikely(Rc(ctx->opcode) != 0))
2339 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2340 }
2341 #endif
2342
2343 /*** Addressing modes ***/
2344 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2345 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2346 target_long maskl)
2347 {
2348 target_long simm = SIMM(ctx->opcode);
2349
2350 simm &= ~maskl;
2351 if (rA(ctx->opcode) == 0) {
2352 if (NARROW_MODE(ctx)) {
2353 simm = (uint32_t)simm;
2354 }
2355 tcg_gen_movi_tl(EA, simm);
2356 } else if (likely(simm != 0)) {
2357 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2358 if (NARROW_MODE(ctx)) {
2359 tcg_gen_ext32u_tl(EA, EA);
2360 }
2361 } else {
2362 if (NARROW_MODE(ctx)) {
2363 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2364 } else {
2365 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2366 }
2367 }
2368 }
2369
2370 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2371 {
2372 if (rA(ctx->opcode) == 0) {
2373 if (NARROW_MODE(ctx)) {
2374 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2375 } else {
2376 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2377 }
2378 } else {
2379 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2380 if (NARROW_MODE(ctx)) {
2381 tcg_gen_ext32u_tl(EA, EA);
2382 }
2383 }
2384 }
2385
2386 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2387 {
2388 if (rA(ctx->opcode) == 0) {
2389 tcg_gen_movi_tl(EA, 0);
2390 } else if (NARROW_MODE(ctx)) {
2391 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2392 } else {
2393 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2394 }
2395 }
2396
2397 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2398 target_long val)
2399 {
2400 tcg_gen_addi_tl(ret, arg1, val);
2401 if (NARROW_MODE(ctx)) {
2402 tcg_gen_ext32u_tl(ret, ret);
2403 }
2404 }
2405
2406 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2407 {
2408 TCGLabel *l1 = gen_new_label();
2409 TCGv t0 = tcg_temp_new();
2410 TCGv_i32 t1, t2;
2411 tcg_gen_andi_tl(t0, EA, mask);
2412 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2413 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2414 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2415 gen_update_nip(ctx, ctx->nip - 4);
2416 gen_helper_raise_exception_err(cpu_env, t1, t2);
2417 tcg_temp_free_i32(t1);
2418 tcg_temp_free_i32(t2);
2419 gen_set_label(l1);
2420 tcg_temp_free(t0);
2421 }
2422
2423 static inline void gen_align_no_le(DisasContext *ctx)
2424 {
2425 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2426 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2427 }
2428
2429 /*** Integer load ***/
2430 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2431 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2432
2433 #define GEN_QEMU_LOAD_TL(ldop, op) \
2434 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2435 TCGv val, \
2436 TCGv addr) \
2437 { \
2438 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2439 }
2440
2441 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2442 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2443 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2444 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2445 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2446
2447 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2448 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2449
2450 #define GEN_QEMU_LOAD_64(ldop, op) \
2451 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2452 TCGv_i64 val, \
2453 TCGv addr) \
2454 { \
2455 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2456 }
2457
2458 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2459 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2460 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2461 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2462 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2463
2464 #if defined(TARGET_PPC64)
2465 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2466 #endif
2467
2468 #define GEN_QEMU_STORE_TL(stop, op) \
2469 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2470 TCGv val, \
2471 TCGv addr) \
2472 { \
2473 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2474 }
2475
2476 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2477 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2478 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2479
2480 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2481 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2482
2483 #define GEN_QEMU_STORE_64(stop, op) \
2484 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2485 TCGv_i64 val, \
2486 TCGv addr) \
2487 { \
2488 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2489 }
2490
2491 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2492 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2493 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2494 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2495
2496 #if defined(TARGET_PPC64)
2497 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2498 #endif
2499
2500 #define GEN_LD(name, ldop, opc, type) \
2501 static void glue(gen_, name)(DisasContext *ctx) \
2502 { \
2503 TCGv EA; \
2504 gen_set_access_type(ctx, ACCESS_INT); \
2505 EA = tcg_temp_new(); \
2506 gen_addr_imm_index(ctx, EA, 0); \
2507 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2508 tcg_temp_free(EA); \
2509 }
2510
2511 #define GEN_LDU(name, ldop, opc, type) \
2512 static void glue(gen_, name##u)(DisasContext *ctx) \
2513 { \
2514 TCGv EA; \
2515 if (unlikely(rA(ctx->opcode) == 0 || \
2516 rA(ctx->opcode) == rD(ctx->opcode))) { \
2517 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2518 return; \
2519 } \
2520 gen_set_access_type(ctx, ACCESS_INT); \
2521 EA = tcg_temp_new(); \
2522 if (type == PPC_64B) \
2523 gen_addr_imm_index(ctx, EA, 0x03); \
2524 else \
2525 gen_addr_imm_index(ctx, EA, 0); \
2526 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2528 tcg_temp_free(EA); \
2529 }
2530
2531 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2532 static void glue(gen_, name##ux)(DisasContext *ctx) \
2533 { \
2534 TCGv EA; \
2535 if (unlikely(rA(ctx->opcode) == 0 || \
2536 rA(ctx->opcode) == rD(ctx->opcode))) { \
2537 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2538 return; \
2539 } \
2540 gen_set_access_type(ctx, ACCESS_INT); \
2541 EA = tcg_temp_new(); \
2542 gen_addr_reg_index(ctx, EA); \
2543 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2544 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2545 tcg_temp_free(EA); \
2546 }
2547
2548 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2549 static void glue(gen_, name##x)(DisasContext *ctx) \
2550 { \
2551 TCGv EA; \
2552 chk; \
2553 gen_set_access_type(ctx, ACCESS_INT); \
2554 EA = tcg_temp_new(); \
2555 gen_addr_reg_index(ctx, EA); \
2556 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2557 tcg_temp_free(EA); \
2558 }
2559
2560 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2561 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2562
2563 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2564 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2565
2566 #define GEN_LDS(name, ldop, op, type) \
2567 GEN_LD(name, ldop, op | 0x20, type); \
2568 GEN_LDU(name, ldop, op | 0x21, type); \
2569 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2570 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2571
2572 /* lbz lbzu lbzux lbzx */
2573 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2574 /* lha lhau lhaux lhax */
2575 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2576 /* lhz lhzu lhzux lhzx */
2577 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2578 /* lwz lwzu lwzux lwzx */
2579 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2580 #if defined(TARGET_PPC64)
2581 /* lwaux */
2582 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2583 /* lwax */
2584 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2585 /* ldux */
2586 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2587 /* ldx */
2588 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2589
2590 /* CI load/store variants */
2591 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2592 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2593 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2594 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2595
2596 static void gen_ld(DisasContext *ctx)
2597 {
2598 TCGv EA;
2599 if (Rc(ctx->opcode)) {
2600 if (unlikely(rA(ctx->opcode) == 0 ||
2601 rA(ctx->opcode) == rD(ctx->opcode))) {
2602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2603 return;
2604 }
2605 }
2606 gen_set_access_type(ctx, ACCESS_INT);
2607 EA = tcg_temp_new();
2608 gen_addr_imm_index(ctx, EA, 0x03);
2609 if (ctx->opcode & 0x02) {
2610 /* lwa (lwau is undefined) */
2611 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2612 } else {
2613 /* ld - ldu */
2614 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2615 }
2616 if (Rc(ctx->opcode))
2617 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2618 tcg_temp_free(EA);
2619 }
2620
2621 /* lq */
2622 static void gen_lq(DisasContext *ctx)
2623 {
2624 int ra, rd;
2625 TCGv EA;
2626
2627 /* lq is a legal user mode instruction starting in ISA 2.07 */
2628 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2629 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2630
2631 if (!legal_in_user_mode && ctx->pr) {
2632 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2633 return;
2634 }
2635
2636 if (!le_is_supported && ctx->le_mode) {
2637 gen_align_no_le(ctx);
2638 return;
2639 }
2640 ra = rA(ctx->opcode);
2641 rd = rD(ctx->opcode);
2642 if (unlikely((rd & 1) || rd == ra)) {
2643 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2644 return;
2645 }
2646
2647 gen_set_access_type(ctx, ACCESS_INT);
2648 EA = tcg_temp_new();
2649 gen_addr_imm_index(ctx, EA, 0x0F);
2650
2651 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2652 necessary 64-bit byteswap already. */
2653 if (unlikely(ctx->le_mode)) {
2654 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2655 gen_addr_add(ctx, EA, EA, 8);
2656 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2657 } else {
2658 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2659 gen_addr_add(ctx, EA, EA, 8);
2660 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2661 }
2662 tcg_temp_free(EA);
2663 }
2664 #endif
2665
2666 /*** Integer store ***/
2667 #define GEN_ST(name, stop, opc, type) \
2668 static void glue(gen_, name)(DisasContext *ctx) \
2669 { \
2670 TCGv EA; \
2671 gen_set_access_type(ctx, ACCESS_INT); \
2672 EA = tcg_temp_new(); \
2673 gen_addr_imm_index(ctx, EA, 0); \
2674 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2675 tcg_temp_free(EA); \
2676 }
2677
2678 #define GEN_STU(name, stop, opc, type) \
2679 static void glue(gen_, stop##u)(DisasContext *ctx) \
2680 { \
2681 TCGv EA; \
2682 if (unlikely(rA(ctx->opcode) == 0)) { \
2683 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2684 return; \
2685 } \
2686 gen_set_access_type(ctx, ACCESS_INT); \
2687 EA = tcg_temp_new(); \
2688 if (type == PPC_64B) \
2689 gen_addr_imm_index(ctx, EA, 0x03); \
2690 else \
2691 gen_addr_imm_index(ctx, EA, 0); \
2692 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2695 }
2696
2697 #define GEN_STUX(name, stop, opc2, opc3, type) \
2698 static void glue(gen_, name##ux)(DisasContext *ctx) \
2699 { \
2700 TCGv EA; \
2701 if (unlikely(rA(ctx->opcode) == 0)) { \
2702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 return; \
2704 } \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 gen_addr_reg_index(ctx, EA); \
2708 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2709 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2710 tcg_temp_free(EA); \
2711 }
2712
2713 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2714 static void glue(gen_, name##x)(DisasContext *ctx) \
2715 { \
2716 TCGv EA; \
2717 chk; \
2718 gen_set_access_type(ctx, ACCESS_INT); \
2719 EA = tcg_temp_new(); \
2720 gen_addr_reg_index(ctx, EA); \
2721 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2722 tcg_temp_free(EA); \
2723 }
2724 #define GEN_STX(name, stop, opc2, opc3, type) \
2725 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2726
2727 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2728 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2729
2730 #define GEN_STS(name, stop, op, type) \
2731 GEN_ST(name, stop, op | 0x20, type); \
2732 GEN_STU(name, stop, op | 0x21, type); \
2733 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2734 GEN_STX(name, stop, 0x17, op | 0x00, type)
2735
2736 /* stb stbu stbux stbx */
2737 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2738 /* sth sthu sthux sthx */
2739 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2740 /* stw stwu stwux stwx */
2741 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2742 #if defined(TARGET_PPC64)
2743 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2744 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2745 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2746 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2747 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2748 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2749
2750 static void gen_std(DisasContext *ctx)
2751 {
2752 int rs;
2753 TCGv EA;
2754
2755 rs = rS(ctx->opcode);
2756 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2757 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2758 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2759
2760 if (!(ctx->insns_flags & PPC_64BX)) {
2761 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2762 }
2763
2764 if (!legal_in_user_mode && ctx->pr) {
2765 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2766 return;
2767 }
2768
2769 if (!le_is_supported && ctx->le_mode) {
2770 gen_align_no_le(ctx);
2771 return;
2772 }
2773
2774 if (unlikely(rs & 1)) {
2775 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2776 return;
2777 }
2778 gen_set_access_type(ctx, ACCESS_INT);
2779 EA = tcg_temp_new();
2780 gen_addr_imm_index(ctx, EA, 0x03);
2781
2782 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2783 necessary 64-bit byteswap already. */
2784 if (unlikely(ctx->le_mode)) {
2785 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2786 gen_addr_add(ctx, EA, EA, 8);
2787 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2788 } else {
2789 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2790 gen_addr_add(ctx, EA, EA, 8);
2791 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2792 }
2793 tcg_temp_free(EA);
2794 } else {
2795 /* std / stdu*/
2796 if (Rc(ctx->opcode)) {
2797 if (unlikely(rA(ctx->opcode) == 0)) {
2798 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2799 return;
2800 }
2801 }
2802 gen_set_access_type(ctx, ACCESS_INT);
2803 EA = tcg_temp_new();
2804 gen_addr_imm_index(ctx, EA, 0x03);
2805 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2806 if (Rc(ctx->opcode))
2807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2808 tcg_temp_free(EA);
2809 }
2810 }
2811 #endif
2812 /*** Integer load and store with byte reverse ***/
2813
2814 /* lhbrx */
2815 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2816
2817 /* lwbrx */
2818 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2819
2820 #if defined(TARGET_PPC64)
2821 /* ldbrx */
2822 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2823 /* stdbrx */
2824 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2825 #endif /* TARGET_PPC64 */
2826
2827 /* sthbrx */
2828 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2829 /* stwbrx */
2830 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2831
2832 /*** Integer load and store multiple ***/
2833
2834 /* lmw */
2835 static void gen_lmw(DisasContext *ctx)
2836 {
2837 TCGv t0;
2838 TCGv_i32 t1;
2839
2840 if (ctx->le_mode) {
2841 gen_align_no_le(ctx);
2842 return;
2843 }
2844 gen_set_access_type(ctx, ACCESS_INT);
2845 t0 = tcg_temp_new();
2846 t1 = tcg_const_i32(rD(ctx->opcode));
2847 gen_addr_imm_index(ctx, t0, 0);
2848 gen_helper_lmw(cpu_env, t0, t1);
2849 tcg_temp_free(t0);
2850 tcg_temp_free_i32(t1);
2851 }
2852
2853 /* stmw */
2854 static void gen_stmw(DisasContext *ctx)
2855 {
2856 TCGv t0;
2857 TCGv_i32 t1;
2858
2859 if (ctx->le_mode) {
2860 gen_align_no_le(ctx);
2861 return;
2862 }
2863 gen_set_access_type(ctx, ACCESS_INT);
2864 t0 = tcg_temp_new();
2865 t1 = tcg_const_i32(rS(ctx->opcode));
2866 gen_addr_imm_index(ctx, t0, 0);
2867 gen_helper_stmw(cpu_env, t0, t1);
2868 tcg_temp_free(t0);
2869 tcg_temp_free_i32(t1);
2870 }
2871
2872 /*** Integer load and store strings ***/
2873
2874 /* lswi */
2875 /* PowerPC32 specification says we must generate an exception if
2876 * rA is in the range of registers to be loaded.
2877 * In an other hand, IBM says this is valid, but rA won't be loaded.
2878 * For now, I'll follow the spec...
2879 */
2880 static void gen_lswi(DisasContext *ctx)
2881 {
2882 TCGv t0;
2883 TCGv_i32 t1, t2;
2884 int nb = NB(ctx->opcode);
2885 int start = rD(ctx->opcode);
2886 int ra = rA(ctx->opcode);
2887 int nr;
2888
2889 if (ctx->le_mode) {
2890 gen_align_no_le(ctx);
2891 return;
2892 }
2893 if (nb == 0)
2894 nb = 32;
2895 nr = DIV_ROUND_UP(nb, 4);
2896 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2897 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2898 return;
2899 }
2900 gen_set_access_type(ctx, ACCESS_INT);
2901 t0 = tcg_temp_new();
2902 gen_addr_register(ctx, t0);
2903 t1 = tcg_const_i32(nb);
2904 t2 = tcg_const_i32(start);
2905 gen_helper_lsw(cpu_env, t0, t1, t2);
2906 tcg_temp_free(t0);
2907 tcg_temp_free_i32(t1);
2908 tcg_temp_free_i32(t2);
2909 }
2910
2911 /* lswx */
2912 static void gen_lswx(DisasContext *ctx)
2913 {
2914 TCGv t0;
2915 TCGv_i32 t1, t2, t3;
2916
2917 if (ctx->le_mode) {
2918 gen_align_no_le(ctx);
2919 return;
2920 }
2921 gen_set_access_type(ctx, ACCESS_INT);
2922 t0 = tcg_temp_new();
2923 gen_addr_reg_index(ctx, t0);
2924 t1 = tcg_const_i32(rD(ctx->opcode));
2925 t2 = tcg_const_i32(rA(ctx->opcode));
2926 t3 = tcg_const_i32(rB(ctx->opcode));
2927 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2928 tcg_temp_free(t0);
2929 tcg_temp_free_i32(t1);
2930 tcg_temp_free_i32(t2);
2931 tcg_temp_free_i32(t3);
2932 }
2933
2934 /* stswi */
2935 static void gen_stswi(DisasContext *ctx)
2936 {
2937 TCGv t0;
2938 TCGv_i32 t1, t2;
2939 int nb = NB(ctx->opcode);
2940
2941 if (ctx->le_mode) {
2942 gen_align_no_le(ctx);
2943 return;
2944 }
2945 gen_set_access_type(ctx, ACCESS_INT);
2946 t0 = tcg_temp_new();
2947 gen_addr_register(ctx, t0);
2948 if (nb == 0)
2949 nb = 32;
2950 t1 = tcg_const_i32(nb);
2951 t2 = tcg_const_i32(rS(ctx->opcode));
2952 gen_helper_stsw(cpu_env, t0, t1, t2);
2953 tcg_temp_free(t0);
2954 tcg_temp_free_i32(t1);
2955 tcg_temp_free_i32(t2);
2956 }
2957
2958 /* stswx */
2959 static void gen_stswx(DisasContext *ctx)
2960 {
2961 TCGv t0;
2962 TCGv_i32 t1, t2;
2963
2964 if (ctx->le_mode) {
2965 gen_align_no_le(ctx);
2966 return;
2967 }
2968 gen_set_access_type(ctx, ACCESS_INT);
2969 t0 = tcg_temp_new();
2970 gen_addr_reg_index(ctx, t0);
2971 t1 = tcg_temp_new_i32();
2972 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2973 tcg_gen_andi_i32(t1, t1, 0x7F);
2974 t2 = tcg_const_i32(rS(ctx->opcode));
2975 gen_helper_stsw(cpu_env, t0, t1, t2);
2976 tcg_temp_free(t0);
2977 tcg_temp_free_i32(t1);
2978 tcg_temp_free_i32(t2);
2979 }
2980
2981 /*** Memory synchronisation ***/
2982 /* eieio */
2983 static void gen_eieio(DisasContext *ctx)
2984 {
2985 tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
2986 }
2987
2988 #if !defined(CONFIG_USER_ONLY)
2989 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2990 {
2991 TCGv_i32 t;
2992 TCGLabel *l;
2993
2994 if (!ctx->lazy_tlb_flush) {
2995 return;
2996 }
2997 l = gen_new_label();
2998 t = tcg_temp_new_i32();
2999 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3000 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3001 if (global) {
3002 gen_helper_check_tlb_flush_global(cpu_env);
3003 } else {
3004 gen_helper_check_tlb_flush_local(cpu_env);
3005 }
3006 gen_set_label(l);
3007 tcg_temp_free_i32(t);
3008 }
3009 #else
3010 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3011 #endif
3012
3013 /* isync */
3014 static void gen_isync(DisasContext *ctx)
3015 {
3016 /*
3017 * We need to check for a pending TLB flush. This can only happen in
3018 * kernel mode however so check MSR_PR
3019 */
3020 if (!ctx->pr) {
3021 gen_check_tlb_flush(ctx, false);
3022 }
3023 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3024 gen_stop_exception(ctx);
3025 }
3026
3027 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3028
3029 #define LARX(name, memop) \
3030 static void gen_##name(DisasContext *ctx) \
3031 { \
3032 TCGv t0; \
3033 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3034 int len = MEMOP_GET_SIZE(memop); \
3035 gen_set_access_type(ctx, ACCESS_RES); \
3036 t0 = tcg_temp_local_new(); \
3037 gen_addr_reg_index(ctx, t0); \
3038 if ((len) > 1) { \
3039 gen_check_align(ctx, t0, (len)-1); \
3040 } \
3041 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3042 tcg_gen_mov_tl(cpu_reserve, t0); \
3043 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
3044 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
3045 tcg_temp_free(t0); \
3046 }
3047
3048 /* lwarx */
3049 LARX(lbarx, DEF_MEMOP(MO_UB))
3050 LARX(lharx, DEF_MEMOP(MO_UW))
3051 LARX(lwarx, DEF_MEMOP(MO_UL))
3052
3053 #define LD_ATOMIC(name, memop, tp, op, eop) \
3054 static void gen_##name(DisasContext *ctx) \
3055 { \
3056 int len = MEMOP_GET_SIZE(memop); \
3057 uint32_t gpr_FC = FC(ctx->opcode); \
3058 TCGv EA = tcg_temp_local_new(); \
3059 TCGv_##tp t0, t1; \
3060 \
3061 gen_addr_register(ctx, EA); \
3062 if (len > 1) { \
3063 gen_check_align(ctx, EA, len - 1); \
3064 } \
3065 t0 = tcg_temp_new_##tp(); \
3066 t1 = tcg_temp_new_##tp(); \
3067 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3068 \
3069 switch (gpr_FC) { \
3070 case 0: /* Fetch and add */ \
3071 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3072 break; \
3073 case 1: /* Fetch and xor */ \
3074 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3075 break; \
3076 case 2: /* Fetch and or */ \
3077 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3078 break; \
3079 case 3: /* Fetch and 'and' */ \
3080 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3081 break; \
3082 case 8: /* Swap */ \
3083 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3084 break; \
3085 case 4: /* Fetch and max unsigned */ \
3086 case 5: /* Fetch and max signed */ \
3087 case 6: /* Fetch and min unsigned */ \
3088 case 7: /* Fetch and min signed */ \
3089 case 16: /* compare and swap not equal */ \
3090 case 24: /* Fetch and increment bounded */ \
3091 case 25: /* Fetch and increment equal */ \
3092 case 28: /* Fetch and decrement bounded */ \
3093 gen_invalid(ctx); \
3094 break; \
3095 default: \
3096 /* invoke data storage error handler */ \
3097 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3098 } \
3099 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3100 tcg_temp_free_##tp(t0); \
3101 tcg_temp_free_##tp(t1); \
3102 tcg_temp_free(EA); \
3103 }
3104
3105 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3106 #if defined(TARGET_PPC64)
3107 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3108 #endif
3109
3110 #define ST_ATOMIC(name, memop, tp, op) \
3111 static void gen_##name(DisasContext *ctx) \
3112 { \
3113 int len = MEMOP_GET_SIZE(memop); \
3114 uint32_t gpr_FC = FC(ctx->opcode); \
3115 TCGv EA = tcg_temp_local_new(); \
3116 TCGv_##tp t0, t1; \
3117 \
3118 gen_addr_register(ctx, EA); \
3119 if (len > 1) { \
3120 gen_check_align(ctx, EA, len - 1); \
3121 } \
3122 t0 = tcg_temp_new_##tp(); \
3123 t1 = tcg_temp_new_##tp(); \
3124 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3125 \
3126 switch (gpr_FC) { \
3127 case 0: /* add and Store */ \
3128 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3129 break; \
3130 case 1: /* xor and Store */ \
3131 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3132 break; \
3133 case 2: /* Or and Store */ \
3134 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3135 break; \
3136 case 3: /* 'and' and Store */ \
3137 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3138 break; \
3139 case 4: /* Store max unsigned */ \
3140 case 5: /* Store max signed */ \
3141 case 6: /* Store min unsigned */ \
3142 case 7: /* Store min signed */ \
3143 case 24: /* Store twin */ \
3144 gen_invalid(ctx); \
3145 break; \
3146 default: \
3147 /* invoke data storage error handler */ \
3148 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3149 } \
3150 tcg_temp_free_##tp(t0); \
3151 tcg_temp_free_##tp(t1); \
3152 tcg_temp_free(EA); \
3153 }
3154
3155 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3156 #if defined(TARGET_PPC64)
3157 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3158 #endif
3159
3160 #if defined(CONFIG_USER_ONLY)
3161 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3162 int reg, int memop)
3163 {
3164 TCGv t0 = tcg_temp_new();
3165
3166 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3167 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3168 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3169 tcg_temp_free(t0);
3170 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3171 }
3172 #else
3173 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3174 int reg, int memop)
3175 {
3176 TCGLabel *l1 = gen_new_label();
3177 TCGLabel *l2 = gen_new_label();
3178 TCGv t0;
3179
3180 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3181
3182 t0 = tcg_temp_new();
3183 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3184 cpu_gpr[reg], ctx->mem_idx,
3185 DEF_MEMOP(memop) | MO_ALIGN);
3186 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3187 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3188 tcg_gen_or_tl(t0, t0, cpu_so);
3189 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3190 tcg_temp_free(t0);
3191 tcg_gen_br(l2);
3192
3193 gen_set_label(l1);
3194
3195 /* Address mismatch implies failure. But we still need to provide the
3196 memory barrier semantics of the instruction. */
3197 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3198 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3199
3200 gen_set_label(l2);
3201 tcg_gen_movi_tl(cpu_reserve, -1);
3202 }
3203 #endif
3204
3205 #define STCX(name, memop) \
3206 static void gen_##name(DisasContext *ctx) \
3207 { \
3208 TCGv t0; \
3209 int len = MEMOP_GET_SIZE(memop); \
3210 gen_set_access_type(ctx, ACCESS_RES); \
3211 t0 = tcg_temp_local_new(); \
3212 gen_addr_reg_index(ctx, t0); \
3213 if (len > 1) { \
3214 gen_check_align(ctx, t0, (len) - 1); \
3215 } \
3216 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3217 tcg_temp_free(t0); \
3218 }
3219
3220 STCX(stbcx_, DEF_MEMOP(MO_UB))
3221 STCX(sthcx_, DEF_MEMOP(MO_UW))
3222 STCX(stwcx_, DEF_MEMOP(MO_UL))
3223
3224 #if defined(TARGET_PPC64)
3225 /* ldarx */
3226 LARX(ldarx, DEF_MEMOP(MO_Q))
3227 /* stdcx. */
3228 STCX(stdcx_, DEF_MEMOP(MO_Q))
3229
3230 /* lqarx */
3231 static void gen_lqarx(DisasContext *ctx)
3232 {
3233 TCGv EA;
3234 int rd = rD(ctx->opcode);
3235 TCGv gpr1, gpr2;
3236
3237 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3238 (rd == rB(ctx->opcode)))) {
3239 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3240 return;
3241 }
3242
3243 gen_set_access_type(ctx, ACCESS_RES);
3244 EA = tcg_temp_local_new();
3245 gen_addr_reg_index(ctx, EA);
3246 gen_check_align(ctx, EA, 15);
3247 if (unlikely(ctx->le_mode)) {
3248 gpr1 = cpu_gpr[rd+1];
3249 gpr2 = cpu_gpr[rd];
3250 } else {
3251 gpr1 = cpu_gpr[rd];
3252 gpr2 = cpu_gpr[rd+1];
3253 }
3254 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3255 tcg_gen_mov_tl(cpu_reserve, EA);
3256 gen_addr_add(ctx, EA, EA, 8);
3257 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3258
3259 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3260 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3261 tcg_temp_free(EA);
3262 }
3263
3264 /* stqcx. */
3265 static void gen_stqcx_(DisasContext *ctx)
3266 {
3267 TCGv EA;
3268 int reg = rS(ctx->opcode);
3269 int len = 16;
3270 #if !defined(CONFIG_USER_ONLY)
3271 TCGLabel *l1;
3272 TCGv gpr1, gpr2;
3273 #endif
3274
3275 if (unlikely((rD(ctx->opcode) & 1))) {
3276 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3277 return;
3278 }
3279 gen_set_access_type(ctx, ACCESS_RES);
3280 EA = tcg_temp_local_new();
3281 gen_addr_reg_index(ctx, EA);
3282 if (len > 1) {
3283 gen_check_align(ctx, EA, (len) - 1);
3284 }
3285
3286 #if defined(CONFIG_USER_ONLY)
3287 gen_conditional_store(ctx, EA, reg, 16);
3288 #else
3289 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3290 l1 = gen_new_label();
3291 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3292 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3293
3294 if (unlikely(ctx->le_mode)) {
3295 gpr1 = cpu_gpr[reg + 1];
3296 gpr2 = cpu_gpr[reg];
3297 } else {
3298 gpr1 = cpu_gpr[reg];
3299 gpr2 = cpu_gpr[reg + 1];
3300 }
3301 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3302 gen_addr_add(ctx, EA, EA, 8);
3303 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3304
3305 gen_set_label(l1);
3306 tcg_gen_movi_tl(cpu_reserve, -1);
3307 #endif
3308 tcg_temp_free(EA);
3309 }
3310
3311 #endif /* defined(TARGET_PPC64) */
3312
3313 /* sync */
3314 static void gen_sync(DisasContext *ctx)
3315 {
3316 uint32_t l = (ctx->opcode >> 21) & 3;
3317
3318 /*
3319 * We may need to check for a pending TLB flush.
3320 *
3321 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3322 *
3323 * Additionally, this can only happen in kernel mode however so
3324 * check MSR_PR as well.
3325 */
3326 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3327 gen_check_tlb_flush(ctx, true);
3328 }
3329 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3330 }
3331
3332 /* wait */
3333 static void gen_wait(DisasContext *ctx)
3334 {
3335 TCGv_i32 t0 = tcg_const_i32(1);
3336 tcg_gen_st_i32(t0, cpu_env,
3337 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3338 tcg_temp_free_i32(t0);
3339 /* Stop translation, as the CPU is supposed to sleep from now */
3340 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3341 }
3342
3343 #if defined(TARGET_PPC64)
3344 static void gen_doze(DisasContext *ctx)
3345 {
3346 #if defined(CONFIG_USER_ONLY)
3347 GEN_PRIV;
3348 #else
3349 TCGv_i32 t;
3350
3351 CHK_HV;
3352 t = tcg_const_i32(PPC_PM_DOZE);
3353 gen_helper_pminsn(cpu_env, t);
3354 tcg_temp_free_i32(t);
3355 gen_stop_exception(ctx);
3356 #endif /* defined(CONFIG_USER_ONLY) */
3357 }
3358
3359 static void gen_nap(DisasContext *ctx)
3360 {
3361 #if defined(CONFIG_USER_ONLY)
3362 GEN_PRIV;
3363 #else
3364 TCGv_i32 t;
3365
3366 CHK_HV;
3367 t = tcg_const_i32(PPC_PM_NAP);
3368 gen_helper_pminsn(cpu_env, t);
3369 tcg_temp_free_i32(t);
3370 gen_stop_exception(ctx);
3371 #endif /* defined(CONFIG_USER_ONLY) */
3372 }
3373
3374 static void gen_stop(DisasContext *ctx)
3375 {
3376 gen_nap(ctx);
3377 }
3378
3379 static void gen_sleep(DisasContext *ctx)
3380 {
3381 #if defined(CONFIG_USER_ONLY)
3382 GEN_PRIV;
3383 #else
3384 TCGv_i32 t;
3385
3386 CHK_HV;
3387 t = tcg_const_i32(PPC_PM_SLEEP);
3388 gen_helper_pminsn(cpu_env, t);
3389 tcg_temp_free_i32(t);
3390 gen_stop_exception(ctx);
3391 #endif /* defined(CONFIG_USER_ONLY) */
3392 }
3393
3394 static void gen_rvwinkle(DisasContext *ctx)
3395 {
3396 #if defined(CONFIG_USER_ONLY)
3397 GEN_PRIV;
3398 #else
3399 TCGv_i32 t;
3400
3401 CHK_HV;
3402 t = tcg_const_i32(PPC_PM_RVWINKLE);
3403 gen_helper_pminsn(cpu_env, t);
3404 tcg_temp_free_i32(t);
3405 gen_stop_exception(ctx);
3406 #endif /* defined(CONFIG_USER_ONLY) */
3407 }
3408 #endif /* #if defined(TARGET_PPC64) */
3409
3410 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3411 {
3412 #if defined(TARGET_PPC64)
3413 if (ctx->has_cfar)
3414 tcg_gen_movi_tl(cpu_cfar, nip);
3415 #endif
3416 }
3417
3418 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3419 {
3420 if (unlikely(ctx->singlestep_enabled)) {
3421 return false;
3422 }
3423
3424 #ifndef CONFIG_USER_ONLY
3425 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3426 #else
3427 return true;
3428 #endif
3429 }
3430
3431 /*** Branch ***/
3432 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3433 {
3434 if (NARROW_MODE(ctx)) {
3435 dest = (uint32_t) dest;
3436 }
3437 if (use_goto_tb(ctx, dest)) {
3438 tcg_gen_goto_tb(n);
3439 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3440 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3441 } else {
3442 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3443 if (unlikely(ctx->singlestep_enabled)) {
3444 if ((ctx->singlestep_enabled &
3445 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3446 (ctx->exception == POWERPC_EXCP_BRANCH ||
3447 ctx->exception == POWERPC_EXCP_TRACE)) {
3448 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3449 }
3450 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3451 gen_debug_exception(ctx);
3452 }
3453 }
3454 tcg_gen_exit_tb(0);
3455 }
3456 }
3457
3458 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3459 {
3460 if (NARROW_MODE(ctx)) {
3461 nip = (uint32_t)nip;
3462 }
3463 tcg_gen_movi_tl(cpu_lr, nip);
3464 }
3465
3466 /* b ba bl bla */
3467 static void gen_b(DisasContext *ctx)
3468 {
3469 target_ulong li, target;
3470
3471 ctx->exception = POWERPC_EXCP_BRANCH;
3472 /* sign extend LI */
3473 li = LI(ctx->opcode);
3474 li = (li ^ 0x02000000) - 0x02000000;
3475 if (likely(AA(ctx->opcode) == 0)) {
3476 target = ctx->nip + li - 4;
3477 } else {
3478 target = li;
3479 }
3480 if (LK(ctx->opcode)) {
3481 gen_setlr(ctx, ctx->nip);
3482 }
3483 gen_update_cfar(ctx, ctx->nip - 4);
3484 gen_goto_tb(ctx, 0, target);
3485 }
3486
3487 #define BCOND_IM 0
3488 #define BCOND_LR 1
3489 #define BCOND_CTR 2
3490 #define BCOND_TAR 3
3491
3492 static inline void gen_bcond(DisasContext *ctx, int type)
3493 {
3494 uint32_t bo = BO(ctx->opcode);
3495 TCGLabel *l1;
3496 TCGv target;
3497
3498 ctx->exception = POWERPC_EXCP_BRANCH;
3499 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3500 target = tcg_temp_local_new();
3501 if (type == BCOND_CTR)
3502 tcg_gen_mov_tl(target, cpu_ctr);
3503 else if (type == BCOND_TAR)
3504 gen_load_spr(target, SPR_TAR);
3505 else
3506 tcg_gen_mov_tl(target, cpu_lr);
3507 } else {
3508 TCGV_UNUSED(target);
3509 }
3510 if (LK(ctx->opcode))
3511 gen_setlr(ctx, ctx->nip);
3512 l1 = gen_new_label();
3513 if ((bo & 0x4) == 0) {
3514 /* Decrement and test CTR */
3515 TCGv temp = tcg_temp_new();
3516 if (unlikely(type == BCOND_CTR)) {
3517 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3518 return;
3519 }
3520 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3521 if (NARROW_MODE(ctx)) {
3522 tcg_gen_ext32u_tl(temp, cpu_ctr);
3523 } else {
3524 tcg_gen_mov_tl(temp, cpu_ctr);
3525 }
3526 if (bo & 0x2) {
3527 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3528 } else {
3529 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3530 }
3531 tcg_temp_free(temp);
3532 }
3533 if ((bo & 0x10) == 0) {
3534 /* Test CR */
3535 uint32_t bi = BI(ctx->opcode);
3536 uint32_t mask = 0x08 >> (bi & 0x03);
3537 TCGv_i32 temp = tcg_temp_new_i32();
3538
3539 if (bo & 0x8) {
3540 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3541 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3542 } else {
3543 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3544 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3545 }
3546 tcg_temp_free_i32(temp);
3547 }
3548 gen_update_cfar(ctx, ctx->nip - 4);
3549 if (type == BCOND_IM) {
3550 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3551 if (likely(AA(ctx->opcode) == 0)) {
3552 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3553 } else {
3554 gen_goto_tb(ctx, 0, li);
3555 }
3556 if ((bo & 0x14) != 0x14) {
3557 gen_set_label(l1);
3558 gen_goto_tb(ctx, 1, ctx->nip);
3559 }
3560 } else {
3561 if (NARROW_MODE(ctx)) {
3562 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3563 } else {
3564 tcg_gen_andi_tl(cpu_nip, target, ~3);
3565 }
3566 tcg_gen_exit_tb(0);
3567 if ((bo & 0x14) != 0x14) {
3568 gen_set_label(l1);
3569 gen_update_nip(ctx, ctx->nip);
3570 tcg_gen_exit_tb(0);
3571 }
3572 }
3573 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3574 tcg_temp_free(target);
3575 }
3576 }
3577
3578 static void gen_bc(DisasContext *ctx)
3579 {
3580 gen_bcond(ctx, BCOND_IM);
3581 }
3582
3583 static void gen_bcctr(DisasContext *ctx)
3584 {
3585 gen_bcond(ctx, BCOND_CTR);
3586 }
3587
3588 static void gen_bclr(DisasContext *ctx)
3589 {
3590 gen_bcond(ctx, BCOND_LR);
3591 }
3592
3593 static void gen_bctar(DisasContext *ctx)
3594 {
3595 gen_bcond(ctx, BCOND_TAR);
3596 }
3597
3598 /*** Condition register logical ***/
3599 #define GEN_CRLOGIC(name, tcg_op, opc) \
3600 static void glue(gen_, name)(DisasContext *ctx) \
3601 { \
3602 uint8_t bitmask; \
3603 int sh; \
3604 TCGv_i32 t0, t1; \
3605 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3606 t0 = tcg_temp_new_i32(); \
3607 if (sh > 0) \
3608 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3609 else if (sh < 0) \
3610 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3611 else \
3612 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3613 t1 = tcg_temp_new_i32(); \
3614 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3615 if (sh > 0) \
3616 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3617 else if (sh < 0) \
3618 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3619 else \
3620 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3621 tcg_op(t0, t0, t1); \
3622 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3623 tcg_gen_andi_i32(t0, t0, bitmask); \
3624 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3625 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3626 tcg_temp_free_i32(t0); \
3627 tcg_temp_free_i32(t1); \
3628 }
3629
3630 /* crand */
3631 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3632 /* crandc */
3633 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3634 /* creqv */
3635 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3636 /* crnand */
3637 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3638 /* crnor */
3639 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3640 /* cror */
3641 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3642 /* crorc */
3643 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3644 /* crxor */
3645 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3646
3647 /* mcrf */
3648 static void gen_mcrf(DisasContext *ctx)
3649 {
3650 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3651 }
3652
3653 /*** System linkage ***/
3654
3655 /* rfi (supervisor only) */
3656 static void gen_rfi(DisasContext *ctx)
3657 {
3658 #if defined(CONFIG_USER_ONLY)
3659 GEN_PRIV;
3660 #else
3661 /* This instruction doesn't exist anymore on 64-bit server
3662 * processors compliant with arch 2.x
3663 */
3664 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3665 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3666 return;
3667 }
3668 /* Restore CPU state */
3669 CHK_SV;
3670 gen_update_cfar(ctx, ctx->nip - 4);
3671 gen_helper_rfi(cpu_env);
3672 gen_sync_exception(ctx);
3673 #endif
3674 }
3675
3676 #if defined(TARGET_PPC64)
3677 static void gen_rfid(DisasContext *ctx)
3678 {
3679 #if defined(CONFIG_USER_ONLY)
3680 GEN_PRIV;
3681 #else
3682 /* Restore CPU state */
3683 CHK_SV;
3684 gen_update_cfar(ctx, ctx->nip - 4);
3685 gen_helper_rfid(cpu_env);
3686 gen_sync_exception(ctx);
3687 #endif
3688 }
3689
3690 static void gen_hrfid(DisasContext *ctx)
3691 {
3692 #if defined(CONFIG_USER_ONLY)
3693 GEN_PRIV;
3694 #else
3695 /* Restore CPU state */
3696 CHK_HV;
3697 gen_helper_hrfid(cpu_env);
3698 gen_sync_exception(ctx);
3699 #endif
3700 }
3701 #endif
3702
3703 /* sc */
3704 #if defined(CONFIG_USER_ONLY)
3705 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3706 #else
3707 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3708 #endif
3709 static void gen_sc(DisasContext *ctx)
3710 {
3711 uint32_t lev;
3712
3713 lev = (ctx->opcode >> 5) & 0x7F;
3714 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3715 }
3716
3717 /*** Trap ***/
3718
3719 /* Check for unconditional traps (always or never) */
3720 static bool check_unconditional_trap(DisasContext *ctx)
3721 {
3722 /* Trap never */
3723 if (TO(ctx->opcode) == 0) {
3724 return true;
3725 }
3726 /* Trap always */
3727 if (TO(ctx->opcode) == 31) {
3728 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3729 return true;
3730 }
3731 return false;
3732 }
3733
3734 /* tw */
3735 static void gen_tw(DisasContext *ctx)
3736 {
3737 TCGv_i32 t0;
3738
3739 if (check_unconditional_trap(ctx)) {
3740 return;
3741 }
3742 t0 = tcg_const_i32(TO(ctx->opcode));
3743 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3744 t0);
3745 tcg_temp_free_i32(t0);
3746 }
3747
3748 /* twi */
3749 static void gen_twi(DisasContext *ctx)
3750 {
3751 TCGv t0;
3752 TCGv_i32 t1;
3753
3754 if (check_unconditional_trap(ctx)) {
3755 return;
3756 }
3757 t0 = tcg_const_tl(SIMM(ctx->opcode));
3758 t1 = tcg_const_i32(TO(ctx->opcode));
3759 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3760 tcg_temp_free(t0);
3761 tcg_temp_free_i32(t1);
3762 }
3763
3764 #if defined(TARGET_PPC64)
3765 /* td */
3766 static void gen_td(DisasContext *ctx)
3767 {
3768 TCGv_i32 t0;
3769
3770 if (check_unconditional_trap(ctx)) {
3771 return;
3772 }
3773 t0 = tcg_const_i32(TO(ctx->opcode));
3774 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3775 t0);
3776 tcg_temp_free_i32(t0);
3777 }
3778
3779 /* tdi */
3780 static void gen_tdi(DisasContext *ctx)
3781 {
3782 TCGv t0;
3783 TCGv_i32 t1;
3784
3785 if (check_unconditional_trap(ctx)) {
3786 return;
3787 }
3788 t0 = tcg_const_tl(SIMM(ctx->opcode));
3789 t1 = tcg_const_i32(TO(ctx->opcode));
3790 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3791 tcg_temp_free(t0);
3792 tcg_temp_free_i32(t1);
3793 }
3794 #endif
3795
3796 /*** Processor control ***/
3797
3798 static void gen_read_xer(DisasContext *ctx, TCGv dst)
3799 {
3800 TCGv t0 = tcg_temp_new();
3801 TCGv t1 = tcg_temp_new();
3802 TCGv t2 = tcg_temp_new();
3803 tcg_gen_mov_tl(dst, cpu_xer);
3804 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3805 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3806 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3807 tcg_gen_or_tl(t0, t0, t1);
3808 tcg_gen_or_tl(dst, dst, t2);
3809 tcg_gen_or_tl(dst, dst, t0);
3810 if (is_isa300(ctx)) {
3811 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3812 tcg_gen_or_tl(dst, dst, t0);
3813 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3814 tcg_gen_or_tl(dst, dst, t0);
3815 }
3816 tcg_temp_free(t0);
3817 tcg_temp_free(t1);
3818 tcg_temp_free(t2);
3819 }
3820
3821 static void gen_write_xer(TCGv src)
3822 {
3823 /* Write all flags, while reading back check for isa300 */
3824 tcg_gen_andi_tl(cpu_xer, src,
3825 ~((1u << XER_SO) |
3826 (1u << XER_OV) | (1u << XER_OV32) |
3827 (1u << XER_CA) | (1u << XER_CA32)));
3828 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3829 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
3830 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3831 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3832 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3833 }
3834
3835 /* mcrxr */
3836 static void gen_mcrxr(DisasContext *ctx)
3837 {
3838 TCGv_i32 t0 = tcg_temp_new_i32();
3839 TCGv_i32 t1 = tcg_temp_new_i32();
3840 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3841
3842 tcg_gen_trunc_tl_i32(t0, cpu_so);
3843 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3844 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3845 tcg_gen_shli_i32(t0, t0, 3);
3846 tcg_gen_shli_i32(t1, t1, 2);
3847 tcg_gen_shli_i32(dst, dst, 1);
3848 tcg_gen_or_i32(dst, dst, t0);
3849 tcg_gen_or_i32(dst, dst, t1);
3850 tcg_temp_free_i32(t0);
3851 tcg_temp_free_i32(t1);
3852
3853 tcg_gen_movi_tl(cpu_so, 0);
3854 tcg_gen_movi_tl(cpu_ov, 0);
3855 tcg_gen_movi_tl(cpu_ca, 0);
3856 }
3857
3858 #ifdef TARGET_PPC64
3859 /* mcrxrx */
3860 static void gen_mcrxrx(DisasContext *ctx)
3861 {
3862 TCGv t0 = tcg_temp_new();
3863 TCGv t1 = tcg_temp_new();
3864 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3865
3866 /* copy OV and OV32 */
3867 tcg_gen_shli_tl(t0, cpu_ov, 1);
3868 tcg_gen_or_tl(t0, t0, cpu_ov32);
3869 tcg_gen_shli_tl(t0, t0, 2);
3870 /* copy CA and CA32 */
3871 tcg_gen_shli_tl(t1, cpu_ca, 1);
3872 tcg_gen_or_tl(t1, t1, cpu_ca32);
3873 tcg_gen_or_tl(t0, t0, t1);
3874 tcg_gen_trunc_tl_i32(dst, t0);
3875 tcg_temp_free(t0);
3876 tcg_temp_free(t1);
3877 }
3878 #endif
3879
3880 /* mfcr mfocrf */
3881 static void gen_mfcr(DisasContext *ctx)
3882 {
3883 uint32_t crm, crn;
3884
3885 if (likely(ctx->opcode & 0x00100000)) {
3886 crm = CRM(ctx->opcode);
3887 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3888 crn = ctz32 (crm);
3889 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3890 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3891 cpu_gpr[rD(ctx->opcode)], crn * 4);
3892 }
3893 } else {
3894 TCGv_i32 t0 = tcg_temp_new_i32();
3895 tcg_gen_mov_i32(t0, cpu_crf[0]);
3896 tcg_gen_shli_i32(t0, t0, 4);
3897 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3898 tcg_gen_shli_i32(t0, t0, 4);
3899 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3900 tcg_gen_shli_i32(t0, t0, 4);
3901 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3902 tcg_gen_shli_i32(t0, t0, 4);
3903 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3904 tcg_gen_shli_i32(t0, t0, 4);
3905 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3906 tcg_gen_shli_i32(t0, t0, 4);
3907 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3908 tcg_gen_shli_i32(t0, t0, 4);
3909 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3910 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3911 tcg_temp_free_i32(t0);
3912 }
3913 }
3914
3915 /* mfmsr */
3916 static void gen_mfmsr(DisasContext *ctx)
3917 {
3918 CHK_SV;
3919 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3920 }
3921
3922 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3923 {
3924 #if 0
3925 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3926 printf("ERROR: try to access SPR %d !\n", sprn);
3927 #endif
3928 }
3929 #define SPR_NOACCESS (&spr_noaccess)
3930
3931 /* mfspr */
3932 static inline void gen_op_mfspr(DisasContext *ctx)
3933 {
3934 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3935 uint32_t sprn = SPR(ctx->opcode);
3936
3937 #if defined(CONFIG_USER_ONLY)
3938 read_cb = ctx->spr_cb[sprn].uea_read;
3939 #else
3940 if (ctx->pr) {
3941 read_cb = ctx->spr_cb[sprn].uea_read;
3942 } else if (ctx->hv) {
3943 read_cb = ctx->spr_cb[sprn].hea_read;
3944 } else {
3945 read_cb = ctx->spr_cb[sprn].oea_read;
3946 }
3947 #endif
3948 if (likely(read_cb != NULL)) {
3949 if (likely(read_cb != SPR_NOACCESS)) {
3950 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3951 } else {
3952 /* Privilege exception */
3953 /* This is a hack to avoid warnings when running Linux:
3954 * this OS breaks the PowerPC virtualisation model,
3955 * allowing userland application to read the PVR
3956 */
3957 if (sprn != SPR_PVR) {
3958 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3959 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3960 if (qemu_log_separate()) {
3961 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3962 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3963 }
3964 }
3965 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3966 }
3967 } else {
3968 /* ISA 2.07 defines these as no-ops */
3969 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3970 (sprn >= 808 && sprn <= 811)) {
3971 /* This is a nop */
3972 return;
3973 }
3974 /* Not defined */
3975 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3976 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3977 if (qemu_log_separate()) {
3978 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3979 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3980 }
3981
3982 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3983 * it can generate a priv, a hv emu or a no-op
3984 */
3985 if (sprn & 0x10) {
3986 if (ctx->pr) {
3987 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3988 }
3989 } else {
3990 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3991 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3992 }
3993 }
3994 }
3995 }
3996
3997 static void gen_mfspr(DisasContext *ctx)
3998 {
3999 gen_op_mfspr(ctx);
4000 }
4001
4002 /* mftb */
4003 static void gen_mftb(DisasContext *ctx)
4004 {
4005 gen_op_mfspr(ctx);
4006 }
4007
4008 /* mtcrf mtocrf*/
4009 static void gen_mtcrf(DisasContext *ctx)
4010 {
4011 uint32_t crm, crn;
4012
4013 crm = CRM(ctx->opcode);
4014 if (likely((ctx->opcode & 0x00100000))) {
4015 if (crm && ((crm & (crm - 1)) == 0)) {
4016 TCGv_i32 temp = tcg_temp_new_i32();
4017 crn = ctz32 (crm);
4018 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4019 tcg_gen_shri_i32(temp, temp, crn * 4);
4020 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4021 tcg_temp_free_i32(temp);
4022 }
4023 } else {
4024 TCGv_i32 temp = tcg_temp_new_i32();
4025 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4026 for (crn = 0 ; crn < 8 ; crn++) {
4027 if (crm & (1 << crn)) {
4028 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4029 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4030 }
4031 }
4032 tcg_temp_free_i32(temp);
4033 }
4034 }
4035
4036 /* mtmsr */
4037 #if defined(TARGET_PPC64)
4038 static void gen_mtmsrd(DisasContext *ctx)
4039 {
4040 CHK_SV;
4041
4042 #if !defined(CONFIG_USER_ONLY)
4043 if (ctx->opcode & 0x00010000) {
4044 /* Special form that does not need any synchronisation */
4045 TCGv t0 = tcg_temp_new();
4046 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4047 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4048 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4049 tcg_temp_free(t0);
4050 } else {
4051 /* XXX: we need to update nip before the store
4052 * if we enter power saving mode, we will exit the loop
4053 * directly from ppc_store_msr
4054 */
4055 gen_update_nip(ctx, ctx->nip);
4056 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4057 /* Must stop the translation as machine state (may have) changed */
4058 /* Note that mtmsr is not always defined as context-synchronizing */
4059 gen_stop_exception(ctx);
4060 }
4061 #endif /* !defined(CONFIG_USER_ONLY) */
4062 }
4063 #endif /* defined(TARGET_PPC64) */
4064
4065 static void gen_mtmsr(DisasContext *ctx)
4066 {
4067 CHK_SV;
4068
4069 #if !defined(CONFIG_USER_ONLY)
4070 if (ctx->opcode & 0x00010000) {
4071 /* Special form that does not need any synchronisation */
4072 TCGv t0 = tcg_temp_new();
4073 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4074 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4075 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4076 tcg_temp_free(t0);
4077 } else {
4078 TCGv msr = tcg_temp_new();
4079
4080 /* XXX: we need to update nip before the store
4081 * if we enter power saving mode, we will exit the loop
4082 * directly from ppc_store_msr
4083 */
4084 gen_update_nip(ctx, ctx->nip);
4085 #if defined(TARGET_PPC64)
4086 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4087 #else
4088 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4089 #endif
4090 gen_helper_store_msr(cpu_env, msr);
4091 tcg_temp_free(msr);
4092 /* Must stop the translation as machine state (may have) changed */
4093 /* Note that mtmsr is not always defined as context-synchronizing */
4094 gen_stop_exception(ctx);
4095 }
4096 #endif
4097 }
4098
4099 /* mtspr */
4100 static void gen_mtspr(DisasContext *ctx)
4101 {
4102 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4103 uint32_t sprn = SPR(ctx->opcode);
4104
4105 #if defined(CONFIG_USER_ONLY)
4106 write_cb = ctx->spr_cb[sprn].uea_write;
4107 #else
4108 if (ctx->pr) {
4109 write_cb = ctx->spr_cb[sprn].uea_write;
4110 } else if (ctx->hv) {
4111 write_cb = ctx->spr_cb[sprn].hea_write;
4112 } else {
4113 write_cb = ctx->spr_cb[sprn].oea_write;
4114 }
4115 #endif
4116 if (likely(write_cb != NULL)) {
4117 if (likely(write_cb != SPR_NOACCESS)) {
4118 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4119 } else {
4120 /* Privilege exception */
4121 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4122 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4123 if (qemu_log_separate()) {
4124 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4125 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4126 }
4127 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4128 }
4129 } else {
4130 /* ISA 2.07 defines these as no-ops */
4131 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4132 (sprn >= 808 && sprn <= 811)) {
4133 /* This is a nop */
4134 return;
4135 }
4136
4137 /* Not defined */
4138 if (qemu_log_separate()) {
4139 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4140 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4141 }
4142 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4143 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4144
4145
4146 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4147 * it can generate a priv, a hv emu or a no-op
4148 */
4149 if (sprn & 0x10) {
4150 if (ctx->pr) {
4151 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4152 }
4153 } else {
4154 if (ctx->pr || sprn == 0) {
4155 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4156 }
4157 }
4158 }
4159 }
4160
4161 #if defined(TARGET_PPC64)
4162 /* setb */
4163 static void gen_setb(DisasContext *ctx)
4164 {
4165 TCGv_i32 t0 = tcg_temp_new_i32();
4166 TCGv_i32 t8 = tcg_temp_new_i32();
4167 TCGv_i32 tm1 = tcg_temp_new_i32();
4168 int crf = crfS(ctx->opcode);
4169
4170 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4171 tcg_gen_movi_i32(t8, 8);
4172 tcg_gen_movi_i32(tm1, -1);
4173 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4174 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4175
4176 tcg_temp_free_i32(t0);
4177 tcg_temp_free_i32(t8);
4178 tcg_temp_free_i32(tm1);
4179 }
4180 #endif
4181
4182 /*** Cache management ***/
4183
4184 /* dcbf */
4185 static void gen_dcbf(DisasContext *ctx)
4186 {
4187 /* XXX: specification says this is treated as a load by the MMU */
4188 TCGv t0;
4189 gen_set_access_type(ctx, ACCESS_CACHE);
4190 t0 = tcg_temp_new();
4191 gen_addr_reg_index(ctx, t0);
4192 gen_qemu_ld8u(ctx, t0, t0);
4193 tcg_temp_free(t0);
4194 }
4195
4196 /* dcbi (Supervisor only) */
4197 static void gen_dcbi(DisasContext *ctx)
4198 {
4199 #if defined(CONFIG_USER_ONLY)
4200 GEN_PRIV;
4201 #else
4202 TCGv EA, val;
4203
4204 CHK_SV;
4205 EA = tcg_temp_new();
4206 gen_set_access_type(ctx, ACCESS_CACHE);
4207 gen_addr_reg_index(ctx, EA);
4208 val = tcg_temp_new();
4209 /* XXX: specification says this should be treated as a store by the MMU */
4210 gen_qemu_ld8u(ctx, val, EA);
4211 gen_qemu_st8(ctx, val, EA);
4212 tcg_temp_free(val);
4213 tcg_temp_free(EA);
4214 #endif /* defined(CONFIG_USER_ONLY) */
4215 }
4216
4217 /* dcdst */
4218 static void gen_dcbst(DisasContext *ctx)
4219 {
4220 /* XXX: specification say this is treated as a load by the MMU */
4221 TCGv t0;
4222 gen_set_access_type(ctx, ACCESS_CACHE);
4223 t0 = tcg_temp_new();
4224 gen_addr_reg_index(ctx, t0);
4225 gen_qemu_ld8u(ctx, t0, t0);
4226 tcg_temp_free(t0);
4227 }
4228
4229 /* dcbt */
4230 static void gen_dcbt(DisasContext *ctx)
4231 {
4232 /* interpreted as no-op */
4233 /* XXX: specification say this is treated as a load by the MMU
4234 * but does not generate any exception
4235 */
4236 }
4237
4238 /* dcbtst */
4239 static void gen_dcbtst(DisasContext *ctx)
4240 {
4241 /* interpreted as no-op */
4242 /* XXX: specification say this is treated as a load by the MMU
4243 * but does not generate any exception
4244 */
4245 }
4246
4247 /* dcbtls */
4248 static void gen_dcbtls(DisasContext *ctx)
4249 {
4250 /* Always fails locking the cache */
4251 TCGv t0 = tcg_temp_new();
4252 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4253 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4254 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4255 tcg_temp_free(t0);
4256 }
4257
4258 /* dcbz */
4259 static void gen_dcbz(DisasContext *ctx)
4260 {
4261 TCGv tcgv_addr;
4262 TCGv_i32 tcgv_op;
4263
4264 gen_set_access_type(ctx, ACCESS_CACHE);
4265 tcgv_addr = tcg_temp_new();
4266 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4267 gen_addr_reg_index(ctx, tcgv_addr);
4268 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4269 tcg_temp_free(tcgv_addr);
4270 tcg_temp_free_i32(tcgv_op);
4271 }
4272
4273 /* dst / dstt */
4274 static void gen_dst(DisasContext *ctx)
4275 {
4276 if (rA(ctx->opcode) == 0) {
4277 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4278 } else {
4279 /* interpreted as no-op */
4280 }
4281 }
4282
4283 /* dstst /dststt */
4284 static void gen_dstst(DisasContext *ctx)
4285 {
4286 if (rA(ctx->opcode) == 0) {
4287 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4288 } else {
4289 /* interpreted as no-op */
4290 }
4291
4292 }
4293
4294 /* dss / dssall */
4295 static void gen_dss(DisasContext *ctx)
4296 {
4297 /* interpreted as no-op */
4298 }
4299
4300 /* icbi */
4301 static void gen_icbi(DisasContext *ctx)
4302 {
4303 TCGv t0;
4304 gen_set_access_type(ctx, ACCESS_CACHE);
4305 t0 = tcg_temp_new();
4306 gen_addr_reg_index(ctx, t0);
4307 gen_helper_icbi(cpu_env, t0);
4308 tcg_temp_free(t0);
4309 }
4310
4311 /* Optional: */
4312 /* dcba */
4313 static void gen_dcba(DisasContext *ctx)
4314 {
4315 /* interpreted as no-op */
4316 /* XXX: specification say this is treated as a store by the MMU
4317 * but does not generate any exception
4318 */
4319 }
4320
4321 /*** Segment register manipulation ***/
4322 /* Supervisor only: */
4323
4324 /* mfsr */
4325 static void gen_mfsr(DisasContext *ctx)
4326 {
4327 #if defined(CONFIG_USER_ONLY)
4328 GEN_PRIV;
4329 #else
4330 TCGv t0;
4331
4332 CHK_SV;
4333 t0 = tcg_const_tl(SR(ctx->opcode));
4334 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4335 tcg_temp_free(t0);
4336 #endif /* defined(CONFIG_USER_ONLY) */
4337 }
4338
4339 /* mfsrin */
4340 static void gen_mfsrin(DisasContext *ctx)
4341 {
4342 #if defined(CONFIG_USER_ONLY)
4343 GEN_PRIV;
4344 #else
4345 TCGv t0;
4346
4347 CHK_SV;
4348 t0 = tcg_temp_new();
4349 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4350 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4351 tcg_temp_free(t0);
4352 #endif /* defined(CONFIG_USER_ONLY) */
4353 }
4354
4355 /* mtsr */
4356 static void gen_mtsr(DisasContext *ctx)
4357 {
4358 #if defined(CONFIG_USER_ONLY)
4359 GEN_PRIV;
4360 #else
4361 TCGv t0;
4362
4363 CHK_SV;
4364 t0 = tcg_const_tl(SR(ctx->opcode));
4365 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4366 tcg_temp_free(t0);
4367 #endif /* defined(CONFIG_USER_ONLY) */
4368 }
4369
4370 /* mtsrin */
4371 static void gen_mtsrin(DisasContext *ctx)
4372 {
4373 #if defined(CONFIG_USER_ONLY)
4374 GEN_PRIV;
4375 #else
4376 TCGv t0;
4377 CHK_SV;
4378
4379 t0 = tcg_temp_new();
4380 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4381 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4382 tcg_temp_free(t0);
4383 #endif /* defined(CONFIG_USER_ONLY) */
4384 }
4385
4386 #if defined(TARGET_PPC64)
4387 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4388
4389 /* mfsr */
4390 static void gen_mfsr_64b(DisasContext *ctx)
4391 {
4392 #if defined(CONFIG_USER_ONLY)
4393 GEN_PRIV;
4394 #else
4395 TCGv t0;
4396
4397 CHK_SV;
4398 t0 = tcg_const_tl(SR(ctx->opcode));
4399 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4400 tcg_temp_free(t0);
4401 #endif /* defined(CONFIG_USER_ONLY) */
4402 }
4403
4404 /* mfsrin */
4405 static void gen_mfsrin_64b(DisasContext *ctx)
4406 {
4407 #if defined(CONFIG_USER_ONLY)
4408 GEN_PRIV;
4409 #else
4410 TCGv t0;
4411
4412 CHK_SV;
4413 t0 = tcg_temp_new();
4414 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4415 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4416 tcg_temp_free(t0);
4417 #endif /* defined(CONFIG_USER_ONLY) */
4418 }
4419
4420 /* mtsr */
4421 static void gen_mtsr_64b(DisasContext *ctx)
4422 {
4423 #if defined(CONFIG_USER_ONLY)
4424 GEN_PRIV;
4425 #else
4426 TCGv t0;
4427
4428 CHK_SV;
4429 t0 = tcg_const_tl(SR(ctx->opcode));
4430 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4431 tcg_temp_free(t0);
4432 #endif /* defined(CONFIG_USER_ONLY) */
4433 }
4434
4435 /* mtsrin */
4436 static void gen_mtsrin_64b(DisasContext *ctx)
4437 {
4438 #if defined(CONFIG_USER_ONLY)
4439 GEN_PRIV;
4440 #else
4441 TCGv t0;
4442
4443 CHK_SV;
4444 t0 = tcg_temp_new();
4445 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4446 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4447 tcg_temp_free(t0);
4448 #endif /* defined(CONFIG_USER_ONLY) */
4449 }
4450
4451 /* slbmte */
4452 static void gen_slbmte(DisasContext *ctx)
4453 {
4454 #if defined(CONFIG_USER_ONLY)
4455 GEN_PRIV;
4456 #else
4457 CHK_SV;
4458
4459 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4460 cpu_gpr[rS(ctx->opcode)]);
4461 #endif /* defined(CONFIG_USER_ONLY) */
4462 }
4463
4464 static void gen_slbmfee(DisasContext *ctx)
4465 {
4466 #if defined(CONFIG_USER_ONLY)
4467 GEN_PRIV;
4468 #else
4469 CHK_SV;
4470
4471 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4472 cpu_gpr[rB(ctx->opcode)]);
4473 #endif /* defined(CONFIG_USER_ONLY) */
4474 }
4475
4476 static void gen_slbmfev(DisasContext *ctx)
4477 {
4478 #if defined(CONFIG_USER_ONLY)
4479 GEN_PRIV;
4480 #else
4481 CHK_SV;
4482
4483 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4484 cpu_gpr[rB(ctx->opcode)]);
4485 #endif /* defined(CONFIG_USER_ONLY) */
4486 }
4487
4488 static void gen_slbfee_(DisasContext *ctx)
4489 {
4490 #if defined(CONFIG_USER_ONLY)
4491 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4492 #else
4493 TCGLabel *l1, *l2;
4494
4495 if (unlikely(ctx->pr)) {
4496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4497 return;
4498 }
4499 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4500 cpu_gpr[rB(ctx->opcode)]);
4501 l1 = gen_new_label();
4502 l2 = gen_new_label();
4503 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4504 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4505 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4506 tcg_gen_br(l2);
4507 gen_set_label(l1);
4508 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4509 gen_set_label(l2);
4510 #endif
4511 }
4512 #endif /* defined(TARGET_PPC64) */
4513
4514 /*** Lookaside buffer management ***/
4515 /* Optional & supervisor only: */
4516
4517 /* tlbia */
4518 static void gen_tlbia(DisasContext *ctx)
4519 {
4520 #if defined(CONFIG_USER_ONLY)
4521 GEN_PRIV;
4522 #else
4523 CHK_HV;
4524
4525 gen_helper_tlbia(cpu_env);
4526 #endif /* defined(CONFIG_USER_ONLY) */
4527 }
4528
4529 /* tlbiel */
4530 static void gen_tlbiel(DisasContext *ctx)
4531 {
4532 #if defined(CONFIG_USER_ONLY)
4533 GEN_PRIV;
4534 #else
4535 CHK_SV;
4536
4537 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4538 #endif /* defined(CONFIG_USER_ONLY) */
4539 }
4540
4541 /* tlbie */
4542 static void gen_tlbie(DisasContext *ctx)
4543 {
4544 #if defined(CONFIG_USER_ONLY)
4545 GEN_PRIV;
4546 #else
4547 TCGv_i32 t1;
4548
4549 if (ctx->gtse) {
4550 CHK_SV; /* If gtse is set then tblie is supervisor privileged */
4551 } else {
4552 CHK_HV; /* Else hypervisor privileged */
4553 }
4554
4555 if (NARROW_MODE(ctx)) {
4556 TCGv t0 = tcg_temp_new();
4557 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4558 gen_helper_tlbie(cpu_env, t0);
4559 tcg_temp_free(t0);
4560 } else {
4561 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4562 }
4563 t1 = tcg_temp_new_i32();
4564 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4565 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4566 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4567 tcg_temp_free_i32(t1);
4568 #endif /* defined(CONFIG_USER_ONLY) */
4569 }
4570
4571 /* tlbsync */
4572 static void gen_tlbsync(DisasContext *ctx)
4573 {
4574 #if defined(CONFIG_USER_ONLY)
4575 GEN_PRIV;
4576 #else
4577 CHK_HV;
4578
4579 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4580 if (ctx->insns_flags & PPC_BOOKE) {
4581 gen_check_tlb_flush(ctx, true);
4582 }
4583 #endif /* defined(CONFIG_USER_ONLY) */
4584 }
4585
4586 #if defined(TARGET_PPC64)
4587 /* slbia */
4588 static void gen_slbia(DisasContext *ctx)
4589 {
4590 #if defined(CONFIG_USER_ONLY)
4591 GEN_PRIV;
4592 #else
4593 CHK_SV;
4594
4595 gen_helper_slbia(cpu_env);
4596 #endif /* defined(CONFIG_USER_ONLY) */
4597 }
4598
4599 /* slbie */
4600 static void gen_slbie(DisasContext *ctx)
4601 {
4602 #if defined(CONFIG_USER_ONLY)
4603 GEN_PRIV;
4604 #else
4605 CHK_SV;
4606
4607 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4608 #endif /* defined(CONFIG_USER_ONLY) */
4609 }
4610
4611 /* slbieg */
4612 static void gen_slbieg(DisasContext *ctx)
4613 {
4614 #if defined(CONFIG_USER_ONLY)
4615 GEN_PRIV;
4616 #else
4617 CHK_SV;
4618
4619 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4620 #endif /* defined(CONFIG_USER_ONLY) */
4621 }
4622
4623 /* slbsync */
4624 static void gen_slbsync(DisasContext *ctx)
4625 {
4626 #if defined(CONFIG_USER_ONLY)
4627 GEN_PRIV;
4628 #else
4629 CHK_SV;
4630 gen_check_tlb_flush(ctx, true);
4631 #endif /* defined(CONFIG_USER_ONLY) */
4632 }
4633
4634 #endif /* defined(TARGET_PPC64) */
4635
4636 /*** External control ***/
4637 /* Optional: */
4638
4639 /* eciwx */
4640 static void gen_eciwx(DisasContext *ctx)
4641 {
4642 TCGv t0;
4643 /* Should check EAR[E] ! */
4644 gen_set_access_type(ctx, ACCESS_EXT);
4645 t0 = tcg_temp_new();
4646 gen_addr_reg_index(ctx, t0);
4647 gen_check_align(ctx, t0, 0x03);
4648 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4649 tcg_temp_free(t0);
4650 }
4651
4652 /* ecowx */
4653 static void gen_ecowx(DisasContext *ctx)
4654 {
4655 TCGv t0;
4656 /* Should check EAR[E] ! */
4657 gen_set_access_type(ctx, ACCESS_EXT);
4658 t0 = tcg_temp_new();
4659 gen_addr_reg_index(ctx, t0);
4660 gen_check_align(ctx, t0, 0x03);
4661 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4662 tcg_temp_free(t0);
4663 }
4664
4665 /* PowerPC 601 specific instructions */
4666
4667 /* abs - abs. */
4668 static void gen_abs(DisasContext *ctx)
4669 {
4670 TCGLabel *l1 = gen_new_label();
4671 TCGLabel *l2 = gen_new_label();
4672 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4673 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4674 tcg_gen_br(l2);
4675 gen_set_label(l1);
4676 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4677 gen_set_label(l2);
4678 if (unlikely(Rc(ctx->opcode) != 0))
4679 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4680 }
4681
4682 /* abso - abso. */
4683 static void gen_abso(DisasContext *ctx)
4684 {
4685 TCGLabel *l1 = gen_new_label();
4686 TCGLabel *l2 = gen_new_label();
4687 TCGLabel *l3 = gen_new_label();
4688 /* Start with XER OV disabled, the most likely case */
4689 tcg_gen_movi_tl(cpu_ov, 0);
4690 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4691 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4692 tcg_gen_movi_tl(cpu_ov, 1);
4693 tcg_gen_movi_tl(cpu_so, 1);
4694 tcg_gen_br(l2);
4695 gen_set_label(l1);
4696 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4697 tcg_gen_br(l3);
4698 gen_set_label(l2);
4699 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4700 gen_set_label(l3);
4701 if (unlikely(Rc(ctx->opcode) != 0))
4702 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4703 }
4704
4705 /* clcs */
4706 static void gen_clcs(DisasContext *ctx)
4707 {
4708 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4709 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4710 tcg_temp_free_i32(t0);
4711 /* Rc=1 sets CR0 to an undefined state */
4712 }
4713
4714 /* div - div. */
4715 static void gen_div(DisasContext *ctx)
4716 {
4717 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4718 cpu_gpr[rB(ctx->opcode)]);
4719 if (unlikely(Rc(ctx->opcode) != 0))
4720 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4721 }
4722
4723 /* divo - divo. */
4724 static void gen_divo(DisasContext *ctx)
4725 {
4726 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4727 cpu_gpr[rB(ctx->opcode)]);
4728 if (unlikely(Rc(ctx->opcode) != 0))
4729 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4730 }
4731
4732 /* divs - divs. */
4733 static void gen_divs(DisasContext *ctx)
4734 {
4735 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4736 cpu_gpr[rB(ctx->opcode)]);
4737 if (unlikely(Rc(ctx->opcode) != 0))
4738 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4739 }
4740
4741 /* divso - divso. */
4742 static void gen_divso(DisasContext *ctx)
4743 {
4744 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4745 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4746 if (unlikely(Rc(ctx->opcode) != 0))
4747 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4748 }
4749
4750 /* doz - doz. */
4751 static void gen_doz(DisasContext *ctx)
4752 {
4753 TCGLabel *l1 = gen_new_label();
4754 TCGLabel *l2 = gen_new_label();
4755 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4756 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4757 tcg_gen_br(l2);
4758 gen_set_label(l1);
4759 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4760 gen_set_label(l2);
4761 if (unlikely(Rc(ctx->opcode) != 0))
4762 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4763 }
4764
4765 /* dozo - dozo. */
4766 static void gen_dozo(DisasContext *ctx)
4767 {
4768 TCGLabel *l1 = gen_new_label();
4769 TCGLabel *l2 = gen_new_label();
4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 TCGv t2 = tcg_temp_new();
4773 /* Start with XER OV disabled, the most likely case */
4774 tcg_gen_movi_tl(cpu_ov, 0);
4775 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4776 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4777 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4778 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4779 tcg_gen_andc_tl(t1, t1, t2);
4780 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4781 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4782 tcg_gen_movi_tl(cpu_ov, 1);
4783 tcg_gen_movi_tl(cpu_so, 1);
4784 tcg_gen_br(l2);
4785 gen_set_label(l1);
4786 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4787 gen_set_label(l2);
4788 tcg_temp_free(t0);
4789 tcg_temp_free(t1);
4790 tcg_temp_free(t2);
4791 if (unlikely(Rc(ctx->opcode) != 0))
4792 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4793 }
4794
4795 /* dozi */
4796 static void gen_dozi(DisasContext *ctx)
4797 {
4798 target_long simm = SIMM(ctx->opcode);
4799 TCGLabel *l1 = gen_new_label();
4800 TCGLabel *l2 = gen_new_label();
4801 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4802 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4803 tcg_gen_br(l2);
4804 gen_set_label(l1);
4805 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4806 gen_set_label(l2);
4807 if (unlikely(Rc(ctx->opcode) != 0))
4808 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4809 }
4810
4811 /* lscbx - lscbx. */
4812 static void gen_lscbx(DisasContext *ctx)
4813 {
4814 TCGv t0 = tcg_temp_new();
4815 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4816 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4817 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4818
4819 gen_addr_reg_index(ctx, t0);
4820 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4821 tcg_temp_free_i32(t1);
4822 tcg_temp_free_i32(t2);
4823 tcg_temp_free_i32(t3);
4824 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4825 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4826 if (unlikely(Rc(ctx->opcode) != 0))
4827 gen_set_Rc0(ctx, t0);
4828 tcg_temp_free(t0);
4829 }
4830
4831 /* maskg - maskg. */
4832 static void gen_maskg(DisasContext *ctx)
4833 {
4834 TCGLabel *l1 = gen_new_label();
4835 TCGv t0 = tcg_temp_new();
4836 TCGv t1 = tcg_temp_new();
4837 TCGv t2 = tcg_temp_new();
4838 TCGv t3 = tcg_temp_new();
4839 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4840 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4841 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4842 tcg_gen_addi_tl(t2, t0, 1);
4843 tcg_gen_shr_tl(t2, t3, t2);
4844 tcg_gen_shr_tl(t3, t3, t1);
4845 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4846 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4847 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4848 gen_set_label(l1);
4849 tcg_temp_free(t0);
4850 tcg_temp_free(t1);
4851 tcg_temp_free(t2);
4852 tcg_temp_free(t3);
4853 if (unlikely(Rc(ctx->opcode) != 0))
4854 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4855 }
4856
4857 /* maskir - maskir. */
4858 static void gen_maskir(DisasContext *ctx)
4859 {
4860 TCGv t0 = tcg_temp_new();
4861 TCGv t1 = tcg_temp_new();
4862 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4863 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4864 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4865 tcg_temp_free(t0);
4866 tcg_temp_free(t1);
4867 if (unlikely(Rc(ctx->opcode) != 0))
4868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4869 }
4870
4871 /* mul - mul. */
4872 static void gen_mul(DisasContext *ctx)
4873 {
4874 TCGv_i64 t0 = tcg_temp_new_i64();
4875 TCGv_i64 t1 = tcg_temp_new_i64();
4876 TCGv t2 = tcg_temp_new();
4877 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4878 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4879 tcg_gen_mul_i64(t0, t0, t1);
4880 tcg_gen_trunc_i64_tl(t2, t0);
4881 gen_store_spr(SPR_MQ, t2);
4882 tcg_gen_shri_i64(t1, t0, 32);
4883 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4884 tcg_temp_free_i64(t0);
4885 tcg_temp_free_i64(t1);
4886 tcg_temp_free(t2);
4887 if (unlikely(Rc(ctx->opcode) != 0))
4888 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4889 }
4890
4891 /* mulo - mulo. */
4892 static void gen_mulo(DisasContext *ctx)
4893 {
4894 TCGLabel *l1 = gen_new_label();
4895 TCGv_i64 t0 = tcg_temp_new_i64();
4896 TCGv_i64 t1 = tcg_temp_new_i64();
4897 TCGv t2 = tcg_temp_new();
4898 /* Start with XER OV disabled, the most likely case */
4899 tcg_gen_movi_tl(cpu_ov, 0);
4900 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4901 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4902 tcg_gen_mul_i64(t0, t0, t1);
4903 tcg_gen_trunc_i64_tl(t2, t0);
4904 gen_store_spr(SPR_MQ, t2);
4905 tcg_gen_shri_i64(t1, t0, 32);
4906 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4907 tcg_gen_ext32s_i64(t1, t0);
4908 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4909 tcg_gen_movi_tl(cpu_ov, 1);
4910 tcg_gen_movi_tl(cpu_so, 1);
4911 gen_set_label(l1);
4912 tcg_temp_free_i64(t0);
4913 tcg_temp_free_i64(t1);
4914 tcg_temp_free(t2);
4915 if (unlikely(Rc(ctx->opcode) != 0))
4916 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4917 }
4918
4919 /* nabs - nabs. */
4920 static void gen_nabs(DisasContext *ctx)
4921 {
4922 TCGLabel *l1 = gen_new_label();
4923 TCGLabel *l2 = gen_new_label();
4924 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4925 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4926 tcg_gen_br(l2);
4927 gen_set_label(l1);
4928 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4929 gen_set_label(l2);
4930 if (unlikely(Rc(ctx->opcode) != 0))
4931 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4932 }
4933
4934 /* nabso - nabso. */
4935 static void gen_nabso(DisasContext *ctx)
4936 {
4937 TCGLabel *l1 = gen_new_label();
4938 TCGLabel *l2 = gen_new_label();
4939 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4940 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4941 tcg_gen_br(l2);
4942 gen_set_label(l1);
4943 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4944 gen_set_label(l2);
4945 /* nabs never overflows */
4946 tcg_gen_movi_tl(cpu_ov, 0);
4947 if (unlikely(Rc(ctx->opcode) != 0))
4948 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4949 }
4950
4951 /* rlmi - rlmi. */
4952 static void gen_rlmi(DisasContext *ctx)
4953 {
4954 uint32_t mb = MB(ctx->opcode);
4955 uint32_t me = ME(ctx->opcode);
4956 TCGv t0 = tcg_temp_new();
4957 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4958 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4959 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4960 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4961 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4962 tcg_temp_free(t0);
4963 if (unlikely(Rc(ctx->opcode) != 0))
4964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4965 }
4966
4967 /* rrib - rrib. */
4968 static void gen_rrib(DisasContext *ctx)
4969 {
4970 TCGv t0 = tcg_temp_new();
4971 TCGv t1 = tcg_temp_new();
4972 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4973 tcg_gen_movi_tl(t1, 0x80000000);
4974 tcg_gen_shr_tl(t1, t1, t0);
4975 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4976 tcg_gen_and_tl(t0, t0, t1);
4977 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4978 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4979 tcg_temp_free(t0);
4980 tcg_temp_free(t1);
4981 if (unlikely(Rc(ctx->opcode) != 0))
4982 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4983 }
4984
4985 /* sle - sle. */
4986 static void gen_sle(DisasContext *ctx)
4987 {
4988 TCGv t0 = tcg_temp_new();
4989 TCGv t1 = tcg_temp_new();
4990 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4991 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4992 tcg_gen_subfi_tl(t1, 32, t1);
4993 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4994 tcg_gen_or_tl(t1, t0, t1);
4995 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4996 gen_store_spr(SPR_MQ, t1);
4997 tcg_temp_free(t0);
4998 tcg_temp_free(t1);
4999 if (unlikely(Rc(ctx->opcode) != 0))
5000 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5001 }
5002
5003 /* sleq - sleq. */
5004 static void gen_sleq(DisasContext *ctx)
5005 {
5006 TCGv t0 = tcg_temp_new();
5007 TCGv t1 = tcg_temp_new();
5008 TCGv t2 = tcg_temp_new();
5009 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5010 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5011 tcg_gen_shl_tl(t2, t2, t0);
5012 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5013 gen_load_spr(t1, SPR_MQ);
5014 gen_store_spr(SPR_MQ, t0);
5015 tcg_gen_and_tl(t0, t0, t2);
5016 tcg_gen_andc_tl(t1, t1, t2);
5017 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5018 tcg_temp_free(t0);
5019 tcg_temp_free(t1);
5020 tcg_temp_free(t2);
5021 if (unlikely(Rc(ctx->opcode) != 0))
5022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5023 }
5024
5025 /* sliq - sliq. */
5026 static void gen_sliq(DisasContext *ctx)
5027 {
5028 int sh = SH(ctx->opcode);
5029 TCGv t0 = tcg_temp_new();
5030 TCGv t1 = tcg_temp_new();
5031 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5032 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5033 tcg_gen_or_tl(t1, t0, t1);
5034 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5035 gen_store_spr(SPR_MQ, t1);
5036 tcg_temp_free(t0);
5037 tcg_temp_free(t1);
5038 if (unlikely(Rc(ctx->opcode) != 0))
5039 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5040 }
5041
5042 /* slliq - slliq. */
5043 static void gen_slliq(DisasContext *ctx)
5044 {
5045 int sh = SH(ctx->opcode);
5046 TCGv t0 = tcg_temp_new();
5047 TCGv t1 = tcg_temp_new();
5048 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5049 gen_load_spr(t1, SPR_MQ);
5050 gen_store_spr(SPR_MQ, t0);
5051 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5052 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5053 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5054 tcg_temp_free(t0);
5055 tcg_temp_free(t1);
5056 if (unlikely(Rc(ctx->opcode) != 0))
5057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5058 }
5059
5060 /* sllq - sllq. */
5061 static void gen_sllq(DisasContext *ctx)
5062 {
5063 TCGLabel *l1 = gen_new_label();
5064 TCGLabel *l2 = gen_new_label();
5065 TCGv t0 = tcg_temp_local_new();
5066 TCGv t1 = tcg_temp_local_new();
5067 TCGv t2 = tcg_temp_local_new();
5068 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5069 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5070 tcg_gen_shl_tl(t1, t1, t2);
5071 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5072 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5073 gen_load_spr(t0, SPR_MQ);
5074 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5075 tcg_gen_br(l2);
5076 gen_set_label(l1);
5077 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5078 gen_load_spr(t2, SPR_MQ);
5079 tcg_gen_andc_tl(t1, t2, t1);
5080 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5081 gen_set_label(l2);
5082 tcg_temp_free(t0);
5083 tcg_temp_free(t1);
5084 tcg_temp_free(t2);
5085 if (unlikely(Rc(ctx->opcode) != 0))
5086 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5087 }
5088
5089 /* slq - slq. */
5090 static void gen_slq(DisasContext *ctx)
5091 {
5092 TCGLabel *l1 = gen_new_label();
5093 TCGv t0 = tcg_temp_new();
5094 TCGv t1 = tcg_temp_new();
5095 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5096 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5097 tcg_gen_subfi_tl(t1, 32, t1);
5098 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5099 tcg_gen_or_tl(t1, t0, t1);
5100 gen_store_spr(SPR_MQ, t1);
5101 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5102 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5103 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5104 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5105 gen_set_label(l1);
5106 tcg_temp_free(t0);
5107 tcg_temp_free(t1);
5108 if (unlikely(Rc(ctx->opcode) != 0))
5109 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5110 }
5111
5112 /* sraiq - sraiq. */
5113 static void gen_sraiq(DisasContext *ctx)
5114 {
5115 int sh = SH(ctx->opcode);
5116 TCGLabel *l1 = gen_new_label();
5117 TCGv t0 = tcg_temp_new();
5118 TCGv t1 = tcg_temp_new();
5119 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5120 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5121 tcg_gen_or_tl(t0, t0, t1);
5122 gen_store_spr(SPR_MQ, t0);
5123 tcg_gen_movi_tl(cpu_ca, 0);
5124 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5125 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5126 tcg_gen_movi_tl(cpu_ca, 1);
5127 gen_set_label(l1);
5128 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5129 tcg_temp_free(t0);
5130 tcg_temp_free(t1);
5131 if (unlikely(Rc(ctx->opcode) != 0))
5132 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5133 }
5134
5135 /* sraq - sraq. */
5136 static void gen_sraq(DisasContext *ctx)
5137 {
5138 TCGLabel *l1 = gen_new_label();
5139 TCGLabel *l2 = gen_new_label();
5140 TCGv t0 = tcg_temp_new();
5141 TCGv t1 = tcg_temp_local_new();
5142 TCGv t2 = tcg_temp_local_new();
5143 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5144 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5145 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5146 tcg_gen_subfi_tl(t2, 32, t2);
5147 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5148 tcg_gen_or_tl(t0, t0, t2);
5149 gen_store_spr(SPR_MQ, t0);
5150 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5151 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5152 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5153 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5154 gen_set_label(l1);
5155 tcg_temp_free(t0);
5156 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5157 tcg_gen_movi_tl(cpu_ca, 0);
5158 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5159 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5160 tcg_gen_movi_tl(cpu_ca, 1);
5161 gen_set_label(l2);
5162 tcg_temp_free(t1);
5163 tcg_temp_free(t2);
5164 if (unlikely(Rc(ctx->opcode) != 0))
5165 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5166 }
5167
5168 /* sre - sre. */
5169 static void gen_sre(DisasContext *ctx)
5170 {
5171 TCGv t0 = tcg_temp_new();
5172 TCGv t1 = tcg_temp_new();
5173 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5174 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5175 tcg_gen_subfi_tl(t1, 32, t1);
5176 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5177 tcg_gen_or_tl(t1, t0, t1);
5178 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5179 gen_store_spr(SPR_MQ, t1);
5180 tcg_temp_free(t0);
5181 tcg_temp_free(t1);
5182 if (unlikely(Rc(ctx->opcode) != 0))
5183 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5184 }
5185
5186 /* srea - srea. */
5187 static void gen_srea(DisasContext *ctx)
5188 {
5189 TCGv t0 = tcg_temp_new();
5190 TCGv t1 = tcg_temp_new();
5191 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5192 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5193 gen_store_spr(SPR_MQ, t0);
5194 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5195 tcg_temp_free(t0);
5196 tcg_temp_free(t1);
5197 if (unlikely(Rc(ctx->opcode) != 0))
5198 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5199 }
5200
5201 /* sreq */
5202 static void gen_sreq(DisasContext *ctx)
5203 {
5204 TCGv t0 = tcg_temp_new();
5205 TCGv t1 = tcg_temp_new();
5206 TCGv t2 = tcg_temp_new();
5207 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5208 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5209 tcg_gen_shr_tl(t1, t1, t0);
5210 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5211 gen_load_spr(t2, SPR_MQ);
5212 gen_store_spr(SPR_MQ, t0);
5213 tcg_gen_and_tl(t0, t0, t1);
5214 tcg_gen_andc_tl(t2, t2, t1);
5215 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5216 tcg_temp_free(t0);
5217 tcg_temp_free(t1);
5218 tcg_temp_free(t2);
5219 if (unlikely(Rc(ctx->opcode) != 0))
5220 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5221 }
5222
5223 /* sriq */
5224 static void gen_sriq(DisasContext *ctx)
5225 {
5226 int sh = SH(ctx->opcode);
5227 TCGv t0 = tcg_temp_new();
5228 TCGv t1 = tcg_temp_new();
5229 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5230 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5231 tcg_gen_or_tl(t1, t0, t1);
5232 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5233 gen_store_spr(SPR_MQ, t1);
5234 tcg_temp_free(t0);
5235 tcg_temp_free(t1);
5236 if (unlikely(Rc(ctx->opcode) != 0))
5237 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5238 }
5239
5240 /* srliq */
5241 static void gen_srliq(DisasContext *ctx)
5242 {
5243 int sh = SH(ctx->opcode);
5244 TCGv t0 = tcg_temp_new();
5245 TCGv t1 = tcg_temp_new();
5246 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5247 gen_load_spr(t1, SPR_MQ);
5248 gen_store_spr(SPR_MQ, t0);
5249 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5250 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5251 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5252 tcg_temp_free(t0);
5253 tcg_temp_free(t1);
5254 if (unlikely(Rc(ctx->opcode) != 0))
5255 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5256 }
5257
5258 /* srlq */
5259 static void gen_srlq(DisasContext *ctx)
5260 {
5261 TCGLabel *l1 = gen_new_label();
5262 TCGLabel *l2 = gen_new_label();
5263 TCGv t0 = tcg_temp_local_new();
5264 TCGv t1 = tcg_temp_local_new();
5265 TCGv t2 = tcg_temp_local_new();
5266 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5267 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5268 tcg_gen_shr_tl(t2, t1, t2);
5269 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5270 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5271 gen_load_spr(t0, SPR_MQ);
5272 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5273 tcg_gen_br(l2);
5274 gen_set_label(l1);
5275 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5276 tcg_gen_and_tl(t0, t0, t2);
5277 gen_load_spr(t1, SPR_MQ);
5278 tcg_gen_andc_tl(t1, t1, t2);
5279 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5280 gen_set_label(l2);
5281 tcg_temp_free(t0);
5282 tcg_temp_free(t1);
5283 tcg_temp_free(t2);
5284 if (unlikely(Rc(ctx->opcode) != 0))
5285 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5286 }
5287
5288 /* srq */
5289 static void gen_srq(DisasContext *ctx)
5290 {
5291 TCGLabel *l1 = gen_new_label();
5292 TCGv t0 = tcg_temp_new();
5293 TCGv t1 = tcg_temp_new();
5294 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5295 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5296 tcg_gen_subfi_tl(t1, 32, t1);
5297 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5298 tcg_gen_or_tl(t1, t0, t1);
5299 gen_store_spr(SPR_MQ, t1);
5300 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5301 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5303 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5304 gen_set_label(l1);
5305 tcg_temp_free(t0);
5306 tcg_temp_free(t1);
5307 if (unlikely(Rc(ctx->opcode) != 0))
5308 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5309 }
5310
5311 /* PowerPC 602 specific instructions */
5312
5313 /* dsa */
5314 static void gen_dsa(DisasContext *ctx)
5315 {
5316 /* XXX: TODO */
5317 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5318 }
5319
5320 /* esa */
5321 static void gen_esa(DisasContext *ctx)
5322 {
5323 /* XXX: TODO */
5324 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5325 }
5326
5327 /* mfrom */
5328 static void gen_mfrom(DisasContext *ctx)
5329 {
5330 #if defined(CONFIG_USER_ONLY)
5331 GEN_PRIV;
5332 #else
5333 CHK_SV;
5334 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5335 #endif /* defined(CONFIG_USER_ONLY) */
5336 }
5337
5338 /* 602 - 603 - G2 TLB management */
5339
5340 /* tlbld */
5341 static void gen_tlbld_6xx(DisasContext *ctx)
5342 {
5343 #if defined(CONFIG_USER_ONLY)
5344 GEN_PRIV;
5345 #else
5346 CHK_SV;
5347 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5348 #endif /* defined(CONFIG_USER_ONLY) */
5349 }
5350
5351 /* tlbli */
5352 static void gen_tlbli_6xx(DisasContext *ctx)
5353 {
5354 #if defined(CONFIG_USER_ONLY)
5355 GEN_PRIV;
5356 #else
5357 CHK_SV;
5358 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5359 #endif /* defined(CONFIG_USER_ONLY) */
5360 }
5361
5362 /* 74xx TLB management */
5363
5364 /* tlbld */
5365 static void gen_tlbld_74xx(DisasContext *ctx)
5366 {
5367 #if defined(CONFIG_USER_ONLY)
5368 GEN_PRIV;
5369 #else
5370 CHK_SV;
5371 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5372 #endif /* defined(CONFIG_USER_ONLY) */
5373 }
5374
5375 /* tlbli */
5376 static void gen_tlbli_74xx(DisasContext *ctx)
5377 {
5378 #if defined(CONFIG_USER_ONLY)
5379 GEN_PRIV;
5380 #else
5381 CHK_SV;
5382 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5383 #endif /* defined(CONFIG_USER_ONLY) */
5384 }
5385
5386 /* POWER instructions not in PowerPC 601 */
5387
5388 /* clf */
5389 static void gen_clf(DisasContext *ctx)
5390 {
5391 /* Cache line flush: implemented as no-op */
5392 }
5393
5394 /* cli */
5395 static void gen_cli(DisasContext *ctx)
5396 {
5397 #if defined(CONFIG_USER_ONLY)
5398 GEN_PRIV;
5399 #else
5400 /* Cache line invalidate: privileged and treated as no-op */
5401 CHK_SV;
5402 #endif /* defined(CONFIG_USER_ONLY) */
5403 }
5404
5405 /* dclst */
5406 static void gen_dclst(DisasContext *ctx)
5407 {
5408 /* Data cache line store: treated as no-op */
5409 }
5410
5411 static void gen_mfsri(DisasContext *ctx)
5412 {
5413 #if defined(CONFIG_USER_ONLY)
5414 GEN_PRIV;
5415 #else
5416 int ra = rA(ctx->opcode);
5417 int rd = rD(ctx->opcode);
5418 TCGv t0;
5419
5420 CHK_SV;
5421 t0 = tcg_temp_new();
5422 gen_addr_reg_index(ctx, t0);
5423 tcg_gen_extract_tl(t0, t0, 28, 4);
5424 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5425 tcg_temp_free(t0);
5426 if (ra != 0 && ra != rd)
5427 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5428 #endif /* defined(CONFIG_USER_ONLY) */
5429 }
5430
5431 static void gen_rac(DisasContext *ctx)
5432 {
5433 #if defined(CONFIG_USER_ONLY)
5434 GEN_PRIV;
5435 #else
5436 TCGv t0;
5437
5438 CHK_SV;
5439 t0 = tcg_temp_new();
5440 gen_addr_reg_index(ctx, t0);
5441 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5442 tcg_temp_free(t0);
5443 #endif /* defined(CONFIG_USER_ONLY) */
5444 }
5445
5446 static void gen_rfsvc(DisasContext *ctx)
5447 {
5448 #if defined(CONFIG_USER_ONLY)
5449 GEN_PRIV;
5450 #else
5451 CHK_SV;
5452
5453 gen_helper_rfsvc(cpu_env);
5454 gen_sync_exception(ctx);
5455 #endif /* defined(CONFIG_USER_ONLY) */
5456 }
5457
5458 /* svc is not implemented for now */
5459
5460 /* BookE specific instructions */
5461
5462 /* XXX: not implemented on 440 ? */
5463 static void gen_mfapidi(DisasContext *ctx)
5464 {
5465 /* XXX: TODO */
5466 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5467 }
5468
5469 /* XXX: not implemented on 440 ? */
5470 static void gen_tlbiva(DisasContext *ctx)
5471 {
5472 #if defined(CONFIG_USER_ONLY)
5473 GEN_PRIV;
5474 #else
5475 TCGv t0;
5476
5477 CHK_SV;
5478 t0 = tcg_temp_new();
5479 gen_addr_reg_index(ctx, t0);
5480 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5481 tcg_temp_free(t0);
5482 #endif /* defined(CONFIG_USER_ONLY) */
5483 }
5484
5485 /* All 405 MAC instructions are translated here */
5486 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5487 int ra, int rb, int rt, int Rc)
5488 {
5489 TCGv t0, t1;
5490
5491 t0 = tcg_temp_local_new();
5492 t1 = tcg_temp_local_new();
5493
5494 switch (opc3 & 0x0D) {
5495 case 0x05:
5496 /* macchw - macchw. - macchwo - macchwo. */
5497 /* macchws - macchws. - macchwso - macchwso. */
5498 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5499 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5500 /* mulchw - mulchw. */
5501 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5502 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5503 tcg_gen_ext16s_tl(t1, t1);
5504 break;
5505 case 0x04:
5506 /* macchwu - macchwu. - macchwuo - macchwuo. */
5507 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5508 /* mulchwu - mulchwu. */
5509 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5510 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5511 tcg_gen_ext16u_tl(t1, t1);
5512 break;
5513 case 0x01:
5514 /* machhw - machhw. - machhwo - machhwo. */
5515 /* machhws - machhws. - machhwso - machhwso. */
5516 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5517 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5518 /* mulhhw - mulhhw. */
5519 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5520 tcg_gen_ext16s_tl(t0, t0);
5521 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5522 tcg_gen_ext16s_tl(t1, t1);
5523 break;
5524 case 0x00:
5525 /* machhwu - machhwu. - machhwuo - machhwuo. */
5526 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5527 /* mulhhwu - mulhhwu. */
5528 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5529 tcg_gen_ext16u_tl(t0, t0);
5530 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5531 tcg_gen_ext16u_tl(t1, t1);
5532 break;
5533 case 0x0D:
5534 /* maclhw - maclhw. - maclhwo - maclhwo. */
5535 /* maclhws - maclhws. - maclhwso - maclhwso. */
5536 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5537 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5538 /* mullhw - mullhw. */
5539 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5540 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5541 break;
5542 case 0x0C:
5543 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5544 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5545 /* mullhwu - mullhwu. */
5546 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5547 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5548 break;
5549 }
5550 if (opc2 & 0x04) {
5551 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5552 tcg_gen_mul_tl(t1, t0, t1);
5553 if (opc2 & 0x02) {
5554 /* nmultiply-and-accumulate (0x0E) */
5555 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5556 } else {
5557 /* multiply-and-accumulate (0x0C) */
5558 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5559 }
5560
5561 if (opc3 & 0x12) {
5562 /* Check overflow and/or saturate */
5563 TCGLabel *l1 = gen_new_label();
5564
5565 if (opc3 & 0x10) {
5566 /* Start with XER OV disabled, the most likely case */
5567 tcg_gen_movi_tl(cpu_ov, 0);
5568 }
5569 if (opc3 & 0x01) {
5570 /* Signed */
5571 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5572 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5573 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5574 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5575 if (opc3 & 0x02) {
5576 /* Saturate */
5577 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5578 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5579 }
5580 } else {
5581 /* Unsigned */
5582 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5583 if (opc3 & 0x02) {
5584 /* Saturate */
5585 tcg_gen_movi_tl(t0, UINT32_MAX);
5586 }
5587 }
5588 if (opc3 & 0x10) {
5589 /* Check overflow */
5590 tcg_gen_movi_tl(cpu_ov, 1);
5591 tcg_gen_movi_tl(cpu_so, 1);
5592 }
5593 gen_set_label(l1);
5594 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5595 }
5596 } else {
5597 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5598 }
5599 tcg_temp_free(t0);
5600 tcg_temp_free(t1);
5601 if (unlikely(Rc) != 0) {
5602 /* Update Rc0 */
5603 gen_set_Rc0(ctx, cpu_gpr[rt]);
5604 }
5605 }
5606
5607 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5608 static void glue(gen_, name)(DisasContext *ctx) \
5609 { \
5610 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5611 rD(ctx->opcode), Rc(ctx->opcode)); \
5612 }
5613
5614 /* macchw - macchw. */
5615 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5616 /* macchwo - macchwo. */
5617 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5618 /* macchws - macchws. */
5619 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5620 /* macchwso - macchwso. */
5621 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5622 /* macchwsu - macchwsu. */
5623 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5624 /* macchwsuo - macchwsuo. */
5625 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5626 /* macchwu - macchwu. */
5627 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5628 /* macchwuo - macchwuo. */
5629 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5630 /* machhw - machhw. */
5631 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5632 /* machhwo - machhwo. */
5633 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5634 /* machhws - machhws. */
5635 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5636 /* machhwso - machhwso. */
5637 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5638 /* machhwsu - machhwsu. */
5639 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5640 /* machhwsuo - machhwsuo. */
5641 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5642 /* machhwu - machhwu. */
5643 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5644 /* machhwuo - machhwuo. */
5645 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5646 /* maclhw - maclhw. */
5647 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5648 /* maclhwo - maclhwo. */
5649 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5650 /* maclhws - maclhws. */
5651 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5652 /* maclhwso - maclhwso. */
5653 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5654 /* maclhwu - maclhwu. */
5655 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5656 /* maclhwuo - maclhwuo. */
5657 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5658 /* maclhwsu - maclhwsu. */
5659 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5660 /* maclhwsuo - maclhwsuo. */
5661 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5662 /* nmacchw - nmacchw. */
5663 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5664 /* nmacchwo - nmacchwo. */
5665 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5666 /* nmacchws - nmacchws. */
5667 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5668 /* nmacchwso - nmacchwso. */
5669 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5670 /* nmachhw - nmachhw. */
5671 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5672 /* nmachhwo - nmachhwo. */
5673 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5674 /* nmachhws - nmachhws. */
5675 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5676 /* nmachhwso - nmachhwso. */
5677 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5678 /* nmaclhw - nmaclhw. */
5679 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5680 /* nmaclhwo - nmaclhwo. */
5681 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5682 /* nmaclhws - nmaclhws. */
5683 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5684 /* nmaclhwso - nmaclhwso. */
5685 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5686
5687 /* mulchw - mulchw. */
5688 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5689 /* mulchwu - mulchwu. */
5690 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5691 /* mulhhw - mulhhw. */
5692 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5693 /* mulhhwu - mulhhwu. */
5694 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5695 /* mullhw - mullhw. */
5696 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5697 /* mullhwu - mullhwu. */
5698 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5699
5700 /* mfdcr */
5701 static void gen_mfdcr(DisasContext *ctx)
5702 {
5703 #if defined(CONFIG_USER_ONLY)
5704 GEN_PRIV;
5705 #else
5706 TCGv dcrn;
5707
5708 CHK_SV;
5709 dcrn = tcg_const_tl(SPR(ctx->opcode));
5710 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5711 tcg_temp_free(dcrn);
5712 #endif /* defined(CONFIG_USER_ONLY) */
5713 }
5714
5715 /* mtdcr */
5716 static void gen_mtdcr(DisasContext *ctx)
5717 {
5718 #if defined(CONFIG_USER_ONLY)
5719 GEN_PRIV;
5720 #else
5721 TCGv dcrn;
5722
5723 CHK_SV;
5724 dcrn = tcg_const_tl(SPR(ctx->opcode));
5725 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5726 tcg_temp_free(dcrn);
5727 #endif /* defined(CONFIG_USER_ONLY) */
5728 }
5729
5730 /* mfdcrx */
5731 /* XXX: not implemented on 440 ? */
5732 static void gen_mfdcrx(DisasContext *ctx)
5733 {
5734 #if defined(CONFIG_USER_ONLY)
5735 GEN_PRIV;
5736 #else
5737 CHK_SV;
5738 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5739 cpu_gpr[rA(ctx->opcode)]);
5740 /* Note: Rc update flag set leads to undefined state of Rc0 */
5741 #endif /* defined(CONFIG_USER_ONLY) */
5742 }
5743
5744 /* mtdcrx */
5745 /* XXX: not implemented on 440 ? */
5746 static void gen_mtdcrx(DisasContext *ctx)
5747 {
5748 #if defined(CONFIG_USER_ONLY)
5749 GEN_PRIV;
5750 #else
5751 CHK_SV;
5752 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5753 cpu_gpr[rS(ctx->opcode)]);
5754 /* Note: Rc update flag set leads to undefined state of Rc0 */
5755 #endif /* defined(CONFIG_USER_ONLY) */
5756 }
5757
5758 /* mfdcrux (PPC 460) : user-mode access to DCR */
5759 static void gen_mfdcrux(DisasContext *ctx)
5760 {
5761 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5762 cpu_gpr[rA(ctx->opcode)]);
5763 /* Note: Rc update flag set leads to undefined state of Rc0 */
5764 }
5765
5766 /* mtdcrux (PPC 460) : user-mode access to DCR */
5767 static void gen_mtdcrux(DisasContext *ctx)
5768 {
5769 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5770 cpu_gpr[rS(ctx->opcode)]);
5771 /* Note: Rc update flag set leads to undefined state of Rc0 */
5772 }
5773
5774 /* dccci */
5775 static void gen_dccci(DisasContext *ctx)
5776 {
5777 CHK_SV;
5778 /* interpreted as no-op */
5779 }
5780
5781 /* dcread */
5782 static void gen_dcread(DisasContext *ctx)
5783 {
5784 #if defined(CONFIG_USER_ONLY)
5785 GEN_PRIV;
5786 #else
5787 TCGv EA, val;
5788
5789 CHK_SV;
5790 gen_set_access_type(ctx, ACCESS_CACHE);
5791 EA = tcg_temp_new();
5792 gen_addr_reg_index(ctx, EA);
5793 val = tcg_temp_new();
5794 gen_qemu_ld32u(ctx, val, EA);
5795 tcg_temp_free(val);
5796 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5797 tcg_temp_free(EA);
5798 #endif /* defined(CONFIG_USER_ONLY) */
5799 }
5800
5801 /* icbt */
5802 static void gen_icbt_40x(DisasContext *ctx)
5803 {
5804 /* interpreted as no-op */
5805 /* XXX: specification say this is treated as a load by the MMU
5806 * but does not generate any exception
5807 */
5808 }
5809
5810 /* iccci */
5811 static void gen_iccci(DisasContext *ctx)
5812 {
5813 CHK_SV;
5814 /* interpreted as no-op */
5815 }
5816
5817 /* icread */
5818 static void gen_icread(DisasContext *ctx)
5819 {
5820 CHK_SV;
5821 /* interpreted as no-op */
5822 }
5823
5824 /* rfci (supervisor only) */
5825 static void gen_rfci_40x(DisasContext *ctx)
5826 {
5827 #if defined(CONFIG_USER_ONLY)
5828 GEN_PRIV;
5829 #else
5830 CHK_SV;
5831 /* Restore CPU state */
5832 gen_helper_40x_rfci(cpu_env);
5833 gen_sync_exception(ctx);
5834 #endif /* defined(CONFIG_USER_ONLY) */
5835 }
5836
5837 static void gen_rfci(DisasContext *ctx)
5838 {
5839 #if defined(CONFIG_USER_ONLY)
5840 GEN_PRIV;
5841 #else
5842 CHK_SV;
5843 /* Restore CPU state */
5844 gen_helper_rfci(cpu_env);
5845 gen_sync_exception(ctx);
5846 #endif /* defined(CONFIG_USER_ONLY) */
5847 }
5848
5849 /* BookE specific */
5850
5851 /* XXX: not implemented on 440 ? */
5852 static void gen_rfdi(DisasContext *ctx)
5853 {
5854 #if defined(CONFIG_USER_ONLY)
5855 GEN_PRIV;
5856 #else
5857 CHK_SV;
5858 /* Restore CPU state */
5859 gen_helper_rfdi(cpu_env);
5860 gen_sync_exception(ctx);
5861 #endif /* defined(CONFIG_USER_ONLY) */
5862 }
5863
5864 /* XXX: not implemented on 440 ? */
5865 static void gen_rfmci(DisasContext *ctx)
5866 {
5867 #if defined(CONFIG_USER_ONLY)
5868 GEN_PRIV;
5869 #else
5870 CHK_SV;
5871 /* Restore CPU state */
5872 gen_helper_rfmci(cpu_env);
5873 gen_sync_exception(ctx);
5874 #endif /* defined(CONFIG_USER_ONLY) */
5875 }
5876
5877 /* TLB management - PowerPC 405 implementation */
5878
5879 /* tlbre */
5880 static void gen_tlbre_40x(DisasContext *ctx)
5881 {
5882 #if defined(CONFIG_USER_ONLY)
5883 GEN_PRIV;
5884 #else
5885 CHK_SV;
5886 switch (rB(ctx->opcode)) {
5887 case 0:
5888 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5889 cpu_gpr[rA(ctx->opcode)]);
5890 break;
5891 case 1:
5892 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5893 cpu_gpr[rA(ctx->opcode)]);
5894 break;
5895 default:
5896 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5897 break;
5898 }
5899 #endif /* defined(CONFIG_USER_ONLY) */
5900 }
5901
5902 /* tlbsx - tlbsx. */
5903 static void gen_tlbsx_40x(DisasContext *ctx)
5904 {
5905 #if defined(CONFIG_USER_ONLY)
5906 GEN_PRIV;
5907 #else
5908 TCGv t0;
5909
5910 CHK_SV;
5911 t0 = tcg_temp_new();
5912 gen_addr_reg_index(ctx, t0);
5913 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5914 tcg_temp_free(t0);
5915 if (Rc(ctx->opcode)) {
5916 TCGLabel *l1 = gen_new_label();
5917 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5918 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5919 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5920 gen_set_label(l1);
5921 }
5922 #endif /* defined(CONFIG_USER_ONLY) */
5923 }
5924
5925 /* tlbwe */
5926 static void gen_tlbwe_40x(DisasContext *ctx)
5927 {
5928 #if defined(CONFIG_USER_ONLY)
5929 GEN_PRIV;
5930 #else
5931 CHK_SV;
5932
5933 switch (rB(ctx->opcode)) {
5934 case 0:
5935 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5936 cpu_gpr[rS(ctx->opcode)]);
5937 break;
5938 case 1:
5939 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5940 cpu_gpr[rS(ctx->opcode)]);
5941 break;
5942 default:
5943 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5944 break;
5945 }
5946 #endif /* defined(CONFIG_USER_ONLY) */
5947 }
5948
5949 /* TLB management - PowerPC 440 implementation */
5950
5951 /* tlbre */
5952 static void gen_tlbre_440(DisasContext *ctx)
5953 {
5954 #if defined(CONFIG_USER_ONLY)
5955 GEN_PRIV;
5956 #else
5957 CHK_SV;
5958
5959 switch (rB(ctx->opcode)) {
5960 case 0:
5961 case 1:
5962 case 2:
5963 {
5964 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5965 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5966 t0, cpu_gpr[rA(ctx->opcode)]);
5967 tcg_temp_free_i32(t0);
5968 }
5969 break;
5970 default:
5971 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5972 break;
5973 }
5974 #endif /* defined(CONFIG_USER_ONLY) */
5975 }
5976
5977 /* tlbsx - tlbsx. */
5978 static void gen_tlbsx_440(DisasContext *ctx)
5979 {
5980 #if defined(CONFIG_USER_ONLY)
5981 GEN_PRIV;
5982 #else
5983 TCGv t0;
5984
5985 CHK_SV;
5986 t0 = tcg_temp_new();
5987 gen_addr_reg_index(ctx, t0);
5988 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5989 tcg_temp_free(t0);
5990 if (Rc(ctx->opcode)) {
5991 TCGLabel *l1 = gen_new_label();
5992 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5993 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5994 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5995 gen_set_label(l1);
5996 }
5997 #endif /* defined(CONFIG_USER_ONLY) */
5998 }
5999
6000 /* tlbwe */
6001 static void gen_tlbwe_440(DisasContext *ctx)
6002 {
6003 #if defined(CONFIG_USER_ONLY)
6004 GEN_PRIV;
6005 #else
6006 CHK_SV;
6007 switch (rB(ctx->opcode)) {
6008 case 0:
6009 case 1:
6010 case 2:
6011 {
6012 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6013 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6014 cpu_gpr[rS(ctx->opcode)]);
6015 tcg_temp_free_i32(t0);
6016 }
6017 break;
6018 default:
6019 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6020 break;
6021 }
6022 #endif /* defined(CONFIG_USER_ONLY) */
6023 }
6024
6025 /* TLB management - PowerPC BookE 2.06 implementation */
6026
6027 /* tlbre */
6028 static void gen_tlbre_booke206(DisasContext *ctx)
6029 {
6030 #if defined(CONFIG_USER_ONLY)
6031 GEN_PRIV;
6032 #else
6033 CHK_SV;
6034 gen_helper_booke206_tlbre(cpu_env);
6035 #endif /* defined(CONFIG_USER_ONLY) */
6036 }
6037
6038 /* tlbsx - tlbsx. */
6039 static void gen_tlbsx_booke206(DisasContext *ctx)
6040 {
6041 #if defined(CONFIG_USER_ONLY)
6042 GEN_PRIV;
6043 #else
6044 TCGv t0;
6045
6046 CHK_SV;
6047 if (rA(ctx->opcode)) {
6048 t0 = tcg_temp_new();
6049 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6050 } else {
6051 t0 = tcg_const_tl(0);
6052 }
6053
6054 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6055 gen_helper_booke206_tlbsx(cpu_env, t0);
6056 tcg_temp_free(t0);
6057 #endif /* defined(CONFIG_USER_ONLY) */
6058 }
6059
6060 /* tlbwe */
6061 static void gen_tlbwe_booke206(DisasContext *ctx)
6062 {
6063 #if defined(CONFIG_USER_ONLY)
6064 GEN_PRIV;
6065 #else
6066 CHK_SV;
6067 gen_helper_booke206_tlbwe(cpu_env);
6068 #endif /* defined(CONFIG_USER_ONLY) */
6069 }
6070
6071 static void gen_tlbivax_booke206(DisasContext *ctx)
6072 {
6073 #if defined(CONFIG_USER_ONLY)
6074 GEN_PRIV;
6075 #else
6076 TCGv t0;
6077
6078 CHK_SV;
6079 t0 = tcg_temp_new();
6080 gen_addr_reg_index(ctx, t0);
6081 gen_helper_booke206_tlbivax(cpu_env, t0);
6082 tcg_temp_free(t0);
6083 #endif /* defined(CONFIG_USER_ONLY) */
6084 }
6085
6086 static void gen_tlbilx_booke206(DisasContext *ctx)
6087 {
6088 #if defined(CONFIG_USER_ONLY)
6089 GEN_PRIV;
6090 #else
6091 TCGv t0;
6092
6093 CHK_SV;
6094 t0 = tcg_temp_new();
6095 gen_addr_reg_index(ctx, t0);
6096
6097 switch((ctx->opcode >> 21) & 0x3) {
6098 case 0:
6099 gen_helper_booke206_tlbilx0(cpu_env, t0);
6100 break;
6101 case 1:
6102 gen_helper_booke206_tlbilx1(cpu_env, t0);
6103 break;
6104 case 3:
6105 gen_helper_booke206_tlbilx3(cpu_env, t0);
6106 break;
6107 default:
6108 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6109 break;
6110 }
6111
6112 tcg_temp_free(t0);
6113 #endif /* defined(CONFIG_USER_ONLY) */
6114 }
6115
6116
6117 /* wrtee */
6118 static void gen_wrtee(DisasContext *ctx)
6119 {
6120 #if defined(CONFIG_USER_ONLY)
6121 GEN_PRIV;
6122 #else
6123 TCGv t0;
6124
6125 CHK_SV;
6126 t0 = tcg_temp_new();
6127 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6128 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6129 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6130 tcg_temp_free(t0);
6131 /* Stop translation to have a chance to raise an exception
6132 * if we just set msr_ee to 1
6133 */
6134 gen_stop_exception(ctx);
6135 #endif /* defined(CONFIG_USER_ONLY) */
6136 }
6137
6138 /* wrteei */
6139 static void gen_wrteei(DisasContext *ctx)
6140 {
6141 #if defined(CONFIG_USER_ONLY)
6142 GEN_PRIV;
6143 #else
6144 CHK_SV;
6145 if (ctx->opcode & 0x00008000) {
6146 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6147 /* Stop translation to have a chance to raise an exception */
6148 gen_stop_exception(ctx);
6149 } else {
6150 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6151 }
6152 #endif /* defined(CONFIG_USER_ONLY) */
6153 }
6154
6155 /* PowerPC 440 specific instructions */
6156
6157 /* dlmzb */
6158 static void gen_dlmzb(DisasContext *ctx)
6159 {
6160 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6161 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6162 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6163 tcg_temp_free_i32(t0);
6164 }
6165
6166 /* mbar replaces eieio on 440 */
6167 static void gen_mbar(DisasContext *ctx)
6168 {
6169 /* interpreted as no-op */
6170 }
6171
6172 /* msync replaces sync on 440 */
6173 static void gen_msync_4xx(DisasContext *ctx)
6174 {
6175 /* interpreted as no-op */
6176 }
6177
6178 /* icbt */
6179 static void gen_icbt_440(DisasContext *ctx)
6180 {
6181 /* interpreted as no-op */
6182 /* XXX: specification say this is treated as a load by the MMU
6183 * but does not generate any exception
6184 */
6185 }
6186
6187 /* Embedded.Processor Control */
6188
6189 static void gen_msgclr(DisasContext *ctx)
6190 {
6191 #if defined(CONFIG_USER_ONLY)
6192 GEN_PRIV;
6193 #else
6194 CHK_SV;
6195 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6196 #endif /* defined(CONFIG_USER_ONLY) */
6197 }
6198
6199 static void gen_msgsnd(DisasContext *ctx)
6200 {
6201 #if defined(CONFIG_USER_ONLY)
6202 GEN_PRIV;
6203 #else
6204 CHK_SV;
6205 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6206 #endif /* defined(CONFIG_USER_ONLY) */
6207 }
6208
6209
6210 #if defined(TARGET_PPC64)
6211 static void gen_maddld(DisasContext *ctx)
6212 {
6213 TCGv_i64 t1 = tcg_temp_new_i64();
6214
6215 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6216 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6217 tcg_temp_free_i64(t1);
6218 }
6219
6220 /* maddhd maddhdu */
6221 static void gen_maddhd_maddhdu(DisasContext *ctx)
6222 {
6223 TCGv_i64 lo = tcg_temp_new_i64();
6224 TCGv_i64 hi = tcg_temp_new_i64();
6225 TCGv_i64 t1 = tcg_temp_new_i64();
6226
6227 if (Rc(ctx->opcode)) {
6228 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6229 cpu_gpr[rB(ctx->opcode)]);
6230 tcg_gen_movi_i64(t1, 0);
6231 } else {
6232 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6233 cpu_gpr[rB(ctx->opcode)]);
6234 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6235 }
6236 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6237 cpu_gpr[rC(ctx->opcode)], t1);
6238 tcg_temp_free_i64(lo);
6239 tcg_temp_free_i64(hi);
6240 tcg_temp_free_i64(t1);
6241 }
6242 #endif /* defined(TARGET_PPC64) */
6243
6244 static void gen_tbegin(DisasContext *ctx)
6245 {
6246 if (unlikely(!ctx->tm_enabled)) {
6247 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6248 return;
6249 }
6250 gen_helper_tbegin(cpu_env);
6251 }
6252
6253 #define GEN_TM_NOOP(name) \
6254 static inline void gen_##name(DisasContext *ctx) \
6255 { \
6256 if (unlikely(!ctx->tm_enabled)) { \
6257 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6258 return; \
6259 } \
6260 /* Because tbegin always fails in QEMU, these user \
6261 * space instructions all have a simple implementation: \
6262 * \
6263 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6264 * = 0b0 || 0b00 || 0b0 \
6265 */ \
6266 tcg_gen_movi_i32(cpu_crf[0], 0); \
6267 }
6268
6269 GEN_TM_NOOP(tend);
6270 GEN_TM_NOOP(tabort);
6271 GEN_TM_NOOP(tabortwc);
6272 GEN_TM_NOOP(tabortwci);
6273 GEN_TM_NOOP(tabortdc);
6274 GEN_TM_NOOP(tabortdci);
6275 GEN_TM_NOOP(tsr);
6276 static inline void gen_cp_abort(DisasContext *ctx)
6277 {
6278 // Do Nothing
6279 }
6280
6281 #define GEN_CP_PASTE_NOOP(name) \
6282 static inline void gen_##name(DisasContext *ctx) \
6283 { \
6284 /* Generate invalid exception until \
6285 * we have an implementation of the copy \
6286 * paste facility \
6287 */ \
6288 gen_invalid(ctx); \
6289 }
6290
6291 GEN_CP_PASTE_NOOP(copy)
6292 GEN_CP_PASTE_NOOP(paste)
6293
6294 static void gen_tcheck(DisasContext *ctx)
6295 {
6296 if (unlikely(!ctx->tm_enabled)) {
6297 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6298 return;
6299 }
6300 /* Because tbegin always fails, the tcheck implementation
6301 * is simple:
6302 *
6303 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6304 * = 0b1 || 0b00 || 0b0
6305 */
6306 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6307 }
6308
6309 #if defined(CONFIG_USER_ONLY)
6310 #define GEN_TM_PRIV_NOOP(name) \
6311 static inline void gen_##name(DisasContext *ctx) \
6312 { \
6313 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6314 }
6315
6316 #else
6317
6318 #define GEN_TM_PRIV_NOOP(name) \
6319 static inline void gen_##name(DisasContext *ctx) \
6320 { \
6321 CHK_SV; \
6322 if (unlikely(!ctx->tm_enabled)) { \
6323 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6324 return; \
6325 } \
6326 /* Because tbegin always fails, the implementation is \
6327 * simple: \
6328 * \
6329 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6330 * = 0b0 || 0b00 | 0b0 \
6331 */ \
6332 tcg_gen_movi_i32(cpu_crf[0], 0); \
6333 }
6334
6335 #endif
6336
6337 GEN_TM_PRIV_NOOP(treclaim);
6338 GEN_TM_PRIV_NOOP(trechkpt);
6339
6340 #include "translate/fp-impl.inc.c"
6341
6342 #include "translate/vmx-impl.inc.c"
6343
6344 #include "translate/vsx-impl.inc.c"
6345
6346 #include "translate/dfp-impl.inc.c"
6347
6348 #include "translate/spe-impl.inc.c"
6349
6350 /* Handles lfdp, lxsd, lxssp */
6351 static void gen_dform39(DisasContext *ctx)
6352 {
6353 switch (ctx->opcode & 0x3) {
6354 case 0: /* lfdp */
6355 if (ctx->insns_flags2 & PPC2_ISA205) {
6356 return gen_lfdp(ctx);
6357 }
6358 break;
6359 case 2: /* lxsd */
6360 if (ctx->insns_flags2 & PPC2_ISA300) {
6361 return gen_lxsd(ctx);
6362 }
6363 break;
6364 case 3: /* lxssp */
6365 if (ctx->insns_flags2 & PPC2_ISA300) {
6366 return gen_lxssp(ctx);
6367 }
6368 break;
6369 }
6370 return gen_invalid(ctx);
6371 }
6372
6373 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6374 static void gen_dform3D(DisasContext *ctx)
6375 {
6376 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6377 switch (ctx->opcode & 0x7) {
6378 case 1: /* lxv */
6379 if (ctx->insns_flags2 & PPC2_ISA300) {
6380 return gen_lxv(ctx);
6381 }
6382 break;
6383 case 5: /* stxv */
6384 if (ctx->insns_flags2 & PPC2_ISA300) {
6385 return gen_stxv(ctx);
6386 }
6387 break;
6388 }
6389 } else { /* DS-FORM */
6390 switch (ctx->opcode & 0x3) {
6391 case 0: /* stfdp */
6392 if (ctx->insns_flags2 & PPC2_ISA205) {
6393 return gen_stfdp(ctx);
6394 }
6395 break;
6396 case 2: /* stxsd */
6397 if (ctx->insns_flags2 & PPC2_ISA300) {
6398 return gen_stxsd(ctx);
6399 }
6400 break;
6401 case 3: /* stxssp */
6402 if (ctx->insns_flags2 & PPC2_ISA300) {
6403 return gen_stxssp(ctx);
6404 }
6405 break;
6406 }
6407 }
6408 return gen_invalid(ctx);
6409 }
6410
6411 static opcode_t opcodes[] = {
6412 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6413 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6414 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6415 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6416 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6417 #if defined(TARGET_PPC64)
6418 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6419 #endif
6420 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6421 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6422 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6423 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6424 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6425 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6426 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6427 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6428 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6429 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6430 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6431 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6432 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6433 #if defined(TARGET_PPC64)
6434 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6435 #endif
6436 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6437 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6438 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6439 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6440 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6441 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6442 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6443 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6444 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6445 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6446 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6447 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6448 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6449 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6450 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6451 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6452 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6453 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6454 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6455 #if defined(TARGET_PPC64)
6456 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6457 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6458 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6459 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6460 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6461 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6462 #endif
6463 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6464 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6465 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6466 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6467 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6468 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6469 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6470 #if defined(TARGET_PPC64)
6471 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6472 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6473 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6474 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6475 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6476 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6477 PPC_NONE, PPC2_ISA300),
6478 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6479 PPC_NONE, PPC2_ISA300),
6480 #endif
6481 #if defined(TARGET_PPC64)
6482 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6483 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6484 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6485 #endif
6486 /* handles lfdp, lxsd, lxssp */
6487 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6488 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6489 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6490 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6491 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6492 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6493 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6494 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6495 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6496 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6497 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6498 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6499 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6500 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6501 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6502 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6503 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6504 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6505 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6506 #if defined(TARGET_PPC64)
6507 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6508 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6509 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6510 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6511 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6512 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6513 #endif
6514 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6515 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6516 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6517 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6518 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6519 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6520 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6521 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6522 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6523 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6524 #if defined(TARGET_PPC64)
6525 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6526 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6527 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6528 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6529 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6530 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6531 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6532 #endif
6533 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6534 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6535 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6536 #if defined(TARGET_PPC64)
6537 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6538 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6539 #endif
6540 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6541 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6542 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6543 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6544 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6545 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6546 #if defined(TARGET_PPC64)
6547 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6548 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6549 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6550 #endif
6551 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6552 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6553 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6554 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6555 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6556 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6557 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6558 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6559 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6560 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6561 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6562 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6563 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6564 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6565 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6566 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6567 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6568 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6569 #if defined(TARGET_PPC64)
6570 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6571 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6572 PPC_SEGMENT_64B),
6573 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6574 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6575 PPC_SEGMENT_64B),
6576 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6577 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6578 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6579 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6580 #endif
6581 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6582 /* XXX Those instructions will need to be handled differently for
6583 * different ISA versions */
6584 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6585 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6586 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6587 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6588 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6589 #if defined(TARGET_PPC64)
6590 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6591 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6592 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6593 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6594 #endif
6595 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6596 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6597 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6598 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6599 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6600 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6601 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6602 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6603 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6604 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6605 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6606 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6607 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6608 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6609 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6610 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6611 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6612 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6613 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6614 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6615 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6616 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6617 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6618 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6619 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6620 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6621 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6622 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6623 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6624 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6625 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6626 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6627 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6628 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6629 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6630 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6631 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6632 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6633 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6634 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6635 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6636 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6637 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6638 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6639 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6640 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6641 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6642 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6643 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6644 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6645 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6646 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6647 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6648 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6649 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6650 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6651 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6652 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6653 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6654 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6655 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6656 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6657 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6658 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6659 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6660 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6661 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6662 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6663 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6664 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6665 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6666 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6667 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6668 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6669 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6670 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6671 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6672 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6673 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6674 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6675 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6676 PPC_NONE, PPC2_BOOKE206),
6677 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6678 PPC_NONE, PPC2_BOOKE206),
6679 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6680 PPC_NONE, PPC2_BOOKE206),
6681 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6682 PPC_NONE, PPC2_BOOKE206),
6683 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6684 PPC_NONE, PPC2_BOOKE206),
6685 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6686 PPC_NONE, PPC2_PRCNTL),
6687 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6688 PPC_NONE, PPC2_PRCNTL),
6689 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6690 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6691 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6692 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6693 PPC_BOOKE, PPC2_BOOKE206),
6694 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6695 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6696 PPC_BOOKE, PPC2_BOOKE206),
6697 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6698 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6699 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6700 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6701 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6702 #if defined(TARGET_PPC64)
6703 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6704 PPC2_ISA300),
6705 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6706 #endif
6707
6708 #undef GEN_INT_ARITH_ADD
6709 #undef GEN_INT_ARITH_ADD_CONST
6710 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6711 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6712 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6713 add_ca, compute_ca, compute_ov) \
6714 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6715 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6716 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6717 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6718 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6719 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6720 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6721 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6722 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6723 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6724 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6725
6726 #undef GEN_INT_ARITH_DIVW
6727 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6728 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6729 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6730 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6731 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6732 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6733 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6734 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6735 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6736 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6737 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6738 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6739
6740 #if defined(TARGET_PPC64)
6741 #undef GEN_INT_ARITH_DIVD
6742 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6743 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6744 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6745 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6746 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6747 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6748
6749 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6750 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6751 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6752 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6753 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6754 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6755
6756 #undef GEN_INT_ARITH_MUL_HELPER
6757 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6758 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6759 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6760 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6761 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6762 #endif
6763
6764 #undef GEN_INT_ARITH_SUBF
6765 #undef GEN_INT_ARITH_SUBF_CONST
6766 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6767 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6768 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6769 add_ca, compute_ca, compute_ov) \
6770 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6771 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6772 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6773 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6774 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6775 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6776 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6777 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6778 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6779 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6780 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6781
6782 #undef GEN_LOGICAL1
6783 #undef GEN_LOGICAL2
6784 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6785 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6786 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6787 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6788 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6789 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6790 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6791 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6792 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6793 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6794 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6795 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6796 #if defined(TARGET_PPC64)
6797 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6798 #endif
6799
6800 #if defined(TARGET_PPC64)
6801 #undef GEN_PPC64_R2
6802 #undef GEN_PPC64_R4
6803 #define GEN_PPC64_R2(name, opc1, opc2) \
6804 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6805 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6806 PPC_64B)
6807 #define GEN_PPC64_R4(name, opc1, opc2) \
6808 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6809 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6810 PPC_64B), \
6811 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6812 PPC_64B), \
6813 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6814 PPC_64B)
6815 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6816 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6817 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6818 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6819 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6820 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6821 #endif
6822
6823 #undef GEN_LD
6824 #undef GEN_LDU
6825 #undef GEN_LDUX
6826 #undef GEN_LDX_E
6827 #undef GEN_LDS
6828 #define GEN_LD(name, ldop, opc, type) \
6829 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6830 #define GEN_LDU(name, ldop, opc, type) \
6831 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6832 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6833 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6834 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6835 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6836 #define GEN_LDS(name, ldop, op, type) \
6837 GEN_LD(name, ldop, op | 0x20, type) \
6838 GEN_LDU(name, ldop, op | 0x21, type) \
6839 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6840 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6841
6842 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6843 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6844 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6845 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6846 #if defined(TARGET_PPC64)
6847 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6848 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6849 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6850 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6851 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6852
6853 /* HV/P7 and later only */
6854 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6855 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6856 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6857 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6858 #endif
6859 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6860 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6861
6862 #undef GEN_ST
6863 #undef GEN_STU
6864 #undef GEN_STUX
6865 #undef GEN_STX_E
6866 #undef GEN_STS
6867 #define GEN_ST(name, stop, opc, type) \
6868 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6869 #define GEN_STU(name, stop, opc, type) \
6870 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6871 #define GEN_STUX(name, stop, opc2, opc3, type) \
6872 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6873 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6874 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6875 #define GEN_STS(name, stop, op, type) \
6876 GEN_ST(name, stop, op | 0x20, type) \
6877 GEN_STU(name, stop, op | 0x21, type) \
6878 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6879 GEN_STX(name, stop, 0x17, op | 0x00, type)
6880
6881 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6882 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6883 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6884 #if defined(TARGET_PPC64)
6885 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6886 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6887 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6888 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6889 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6890 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6891 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6892 #endif
6893 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6894 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6895
6896 #undef GEN_CRLOGIC
6897 #define GEN_CRLOGIC(name, tcg_op, opc) \
6898 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6899 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6900 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6901 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6902 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6903 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6904 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6905 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6906 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6907
6908 #undef GEN_MAC_HANDLER
6909 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6910 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6911 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6912 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6913 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6914 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6915 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6916 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6917 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6918 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6919 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6920 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6921 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6922 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6923 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6924 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6925 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6926 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6927 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6928 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6929 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6930 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6931 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6932 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6933 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6934 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6935 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6936 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6937 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6938 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6939 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6940 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6941 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6942 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6943 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6944 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6945 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6946 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6947 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6948 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6949 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6950 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6951 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6952 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6953
6954 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6955 PPC_NONE, PPC2_TM),
6956 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6957 PPC_NONE, PPC2_TM),
6958 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6959 PPC_NONE, PPC2_TM),
6960 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6961 PPC_NONE, PPC2_TM),
6962 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6963 PPC_NONE, PPC2_TM),
6964 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6965 PPC_NONE, PPC2_TM),
6966 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6967 PPC_NONE, PPC2_TM),
6968 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6969 PPC_NONE, PPC2_TM),
6970 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6971 PPC_NONE, PPC2_TM),
6972 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6973 PPC_NONE, PPC2_TM),
6974 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6975 PPC_NONE, PPC2_TM),
6976
6977 #include "translate/fp-ops.inc.c"
6978
6979 #include "translate/vmx-ops.inc.c"
6980
6981 #include "translate/vsx-ops.inc.c"
6982
6983 #include "translate/dfp-ops.inc.c"
6984
6985 #include "translate/spe-ops.inc.c"
6986 };
6987
6988 #include "helper_regs.h"
6989 #include "translate_init.c"
6990
6991 /*****************************************************************************/
6992 /* Misc PowerPC helpers */
6993 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6994 int flags)
6995 {
6996 #define RGPL 4
6997 #define RFPL 4
6998
6999 PowerPCCPU *cpu = POWERPC_CPU(cs);
7000 CPUPPCState *env = &cpu->env;
7001 int i;
7002
7003 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7004 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7005 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7006 cs->cpu_index);
7007 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7008 TARGET_FMT_lx " iidx %d didx %d\n",
7009 env->msr, env->spr[SPR_HID0],
7010 env->hflags, env->immu_idx, env->dmmu_idx);
7011 #if !defined(NO_TIMER_DUMP)
7012 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7013 #if !defined(CONFIG_USER_ONLY)
7014 " DECR %08" PRIu32
7015 #endif
7016 "\n",
7017 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7018 #if !defined(CONFIG_USER_ONLY)
7019 , cpu_ppc_load_decr(env)
7020 #endif
7021 );
7022 #endif
7023 for (i = 0; i < 32; i++) {
7024 if ((i & (RGPL - 1)) == 0)
7025 cpu_fprintf(f, "GPR%02d", i);
7026 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7027 if ((i & (RGPL - 1)) == (RGPL - 1))
7028 cpu_fprintf(f, "\n");
7029 }
7030 cpu_fprintf(f, "CR ");
7031 for (i = 0; i < 8; i++)
7032 cpu_fprintf(f, "%01x", env->crf[i]);
7033 cpu_fprintf(f, " [");
7034 for (i = 0; i < 8; i++) {
7035 char a = '-';
7036 if (env->crf[i] & 0x08)
7037 a = 'L';
7038 else if (env->crf[i] & 0x04)
7039 a = 'G';
7040 else if (env->crf[i] & 0x02)
7041 a = 'E';
7042 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7043 }
7044 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7045 env->reserve_addr);
7046 for (i = 0; i < 32; i++) {
7047 if ((i & (RFPL - 1)) == 0)
7048 cpu_fprintf(f, "FPR%02d", i);
7049 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7050 if ((i & (RFPL - 1)) == (RFPL - 1))
7051 cpu_fprintf(f, "\n");
7052 }
7053 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7054 #if !defined(CONFIG_USER_ONLY)
7055 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7056 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7057 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7058 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7059
7060 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7061 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7062 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7063 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7064
7065 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7066 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7067 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7068 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7069
7070 #if defined(TARGET_PPC64)
7071 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7072 env->excp_model == POWERPC_EXCP_POWER8) {
7073 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7074 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7075 }
7076 #endif
7077 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7078 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7079 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7080 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7081 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7082
7083 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7084 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7085 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7086 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7087
7088 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7089 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7090 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7091 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7092
7093 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7094 " EPR " TARGET_FMT_lx "\n",
7095 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7096 env->spr[SPR_BOOKE_EPR]);
7097
7098 /* FSL-specific */
7099 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7100 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7101 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7102 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7103
7104 /*
7105 * IVORs are left out as they are large and do not change often --
7106 * they can be read with "p $ivor0", "p $ivor1", etc.
7107 */
7108 }
7109
7110 #if defined(TARGET_PPC64)
7111 if (env->flags & POWERPC_FLAG_CFAR) {
7112 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7113 }
7114 #endif
7115
7116 if (env->spr_cb[SPR_LPCR].name)
7117 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7118
7119 switch (POWERPC_MMU_VER(env->mmu_model)) {
7120 case POWERPC_MMU_32B:
7121 case POWERPC_MMU_601:
7122 case POWERPC_MMU_SOFT_6xx:
7123 case POWERPC_MMU_SOFT_74xx:
7124 #if defined(TARGET_PPC64)
7125 case POWERPC_MMU_VER_64B:
7126 case POWERPC_MMU_VER_2_03:
7127 case POWERPC_MMU_VER_2_06:
7128 case POWERPC_MMU_VER_2_07:
7129 case POWERPC_MMU_VER_3_00:
7130 #endif
7131 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7132 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7133 }
7134 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7135 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7136 break;
7137 case POWERPC_MMU_BOOKE206:
7138 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7139 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7140 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7141 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7142
7143 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7144 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7145 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7146 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7147
7148 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7149 " TLB1CFG " TARGET_FMT_lx "\n",
7150 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7151 env->spr[SPR_BOOKE_TLB1CFG]);
7152 break;
7153 default:
7154 break;
7155 }
7156 #endif
7157
7158 #undef RGPL
7159 #undef RFPL
7160 }
7161
7162 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7163 fprintf_function cpu_fprintf, int flags)
7164 {
7165 #if defined(DO_PPC_STATISTICS)
7166 PowerPCCPU *cpu = POWERPC_CPU(cs);
7167 opc_handler_t **t1, **t2, **t3, *handler;
7168 int op1, op2, op3;
7169
7170 t1 = cpu->env.opcodes;
7171 for (op1 = 0; op1 < 64; op1++) {
7172 handler = t1[op1];
7173 if (is_indirect_opcode(handler)) {
7174 t2 = ind_table(handler);
7175 for (op2 = 0; op2 < 32; op2++) {
7176 handler = t2[op2];
7177 if (is_indirect_opcode(handler)) {
7178 t3 = ind_table(handler);
7179 for (op3 = 0; op3 < 32; op3++) {
7180 handler = t3[op3];
7181 if (handler->count == 0)
7182 continue;
7183 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7184 "%016" PRIx64 " %" PRId64 "\n",
7185 op1, op2, op3, op1, (op3 << 5) | op2,
7186 handler->oname,
7187 handler->count, handler->count);
7188 }
7189 } else {
7190 if (handler->count == 0)
7191 continue;
7192 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7193 "%016" PRIx64 " %" PRId64 "\n",
7194 op1, op2, op1, op2, handler->oname,
7195 handler->count, handler->count);
7196 }
7197 }
7198 } else {
7199 if (handler->count == 0)
7200 continue;
7201 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7202 " %" PRId64 "\n",
7203 op1, op1, handler->oname,
7204 handler->count, handler->count);
7205 }
7206 }
7207 #endif
7208 }
7209
7210 /*****************************************************************************/
7211 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
7212 {
7213 CPUPPCState *env = cs->env_ptr;
7214 DisasContext ctx, *ctxp = &ctx;
7215 opc_handler_t **table, *handler;
7216 target_ulong pc_start;
7217 int num_insns;
7218 int max_insns;
7219
7220 pc_start = tb->pc;
7221 ctx.nip = pc_start;
7222 ctx.tb = tb;
7223 ctx.exception = POWERPC_EXCP_NONE;
7224 ctx.spr_cb = env->spr_cb;
7225 ctx.pr = msr_pr;
7226 ctx.mem_idx = env->dmmu_idx;
7227 ctx.dr = msr_dr;
7228 #if !defined(CONFIG_USER_ONLY)
7229 ctx.hv = msr_hv || !env->has_hv_mode;
7230 #endif
7231 ctx.insns_flags = env->insns_flags;
7232 ctx.insns_flags2 = env->insns_flags2;
7233 ctx.access_type = -1;
7234 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7235 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7236 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7237 #if defined(TARGET_PPC64)
7238 ctx.sf_mode = msr_is_64bit(env, env->msr);
7239 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7240 #endif
7241 if (env->mmu_model == POWERPC_MMU_32B ||
7242 env->mmu_model == POWERPC_MMU_601 ||
7243 (env->mmu_model & POWERPC_MMU_64B))
7244 ctx.lazy_tlb_flush = true;
7245
7246 ctx.fpu_enabled = !!msr_fp;
7247 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7248 ctx.spe_enabled = !!msr_spe;
7249 else
7250 ctx.spe_enabled = false;
7251 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7252 ctx.altivec_enabled = !!msr_vr;
7253 else
7254 ctx.altivec_enabled = false;
7255 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7256 ctx.vsx_enabled = !!msr_vsx;
7257 } else {
7258 ctx.vsx_enabled = false;
7259 }
7260 #if defined(TARGET_PPC64)
7261 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7262 ctx.tm_enabled = !!msr_tm;
7263 } else {
7264 ctx.tm_enabled = false;
7265 }
7266 #endif
7267 ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7268 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7269 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7270 else
7271 ctx.singlestep_enabled = 0;
7272 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7273 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7274 if (unlikely(cs->singlestep_enabled)) {
7275 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7276 }
7277 #if defined (DO_SINGLE_STEP) && 0
7278 /* Single step trace mode */
7279 msr_se = 1;
7280 #endif
7281 num_insns = 0;
7282 max_insns = tb->cflags & CF_COUNT_MASK;
7283 if (max_insns == 0) {
7284 max_insns = CF_COUNT_MASK;
7285 }
7286 if (max_insns > TCG_MAX_INSNS) {
7287 max_insns = TCG_MAX_INSNS;
7288 }
7289
7290 gen_tb_start(tb);
7291 tcg_clear_temp_count();
7292 /* Set env in case of segfault during code fetch */
7293 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7294 tcg_gen_insn_start(ctx.nip);
7295 num_insns++;
7296
7297 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7298 gen_debug_exception(ctxp);
7299 /* The address covered by the breakpoint must be included in
7300 [tb->pc, tb->pc + tb->size) in order to for it to be
7301 properly cleared -- thus we increment the PC here so that
7302 the logic setting tb->size below does the right thing. */
7303 ctx.nip += 4;
7304 break;
7305 }
7306
7307 LOG_DISAS("----------------\n");
7308 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7309 ctx.nip, ctx.mem_idx, (int)msr_ir);
7310 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7311 gen_io_start();
7312 if (unlikely(need_byteswap(&ctx))) {
7313 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7314 } else {
7315 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7316 }
7317 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7318 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7319 opc3(ctx.opcode), opc4(ctx.opcode),
7320 ctx.le_mode ? "little" : "big");
7321 ctx.nip += 4;
7322 table = env->opcodes;
7323 handler = table[opc1(ctx.opcode)];
7324 if (is_indirect_opcode(handler)) {
7325 table = ind_table(handler);
7326 handler = table[opc2(ctx.opcode)];
7327 if (is_indirect_opcode(handler)) {
7328 table = ind_table(handler);
7329 handler = table[opc3(ctx.opcode)];
7330 if (is_indirect_opcode(handler)) {
7331 table = ind_table(handler);
7332 handler = table[opc4(ctx.opcode)];
7333 }
7334 }
7335 }
7336 /* Is opcode *REALLY* valid ? */
7337 if (unlikely(handler->handler == &gen_invalid)) {
7338 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7339 "%02x - %02x - %02x - %02x (%08x) "
7340 TARGET_FMT_lx " %d\n",
7341 opc1(ctx.opcode), opc2(ctx.opcode),
7342 opc3(ctx.opcode), opc4(ctx.opcode),
7343 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7344 } else {
7345 uint32_t inval;
7346
7347 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7348 inval = handler->inval2;
7349 } else {
7350 inval = handler->inval1;
7351 }
7352
7353 if (unlikely((ctx.opcode & inval) != 0)) {
7354 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7355 "%02x - %02x - %02x - %02x (%08x) "
7356 TARGET_FMT_lx "\n", ctx.opcode & inval,
7357 opc1(ctx.opcode), opc2(ctx.opcode),
7358 opc3(ctx.opcode), opc4(ctx.opcode),
7359 ctx.opcode, ctx.nip - 4);
7360 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7361 break;
7362 }
7363 }
7364 (*(handler->handler))(&ctx);
7365 #if defined(DO_PPC_STATISTICS)
7366 handler->count++;
7367 #endif
7368 /* Check trace mode exceptions */
7369 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7370 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7371 ctx.exception != POWERPC_SYSCALL &&
7372 ctx.exception != POWERPC_EXCP_TRAP &&
7373 ctx.exception != POWERPC_EXCP_BRANCH)) {
7374 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7375 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7376 (cs->singlestep_enabled) ||
7377 singlestep ||
7378 num_insns >= max_insns)) {
7379 /* if we reach a page boundary or are single stepping, stop
7380 * generation
7381 */
7382 break;
7383 }
7384 if (tcg_check_temp_count()) {
7385 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7386 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7387 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7388 exit(1);
7389 }
7390 }
7391 if (tb->cflags & CF_LAST_IO)
7392 gen_io_end();
7393 if (ctx.exception == POWERPC_EXCP_NONE) {
7394 gen_goto_tb(&ctx, 0, ctx.nip);
7395 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7396 if (unlikely(cs->singlestep_enabled)) {
7397 gen_debug_exception(ctxp);
7398 }
7399 /* Generate the return instruction */
7400 tcg_gen_exit_tb(0);
7401 }
7402 gen_tb_end(tb, num_insns);
7403
7404 tb->size = ctx.nip - pc_start;
7405 tb->icount = num_insns;
7406
7407 #if defined(DEBUG_DISAS)
7408 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7409 && qemu_log_in_addr_range(pc_start)) {
7410 int flags;
7411 flags = env->bfd_mach;
7412 flags |= ctx.le_mode << 16;
7413 qemu_log_lock();
7414 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7415 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7416 qemu_log("\n");
7417 qemu_log_unlock();
7418 }
7419 #endif
7420 }
7421
7422 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7423 target_ulong *data)
7424 {
7425 env->nip = data[0];
7426 }
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