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target/ppc: Add cia field to DisasContext
[mirror_qemu.git] / target / ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
31
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34
35 #include "trace-tcg.h"
36 #include "exec/translator.h"
37 #include "exec/log.h"
38 #include "qemu/atomic128.h"
39 #include "spr_tcg.h"
40
41 #include "qemu/qemu-print.h"
42 #include "qapi/error.h"
43
44 #define CPU_SINGLE_STEP 0x1
45 #define CPU_BRANCH_STEP 0x2
46 #define GDBSTUB_SINGLE_STEP 0x4
47
48 /* Include definitions for instructions classes and implementations flags */
49 /* #define PPC_DEBUG_DISAS */
50 /* #define DO_PPC_STATISTICS */
51
52 #ifdef PPC_DEBUG_DISAS
53 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
54 #else
55 # define LOG_DISAS(...) do { } while (0)
56 #endif
57 /*****************************************************************************/
58 /* Code translation helpers */
59
60 /* global register indexes */
61 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
62 + 10 * 4 + 22 * 5 /* SPE GPRh */
63 + 8 * 5 /* CRF */];
64 static TCGv cpu_gpr[32];
65 static TCGv cpu_gprh[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char *p;
86 size_t cpu_reg_names_size;
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 snprintf(p, cpu_reg_names_size, "r%dH", i);
106 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gprh[i]), p);
108 p += (i < 10) ? 4 : 5;
109 cpu_reg_names_size -= (i < 10) ? 4 : 5;
110 }
111
112 cpu_nip = tcg_global_mem_new(cpu_env,
113 offsetof(CPUPPCState, nip), "nip");
114
115 cpu_msr = tcg_global_mem_new(cpu_env,
116 offsetof(CPUPPCState, msr), "msr");
117
118 cpu_ctr = tcg_global_mem_new(cpu_env,
119 offsetof(CPUPPCState, ctr), "ctr");
120
121 cpu_lr = tcg_global_mem_new(cpu_env,
122 offsetof(CPUPPCState, lr), "lr");
123
124 #if defined(TARGET_PPC64)
125 cpu_cfar = tcg_global_mem_new(cpu_env,
126 offsetof(CPUPPCState, cfar), "cfar");
127 #endif
128
129 cpu_xer = tcg_global_mem_new(cpu_env,
130 offsetof(CPUPPCState, xer), "xer");
131 cpu_so = tcg_global_mem_new(cpu_env,
132 offsetof(CPUPPCState, so), "SO");
133 cpu_ov = tcg_global_mem_new(cpu_env,
134 offsetof(CPUPPCState, ov), "OV");
135 cpu_ca = tcg_global_mem_new(cpu_env,
136 offsetof(CPUPPCState, ca), "CA");
137 cpu_ov32 = tcg_global_mem_new(cpu_env,
138 offsetof(CPUPPCState, ov32), "OV32");
139 cpu_ca32 = tcg_global_mem_new(cpu_env,
140 offsetof(CPUPPCState, ca32), "CA32");
141
142 cpu_reserve = tcg_global_mem_new(cpu_env,
143 offsetof(CPUPPCState, reserve_addr),
144 "reserve_addr");
145 cpu_reserve_val = tcg_global_mem_new(cpu_env,
146 offsetof(CPUPPCState, reserve_val),
147 "reserve_val");
148
149 cpu_fpscr = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, fpscr), "fpscr");
151
152 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
153 offsetof(CPUPPCState, access_type),
154 "access_type");
155 }
156
157 /* internal defines */
158 struct DisasContext {
159 DisasContextBase base;
160 target_ulong cia; /* current instruction address */
161 uint32_t opcode;
162 uint32_t exception;
163 /* Routine used to access memory */
164 bool pr, hv, dr, le_mode;
165 bool lazy_tlb_flush;
166 bool need_access_type;
167 int mem_idx;
168 int access_type;
169 /* Translation flags */
170 MemOp default_tcg_memop_mask;
171 #if defined(TARGET_PPC64)
172 bool sf_mode;
173 bool has_cfar;
174 #endif
175 bool fpu_enabled;
176 bool altivec_enabled;
177 bool vsx_enabled;
178 bool spe_enabled;
179 bool tm_enabled;
180 bool gtse;
181 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
182 int singlestep_enabled;
183 uint32_t flags;
184 uint64_t insns_flags;
185 uint64_t insns_flags2;
186 };
187
188 /* Return true iff byteswap is needed in a scalar memop */
189 static inline bool need_byteswap(const DisasContext *ctx)
190 {
191 #if defined(TARGET_WORDS_BIGENDIAN)
192 return ctx->le_mode;
193 #else
194 return !ctx->le_mode;
195 #endif
196 }
197
198 /* True when active word size < size of target_long. */
199 #ifdef TARGET_PPC64
200 # define NARROW_MODE(C) (!(C)->sf_mode)
201 #else
202 # define NARROW_MODE(C) 0
203 #endif
204
205 struct opc_handler_t {
206 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
207 uint32_t inval1;
208 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
209 uint32_t inval2;
210 /* instruction type */
211 uint64_t type;
212 /* extended instruction type */
213 uint64_t type2;
214 /* handler */
215 void (*handler)(DisasContext *ctx);
216 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
217 const char *oname;
218 #endif
219 #if defined(DO_PPC_STATISTICS)
220 uint64_t count;
221 #endif
222 };
223
224 /* SPR load/store helpers */
225 static inline void gen_load_spr(TCGv t, int reg)
226 {
227 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
228 }
229
230 static inline void gen_store_spr(int reg, TCGv t)
231 {
232 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
233 }
234
235 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
236 {
237 if (ctx->need_access_type && ctx->access_type != access_type) {
238 tcg_gen_movi_i32(cpu_access_type, access_type);
239 ctx->access_type = access_type;
240 }
241 }
242
243 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
244 {
245 if (NARROW_MODE(ctx)) {
246 nip = (uint32_t)nip;
247 }
248 tcg_gen_movi_tl(cpu_nip, nip);
249 }
250
251 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
252 {
253 TCGv_i32 t0, t1;
254
255 /*
256 * These are all synchronous exceptions, we set the PC back to the
257 * faulting instruction
258 */
259 if (ctx->exception == POWERPC_EXCP_NONE) {
260 gen_update_nip(ctx, ctx->cia);
261 }
262 t0 = tcg_const_i32(excp);
263 t1 = tcg_const_i32(error);
264 gen_helper_raise_exception_err(cpu_env, t0, t1);
265 tcg_temp_free_i32(t0);
266 tcg_temp_free_i32(t1);
267 ctx->exception = (excp);
268 }
269
270 static void gen_exception(DisasContext *ctx, uint32_t excp)
271 {
272 TCGv_i32 t0;
273
274 /*
275 * These are all synchronous exceptions, we set the PC back to the
276 * faulting instruction
277 */
278 if (ctx->exception == POWERPC_EXCP_NONE) {
279 gen_update_nip(ctx, ctx->cia);
280 }
281 t0 = tcg_const_i32(excp);
282 gen_helper_raise_exception(cpu_env, t0);
283 tcg_temp_free_i32(t0);
284 ctx->exception = (excp);
285 }
286
287 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
288 target_ulong nip)
289 {
290 TCGv_i32 t0;
291
292 gen_update_nip(ctx, nip);
293 t0 = tcg_const_i32(excp);
294 gen_helper_raise_exception(cpu_env, t0);
295 tcg_temp_free_i32(t0);
296 ctx->exception = (excp);
297 }
298
299 /*
300 * Tells the caller what is the appropriate exception to generate and prepares
301 * SPR registers for this exception.
302 *
303 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
304 * POWERPC_EXCP_DEBUG (on BookE).
305 */
306 static uint32_t gen_prep_dbgex(DisasContext *ctx)
307 {
308 if (ctx->flags & POWERPC_FLAG_DE) {
309 target_ulong dbsr = 0;
310 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
311 dbsr = DBCR0_ICMP;
312 } else {
313 /* Must have been branch */
314 dbsr = DBCR0_BRT;
315 }
316 TCGv t0 = tcg_temp_new();
317 gen_load_spr(t0, SPR_BOOKE_DBSR);
318 tcg_gen_ori_tl(t0, t0, dbsr);
319 gen_store_spr(SPR_BOOKE_DBSR, t0);
320 tcg_temp_free(t0);
321 return POWERPC_EXCP_DEBUG;
322 } else {
323 return POWERPC_EXCP_TRACE;
324 }
325 }
326
327 static void gen_debug_exception(DisasContext *ctx)
328 {
329 TCGv_i32 t0;
330
331 /*
332 * These are all synchronous exceptions, we set the PC back to the
333 * faulting instruction
334 */
335 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
336 (ctx->exception != POWERPC_EXCP_SYNC)) {
337 gen_update_nip(ctx, ctx->base.pc_next);
338 }
339 t0 = tcg_const_i32(EXCP_DEBUG);
340 gen_helper_raise_exception(cpu_env, t0);
341 tcg_temp_free_i32(t0);
342 }
343
344 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
345 {
346 /* Will be converted to program check if needed */
347 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
348 }
349
350 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
351 {
352 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
353 }
354
355 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
356 {
357 /* Will be converted to program check if needed */
358 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
359 }
360
361 /* Stop translation */
362 static inline void gen_stop_exception(DisasContext *ctx)
363 {
364 gen_update_nip(ctx, ctx->base.pc_next);
365 ctx->exception = POWERPC_EXCP_STOP;
366 }
367
368 #ifndef CONFIG_USER_ONLY
369 /* No need to update nip here, as execution flow will change */
370 static inline void gen_sync_exception(DisasContext *ctx)
371 {
372 ctx->exception = POWERPC_EXCP_SYNC;
373 }
374 #endif
375
376 /*****************************************************************************/
377 /* SPR READ/WRITE CALLBACKS */
378
379 void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
380 {
381 #if 0
382 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
383 printf("ERROR: try to access SPR %d !\n", sprn);
384 #endif
385 }
386
387 /* #define PPC_DUMP_SPR_ACCESSES */
388
389 /*
390 * Generic callbacks:
391 * do nothing but store/retrieve spr value
392 */
393 static void spr_load_dump_spr(int sprn)
394 {
395 #ifdef PPC_DUMP_SPR_ACCESSES
396 TCGv_i32 t0 = tcg_const_i32(sprn);
397 gen_helper_load_dump_spr(cpu_env, t0);
398 tcg_temp_free_i32(t0);
399 #endif
400 }
401
402 void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
403 {
404 gen_load_spr(cpu_gpr[gprn], sprn);
405 spr_load_dump_spr(sprn);
406 }
407
408 static void spr_store_dump_spr(int sprn)
409 {
410 #ifdef PPC_DUMP_SPR_ACCESSES
411 TCGv_i32 t0 = tcg_const_i32(sprn);
412 gen_helper_store_dump_spr(cpu_env, t0);
413 tcg_temp_free_i32(t0);
414 #endif
415 }
416
417 void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
418 {
419 gen_store_spr(sprn, cpu_gpr[gprn]);
420 spr_store_dump_spr(sprn);
421 }
422
423 #if !defined(CONFIG_USER_ONLY)
424 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
425 {
426 #ifdef TARGET_PPC64
427 TCGv t0 = tcg_temp_new();
428 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
429 gen_store_spr(sprn, t0);
430 tcg_temp_free(t0);
431 spr_store_dump_spr(sprn);
432 #else
433 spr_write_generic(ctx, sprn, gprn);
434 #endif
435 }
436
437 void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
438 {
439 TCGv t0 = tcg_temp_new();
440 TCGv t1 = tcg_temp_new();
441 gen_load_spr(t0, sprn);
442 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
443 tcg_gen_and_tl(t0, t0, t1);
444 gen_store_spr(sprn, t0);
445 tcg_temp_free(t0);
446 tcg_temp_free(t1);
447 }
448
449 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
450 {
451 }
452
453 #endif
454
455 /* SPR common to all PowerPC */
456 /* XER */
457 void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
458 {
459 TCGv dst = cpu_gpr[gprn];
460 TCGv t0 = tcg_temp_new();
461 TCGv t1 = tcg_temp_new();
462 TCGv t2 = tcg_temp_new();
463 tcg_gen_mov_tl(dst, cpu_xer);
464 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
465 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
466 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
467 tcg_gen_or_tl(t0, t0, t1);
468 tcg_gen_or_tl(dst, dst, t2);
469 tcg_gen_or_tl(dst, dst, t0);
470 if (is_isa300(ctx)) {
471 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
472 tcg_gen_or_tl(dst, dst, t0);
473 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
474 tcg_gen_or_tl(dst, dst, t0);
475 }
476 tcg_temp_free(t0);
477 tcg_temp_free(t1);
478 tcg_temp_free(t2);
479 }
480
481 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
482 {
483 TCGv src = cpu_gpr[gprn];
484 /* Write all flags, while reading back check for isa300 */
485 tcg_gen_andi_tl(cpu_xer, src,
486 ~((1u << XER_SO) |
487 (1u << XER_OV) | (1u << XER_OV32) |
488 (1u << XER_CA) | (1u << XER_CA32)));
489 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
490 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
491 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
492 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
493 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
494 }
495
496 /* LR */
497 void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
498 {
499 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
500 }
501
502 void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
503 {
504 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
505 }
506
507 /* CFAR */
508 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
509 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
510 {
511 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
512 }
513
514 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
515 {
516 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
517 }
518 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
519
520 /* CTR */
521 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
522 {
523 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
524 }
525
526 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
527 {
528 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
529 }
530
531 /* User read access to SPR */
532 /* USPRx */
533 /* UMMCRx */
534 /* UPMCx */
535 /* USIA */
536 /* UDECR */
537 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
538 {
539 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
540 }
541
542 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
543 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
544 {
545 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
546 }
547 #endif
548
549 /* SPR common to all non-embedded PowerPC */
550 /* DECR */
551 #if !defined(CONFIG_USER_ONLY)
552 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
553 {
554 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
555 gen_io_start();
556 }
557 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
558 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
559 gen_stop_exception(ctx);
560 }
561 }
562
563 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
564 {
565 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
566 gen_io_start();
567 }
568 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
569 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
570 gen_stop_exception(ctx);
571 }
572 }
573 #endif
574
575 /* SPR common to all non-embedded PowerPC, except 601 */
576 /* Time base */
577 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
578 {
579 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
580 gen_io_start();
581 }
582 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
583 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
584 gen_io_end();
585 gen_stop_exception(ctx);
586 }
587 }
588
589 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
590 {
591 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
592 gen_io_start();
593 }
594 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
595 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
596 gen_io_end();
597 gen_stop_exception(ctx);
598 }
599 }
600
601 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
602 {
603 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
604 }
605
606 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
607 {
608 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
609 }
610
611 #if !defined(CONFIG_USER_ONLY)
612 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
613 {
614 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
615 gen_io_start();
616 }
617 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
618 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
619 gen_io_end();
620 gen_stop_exception(ctx);
621 }
622 }
623
624 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
625 {
626 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
627 gen_io_start();
628 }
629 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
630 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
631 gen_io_end();
632 gen_stop_exception(ctx);
633 }
634 }
635
636 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
637 {
638 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
639 }
640
641 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
642 {
643 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
644 }
645
646 #if defined(TARGET_PPC64)
647 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
648 {
649 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
650 gen_io_start();
651 }
652 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
653 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
654 gen_stop_exception(ctx);
655 }
656 }
657
658 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
659 {
660 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
661 gen_io_start();
662 }
663 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
664 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
665 gen_stop_exception(ctx);
666 }
667 }
668
669 /* HDECR */
670 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
671 {
672 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
673 gen_io_start();
674 }
675 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
676 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
677 gen_io_end();
678 gen_stop_exception(ctx);
679 }
680 }
681
682 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
683 {
684 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
685 gen_io_start();
686 }
687 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
688 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
689 gen_io_end();
690 gen_stop_exception(ctx);
691 }
692 }
693
694 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
695 {
696 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
697 gen_io_start();
698 }
699 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
700 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
701 gen_stop_exception(ctx);
702 }
703 }
704
705 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
706 {
707 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
708 gen_io_start();
709 }
710 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
711 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
712 gen_stop_exception(ctx);
713 }
714 }
715
716 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
717 {
718 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
719 gen_io_start();
720 }
721 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
722 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
723 gen_stop_exception(ctx);
724 }
725 }
726
727 #endif
728 #endif
729
730 #if !defined(CONFIG_USER_ONLY)
731 /* IBAT0U...IBAT0U */
732 /* IBAT0L...IBAT7L */
733 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
734 {
735 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
736 offsetof(CPUPPCState,
737 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
738 }
739
740 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
741 {
742 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
743 offsetof(CPUPPCState,
744 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
745 }
746
747 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
748 {
749 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
750 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
751 tcg_temp_free_i32(t0);
752 }
753
754 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
755 {
756 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
757 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
758 tcg_temp_free_i32(t0);
759 }
760
761 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
762 {
763 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
764 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
765 tcg_temp_free_i32(t0);
766 }
767
768 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
769 {
770 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
771 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
772 tcg_temp_free_i32(t0);
773 }
774
775 /* DBAT0U...DBAT7U */
776 /* DBAT0L...DBAT7L */
777 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
778 {
779 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
780 offsetof(CPUPPCState,
781 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
782 }
783
784 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
785 {
786 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
787 offsetof(CPUPPCState,
788 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
789 }
790
791 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
792 {
793 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
794 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
795 tcg_temp_free_i32(t0);
796 }
797
798 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
799 {
800 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
801 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
802 tcg_temp_free_i32(t0);
803 }
804
805 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
806 {
807 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
808 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
809 tcg_temp_free_i32(t0);
810 }
811
812 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
813 {
814 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
815 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
816 tcg_temp_free_i32(t0);
817 }
818
819 /* SDR1 */
820 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
821 {
822 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
823 }
824
825 #if defined(TARGET_PPC64)
826 /* 64 bits PowerPC specific SPRs */
827 /* PIDR */
828 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
829 {
830 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
831 }
832
833 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
834 {
835 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
836 }
837
838 void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
839 {
840 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
841 }
842
843 void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
844 {
845 TCGv t0 = tcg_temp_new();
846 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
847 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
848 tcg_temp_free(t0);
849 }
850 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
851 {
852 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
853 }
854
855 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
856 {
857 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
858 }
859
860 /* DPDES */
861 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
862 {
863 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
864 }
865
866 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
867 {
868 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
869 }
870 #endif
871 #endif
872
873 /* PowerPC 601 specific registers */
874 /* RTC */
875 void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
876 {
877 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
878 }
879
880 void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
881 {
882 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
883 }
884
885 #if !defined(CONFIG_USER_ONLY)
886 void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
887 {
888 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
889 }
890
891 void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
892 {
893 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
894 }
895
896 void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
897 {
898 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
899 /* Must stop the translation as endianness may have changed */
900 gen_stop_exception(ctx);
901 }
902 #endif
903
904 /* Unified bats */
905 #if !defined(CONFIG_USER_ONLY)
906 void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
907 {
908 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
909 offsetof(CPUPPCState,
910 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
911 }
912
913 void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
914 {
915 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
916 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
917 tcg_temp_free_i32(t0);
918 }
919
920 void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
921 {
922 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
923 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
924 tcg_temp_free_i32(t0);
925 }
926 #endif
927
928 /* PowerPC 40x specific registers */
929 #if !defined(CONFIG_USER_ONLY)
930 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
931 {
932 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
933 gen_io_start();
934 }
935 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
936 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
937 gen_stop_exception(ctx);
938 }
939 }
940
941 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
942 {
943 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
944 gen_io_start();
945 }
946 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
947 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
948 gen_stop_exception(ctx);
949 }
950 }
951
952 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
953 {
954 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
955 gen_io_start();
956 }
957 gen_store_spr(sprn, cpu_gpr[gprn]);
958 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
959 /* We must stop translation as we may have rebooted */
960 gen_stop_exception(ctx);
961 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
962 gen_stop_exception(ctx);
963 }
964 }
965
966 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
967 {
968 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
969 gen_io_start();
970 }
971 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
972 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
973 gen_stop_exception(ctx);
974 }
975 }
976
977 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
978 {
979 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
980 gen_io_start();
981 }
982 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
983 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
984 gen_stop_exception(ctx);
985 }
986 }
987
988 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
989 {
990 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
991 gen_io_start();
992 }
993 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
994 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
995 gen_stop_exception(ctx);
996 }
997 }
998 #endif
999
1000 /* PowerPC 403 specific registers */
1001 /* PBL1 / PBU1 / PBL2 / PBU2 */
1002 #if !defined(CONFIG_USER_ONLY)
1003 void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
1004 {
1005 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
1006 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
1007 }
1008
1009 void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
1010 {
1011 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
1012 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
1013 tcg_temp_free_i32(t0);
1014 }
1015
1016 void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
1017 {
1018 TCGv t0 = tcg_temp_new();
1019 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
1020 gen_store_spr(SPR_PIR, t0);
1021 tcg_temp_free(t0);
1022 }
1023 #endif
1024
1025 /* SPE specific registers */
1026 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
1027 {
1028 TCGv_i32 t0 = tcg_temp_new_i32();
1029 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
1030 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
1031 tcg_temp_free_i32(t0);
1032 }
1033
1034 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
1035 {
1036 TCGv_i32 t0 = tcg_temp_new_i32();
1037 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1038 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
1039 tcg_temp_free_i32(t0);
1040 }
1041
1042 #if !defined(CONFIG_USER_ONLY)
1043 /* Callback used to write the exception vector base */
1044 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
1045 {
1046 TCGv t0 = tcg_temp_new();
1047 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
1048 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1049 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
1050 gen_store_spr(sprn, t0);
1051 tcg_temp_free(t0);
1052 }
1053
1054 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
1055 {
1056 int sprn_offs;
1057
1058 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
1059 sprn_offs = sprn - SPR_BOOKE_IVOR0;
1060 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
1061 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
1062 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
1063 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
1064 } else {
1065 printf("Trying to write an unknown exception vector %d %03x\n",
1066 sprn, sprn);
1067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
1068 return;
1069 }
1070
1071 TCGv t0 = tcg_temp_new();
1072 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
1073 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1074 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
1075 gen_store_spr(sprn, t0);
1076 tcg_temp_free(t0);
1077 }
1078 #endif
1079
1080 #ifdef TARGET_PPC64
1081 #ifndef CONFIG_USER_ONLY
1082 void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1083 {
1084 TCGv t0 = tcg_temp_new();
1085 TCGv t1 = tcg_temp_new();
1086 TCGv t2 = tcg_temp_new();
1087
1088 /*
1089 * Note, the HV=1 PR=0 case is handled earlier by simply using
1090 * spr_write_generic for HV mode in the SPR table
1091 */
1092
1093 /* Build insertion mask into t1 based on context */
1094 if (ctx->pr) {
1095 gen_load_spr(t1, SPR_UAMOR);
1096 } else {
1097 gen_load_spr(t1, SPR_AMOR);
1098 }
1099
1100 /* Mask new bits into t2 */
1101 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1102
1103 /* Load AMR and clear new bits in t0 */
1104 gen_load_spr(t0, SPR_AMR);
1105 tcg_gen_andc_tl(t0, t0, t1);
1106
1107 /* Or'in new bits and write it out */
1108 tcg_gen_or_tl(t0, t0, t2);
1109 gen_store_spr(SPR_AMR, t0);
1110 spr_store_dump_spr(SPR_AMR);
1111
1112 tcg_temp_free(t0);
1113 tcg_temp_free(t1);
1114 tcg_temp_free(t2);
1115 }
1116
1117 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1118 {
1119 TCGv t0 = tcg_temp_new();
1120 TCGv t1 = tcg_temp_new();
1121 TCGv t2 = tcg_temp_new();
1122
1123 /*
1124 * Note, the HV=1 case is handled earlier by simply using
1125 * spr_write_generic for HV mode in the SPR table
1126 */
1127
1128 /* Build insertion mask into t1 based on context */
1129 gen_load_spr(t1, SPR_AMOR);
1130
1131 /* Mask new bits into t2 */
1132 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1133
1134 /* Load AMR and clear new bits in t0 */
1135 gen_load_spr(t0, SPR_UAMOR);
1136 tcg_gen_andc_tl(t0, t0, t1);
1137
1138 /* Or'in new bits and write it out */
1139 tcg_gen_or_tl(t0, t0, t2);
1140 gen_store_spr(SPR_UAMOR, t0);
1141 spr_store_dump_spr(SPR_UAMOR);
1142
1143 tcg_temp_free(t0);
1144 tcg_temp_free(t1);
1145 tcg_temp_free(t2);
1146 }
1147
1148 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1149 {
1150 TCGv t0 = tcg_temp_new();
1151 TCGv t1 = tcg_temp_new();
1152 TCGv t2 = tcg_temp_new();
1153
1154 /*
1155 * Note, the HV=1 case is handled earlier by simply using
1156 * spr_write_generic for HV mode in the SPR table
1157 */
1158
1159 /* Build insertion mask into t1 based on context */
1160 gen_load_spr(t1, SPR_AMOR);
1161
1162 /* Mask new bits into t2 */
1163 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1164
1165 /* Load AMR and clear new bits in t0 */
1166 gen_load_spr(t0, SPR_IAMR);
1167 tcg_gen_andc_tl(t0, t0, t1);
1168
1169 /* Or'in new bits and write it out */
1170 tcg_gen_or_tl(t0, t0, t2);
1171 gen_store_spr(SPR_IAMR, t0);
1172 spr_store_dump_spr(SPR_IAMR);
1173
1174 tcg_temp_free(t0);
1175 tcg_temp_free(t1);
1176 tcg_temp_free(t2);
1177 }
1178 #endif
1179 #endif
1180
1181 #ifndef CONFIG_USER_ONLY
1182 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1183 {
1184 gen_helper_fixup_thrm(cpu_env);
1185 gen_load_spr(cpu_gpr[gprn], sprn);
1186 spr_load_dump_spr(sprn);
1187 }
1188 #endif /* !CONFIG_USER_ONLY */
1189
1190 #if !defined(CONFIG_USER_ONLY)
1191 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1192 {
1193 TCGv t0 = tcg_temp_new();
1194
1195 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1196 gen_store_spr(sprn, t0);
1197 tcg_temp_free(t0);
1198 }
1199
1200 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1201 {
1202 TCGv t0 = tcg_temp_new();
1203
1204 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1205 gen_store_spr(sprn, t0);
1206 tcg_temp_free(t0);
1207 }
1208
1209 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
1210 {
1211 TCGv t0 = tcg_temp_new();
1212
1213 tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1214 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1215 gen_store_spr(sprn, t0);
1216 tcg_temp_free(t0);
1217 }
1218
1219 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1220 {
1221 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1222 }
1223
1224 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1225 {
1226 TCGv_i32 t0 = tcg_const_i32(sprn);
1227 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1228 tcg_temp_free_i32(t0);
1229 }
1230 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1231 {
1232 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1233 }
1234 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1235 {
1236 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1237 }
1238
1239 #endif
1240
1241 #if !defined(CONFIG_USER_ONLY)
1242 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
1243 {
1244 TCGv val = tcg_temp_new();
1245 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1246 gen_store_spr(SPR_BOOKE_MAS3, val);
1247 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1248 gen_store_spr(SPR_BOOKE_MAS7, val);
1249 tcg_temp_free(val);
1250 }
1251
1252 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
1253 {
1254 TCGv mas7 = tcg_temp_new();
1255 TCGv mas3 = tcg_temp_new();
1256 gen_load_spr(mas7, SPR_BOOKE_MAS7);
1257 tcg_gen_shli_tl(mas7, mas7, 32);
1258 gen_load_spr(mas3, SPR_BOOKE_MAS3);
1259 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1260 tcg_temp_free(mas3);
1261 tcg_temp_free(mas7);
1262 }
1263
1264 #endif
1265
1266 #ifdef TARGET_PPC64
1267 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1268 int bit, int sprn, int cause)
1269 {
1270 TCGv_i32 t1 = tcg_const_i32(bit);
1271 TCGv_i32 t2 = tcg_const_i32(sprn);
1272 TCGv_i32 t3 = tcg_const_i32(cause);
1273
1274 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
1275
1276 tcg_temp_free_i32(t3);
1277 tcg_temp_free_i32(t2);
1278 tcg_temp_free_i32(t1);
1279 }
1280
1281 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1282 int bit, int sprn, int cause)
1283 {
1284 TCGv_i32 t1 = tcg_const_i32(bit);
1285 TCGv_i32 t2 = tcg_const_i32(sprn);
1286 TCGv_i32 t3 = tcg_const_i32(cause);
1287
1288 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
1289
1290 tcg_temp_free_i32(t3);
1291 tcg_temp_free_i32(t2);
1292 tcg_temp_free_i32(t1);
1293 }
1294
1295 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
1296 {
1297 TCGv spr_up = tcg_temp_new();
1298 TCGv spr = tcg_temp_new();
1299
1300 gen_load_spr(spr, sprn - 1);
1301 tcg_gen_shri_tl(spr_up, spr, 32);
1302 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1303
1304 tcg_temp_free(spr);
1305 tcg_temp_free(spr_up);
1306 }
1307
1308 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
1309 {
1310 TCGv spr = tcg_temp_new();
1311
1312 gen_load_spr(spr, sprn - 1);
1313 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1314 gen_store_spr(sprn - 1, spr);
1315
1316 tcg_temp_free(spr);
1317 }
1318
1319 #if !defined(CONFIG_USER_ONLY)
1320 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
1321 {
1322 TCGv hmer = tcg_temp_new();
1323
1324 gen_load_spr(hmer, sprn);
1325 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1326 gen_store_spr(sprn, hmer);
1327 spr_store_dump_spr(sprn);
1328 tcg_temp_free(hmer);
1329 }
1330
1331 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
1332 {
1333 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
1334 }
1335 #endif /* !defined(CONFIG_USER_ONLY) */
1336
1337 void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
1338 {
1339 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1340 spr_read_generic(ctx, gprn, sprn);
1341 }
1342
1343 void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
1344 {
1345 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1346 spr_write_generic(ctx, sprn, gprn);
1347 }
1348
1349 void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
1350 {
1351 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1352 spr_read_generic(ctx, gprn, sprn);
1353 }
1354
1355 void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
1356 {
1357 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1358 spr_write_generic(ctx, sprn, gprn);
1359 }
1360
1361 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
1362 {
1363 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1364 spr_read_prev_upper32(ctx, gprn, sprn);
1365 }
1366
1367 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
1368 {
1369 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1370 spr_write_prev_upper32(ctx, sprn, gprn);
1371 }
1372
1373 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
1374 {
1375 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1376 spr_read_generic(ctx, gprn, sprn);
1377 }
1378
1379 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
1380 {
1381 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1382 spr_write_generic(ctx, sprn, gprn);
1383 }
1384
1385 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
1386 {
1387 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1388 spr_read_prev_upper32(ctx, gprn, sprn);
1389 }
1390
1391 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
1392 {
1393 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1394 spr_write_prev_upper32(ctx, sprn, gprn);
1395 }
1396 #endif
1397
1398 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
1399 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1400
1401 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
1402 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1403
1404 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
1405 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1406
1407 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
1408 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1409
1410 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
1411 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1412
1413 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1414 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1415
1416 typedef struct opcode_t {
1417 unsigned char opc1, opc2, opc3, opc4;
1418 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1419 unsigned char pad[4];
1420 #endif
1421 opc_handler_t handler;
1422 const char *oname;
1423 } opcode_t;
1424
1425 /* Helpers for priv. check */
1426 #define GEN_PRIV \
1427 do { \
1428 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
1429 } while (0)
1430
1431 #if defined(CONFIG_USER_ONLY)
1432 #define CHK_HV GEN_PRIV
1433 #define CHK_SV GEN_PRIV
1434 #define CHK_HVRM GEN_PRIV
1435 #else
1436 #define CHK_HV \
1437 do { \
1438 if (unlikely(ctx->pr || !ctx->hv)) { \
1439 GEN_PRIV; \
1440 } \
1441 } while (0)
1442 #define CHK_SV \
1443 do { \
1444 if (unlikely(ctx->pr)) { \
1445 GEN_PRIV; \
1446 } \
1447 } while (0)
1448 #define CHK_HVRM \
1449 do { \
1450 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1451 GEN_PRIV; \
1452 } \
1453 } while (0)
1454 #endif
1455
1456 #define CHK_NONE
1457
1458 /*****************************************************************************/
1459 /* PowerPC instructions table */
1460
1461 #if defined(DO_PPC_STATISTICS)
1462 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1463 { \
1464 .opc1 = op1, \
1465 .opc2 = op2, \
1466 .opc3 = op3, \
1467 .opc4 = 0xff, \
1468 .handler = { \
1469 .inval1 = invl, \
1470 .type = _typ, \
1471 .type2 = _typ2, \
1472 .handler = &gen_##name, \
1473 .oname = stringify(name), \
1474 }, \
1475 .oname = stringify(name), \
1476 }
1477 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1478 { \
1479 .opc1 = op1, \
1480 .opc2 = op2, \
1481 .opc3 = op3, \
1482 .opc4 = 0xff, \
1483 .handler = { \
1484 .inval1 = invl1, \
1485 .inval2 = invl2, \
1486 .type = _typ, \
1487 .type2 = _typ2, \
1488 .handler = &gen_##name, \
1489 .oname = stringify(name), \
1490 }, \
1491 .oname = stringify(name), \
1492 }
1493 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1494 { \
1495 .opc1 = op1, \
1496 .opc2 = op2, \
1497 .opc3 = op3, \
1498 .opc4 = 0xff, \
1499 .handler = { \
1500 .inval1 = invl, \
1501 .type = _typ, \
1502 .type2 = _typ2, \
1503 .handler = &gen_##name, \
1504 .oname = onam, \
1505 }, \
1506 .oname = onam, \
1507 }
1508 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1509 { \
1510 .opc1 = op1, \
1511 .opc2 = op2, \
1512 .opc3 = op3, \
1513 .opc4 = op4, \
1514 .handler = { \
1515 .inval1 = invl, \
1516 .type = _typ, \
1517 .type2 = _typ2, \
1518 .handler = &gen_##name, \
1519 .oname = stringify(name), \
1520 }, \
1521 .oname = stringify(name), \
1522 }
1523 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1524 { \
1525 .opc1 = op1, \
1526 .opc2 = op2, \
1527 .opc3 = op3, \
1528 .opc4 = op4, \
1529 .handler = { \
1530 .inval1 = invl, \
1531 .type = _typ, \
1532 .type2 = _typ2, \
1533 .handler = &gen_##name, \
1534 .oname = onam, \
1535 }, \
1536 .oname = onam, \
1537 }
1538 #else
1539 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1540 { \
1541 .opc1 = op1, \
1542 .opc2 = op2, \
1543 .opc3 = op3, \
1544 .opc4 = 0xff, \
1545 .handler = { \
1546 .inval1 = invl, \
1547 .type = _typ, \
1548 .type2 = _typ2, \
1549 .handler = &gen_##name, \
1550 }, \
1551 .oname = stringify(name), \
1552 }
1553 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1554 { \
1555 .opc1 = op1, \
1556 .opc2 = op2, \
1557 .opc3 = op3, \
1558 .opc4 = 0xff, \
1559 .handler = { \
1560 .inval1 = invl1, \
1561 .inval2 = invl2, \
1562 .type = _typ, \
1563 .type2 = _typ2, \
1564 .handler = &gen_##name, \
1565 }, \
1566 .oname = stringify(name), \
1567 }
1568 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1569 { \
1570 .opc1 = op1, \
1571 .opc2 = op2, \
1572 .opc3 = op3, \
1573 .opc4 = 0xff, \
1574 .handler = { \
1575 .inval1 = invl, \
1576 .type = _typ, \
1577 .type2 = _typ2, \
1578 .handler = &gen_##name, \
1579 }, \
1580 .oname = onam, \
1581 }
1582 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1583 { \
1584 .opc1 = op1, \
1585 .opc2 = op2, \
1586 .opc3 = op3, \
1587 .opc4 = op4, \
1588 .handler = { \
1589 .inval1 = invl, \
1590 .type = _typ, \
1591 .type2 = _typ2, \
1592 .handler = &gen_##name, \
1593 }, \
1594 .oname = stringify(name), \
1595 }
1596 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1597 { \
1598 .opc1 = op1, \
1599 .opc2 = op2, \
1600 .opc3 = op3, \
1601 .opc4 = op4, \
1602 .handler = { \
1603 .inval1 = invl, \
1604 .type = _typ, \
1605 .type2 = _typ2, \
1606 .handler = &gen_##name, \
1607 }, \
1608 .oname = onam, \
1609 }
1610 #endif
1611
1612 /* Invalid instruction */
1613 static void gen_invalid(DisasContext *ctx)
1614 {
1615 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1616 }
1617
1618 static opc_handler_t invalid_handler = {
1619 .inval1 = 0xFFFFFFFF,
1620 .inval2 = 0xFFFFFFFF,
1621 .type = PPC_NONE,
1622 .type2 = PPC_NONE,
1623 .handler = gen_invalid,
1624 };
1625
1626 /*** Integer comparison ***/
1627
1628 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
1629 {
1630 TCGv t0 = tcg_temp_new();
1631 TCGv t1 = tcg_temp_new();
1632 TCGv_i32 t = tcg_temp_new_i32();
1633
1634 tcg_gen_movi_tl(t0, CRF_EQ);
1635 tcg_gen_movi_tl(t1, CRF_LT);
1636 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1637 t0, arg0, arg1, t1, t0);
1638 tcg_gen_movi_tl(t1, CRF_GT);
1639 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1640 t0, arg0, arg1, t1, t0);
1641
1642 tcg_gen_trunc_tl_i32(t, t0);
1643 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1644 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
1645
1646 tcg_temp_free(t0);
1647 tcg_temp_free(t1);
1648 tcg_temp_free_i32(t);
1649 }
1650
1651 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
1652 {
1653 TCGv t0 = tcg_const_tl(arg1);
1654 gen_op_cmp(arg0, t0, s, crf);
1655 tcg_temp_free(t0);
1656 }
1657
1658 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
1659 {
1660 TCGv t0, t1;
1661 t0 = tcg_temp_new();
1662 t1 = tcg_temp_new();
1663 if (s) {
1664 tcg_gen_ext32s_tl(t0, arg0);
1665 tcg_gen_ext32s_tl(t1, arg1);
1666 } else {
1667 tcg_gen_ext32u_tl(t0, arg0);
1668 tcg_gen_ext32u_tl(t1, arg1);
1669 }
1670 gen_op_cmp(t0, t1, s, crf);
1671 tcg_temp_free(t1);
1672 tcg_temp_free(t0);
1673 }
1674
1675 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
1676 {
1677 TCGv t0 = tcg_const_tl(arg1);
1678 gen_op_cmp32(arg0, t0, s, crf);
1679 tcg_temp_free(t0);
1680 }
1681
1682 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
1683 {
1684 if (NARROW_MODE(ctx)) {
1685 gen_op_cmpi32(reg, 0, 1, 0);
1686 } else {
1687 gen_op_cmpi(reg, 0, 1, 0);
1688 }
1689 }
1690
1691 /* cmp */
1692 static void gen_cmp(DisasContext *ctx)
1693 {
1694 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1695 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1696 1, crfD(ctx->opcode));
1697 } else {
1698 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1699 1, crfD(ctx->opcode));
1700 }
1701 }
1702
1703 /* cmpi */
1704 static void gen_cmpi(DisasContext *ctx)
1705 {
1706 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1707 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1708 1, crfD(ctx->opcode));
1709 } else {
1710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1711 1, crfD(ctx->opcode));
1712 }
1713 }
1714
1715 /* cmpl */
1716 static void gen_cmpl(DisasContext *ctx)
1717 {
1718 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1719 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1720 0, crfD(ctx->opcode));
1721 } else {
1722 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1723 0, crfD(ctx->opcode));
1724 }
1725 }
1726
1727 /* cmpli */
1728 static void gen_cmpli(DisasContext *ctx)
1729 {
1730 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1731 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
1732 0, crfD(ctx->opcode));
1733 } else {
1734 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
1735 0, crfD(ctx->opcode));
1736 }
1737 }
1738
1739 /* cmprb - range comparison: isupper, isaplha, islower*/
1740 static void gen_cmprb(DisasContext *ctx)
1741 {
1742 TCGv_i32 src1 = tcg_temp_new_i32();
1743 TCGv_i32 src2 = tcg_temp_new_i32();
1744 TCGv_i32 src2lo = tcg_temp_new_i32();
1745 TCGv_i32 src2hi = tcg_temp_new_i32();
1746 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
1747
1748 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
1749 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
1750
1751 tcg_gen_andi_i32(src1, src1, 0xFF);
1752 tcg_gen_ext8u_i32(src2lo, src2);
1753 tcg_gen_shri_i32(src2, src2, 8);
1754 tcg_gen_ext8u_i32(src2hi, src2);
1755
1756 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1757 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1758 tcg_gen_and_i32(crf, src2lo, src2hi);
1759
1760 if (ctx->opcode & 0x00200000) {
1761 tcg_gen_shri_i32(src2, src2, 8);
1762 tcg_gen_ext8u_i32(src2lo, src2);
1763 tcg_gen_shri_i32(src2, src2, 8);
1764 tcg_gen_ext8u_i32(src2hi, src2);
1765 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1766 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1767 tcg_gen_and_i32(src2lo, src2lo, src2hi);
1768 tcg_gen_or_i32(crf, crf, src2lo);
1769 }
1770 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
1771 tcg_temp_free_i32(src1);
1772 tcg_temp_free_i32(src2);
1773 tcg_temp_free_i32(src2lo);
1774 tcg_temp_free_i32(src2hi);
1775 }
1776
1777 #if defined(TARGET_PPC64)
1778 /* cmpeqb */
1779 static void gen_cmpeqb(DisasContext *ctx)
1780 {
1781 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1782 cpu_gpr[rB(ctx->opcode)]);
1783 }
1784 #endif
1785
1786 /* isel (PowerPC 2.03 specification) */
1787 static void gen_isel(DisasContext *ctx)
1788 {
1789 uint32_t bi = rC(ctx->opcode);
1790 uint32_t mask = 0x08 >> (bi & 0x03);
1791 TCGv t0 = tcg_temp_new();
1792 TCGv zr;
1793
1794 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
1795 tcg_gen_andi_tl(t0, t0, mask);
1796
1797 zr = tcg_const_tl(0);
1798 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
1799 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
1800 cpu_gpr[rB(ctx->opcode)]);
1801 tcg_temp_free(zr);
1802 tcg_temp_free(t0);
1803 }
1804
1805 /* cmpb: PowerPC 2.05 specification */
1806 static void gen_cmpb(DisasContext *ctx)
1807 {
1808 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1809 cpu_gpr[rB(ctx->opcode)]);
1810 }
1811
1812 /*** Integer arithmetic ***/
1813
1814 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1815 TCGv arg1, TCGv arg2, int sub)
1816 {
1817 TCGv t0 = tcg_temp_new();
1818
1819 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
1820 tcg_gen_xor_tl(t0, arg1, arg2);
1821 if (sub) {
1822 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1823 } else {
1824 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1825 }
1826 tcg_temp_free(t0);
1827 if (NARROW_MODE(ctx)) {
1828 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1829 if (is_isa300(ctx)) {
1830 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1831 }
1832 } else {
1833 if (is_isa300(ctx)) {
1834 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1835 }
1836 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
1837 }
1838 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1839 }
1840
1841 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1842 TCGv res, TCGv arg0, TCGv arg1,
1843 TCGv ca32, int sub)
1844 {
1845 TCGv t0;
1846
1847 if (!is_isa300(ctx)) {
1848 return;
1849 }
1850
1851 t0 = tcg_temp_new();
1852 if (sub) {
1853 tcg_gen_eqv_tl(t0, arg0, arg1);
1854 } else {
1855 tcg_gen_xor_tl(t0, arg0, arg1);
1856 }
1857 tcg_gen_xor_tl(t0, t0, res);
1858 tcg_gen_extract_tl(ca32, t0, 32, 1);
1859 tcg_temp_free(t0);
1860 }
1861
1862 /* Common add function */
1863 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
1864 TCGv arg2, TCGv ca, TCGv ca32,
1865 bool add_ca, bool compute_ca,
1866 bool compute_ov, bool compute_rc0)
1867 {
1868 TCGv t0 = ret;
1869
1870 if (compute_ca || compute_ov) {
1871 t0 = tcg_temp_new();
1872 }
1873
1874 if (compute_ca) {
1875 if (NARROW_MODE(ctx)) {
1876 /*
1877 * Caution: a non-obvious corner case of the spec is that
1878 * we must produce the *entire* 64-bit addition, but
1879 * produce the carry into bit 32.
1880 */
1881 TCGv t1 = tcg_temp_new();
1882 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
1883 tcg_gen_add_tl(t0, arg1, arg2);
1884 if (add_ca) {
1885 tcg_gen_add_tl(t0, t0, ca);
1886 }
1887 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */
1888 tcg_temp_free(t1);
1889 tcg_gen_extract_tl(ca, ca, 32, 1);
1890 if (is_isa300(ctx)) {
1891 tcg_gen_mov_tl(ca32, ca);
1892 }
1893 } else {
1894 TCGv zero = tcg_const_tl(0);
1895 if (add_ca) {
1896 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
1897 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
1898 } else {
1899 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
1900 }
1901 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
1902 tcg_temp_free(zero);
1903 }
1904 } else {
1905 tcg_gen_add_tl(t0, arg1, arg2);
1906 if (add_ca) {
1907 tcg_gen_add_tl(t0, t0, ca);
1908 }
1909 }
1910
1911 if (compute_ov) {
1912 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1913 }
1914 if (unlikely(compute_rc0)) {
1915 gen_set_Rc0(ctx, t0);
1916 }
1917
1918 if (t0 != ret) {
1919 tcg_gen_mov_tl(ret, t0);
1920 tcg_temp_free(t0);
1921 }
1922 }
1923 /* Add functions with two operands */
1924 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
1925 static void glue(gen_, name)(DisasContext *ctx) \
1926 { \
1927 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1928 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1929 ca, glue(ca, 32), \
1930 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1931 }
1932 /* Add functions with one operand and one immediate */
1933 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
1934 add_ca, compute_ca, compute_ov) \
1935 static void glue(gen_, name)(DisasContext *ctx) \
1936 { \
1937 TCGv t0 = tcg_const_tl(const_val); \
1938 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1939 cpu_gpr[rA(ctx->opcode)], t0, \
1940 ca, glue(ca, 32), \
1941 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1942 tcg_temp_free(t0); \
1943 }
1944
1945 /* add add. addo addo. */
1946 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
1947 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
1948 /* addc addc. addco addco. */
1949 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
1950 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
1951 /* adde adde. addeo addeo. */
1952 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
1953 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
1954 /* addme addme. addmeo addmeo. */
1955 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
1956 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
1957 /* addex */
1958 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
1959 /* addze addze. addzeo addzeo.*/
1960 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
1961 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
1962 /* addi */
1963 static void gen_addi(DisasContext *ctx)
1964 {
1965 target_long simm = SIMM(ctx->opcode);
1966
1967 if (rA(ctx->opcode) == 0) {
1968 /* li case */
1969 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1970 } else {
1971 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1972 cpu_gpr[rA(ctx->opcode)], simm);
1973 }
1974 }
1975 /* addic addic.*/
1976 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1977 {
1978 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1979 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1980 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
1981 tcg_temp_free(c);
1982 }
1983
1984 static void gen_addic(DisasContext *ctx)
1985 {
1986 gen_op_addic(ctx, 0);
1987 }
1988
1989 static void gen_addic_(DisasContext *ctx)
1990 {
1991 gen_op_addic(ctx, 1);
1992 }
1993
1994 /* addis */
1995 static void gen_addis(DisasContext *ctx)
1996 {
1997 target_long simm = SIMM(ctx->opcode);
1998
1999 if (rA(ctx->opcode) == 0) {
2000 /* lis case */
2001 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
2002 } else {
2003 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
2004 cpu_gpr[rA(ctx->opcode)], simm << 16);
2005 }
2006 }
2007
2008 /* addpcis */
2009 static void gen_addpcis(DisasContext *ctx)
2010 {
2011 target_long d = DX(ctx->opcode);
2012
2013 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
2014 }
2015
2016 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
2017 TCGv arg2, int sign, int compute_ov)
2018 {
2019 TCGv_i32 t0 = tcg_temp_new_i32();
2020 TCGv_i32 t1 = tcg_temp_new_i32();
2021 TCGv_i32 t2 = tcg_temp_new_i32();
2022 TCGv_i32 t3 = tcg_temp_new_i32();
2023
2024 tcg_gen_trunc_tl_i32(t0, arg1);
2025 tcg_gen_trunc_tl_i32(t1, arg2);
2026 if (sign) {
2027 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
2028 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
2029 tcg_gen_and_i32(t2, t2, t3);
2030 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
2031 tcg_gen_or_i32(t2, t2, t3);
2032 tcg_gen_movi_i32(t3, 0);
2033 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2034 tcg_gen_div_i32(t3, t0, t1);
2035 tcg_gen_extu_i32_tl(ret, t3);
2036 } else {
2037 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
2038 tcg_gen_movi_i32(t3, 0);
2039 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2040 tcg_gen_divu_i32(t3, t0, t1);
2041 tcg_gen_extu_i32_tl(ret, t3);
2042 }
2043 if (compute_ov) {
2044 tcg_gen_extu_i32_tl(cpu_ov, t2);
2045 if (is_isa300(ctx)) {
2046 tcg_gen_extu_i32_tl(cpu_ov32, t2);
2047 }
2048 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2049 }
2050 tcg_temp_free_i32(t0);
2051 tcg_temp_free_i32(t1);
2052 tcg_temp_free_i32(t2);
2053 tcg_temp_free_i32(t3);
2054
2055 if (unlikely(Rc(ctx->opcode) != 0)) {
2056 gen_set_Rc0(ctx, ret);
2057 }
2058 }
2059 /* Div functions */
2060 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
2061 static void glue(gen_, name)(DisasContext *ctx) \
2062 { \
2063 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
2064 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2065 sign, compute_ov); \
2066 }
2067 /* divwu divwu. divwuo divwuo. */
2068 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
2069 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
2070 /* divw divw. divwo divwo. */
2071 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
2072 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
2073
2074 /* div[wd]eu[o][.] */
2075 #define GEN_DIVE(name, hlpr, compute_ov) \
2076 static void gen_##name(DisasContext *ctx) \
2077 { \
2078 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
2079 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
2080 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
2081 tcg_temp_free_i32(t0); \
2082 if (unlikely(Rc(ctx->opcode) != 0)) { \
2083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
2084 } \
2085 }
2086
2087 GEN_DIVE(divweu, divweu, 0);
2088 GEN_DIVE(divweuo, divweu, 1);
2089 GEN_DIVE(divwe, divwe, 0);
2090 GEN_DIVE(divweo, divwe, 1);
2091
2092 #if defined(TARGET_PPC64)
2093 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
2094 TCGv arg2, int sign, int compute_ov)
2095 {
2096 TCGv_i64 t0 = tcg_temp_new_i64();
2097 TCGv_i64 t1 = tcg_temp_new_i64();
2098 TCGv_i64 t2 = tcg_temp_new_i64();
2099 TCGv_i64 t3 = tcg_temp_new_i64();
2100
2101 tcg_gen_mov_i64(t0, arg1);
2102 tcg_gen_mov_i64(t1, arg2);
2103 if (sign) {
2104 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
2105 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
2106 tcg_gen_and_i64(t2, t2, t3);
2107 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
2108 tcg_gen_or_i64(t2, t2, t3);
2109 tcg_gen_movi_i64(t3, 0);
2110 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2111 tcg_gen_div_i64(ret, t0, t1);
2112 } else {
2113 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
2114 tcg_gen_movi_i64(t3, 0);
2115 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2116 tcg_gen_divu_i64(ret, t0, t1);
2117 }
2118 if (compute_ov) {
2119 tcg_gen_mov_tl(cpu_ov, t2);
2120 if (is_isa300(ctx)) {
2121 tcg_gen_mov_tl(cpu_ov32, t2);
2122 }
2123 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2124 }
2125 tcg_temp_free_i64(t0);
2126 tcg_temp_free_i64(t1);
2127 tcg_temp_free_i64(t2);
2128 tcg_temp_free_i64(t3);
2129
2130 if (unlikely(Rc(ctx->opcode) != 0)) {
2131 gen_set_Rc0(ctx, ret);
2132 }
2133 }
2134
2135 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
2136 static void glue(gen_, name)(DisasContext *ctx) \
2137 { \
2138 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
2139 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2140 sign, compute_ov); \
2141 }
2142 /* divdu divdu. divduo divduo. */
2143 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
2144 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
2145 /* divd divd. divdo divdo. */
2146 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
2147 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
2148
2149 GEN_DIVE(divdeu, divdeu, 0);
2150 GEN_DIVE(divdeuo, divdeu, 1);
2151 GEN_DIVE(divde, divde, 0);
2152 GEN_DIVE(divdeo, divde, 1);
2153 #endif
2154
2155 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
2156 TCGv arg2, int sign)
2157 {
2158 TCGv_i32 t0 = tcg_temp_new_i32();
2159 TCGv_i32 t1 = tcg_temp_new_i32();
2160
2161 tcg_gen_trunc_tl_i32(t0, arg1);
2162 tcg_gen_trunc_tl_i32(t1, arg2);
2163 if (sign) {
2164 TCGv_i32 t2 = tcg_temp_new_i32();
2165 TCGv_i32 t3 = tcg_temp_new_i32();
2166 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
2167 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
2168 tcg_gen_and_i32(t2, t2, t3);
2169 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
2170 tcg_gen_or_i32(t2, t2, t3);
2171 tcg_gen_movi_i32(t3, 0);
2172 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2173 tcg_gen_rem_i32(t3, t0, t1);
2174 tcg_gen_ext_i32_tl(ret, t3);
2175 tcg_temp_free_i32(t2);
2176 tcg_temp_free_i32(t3);
2177 } else {
2178 TCGv_i32 t2 = tcg_const_i32(1);
2179 TCGv_i32 t3 = tcg_const_i32(0);
2180 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
2181 tcg_gen_remu_i32(t3, t0, t1);
2182 tcg_gen_extu_i32_tl(ret, t3);
2183 tcg_temp_free_i32(t2);
2184 tcg_temp_free_i32(t3);
2185 }
2186 tcg_temp_free_i32(t0);
2187 tcg_temp_free_i32(t1);
2188 }
2189
2190 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
2191 static void glue(gen_, name)(DisasContext *ctx) \
2192 { \
2193 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
2194 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2195 sign); \
2196 }
2197
2198 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
2199 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
2200
2201 #if defined(TARGET_PPC64)
2202 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
2203 TCGv arg2, int sign)
2204 {
2205 TCGv_i64 t0 = tcg_temp_new_i64();
2206 TCGv_i64 t1 = tcg_temp_new_i64();
2207
2208 tcg_gen_mov_i64(t0, arg1);
2209 tcg_gen_mov_i64(t1, arg2);
2210 if (sign) {
2211 TCGv_i64 t2 = tcg_temp_new_i64();
2212 TCGv_i64 t3 = tcg_temp_new_i64();
2213 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
2214 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
2215 tcg_gen_and_i64(t2, t2, t3);
2216 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
2217 tcg_gen_or_i64(t2, t2, t3);
2218 tcg_gen_movi_i64(t3, 0);
2219 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2220 tcg_gen_rem_i64(ret, t0, t1);
2221 tcg_temp_free_i64(t2);
2222 tcg_temp_free_i64(t3);
2223 } else {
2224 TCGv_i64 t2 = tcg_const_i64(1);
2225 TCGv_i64 t3 = tcg_const_i64(0);
2226 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
2227 tcg_gen_remu_i64(ret, t0, t1);
2228 tcg_temp_free_i64(t2);
2229 tcg_temp_free_i64(t3);
2230 }
2231 tcg_temp_free_i64(t0);
2232 tcg_temp_free_i64(t1);
2233 }
2234
2235 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
2236 static void glue(gen_, name)(DisasContext *ctx) \
2237 { \
2238 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
2239 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2240 sign); \
2241 }
2242
2243 GEN_INT_ARITH_MODD(modud, 0x08, 0);
2244 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
2245 #endif
2246
2247 /* mulhw mulhw. */
2248 static void gen_mulhw(DisasContext *ctx)
2249 {
2250 TCGv_i32 t0 = tcg_temp_new_i32();
2251 TCGv_i32 t1 = tcg_temp_new_i32();
2252
2253 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2254 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2255 tcg_gen_muls2_i32(t0, t1, t0, t1);
2256 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2257 tcg_temp_free_i32(t0);
2258 tcg_temp_free_i32(t1);
2259 if (unlikely(Rc(ctx->opcode) != 0)) {
2260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2261 }
2262 }
2263
2264 /* mulhwu mulhwu. */
2265 static void gen_mulhwu(DisasContext *ctx)
2266 {
2267 TCGv_i32 t0 = tcg_temp_new_i32();
2268 TCGv_i32 t1 = tcg_temp_new_i32();
2269
2270 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2271 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2272 tcg_gen_mulu2_i32(t0, t1, t0, t1);
2273 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2274 tcg_temp_free_i32(t0);
2275 tcg_temp_free_i32(t1);
2276 if (unlikely(Rc(ctx->opcode) != 0)) {
2277 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2278 }
2279 }
2280
2281 /* mullw mullw. */
2282 static void gen_mullw(DisasContext *ctx)
2283 {
2284 #if defined(TARGET_PPC64)
2285 TCGv_i64 t0, t1;
2286 t0 = tcg_temp_new_i64();
2287 t1 = tcg_temp_new_i64();
2288 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
2289 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
2290 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2291 tcg_temp_free(t0);
2292 tcg_temp_free(t1);
2293 #else
2294 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2295 cpu_gpr[rB(ctx->opcode)]);
2296 #endif
2297 if (unlikely(Rc(ctx->opcode) != 0)) {
2298 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2299 }
2300 }
2301
2302 /* mullwo mullwo. */
2303 static void gen_mullwo(DisasContext *ctx)
2304 {
2305 TCGv_i32 t0 = tcg_temp_new_i32();
2306 TCGv_i32 t1 = tcg_temp_new_i32();
2307
2308 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2309 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2310 tcg_gen_muls2_i32(t0, t1, t0, t1);
2311 #if defined(TARGET_PPC64)
2312 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2313 #else
2314 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
2315 #endif
2316
2317 tcg_gen_sari_i32(t0, t0, 31);
2318 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
2319 tcg_gen_extu_i32_tl(cpu_ov, t0);
2320 if (is_isa300(ctx)) {
2321 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2322 }
2323 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2324
2325 tcg_temp_free_i32(t0);
2326 tcg_temp_free_i32(t1);
2327 if (unlikely(Rc(ctx->opcode) != 0)) {
2328 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2329 }
2330 }
2331
2332 /* mulli */
2333 static void gen_mulli(DisasContext *ctx)
2334 {
2335 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2336 SIMM(ctx->opcode));
2337 }
2338
2339 #if defined(TARGET_PPC64)
2340 /* mulhd mulhd. */
2341 static void gen_mulhd(DisasContext *ctx)
2342 {
2343 TCGv lo = tcg_temp_new();
2344 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2345 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2346 tcg_temp_free(lo);
2347 if (unlikely(Rc(ctx->opcode) != 0)) {
2348 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2349 }
2350 }
2351
2352 /* mulhdu mulhdu. */
2353 static void gen_mulhdu(DisasContext *ctx)
2354 {
2355 TCGv lo = tcg_temp_new();
2356 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2357 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2358 tcg_temp_free(lo);
2359 if (unlikely(Rc(ctx->opcode) != 0)) {
2360 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2361 }
2362 }
2363
2364 /* mulld mulld. */
2365 static void gen_mulld(DisasContext *ctx)
2366 {
2367 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2368 cpu_gpr[rB(ctx->opcode)]);
2369 if (unlikely(Rc(ctx->opcode) != 0)) {
2370 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2371 }
2372 }
2373
2374 /* mulldo mulldo. */
2375 static void gen_mulldo(DisasContext *ctx)
2376 {
2377 TCGv_i64 t0 = tcg_temp_new_i64();
2378 TCGv_i64 t1 = tcg_temp_new_i64();
2379
2380 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
2381 cpu_gpr[rB(ctx->opcode)]);
2382 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
2383
2384 tcg_gen_sari_i64(t0, t0, 63);
2385 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
2386 if (is_isa300(ctx)) {
2387 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2388 }
2389 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2390
2391 tcg_temp_free_i64(t0);
2392 tcg_temp_free_i64(t1);
2393
2394 if (unlikely(Rc(ctx->opcode) != 0)) {
2395 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2396 }
2397 }
2398 #endif
2399
2400 /* Common subf function */
2401 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
2402 TCGv arg2, bool add_ca, bool compute_ca,
2403 bool compute_ov, bool compute_rc0)
2404 {
2405 TCGv t0 = ret;
2406
2407 if (compute_ca || compute_ov) {
2408 t0 = tcg_temp_new();
2409 }
2410
2411 if (compute_ca) {
2412 /* dest = ~arg1 + arg2 [+ ca]. */
2413 if (NARROW_MODE(ctx)) {
2414 /*
2415 * Caution: a non-obvious corner case of the spec is that
2416 * we must produce the *entire* 64-bit addition, but
2417 * produce the carry into bit 32.
2418 */
2419 TCGv inv1 = tcg_temp_new();
2420 TCGv t1 = tcg_temp_new();
2421 tcg_gen_not_tl(inv1, arg1);
2422 if (add_ca) {
2423 tcg_gen_add_tl(t0, arg2, cpu_ca);
2424 } else {
2425 tcg_gen_addi_tl(t0, arg2, 1);
2426 }
2427 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
2428 tcg_gen_add_tl(t0, t0, inv1);
2429 tcg_temp_free(inv1);
2430 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
2431 tcg_temp_free(t1);
2432 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
2433 if (is_isa300(ctx)) {
2434 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2435 }
2436 } else if (add_ca) {
2437 TCGv zero, inv1 = tcg_temp_new();
2438 tcg_gen_not_tl(inv1, arg1);
2439 zero = tcg_const_tl(0);
2440 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
2441 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
2442 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
2443 tcg_temp_free(zero);
2444 tcg_temp_free(inv1);
2445 } else {
2446 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
2447 tcg_gen_sub_tl(t0, arg2, arg1);
2448 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
2449 }
2450 } else if (add_ca) {
2451 /*
2452 * Since we're ignoring carry-out, we can simplify the
2453 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2454 */
2455 tcg_gen_sub_tl(t0, arg2, arg1);
2456 tcg_gen_add_tl(t0, t0, cpu_ca);
2457 tcg_gen_subi_tl(t0, t0, 1);
2458 } else {
2459 tcg_gen_sub_tl(t0, arg2, arg1);
2460 }
2461
2462 if (compute_ov) {
2463 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
2464 }
2465 if (unlikely(compute_rc0)) {
2466 gen_set_Rc0(ctx, t0);
2467 }
2468
2469 if (t0 != ret) {
2470 tcg_gen_mov_tl(ret, t0);
2471 tcg_temp_free(t0);
2472 }
2473 }
2474 /* Sub functions with Two operands functions */
2475 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
2476 static void glue(gen_, name)(DisasContext *ctx) \
2477 { \
2478 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2479 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2480 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2481 }
2482 /* Sub functions with one operand and one immediate */
2483 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
2484 add_ca, compute_ca, compute_ov) \
2485 static void glue(gen_, name)(DisasContext *ctx) \
2486 { \
2487 TCGv t0 = tcg_const_tl(const_val); \
2488 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2489 cpu_gpr[rA(ctx->opcode)], t0, \
2490 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2491 tcg_temp_free(t0); \
2492 }
2493 /* subf subf. subfo subfo. */
2494 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
2495 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
2496 /* subfc subfc. subfco subfco. */
2497 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
2498 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
2499 /* subfe subfe. subfeo subfo. */
2500 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
2501 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
2502 /* subfme subfme. subfmeo subfmeo. */
2503 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
2504 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
2505 /* subfze subfze. subfzeo subfzeo.*/
2506 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
2507 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
2508
2509 /* subfic */
2510 static void gen_subfic(DisasContext *ctx)
2511 {
2512 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
2513 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2514 c, 0, 1, 0, 0);
2515 tcg_temp_free(c);
2516 }
2517
2518 /* neg neg. nego nego. */
2519 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
2520 {
2521 TCGv zero = tcg_const_tl(0);
2522 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2523 zero, 0, 0, compute_ov, Rc(ctx->opcode));
2524 tcg_temp_free(zero);
2525 }
2526
2527 static void gen_neg(DisasContext *ctx)
2528 {
2529 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2530 if (unlikely(Rc(ctx->opcode))) {
2531 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2532 }
2533 }
2534
2535 static void gen_nego(DisasContext *ctx)
2536 {
2537 gen_op_arith_neg(ctx, 1);
2538 }
2539
2540 /*** Integer logical ***/
2541 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
2542 static void glue(gen_, name)(DisasContext *ctx) \
2543 { \
2544 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
2545 cpu_gpr[rB(ctx->opcode)]); \
2546 if (unlikely(Rc(ctx->opcode) != 0)) \
2547 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2548 }
2549
2550 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
2551 static void glue(gen_, name)(DisasContext *ctx) \
2552 { \
2553 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
2554 if (unlikely(Rc(ctx->opcode) != 0)) \
2555 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2556 }
2557
2558 /* and & and. */
2559 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
2560 /* andc & andc. */
2561 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
2562
2563 /* andi. */
2564 static void gen_andi_(DisasContext *ctx)
2565 {
2566 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2567 UIMM(ctx->opcode));
2568 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2569 }
2570
2571 /* andis. */
2572 static void gen_andis_(DisasContext *ctx)
2573 {
2574 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2575 UIMM(ctx->opcode) << 16);
2576 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2577 }
2578
2579 /* cntlzw */
2580 static void gen_cntlzw(DisasContext *ctx)
2581 {
2582 TCGv_i32 t = tcg_temp_new_i32();
2583
2584 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2585 tcg_gen_clzi_i32(t, t, 32);
2586 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2587 tcg_temp_free_i32(t);
2588
2589 if (unlikely(Rc(ctx->opcode) != 0)) {
2590 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2591 }
2592 }
2593
2594 /* cnttzw */
2595 static void gen_cnttzw(DisasContext *ctx)
2596 {
2597 TCGv_i32 t = tcg_temp_new_i32();
2598
2599 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2600 tcg_gen_ctzi_i32(t, t, 32);
2601 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2602 tcg_temp_free_i32(t);
2603
2604 if (unlikely(Rc(ctx->opcode) != 0)) {
2605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2606 }
2607 }
2608
2609 /* eqv & eqv. */
2610 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
2611 /* extsb & extsb. */
2612 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
2613 /* extsh & extsh. */
2614 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
2615 /* nand & nand. */
2616 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
2617 /* nor & nor. */
2618 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
2619
2620 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2621 static void gen_pause(DisasContext *ctx)
2622 {
2623 TCGv_i32 t0 = tcg_const_i32(0);
2624 tcg_gen_st_i32(t0, cpu_env,
2625 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
2626 tcg_temp_free_i32(t0);
2627
2628 /* Stop translation, this gives other CPUs a chance to run */
2629 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
2630 }
2631 #endif /* defined(TARGET_PPC64) */
2632
2633 /* or & or. */
2634 static void gen_or(DisasContext *ctx)
2635 {
2636 int rs, ra, rb;
2637
2638 rs = rS(ctx->opcode);
2639 ra = rA(ctx->opcode);
2640 rb = rB(ctx->opcode);
2641 /* Optimisation for mr. ri case */
2642 if (rs != ra || rs != rb) {
2643 if (rs != rb) {
2644 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
2645 } else {
2646 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
2647 }
2648 if (unlikely(Rc(ctx->opcode) != 0)) {
2649 gen_set_Rc0(ctx, cpu_gpr[ra]);
2650 }
2651 } else if (unlikely(Rc(ctx->opcode) != 0)) {
2652 gen_set_Rc0(ctx, cpu_gpr[rs]);
2653 #if defined(TARGET_PPC64)
2654 } else if (rs != 0) { /* 0 is nop */
2655 int prio = 0;
2656
2657 switch (rs) {
2658 case 1:
2659 /* Set process priority to low */
2660 prio = 2;
2661 break;
2662 case 6:
2663 /* Set process priority to medium-low */
2664 prio = 3;
2665 break;
2666 case 2:
2667 /* Set process priority to normal */
2668 prio = 4;
2669 break;
2670 #if !defined(CONFIG_USER_ONLY)
2671 case 31:
2672 if (!ctx->pr) {
2673 /* Set process priority to very low */
2674 prio = 1;
2675 }
2676 break;
2677 case 5:
2678 if (!ctx->pr) {
2679 /* Set process priority to medium-hight */
2680 prio = 5;
2681 }
2682 break;
2683 case 3:
2684 if (!ctx->pr) {
2685 /* Set process priority to high */
2686 prio = 6;
2687 }
2688 break;
2689 case 7:
2690 if (ctx->hv && !ctx->pr) {
2691 /* Set process priority to very high */
2692 prio = 7;
2693 }
2694 break;
2695 #endif
2696 default:
2697 break;
2698 }
2699 if (prio) {
2700 TCGv t0 = tcg_temp_new();
2701 gen_load_spr(t0, SPR_PPR);
2702 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
2703 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
2704 gen_store_spr(SPR_PPR, t0);
2705 tcg_temp_free(t0);
2706 }
2707 #if !defined(CONFIG_USER_ONLY)
2708 /*
2709 * Pause out of TCG otherwise spin loops with smt_low eat too
2710 * much CPU and the kernel hangs. This applies to all
2711 * encodings other than no-op, e.g., miso(rs=26), yield(27),
2712 * mdoio(29), mdoom(30), and all currently undefined.
2713 */
2714 gen_pause(ctx);
2715 #endif
2716 #endif
2717 }
2718 }
2719 /* orc & orc. */
2720 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
2721
2722 /* xor & xor. */
2723 static void gen_xor(DisasContext *ctx)
2724 {
2725 /* Optimisation for "set to zero" case */
2726 if (rS(ctx->opcode) != rB(ctx->opcode)) {
2727 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2728 cpu_gpr[rB(ctx->opcode)]);
2729 } else {
2730 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2731 }
2732 if (unlikely(Rc(ctx->opcode) != 0)) {
2733 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2734 }
2735 }
2736
2737 /* ori */
2738 static void gen_ori(DisasContext *ctx)
2739 {
2740 target_ulong uimm = UIMM(ctx->opcode);
2741
2742 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2743 return;
2744 }
2745 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2746 }
2747
2748 /* oris */
2749 static void gen_oris(DisasContext *ctx)
2750 {
2751 target_ulong uimm = UIMM(ctx->opcode);
2752
2753 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2754 /* NOP */
2755 return;
2756 }
2757 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2758 uimm << 16);
2759 }
2760
2761 /* xori */
2762 static void gen_xori(DisasContext *ctx)
2763 {
2764 target_ulong uimm = UIMM(ctx->opcode);
2765
2766 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2767 /* NOP */
2768 return;
2769 }
2770 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2771 }
2772
2773 /* xoris */
2774 static void gen_xoris(DisasContext *ctx)
2775 {
2776 target_ulong uimm = UIMM(ctx->opcode);
2777
2778 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2779 /* NOP */
2780 return;
2781 }
2782 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2783 uimm << 16);
2784 }
2785
2786 /* popcntb : PowerPC 2.03 specification */
2787 static void gen_popcntb(DisasContext *ctx)
2788 {
2789 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2790 }
2791
2792 static void gen_popcntw(DisasContext *ctx)
2793 {
2794 #if defined(TARGET_PPC64)
2795 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2796 #else
2797 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2798 #endif
2799 }
2800
2801 #if defined(TARGET_PPC64)
2802 /* popcntd: PowerPC 2.06 specification */
2803 static void gen_popcntd(DisasContext *ctx)
2804 {
2805 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2806 }
2807 #endif
2808
2809 /* prtyw: PowerPC 2.05 specification */
2810 static void gen_prtyw(DisasContext *ctx)
2811 {
2812 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2813 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2814 TCGv t0 = tcg_temp_new();
2815 tcg_gen_shri_tl(t0, rs, 16);
2816 tcg_gen_xor_tl(ra, rs, t0);
2817 tcg_gen_shri_tl(t0, ra, 8);
2818 tcg_gen_xor_tl(ra, ra, t0);
2819 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
2820 tcg_temp_free(t0);
2821 }
2822
2823 #if defined(TARGET_PPC64)
2824 /* prtyd: PowerPC 2.05 specification */
2825 static void gen_prtyd(DisasContext *ctx)
2826 {
2827 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2828 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2829 TCGv t0 = tcg_temp_new();
2830 tcg_gen_shri_tl(t0, rs, 32);
2831 tcg_gen_xor_tl(ra, rs, t0);
2832 tcg_gen_shri_tl(t0, ra, 16);
2833 tcg_gen_xor_tl(ra, ra, t0);
2834 tcg_gen_shri_tl(t0, ra, 8);
2835 tcg_gen_xor_tl(ra, ra, t0);
2836 tcg_gen_andi_tl(ra, ra, 1);
2837 tcg_temp_free(t0);
2838 }
2839 #endif
2840
2841 #if defined(TARGET_PPC64)
2842 /* bpermd */
2843 static void gen_bpermd(DisasContext *ctx)
2844 {
2845 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
2846 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2847 }
2848 #endif
2849
2850 #if defined(TARGET_PPC64)
2851 /* extsw & extsw. */
2852 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
2853
2854 /* cntlzd */
2855 static void gen_cntlzd(DisasContext *ctx)
2856 {
2857 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2858 if (unlikely(Rc(ctx->opcode) != 0)) {
2859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2860 }
2861 }
2862
2863 /* cnttzd */
2864 static void gen_cnttzd(DisasContext *ctx)
2865 {
2866 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2867 if (unlikely(Rc(ctx->opcode) != 0)) {
2868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2869 }
2870 }
2871
2872 /* darn */
2873 static void gen_darn(DisasContext *ctx)
2874 {
2875 int l = L(ctx->opcode);
2876
2877 if (l > 2) {
2878 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
2879 } else {
2880 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
2881 gen_io_start();
2882 }
2883 if (l == 0) {
2884 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
2885 } else {
2886 /* Return 64-bit random for both CRN and RRN */
2887 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
2888 }
2889 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
2890 gen_stop_exception(ctx);
2891 }
2892 }
2893 }
2894 #endif
2895
2896 /*** Integer rotate ***/
2897
2898 /* rlwimi & rlwimi. */
2899 static void gen_rlwimi(DisasContext *ctx)
2900 {
2901 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2902 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2903 uint32_t sh = SH(ctx->opcode);
2904 uint32_t mb = MB(ctx->opcode);
2905 uint32_t me = ME(ctx->opcode);
2906
2907 if (sh == (31 - me) && mb <= me) {
2908 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2909 } else {
2910 target_ulong mask;
2911 bool mask_in_32b = true;
2912 TCGv t1;
2913
2914 #if defined(TARGET_PPC64)
2915 mb += 32;
2916 me += 32;
2917 #endif
2918 mask = MASK(mb, me);
2919
2920 #if defined(TARGET_PPC64)
2921 if (mask > 0xffffffffu) {
2922 mask_in_32b = false;
2923 }
2924 #endif
2925 t1 = tcg_temp_new();
2926 if (mask_in_32b) {
2927 TCGv_i32 t0 = tcg_temp_new_i32();
2928 tcg_gen_trunc_tl_i32(t0, t_rs);
2929 tcg_gen_rotli_i32(t0, t0, sh);
2930 tcg_gen_extu_i32_tl(t1, t0);
2931 tcg_temp_free_i32(t0);
2932 } else {
2933 #if defined(TARGET_PPC64)
2934 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2935 tcg_gen_rotli_i64(t1, t1, sh);
2936 #else
2937 g_assert_not_reached();
2938 #endif
2939 }
2940
2941 tcg_gen_andi_tl(t1, t1, mask);
2942 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2943 tcg_gen_or_tl(t_ra, t_ra, t1);
2944 tcg_temp_free(t1);
2945 }
2946 if (unlikely(Rc(ctx->opcode) != 0)) {
2947 gen_set_Rc0(ctx, t_ra);
2948 }
2949 }
2950
2951 /* rlwinm & rlwinm. */
2952 static void gen_rlwinm(DisasContext *ctx)
2953 {
2954 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2955 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2956 int sh = SH(ctx->opcode);
2957 int mb = MB(ctx->opcode);
2958 int me = ME(ctx->opcode);
2959 int len = me - mb + 1;
2960 int rsh = (32 - sh) & 31;
2961
2962 if (sh != 0 && len > 0 && me == (31 - sh)) {
2963 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2964 } else if (me == 31 && rsh + len <= 32) {
2965 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2966 } else {
2967 target_ulong mask;
2968 bool mask_in_32b = true;
2969 #if defined(TARGET_PPC64)
2970 mb += 32;
2971 me += 32;
2972 #endif
2973 mask = MASK(mb, me);
2974 #if defined(TARGET_PPC64)
2975 if (mask > 0xffffffffu) {
2976 mask_in_32b = false;
2977 }
2978 #endif
2979 if (mask_in_32b) {
2980 if (sh == 0) {
2981 tcg_gen_andi_tl(t_ra, t_rs, mask);
2982 } else {
2983 TCGv_i32 t0 = tcg_temp_new_i32();
2984 tcg_gen_trunc_tl_i32(t0, t_rs);
2985 tcg_gen_rotli_i32(t0, t0, sh);
2986 tcg_gen_andi_i32(t0, t0, mask);
2987 tcg_gen_extu_i32_tl(t_ra, t0);
2988 tcg_temp_free_i32(t0);
2989 }
2990 } else {
2991 #if defined(TARGET_PPC64)
2992 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2993 tcg_gen_rotli_i64(t_ra, t_ra, sh);
2994 tcg_gen_andi_i64(t_ra, t_ra, mask);
2995 #else
2996 g_assert_not_reached();
2997 #endif
2998 }
2999 }
3000 if (unlikely(Rc(ctx->opcode) != 0)) {
3001 gen_set_Rc0(ctx, t_ra);
3002 }
3003 }
3004
3005 /* rlwnm & rlwnm. */
3006 static void gen_rlwnm(DisasContext *ctx)
3007 {
3008 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3009 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3010 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
3011 uint32_t mb = MB(ctx->opcode);
3012 uint32_t me = ME(ctx->opcode);
3013 target_ulong mask;
3014 bool mask_in_32b = true;
3015
3016 #if defined(TARGET_PPC64)
3017 mb += 32;
3018 me += 32;
3019 #endif
3020 mask = MASK(mb, me);
3021
3022 #if defined(TARGET_PPC64)
3023 if (mask > 0xffffffffu) {
3024 mask_in_32b = false;
3025 }
3026 #endif
3027 if (mask_in_32b) {
3028 TCGv_i32 t0 = tcg_temp_new_i32();
3029 TCGv_i32 t1 = tcg_temp_new_i32();
3030 tcg_gen_trunc_tl_i32(t0, t_rb);
3031 tcg_gen_trunc_tl_i32(t1, t_rs);
3032 tcg_gen_andi_i32(t0, t0, 0x1f);
3033 tcg_gen_rotl_i32(t1, t1, t0);
3034 tcg_gen_extu_i32_tl(t_ra, t1);
3035 tcg_temp_free_i32(t0);
3036 tcg_temp_free_i32(t1);
3037 } else {
3038 #if defined(TARGET_PPC64)
3039 TCGv_i64 t0 = tcg_temp_new_i64();
3040 tcg_gen_andi_i64(t0, t_rb, 0x1f);
3041 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
3042 tcg_gen_rotl_i64(t_ra, t_ra, t0);
3043 tcg_temp_free_i64(t0);
3044 #else
3045 g_assert_not_reached();
3046 #endif
3047 }
3048
3049 tcg_gen_andi_tl(t_ra, t_ra, mask);
3050
3051 if (unlikely(Rc(ctx->opcode) != 0)) {
3052 gen_set_Rc0(ctx, t_ra);
3053 }
3054 }
3055
3056 #if defined(TARGET_PPC64)
3057 #define GEN_PPC64_R2(name, opc1, opc2) \
3058 static void glue(gen_, name##0)(DisasContext *ctx) \
3059 { \
3060 gen_##name(ctx, 0); \
3061 } \
3062 \
3063 static void glue(gen_, name##1)(DisasContext *ctx) \
3064 { \
3065 gen_##name(ctx, 1); \
3066 }
3067 #define GEN_PPC64_R4(name, opc1, opc2) \
3068 static void glue(gen_, name##0)(DisasContext *ctx) \
3069 { \
3070 gen_##name(ctx, 0, 0); \
3071 } \
3072 \
3073 static void glue(gen_, name##1)(DisasContext *ctx) \
3074 { \
3075 gen_##name(ctx, 0, 1); \
3076 } \
3077 \
3078 static void glue(gen_, name##2)(DisasContext *ctx) \
3079 { \
3080 gen_##name(ctx, 1, 0); \
3081 } \
3082 \
3083 static void glue(gen_, name##3)(DisasContext *ctx) \
3084 { \
3085 gen_##name(ctx, 1, 1); \
3086 }
3087
3088 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
3089 {
3090 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3091 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3092 int len = me - mb + 1;
3093 int rsh = (64 - sh) & 63;
3094
3095 if (sh != 0 && len > 0 && me == (63 - sh)) {
3096 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
3097 } else if (me == 63 && rsh + len <= 64) {
3098 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
3099 } else {
3100 tcg_gen_rotli_tl(t_ra, t_rs, sh);
3101 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
3102 }
3103 if (unlikely(Rc(ctx->opcode) != 0)) {
3104 gen_set_Rc0(ctx, t_ra);
3105 }
3106 }
3107
3108 /* rldicl - rldicl. */
3109 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
3110 {
3111 uint32_t sh, mb;
3112
3113 sh = SH(ctx->opcode) | (shn << 5);
3114 mb = MB(ctx->opcode) | (mbn << 5);
3115 gen_rldinm(ctx, mb, 63, sh);
3116 }
3117 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
3118
3119 /* rldicr - rldicr. */
3120 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
3121 {
3122 uint32_t sh, me;
3123
3124 sh = SH(ctx->opcode) | (shn << 5);
3125 me = MB(ctx->opcode) | (men << 5);
3126 gen_rldinm(ctx, 0, me, sh);
3127 }
3128 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
3129
3130 /* rldic - rldic. */
3131 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
3132 {
3133 uint32_t sh, mb;
3134
3135 sh = SH(ctx->opcode) | (shn << 5);
3136 mb = MB(ctx->opcode) | (mbn << 5);
3137 gen_rldinm(ctx, mb, 63 - sh, sh);
3138 }
3139 GEN_PPC64_R4(rldic, 0x1E, 0x04);
3140
3141 static void gen_rldnm(DisasContext *ctx, int mb, int me)
3142 {
3143 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3144 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3145 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
3146 TCGv t0;
3147
3148 t0 = tcg_temp_new();
3149 tcg_gen_andi_tl(t0, t_rb, 0x3f);
3150 tcg_gen_rotl_tl(t_ra, t_rs, t0);
3151 tcg_temp_free(t0);
3152
3153 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
3154 if (unlikely(Rc(ctx->opcode) != 0)) {
3155 gen_set_Rc0(ctx, t_ra);
3156 }
3157 }
3158
3159 /* rldcl - rldcl. */
3160 static inline void gen_rldcl(DisasContext *ctx, int mbn)
3161 {
3162 uint32_t mb;
3163
3164 mb = MB(ctx->opcode) | (mbn << 5);
3165 gen_rldnm(ctx, mb, 63);
3166 }
3167 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
3168
3169 /* rldcr - rldcr. */
3170 static inline void gen_rldcr(DisasContext *ctx, int men)
3171 {
3172 uint32_t me;
3173
3174 me = MB(ctx->opcode) | (men << 5);
3175 gen_rldnm(ctx, 0, me);
3176 }
3177 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
3178
3179 /* rldimi - rldimi. */
3180 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
3181 {
3182 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3183 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3184 uint32_t sh = SH(ctx->opcode) | (shn << 5);
3185 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
3186 uint32_t me = 63 - sh;
3187
3188 if (mb <= me) {
3189 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
3190 } else {
3191 target_ulong mask = MASK(mb, me);
3192 TCGv t1 = tcg_temp_new();
3193
3194 tcg_gen_rotli_tl(t1, t_rs, sh);
3195 tcg_gen_andi_tl(t1, t1, mask);
3196 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
3197 tcg_gen_or_tl(t_ra, t_ra, t1);
3198 tcg_temp_free(t1);
3199 }
3200 if (unlikely(Rc(ctx->opcode) != 0)) {
3201 gen_set_Rc0(ctx, t_ra);
3202 }
3203 }
3204 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
3205 #endif
3206
3207 /*** Integer shift ***/
3208
3209 /* slw & slw. */
3210 static void gen_slw(DisasContext *ctx)
3211 {
3212 TCGv t0, t1;
3213
3214 t0 = tcg_temp_new();
3215 /* AND rS with a mask that is 0 when rB >= 0x20 */
3216 #if defined(TARGET_PPC64)
3217 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
3218 tcg_gen_sari_tl(t0, t0, 0x3f);
3219 #else
3220 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
3221 tcg_gen_sari_tl(t0, t0, 0x1f);
3222 #endif
3223 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3224 t1 = tcg_temp_new();
3225 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
3226 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3227 tcg_temp_free(t1);
3228 tcg_temp_free(t0);
3229 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
3230 if (unlikely(Rc(ctx->opcode) != 0)) {
3231 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3232 }
3233 }
3234
3235 /* sraw & sraw. */
3236 static void gen_sraw(DisasContext *ctx)
3237 {
3238 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
3239 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3240 if (unlikely(Rc(ctx->opcode) != 0)) {
3241 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3242 }
3243 }
3244
3245 /* srawi & srawi. */
3246 static void gen_srawi(DisasContext *ctx)
3247 {
3248 int sh = SH(ctx->opcode);
3249 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3250 TCGv src = cpu_gpr[rS(ctx->opcode)];
3251 if (sh == 0) {
3252 tcg_gen_ext32s_tl(dst, src);
3253 tcg_gen_movi_tl(cpu_ca, 0);
3254 if (is_isa300(ctx)) {
3255 tcg_gen_movi_tl(cpu_ca32, 0);
3256 }
3257 } else {
3258 TCGv t0;
3259 tcg_gen_ext32s_tl(dst, src);
3260 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
3261 t0 = tcg_temp_new();
3262 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
3263 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3264 tcg_temp_free(t0);
3265 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
3266 if (is_isa300(ctx)) {
3267 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3268 }
3269 tcg_gen_sari_tl(dst, dst, sh);
3270 }
3271 if (unlikely(Rc(ctx->opcode) != 0)) {
3272 gen_set_Rc0(ctx, dst);
3273 }
3274 }
3275
3276 /* srw & srw. */
3277 static void gen_srw(DisasContext *ctx)
3278 {
3279 TCGv t0, t1;
3280
3281 t0 = tcg_temp_new();
3282 /* AND rS with a mask that is 0 when rB >= 0x20 */
3283 #if defined(TARGET_PPC64)
3284 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
3285 tcg_gen_sari_tl(t0, t0, 0x3f);
3286 #else
3287 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
3288 tcg_gen_sari_tl(t0, t0, 0x1f);
3289 #endif
3290 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3291 tcg_gen_ext32u_tl(t0, t0);
3292 t1 = tcg_temp_new();
3293 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
3294 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3295 tcg_temp_free(t1);
3296 tcg_temp_free(t0);
3297 if (unlikely(Rc(ctx->opcode) != 0)) {
3298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3299 }
3300 }
3301
3302 #if defined(TARGET_PPC64)
3303 /* sld & sld. */
3304 static void gen_sld(DisasContext *ctx)
3305 {
3306 TCGv t0, t1;
3307
3308 t0 = tcg_temp_new();
3309 /* AND rS with a mask that is 0 when rB >= 0x40 */
3310 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3311 tcg_gen_sari_tl(t0, t0, 0x3f);
3312 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3313 t1 = tcg_temp_new();
3314 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3315 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3316 tcg_temp_free(t1);
3317 tcg_temp_free(t0);
3318 if (unlikely(Rc(ctx->opcode) != 0)) {
3319 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3320 }
3321 }
3322
3323 /* srad & srad. */
3324 static void gen_srad(DisasContext *ctx)
3325 {
3326 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
3327 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3328 if (unlikely(Rc(ctx->opcode) != 0)) {
3329 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3330 }
3331 }
3332 /* sradi & sradi. */
3333 static inline void gen_sradi(DisasContext *ctx, int n)
3334 {
3335 int sh = SH(ctx->opcode) + (n << 5);
3336 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3337 TCGv src = cpu_gpr[rS(ctx->opcode)];
3338 if (sh == 0) {
3339 tcg_gen_mov_tl(dst, src);
3340 tcg_gen_movi_tl(cpu_ca, 0);
3341 if (is_isa300(ctx)) {
3342 tcg_gen_movi_tl(cpu_ca32, 0);
3343 }
3344 } else {
3345 TCGv t0;
3346 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
3347 t0 = tcg_temp_new();
3348 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
3349 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3350 tcg_temp_free(t0);
3351 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
3352 if (is_isa300(ctx)) {
3353 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3354 }
3355 tcg_gen_sari_tl(dst, src, sh);
3356 }
3357 if (unlikely(Rc(ctx->opcode) != 0)) {
3358 gen_set_Rc0(ctx, dst);
3359 }
3360 }
3361
3362 static void gen_sradi0(DisasContext *ctx)
3363 {
3364 gen_sradi(ctx, 0);
3365 }
3366
3367 static void gen_sradi1(DisasContext *ctx)
3368 {
3369 gen_sradi(ctx, 1);
3370 }
3371
3372 /* extswsli & extswsli. */
3373 static inline void gen_extswsli(DisasContext *ctx, int n)
3374 {
3375 int sh = SH(ctx->opcode) + (n << 5);
3376 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3377 TCGv src = cpu_gpr[rS(ctx->opcode)];
3378
3379 tcg_gen_ext32s_tl(dst, src);
3380 tcg_gen_shli_tl(dst, dst, sh);
3381 if (unlikely(Rc(ctx->opcode) != 0)) {
3382 gen_set_Rc0(ctx, dst);
3383 }
3384 }
3385
3386 static void gen_extswsli0(DisasContext *ctx)
3387 {
3388 gen_extswsli(ctx, 0);
3389 }
3390
3391 static void gen_extswsli1(DisasContext *ctx)
3392 {
3393 gen_extswsli(ctx, 1);
3394 }
3395
3396 /* srd & srd. */
3397 static void gen_srd(DisasContext *ctx)
3398 {
3399 TCGv t0, t1;
3400
3401 t0 = tcg_temp_new();
3402 /* AND rS with a mask that is 0 when rB >= 0x40 */
3403 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3404 tcg_gen_sari_tl(t0, t0, 0x3f);
3405 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3406 t1 = tcg_temp_new();
3407 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3408 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3409 tcg_temp_free(t1);
3410 tcg_temp_free(t0);
3411 if (unlikely(Rc(ctx->opcode) != 0)) {
3412 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3413 }
3414 }
3415 #endif
3416
3417 /*** Addressing modes ***/
3418 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
3419 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
3420 target_long maskl)
3421 {
3422 target_long simm = SIMM(ctx->opcode);
3423
3424 simm &= ~maskl;
3425 if (rA(ctx->opcode) == 0) {
3426 if (NARROW_MODE(ctx)) {
3427 simm = (uint32_t)simm;
3428 }
3429 tcg_gen_movi_tl(EA, simm);
3430 } else if (likely(simm != 0)) {
3431 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
3432 if (NARROW_MODE(ctx)) {
3433 tcg_gen_ext32u_tl(EA, EA);
3434 }
3435 } else {
3436 if (NARROW_MODE(ctx)) {
3437 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3438 } else {
3439 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3440 }
3441 }
3442 }
3443
3444 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
3445 {
3446 if (rA(ctx->opcode) == 0) {
3447 if (NARROW_MODE(ctx)) {
3448 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3449 } else {
3450 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3451 }
3452 } else {
3453 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3454 if (NARROW_MODE(ctx)) {
3455 tcg_gen_ext32u_tl(EA, EA);
3456 }
3457 }
3458 }
3459
3460 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
3461 {
3462 if (rA(ctx->opcode) == 0) {
3463 tcg_gen_movi_tl(EA, 0);
3464 } else if (NARROW_MODE(ctx)) {
3465 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3466 } else {
3467 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3468 }
3469 }
3470
3471 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
3472 target_long val)
3473 {
3474 tcg_gen_addi_tl(ret, arg1, val);
3475 if (NARROW_MODE(ctx)) {
3476 tcg_gen_ext32u_tl(ret, ret);
3477 }
3478 }
3479
3480 static inline void gen_align_no_le(DisasContext *ctx)
3481 {
3482 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
3483 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
3484 }
3485
3486 /*** Integer load ***/
3487 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
3488 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
3489
3490 #define GEN_QEMU_LOAD_TL(ldop, op) \
3491 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
3492 TCGv val, \
3493 TCGv addr) \
3494 { \
3495 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
3496 }
3497
3498 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
3499 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
3500 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
3501 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
3502 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
3503
3504 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
3505 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
3506
3507 #define GEN_QEMU_LOAD_64(ldop, op) \
3508 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
3509 TCGv_i64 val, \
3510 TCGv addr) \
3511 { \
3512 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
3513 }
3514
3515 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
3516 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
3517 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
3518 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
3519 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
3520
3521 #if defined(TARGET_PPC64)
3522 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
3523 #endif
3524
3525 #define GEN_QEMU_STORE_TL(stop, op) \
3526 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
3527 TCGv val, \
3528 TCGv addr) \
3529 { \
3530 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
3531 }
3532
3533 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
3534 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
3535 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
3536
3537 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
3538 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
3539
3540 #define GEN_QEMU_STORE_64(stop, op) \
3541 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
3542 TCGv_i64 val, \
3543 TCGv addr) \
3544 { \
3545 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
3546 }
3547
3548 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
3549 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
3550 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
3551 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
3552
3553 #if defined(TARGET_PPC64)
3554 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
3555 #endif
3556
3557 #define GEN_LD(name, ldop, opc, type) \
3558 static void glue(gen_, name)(DisasContext *ctx) \
3559 { \
3560 TCGv EA; \
3561 gen_set_access_type(ctx, ACCESS_INT); \
3562 EA = tcg_temp_new(); \
3563 gen_addr_imm_index(ctx, EA, 0); \
3564 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3565 tcg_temp_free(EA); \
3566 }
3567
3568 #define GEN_LDU(name, ldop, opc, type) \
3569 static void glue(gen_, name##u)(DisasContext *ctx) \
3570 { \
3571 TCGv EA; \
3572 if (unlikely(rA(ctx->opcode) == 0 || \
3573 rA(ctx->opcode) == rD(ctx->opcode))) { \
3574 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3575 return; \
3576 } \
3577 gen_set_access_type(ctx, ACCESS_INT); \
3578 EA = tcg_temp_new(); \
3579 if (type == PPC_64B) \
3580 gen_addr_imm_index(ctx, EA, 0x03); \
3581 else \
3582 gen_addr_imm_index(ctx, EA, 0); \
3583 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3584 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3585 tcg_temp_free(EA); \
3586 }
3587
3588 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
3589 static void glue(gen_, name##ux)(DisasContext *ctx) \
3590 { \
3591 TCGv EA; \
3592 if (unlikely(rA(ctx->opcode) == 0 || \
3593 rA(ctx->opcode) == rD(ctx->opcode))) { \
3594 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3595 return; \
3596 } \
3597 gen_set_access_type(ctx, ACCESS_INT); \
3598 EA = tcg_temp_new(); \
3599 gen_addr_reg_index(ctx, EA); \
3600 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3601 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3602 tcg_temp_free(EA); \
3603 }
3604
3605 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
3606 static void glue(gen_, name##x)(DisasContext *ctx) \
3607 { \
3608 TCGv EA; \
3609 chk; \
3610 gen_set_access_type(ctx, ACCESS_INT); \
3611 EA = tcg_temp_new(); \
3612 gen_addr_reg_index(ctx, EA); \
3613 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3614 tcg_temp_free(EA); \
3615 }
3616
3617 #define GEN_LDX(name, ldop, opc2, opc3, type) \
3618 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3619
3620 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
3621 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3622
3623 #define GEN_LDS(name, ldop, op, type) \
3624 GEN_LD(name, ldop, op | 0x20, type); \
3625 GEN_LDU(name, ldop, op | 0x21, type); \
3626 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
3627 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
3628
3629 /* lbz lbzu lbzux lbzx */
3630 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
3631 /* lha lhau lhaux lhax */
3632 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
3633 /* lhz lhzu lhzux lhzx */
3634 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
3635 /* lwz lwzu lwzux lwzx */
3636 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
3637
3638 #define GEN_LDEPX(name, ldop, opc2, opc3) \
3639 static void glue(gen_, name##epx)(DisasContext *ctx) \
3640 { \
3641 TCGv EA; \
3642 CHK_SV; \
3643 gen_set_access_type(ctx, ACCESS_INT); \
3644 EA = tcg_temp_new(); \
3645 gen_addr_reg_index(ctx, EA); \
3646 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3647 tcg_temp_free(EA); \
3648 }
3649
3650 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
3651 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
3652 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
3653 #if defined(TARGET_PPC64)
3654 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
3655 #endif
3656
3657 #if defined(TARGET_PPC64)
3658 /* lwaux */
3659 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
3660 /* lwax */
3661 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
3662 /* ldux */
3663 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
3664 /* ldx */
3665 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
3666
3667 /* CI load/store variants */
3668 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
3669 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3670 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3671 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3672
3673 static void gen_ld(DisasContext *ctx)
3674 {
3675 TCGv EA;
3676 if (Rc(ctx->opcode)) {
3677 if (unlikely(rA(ctx->opcode) == 0 ||
3678 rA(ctx->opcode) == rD(ctx->opcode))) {
3679 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3680 return;
3681 }
3682 }
3683 gen_set_access_type(ctx, ACCESS_INT);
3684 EA = tcg_temp_new();
3685 gen_addr_imm_index(ctx, EA, 0x03);
3686 if (ctx->opcode & 0x02) {
3687 /* lwa (lwau is undefined) */
3688 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3689 } else {
3690 /* ld - ldu */
3691 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3692 }
3693 if (Rc(ctx->opcode)) {
3694 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3695 }
3696 tcg_temp_free(EA);
3697 }
3698
3699 /* lq */
3700 static void gen_lq(DisasContext *ctx)
3701 {
3702 int ra, rd;
3703 TCGv EA, hi, lo;
3704
3705 /* lq is a legal user mode instruction starting in ISA 2.07 */
3706 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3707 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3708
3709 if (!legal_in_user_mode && ctx->pr) {
3710 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3711 return;
3712 }
3713
3714 if (!le_is_supported && ctx->le_mode) {
3715 gen_align_no_le(ctx);
3716 return;
3717 }
3718 ra = rA(ctx->opcode);
3719 rd = rD(ctx->opcode);
3720 if (unlikely((rd & 1) || rd == ra)) {
3721 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3722 return;
3723 }
3724
3725 gen_set_access_type(ctx, ACCESS_INT);
3726 EA = tcg_temp_new();
3727 gen_addr_imm_index(ctx, EA, 0x0F);
3728
3729 /* Note that the low part is always in RD+1, even in LE mode. */
3730 lo = cpu_gpr[rd + 1];
3731 hi = cpu_gpr[rd];
3732
3733 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3734 if (HAVE_ATOMIC128) {
3735 TCGv_i32 oi = tcg_temp_new_i32();
3736 if (ctx->le_mode) {
3737 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
3738 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3739 } else {
3740 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
3741 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3742 }
3743 tcg_temp_free_i32(oi);
3744 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3745 } else {
3746 /* Restart with exclusive lock. */
3747 gen_helper_exit_atomic(cpu_env);
3748 ctx->base.is_jmp = DISAS_NORETURN;
3749 }
3750 } else if (ctx->le_mode) {
3751 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
3752 gen_addr_add(ctx, EA, EA, 8);
3753 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3754 } else {
3755 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
3756 gen_addr_add(ctx, EA, EA, 8);
3757 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3758 }
3759 tcg_temp_free(EA);
3760 }
3761 #endif
3762
3763 /*** Integer store ***/
3764 #define GEN_ST(name, stop, opc, type) \
3765 static void glue(gen_, name)(DisasContext *ctx) \
3766 { \
3767 TCGv EA; \
3768 gen_set_access_type(ctx, ACCESS_INT); \
3769 EA = tcg_temp_new(); \
3770 gen_addr_imm_index(ctx, EA, 0); \
3771 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3772 tcg_temp_free(EA); \
3773 }
3774
3775 #define GEN_STU(name, stop, opc, type) \
3776 static void glue(gen_, stop##u)(DisasContext *ctx) \
3777 { \
3778 TCGv EA; \
3779 if (unlikely(rA(ctx->opcode) == 0)) { \
3780 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3781 return; \
3782 } \
3783 gen_set_access_type(ctx, ACCESS_INT); \
3784 EA = tcg_temp_new(); \
3785 if (type == PPC_64B) \
3786 gen_addr_imm_index(ctx, EA, 0x03); \
3787 else \
3788 gen_addr_imm_index(ctx, EA, 0); \
3789 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3791 tcg_temp_free(EA); \
3792 }
3793
3794 #define GEN_STUX(name, stop, opc2, opc3, type) \
3795 static void glue(gen_, name##ux)(DisasContext *ctx) \
3796 { \
3797 TCGv EA; \
3798 if (unlikely(rA(ctx->opcode) == 0)) { \
3799 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3800 return; \
3801 } \
3802 gen_set_access_type(ctx, ACCESS_INT); \
3803 EA = tcg_temp_new(); \
3804 gen_addr_reg_index(ctx, EA); \
3805 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3807 tcg_temp_free(EA); \
3808 }
3809
3810 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3811 static void glue(gen_, name##x)(DisasContext *ctx) \
3812 { \
3813 TCGv EA; \
3814 chk; \
3815 gen_set_access_type(ctx, ACCESS_INT); \
3816 EA = tcg_temp_new(); \
3817 gen_addr_reg_index(ctx, EA); \
3818 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3819 tcg_temp_free(EA); \
3820 }
3821 #define GEN_STX(name, stop, opc2, opc3, type) \
3822 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3823
3824 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3825 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3826
3827 #define GEN_STS(name, stop, op, type) \
3828 GEN_ST(name, stop, op | 0x20, type); \
3829 GEN_STU(name, stop, op | 0x21, type); \
3830 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3831 GEN_STX(name, stop, 0x17, op | 0x00, type)
3832
3833 /* stb stbu stbux stbx */
3834 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3835 /* sth sthu sthux sthx */
3836 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3837 /* stw stwu stwux stwx */
3838 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3839
3840 #define GEN_STEPX(name, stop, opc2, opc3) \
3841 static void glue(gen_, name##epx)(DisasContext *ctx) \
3842 { \
3843 TCGv EA; \
3844 CHK_SV; \
3845 gen_set_access_type(ctx, ACCESS_INT); \
3846 EA = tcg_temp_new(); \
3847 gen_addr_reg_index(ctx, EA); \
3848 tcg_gen_qemu_st_tl( \
3849 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
3850 tcg_temp_free(EA); \
3851 }
3852
3853 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
3854 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
3855 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
3856 #if defined(TARGET_PPC64)
3857 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
3858 #endif
3859
3860 #if defined(TARGET_PPC64)
3861 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
3862 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
3863 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
3864 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3865 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3866 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3867
3868 static void gen_std(DisasContext *ctx)
3869 {
3870 int rs;
3871 TCGv EA;
3872
3873 rs = rS(ctx->opcode);
3874 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3875 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3876 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3877 TCGv hi, lo;
3878
3879 if (!(ctx->insns_flags & PPC_64BX)) {
3880 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3881 }
3882
3883 if (!legal_in_user_mode && ctx->pr) {
3884 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3885 return;
3886 }
3887
3888 if (!le_is_supported && ctx->le_mode) {
3889 gen_align_no_le(ctx);
3890 return;
3891 }
3892
3893 if (unlikely(rs & 1)) {
3894 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3895 return;
3896 }
3897 gen_set_access_type(ctx, ACCESS_INT);
3898 EA = tcg_temp_new();
3899 gen_addr_imm_index(ctx, EA, 0x03);
3900
3901 /* Note that the low part is always in RS+1, even in LE mode. */
3902 lo = cpu_gpr[rs + 1];
3903 hi = cpu_gpr[rs];
3904
3905 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3906 if (HAVE_ATOMIC128) {
3907 TCGv_i32 oi = tcg_temp_new_i32();
3908 if (ctx->le_mode) {
3909 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
3910 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
3911 } else {
3912 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
3913 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
3914 }
3915 tcg_temp_free_i32(oi);
3916 } else {
3917 /* Restart with exclusive lock. */
3918 gen_helper_exit_atomic(cpu_env);
3919 ctx->base.is_jmp = DISAS_NORETURN;
3920 }
3921 } else if (ctx->le_mode) {
3922 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
3923 gen_addr_add(ctx, EA, EA, 8);
3924 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3925 } else {
3926 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
3927 gen_addr_add(ctx, EA, EA, 8);
3928 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3929 }
3930 tcg_temp_free(EA);
3931 } else {
3932 /* std / stdu */
3933 if (Rc(ctx->opcode)) {
3934 if (unlikely(rA(ctx->opcode) == 0)) {
3935 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3936 return;
3937 }
3938 }
3939 gen_set_access_type(ctx, ACCESS_INT);
3940 EA = tcg_temp_new();
3941 gen_addr_imm_index(ctx, EA, 0x03);
3942 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
3943 if (Rc(ctx->opcode)) {
3944 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3945 }
3946 tcg_temp_free(EA);
3947 }
3948 }
3949 #endif
3950 /*** Integer load and store with byte reverse ***/
3951
3952 /* lhbrx */
3953 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3954
3955 /* lwbrx */
3956 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3957
3958 #if defined(TARGET_PPC64)
3959 /* ldbrx */
3960 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3961 /* stdbrx */
3962 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3963 #endif /* TARGET_PPC64 */
3964
3965 /* sthbrx */
3966 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3967 /* stwbrx */
3968 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3969
3970 /*** Integer load and store multiple ***/
3971
3972 /* lmw */
3973 static void gen_lmw(DisasContext *ctx)
3974 {
3975 TCGv t0;
3976 TCGv_i32 t1;
3977
3978 if (ctx->le_mode) {
3979 gen_align_no_le(ctx);
3980 return;
3981 }
3982 gen_set_access_type(ctx, ACCESS_INT);
3983 t0 = tcg_temp_new();
3984 t1 = tcg_const_i32(rD(ctx->opcode));
3985 gen_addr_imm_index(ctx, t0, 0);
3986 gen_helper_lmw(cpu_env, t0, t1);
3987 tcg_temp_free(t0);
3988 tcg_temp_free_i32(t1);
3989 }
3990
3991 /* stmw */
3992 static void gen_stmw(DisasContext *ctx)
3993 {
3994 TCGv t0;
3995 TCGv_i32 t1;
3996
3997 if (ctx->le_mode) {
3998 gen_align_no_le(ctx);
3999 return;
4000 }
4001 gen_set_access_type(ctx, ACCESS_INT);
4002 t0 = tcg_temp_new();
4003 t1 = tcg_const_i32(rS(ctx->opcode));
4004 gen_addr_imm_index(ctx, t0, 0);
4005 gen_helper_stmw(cpu_env, t0, t1);
4006 tcg_temp_free(t0);
4007 tcg_temp_free_i32(t1);
4008 }
4009
4010 /*** Integer load and store strings ***/
4011
4012 /* lswi */
4013 /*
4014 * PowerPC32 specification says we must generate an exception if rA is
4015 * in the range of registers to be loaded. In an other hand, IBM says
4016 * this is valid, but rA won't be loaded. For now, I'll follow the
4017 * spec...
4018 */
4019 static void gen_lswi(DisasContext *ctx)
4020 {
4021 TCGv t0;
4022 TCGv_i32 t1, t2;
4023 int nb = NB(ctx->opcode);
4024 int start = rD(ctx->opcode);
4025 int ra = rA(ctx->opcode);
4026 int nr;
4027
4028 if (ctx->le_mode) {
4029 gen_align_no_le(ctx);
4030 return;
4031 }
4032 if (nb == 0) {
4033 nb = 32;
4034 }
4035 nr = DIV_ROUND_UP(nb, 4);
4036 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
4037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4038 return;
4039 }
4040 gen_set_access_type(ctx, ACCESS_INT);
4041 t0 = tcg_temp_new();
4042 gen_addr_register(ctx, t0);
4043 t1 = tcg_const_i32(nb);
4044 t2 = tcg_const_i32(start);
4045 gen_helper_lsw(cpu_env, t0, t1, t2);
4046 tcg_temp_free(t0);
4047 tcg_temp_free_i32(t1);
4048 tcg_temp_free_i32(t2);
4049 }
4050
4051 /* lswx */
4052 static void gen_lswx(DisasContext *ctx)
4053 {
4054 TCGv t0;
4055 TCGv_i32 t1, t2, t3;
4056
4057 if (ctx->le_mode) {
4058 gen_align_no_le(ctx);
4059 return;
4060 }
4061 gen_set_access_type(ctx, ACCESS_INT);
4062 t0 = tcg_temp_new();
4063 gen_addr_reg_index(ctx, t0);
4064 t1 = tcg_const_i32(rD(ctx->opcode));
4065 t2 = tcg_const_i32(rA(ctx->opcode));
4066 t3 = tcg_const_i32(rB(ctx->opcode));
4067 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
4068 tcg_temp_free(t0);
4069 tcg_temp_free_i32(t1);
4070 tcg_temp_free_i32(t2);
4071 tcg_temp_free_i32(t3);
4072 }
4073
4074 /* stswi */
4075 static void gen_stswi(DisasContext *ctx)
4076 {
4077 TCGv t0;
4078 TCGv_i32 t1, t2;
4079 int nb = NB(ctx->opcode);
4080
4081 if (ctx->le_mode) {
4082 gen_align_no_le(ctx);
4083 return;
4084 }
4085 gen_set_access_type(ctx, ACCESS_INT);
4086 t0 = tcg_temp_new();
4087 gen_addr_register(ctx, t0);
4088 if (nb == 0) {
4089 nb = 32;
4090 }
4091 t1 = tcg_const_i32(nb);
4092 t2 = tcg_const_i32(rS(ctx->opcode));
4093 gen_helper_stsw(cpu_env, t0, t1, t2);
4094 tcg_temp_free(t0);
4095 tcg_temp_free_i32(t1);
4096 tcg_temp_free_i32(t2);
4097 }
4098
4099 /* stswx */
4100 static void gen_stswx(DisasContext *ctx)
4101 {
4102 TCGv t0;
4103 TCGv_i32 t1, t2;
4104
4105 if (ctx->le_mode) {
4106 gen_align_no_le(ctx);
4107 return;
4108 }
4109 gen_set_access_type(ctx, ACCESS_INT);
4110 t0 = tcg_temp_new();
4111 gen_addr_reg_index(ctx, t0);
4112 t1 = tcg_temp_new_i32();
4113 tcg_gen_trunc_tl_i32(t1, cpu_xer);
4114 tcg_gen_andi_i32(t1, t1, 0x7F);
4115 t2 = tcg_const_i32(rS(ctx->opcode));
4116 gen_helper_stsw(cpu_env, t0, t1, t2);
4117 tcg_temp_free(t0);
4118 tcg_temp_free_i32(t1);
4119 tcg_temp_free_i32(t2);
4120 }
4121
4122 /*** Memory synchronisation ***/
4123 /* eieio */
4124 static void gen_eieio(DisasContext *ctx)
4125 {
4126 TCGBar bar = TCG_MO_LD_ST;
4127
4128 /*
4129 * POWER9 has a eieio instruction variant using bit 6 as a hint to
4130 * tell the CPU it is a store-forwarding barrier.
4131 */
4132 if (ctx->opcode & 0x2000000) {
4133 /*
4134 * ISA says that "Reserved fields in instructions are ignored
4135 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
4136 * as this is not an instruction software should be using,
4137 * complain to the user.
4138 */
4139 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
4140 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
4141 TARGET_FMT_lx "\n", ctx->cia);
4142 } else {
4143 bar = TCG_MO_ST_LD;
4144 }
4145 }
4146
4147 tcg_gen_mb(bar | TCG_BAR_SC);
4148 }
4149
4150 #if !defined(CONFIG_USER_ONLY)
4151 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
4152 {
4153 TCGv_i32 t;
4154 TCGLabel *l;
4155
4156 if (!ctx->lazy_tlb_flush) {
4157 return;
4158 }
4159 l = gen_new_label();
4160 t = tcg_temp_new_i32();
4161 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4162 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
4163 if (global) {
4164 gen_helper_check_tlb_flush_global(cpu_env);
4165 } else {
4166 gen_helper_check_tlb_flush_local(cpu_env);
4167 }
4168 gen_set_label(l);
4169 tcg_temp_free_i32(t);
4170 }
4171 #else
4172 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
4173 #endif
4174
4175 /* isync */
4176 static void gen_isync(DisasContext *ctx)
4177 {
4178 /*
4179 * We need to check for a pending TLB flush. This can only happen in
4180 * kernel mode however so check MSR_PR
4181 */
4182 if (!ctx->pr) {
4183 gen_check_tlb_flush(ctx, false);
4184 }
4185 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
4186 gen_stop_exception(ctx);
4187 }
4188
4189 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
4190
4191 static void gen_load_locked(DisasContext *ctx, MemOp memop)
4192 {
4193 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
4194 TCGv t0 = tcg_temp_new();
4195
4196 gen_set_access_type(ctx, ACCESS_RES);
4197 gen_addr_reg_index(ctx, t0);
4198 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
4199 tcg_gen_mov_tl(cpu_reserve, t0);
4200 tcg_gen_mov_tl(cpu_reserve_val, gpr);
4201 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
4202 tcg_temp_free(t0);
4203 }
4204
4205 #define LARX(name, memop) \
4206 static void gen_##name(DisasContext *ctx) \
4207 { \
4208 gen_load_locked(ctx, memop); \
4209 }
4210
4211 /* lwarx */
4212 LARX(lbarx, DEF_MEMOP(MO_UB))
4213 LARX(lharx, DEF_MEMOP(MO_UW))
4214 LARX(lwarx, DEF_MEMOP(MO_UL))
4215
4216 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
4217 TCGv EA, TCGCond cond, int addend)
4218 {
4219 TCGv t = tcg_temp_new();
4220 TCGv t2 = tcg_temp_new();
4221 TCGv u = tcg_temp_new();
4222
4223 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
4224 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
4225 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
4226 tcg_gen_addi_tl(u, t, addend);
4227
4228 /* E.g. for fetch and increment bounded... */
4229 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
4230 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
4231 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
4232
4233 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
4234 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
4235 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
4236
4237 tcg_temp_free(t);
4238 tcg_temp_free(t2);
4239 tcg_temp_free(u);
4240 }
4241
4242 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
4243 {
4244 uint32_t gpr_FC = FC(ctx->opcode);
4245 TCGv EA = tcg_temp_new();
4246 int rt = rD(ctx->opcode);
4247 bool need_serial;
4248 TCGv src, dst;
4249
4250 gen_addr_register(ctx, EA);
4251 dst = cpu_gpr[rt];
4252 src = cpu_gpr[(rt + 1) & 31];
4253
4254 need_serial = false;
4255 memop |= MO_ALIGN;
4256 switch (gpr_FC) {
4257 case 0: /* Fetch and add */
4258 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
4259 break;
4260 case 1: /* Fetch and xor */
4261 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
4262 break;
4263 case 2: /* Fetch and or */
4264 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
4265 break;
4266 case 3: /* Fetch and 'and' */
4267 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
4268 break;
4269 case 4: /* Fetch and max unsigned */
4270 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
4271 break;
4272 case 5: /* Fetch and max signed */
4273 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
4274 break;
4275 case 6: /* Fetch and min unsigned */
4276 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
4277 break;
4278 case 7: /* Fetch and min signed */
4279 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
4280 break;
4281 case 8: /* Swap */
4282 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
4283 break;
4284
4285 case 16: /* Compare and swap not equal */
4286 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4287 need_serial = true;
4288 } else {
4289 TCGv t0 = tcg_temp_new();
4290 TCGv t1 = tcg_temp_new();
4291
4292 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
4293 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
4294 tcg_gen_mov_tl(t1, src);
4295 } else {
4296 tcg_gen_ext32u_tl(t1, src);
4297 }
4298 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
4299 cpu_gpr[(rt + 2) & 31], t0);
4300 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
4301 tcg_gen_mov_tl(dst, t0);
4302
4303 tcg_temp_free(t0);
4304 tcg_temp_free(t1);
4305 }
4306 break;
4307
4308 case 24: /* Fetch and increment bounded */
4309 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4310 need_serial = true;
4311 } else {
4312 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
4313 }
4314 break;
4315 case 25: /* Fetch and increment equal */
4316 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4317 need_serial = true;
4318 } else {
4319 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
4320 }
4321 break;
4322 case 28: /* Fetch and decrement bounded */
4323 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4324 need_serial = true;
4325 } else {
4326 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
4327 }
4328 break;
4329
4330 default:
4331 /* invoke data storage error handler */
4332 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
4333 }
4334 tcg_temp_free(EA);
4335
4336 if (need_serial) {
4337 /* Restart with exclusive lock. */
4338 gen_helper_exit_atomic(cpu_env);
4339 ctx->base.is_jmp = DISAS_NORETURN;
4340 }
4341 }
4342
4343 static void gen_lwat(DisasContext *ctx)
4344 {
4345 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
4346 }
4347
4348 #ifdef TARGET_PPC64
4349 static void gen_ldat(DisasContext *ctx)
4350 {
4351 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
4352 }
4353 #endif
4354
4355 static void gen_st_atomic(DisasContext *ctx, MemOp memop)
4356 {
4357 uint32_t gpr_FC = FC(ctx->opcode);
4358 TCGv EA = tcg_temp_new();
4359 TCGv src, discard;
4360
4361 gen_addr_register(ctx, EA);
4362 src = cpu_gpr[rD(ctx->opcode)];
4363 discard = tcg_temp_new();
4364
4365 memop |= MO_ALIGN;
4366 switch (gpr_FC) {
4367 case 0: /* add and Store */
4368 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4369 break;
4370 case 1: /* xor and Store */
4371 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4372 break;
4373 case 2: /* Or and Store */
4374 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4375 break;
4376 case 3: /* 'and' and Store */
4377 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4378 break;
4379 case 4: /* Store max unsigned */
4380 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4381 break;
4382 case 5: /* Store max signed */
4383 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4384 break;
4385 case 6: /* Store min unsigned */
4386 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4387 break;
4388 case 7: /* Store min signed */
4389 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4390 break;
4391 case 24: /* Store twin */
4392 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4393 /* Restart with exclusive lock. */
4394 gen_helper_exit_atomic(cpu_env);
4395 ctx->base.is_jmp = DISAS_NORETURN;
4396 } else {
4397 TCGv t = tcg_temp_new();
4398 TCGv t2 = tcg_temp_new();
4399 TCGv s = tcg_temp_new();
4400 TCGv s2 = tcg_temp_new();
4401 TCGv ea_plus_s = tcg_temp_new();
4402
4403 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
4404 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
4405 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
4406 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
4407 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
4408 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
4409 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
4410
4411 tcg_temp_free(ea_plus_s);
4412 tcg_temp_free(s2);
4413 tcg_temp_free(s);
4414 tcg_temp_free(t2);
4415 tcg_temp_free(t);
4416 }
4417 break;
4418 default:
4419 /* invoke data storage error handler */
4420 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
4421 }
4422 tcg_temp_free(discard);
4423 tcg_temp_free(EA);
4424 }
4425
4426 static void gen_stwat(DisasContext *ctx)
4427 {
4428 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
4429 }
4430
4431 #ifdef TARGET_PPC64
4432 static void gen_stdat(DisasContext *ctx)
4433 {
4434 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
4435 }
4436 #endif
4437
4438 static void gen_conditional_store(DisasContext *ctx, MemOp memop)
4439 {
4440 TCGLabel *l1 = gen_new_label();
4441 TCGLabel *l2 = gen_new_label();
4442 TCGv t0 = tcg_temp_new();
4443 int reg = rS(ctx->opcode);
4444
4445 gen_set_access_type(ctx, ACCESS_RES);
4446 gen_addr_reg_index(ctx, t0);
4447 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
4448 tcg_temp_free(t0);
4449
4450 t0 = tcg_temp_new();
4451 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
4452 cpu_gpr[reg], ctx->mem_idx,
4453 DEF_MEMOP(memop) | MO_ALIGN);
4454 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
4455 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
4456 tcg_gen_or_tl(t0, t0, cpu_so);
4457 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
4458 tcg_temp_free(t0);
4459 tcg_gen_br(l2);
4460
4461 gen_set_label(l1);
4462
4463 /*
4464 * Address mismatch implies failure. But we still need to provide
4465 * the memory barrier semantics of the instruction.
4466 */
4467 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
4468 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4469
4470 gen_set_label(l2);
4471 tcg_gen_movi_tl(cpu_reserve, -1);
4472 }
4473
4474 #define STCX(name, memop) \
4475 static void gen_##name(DisasContext *ctx) \
4476 { \
4477 gen_conditional_store(ctx, memop); \
4478 }
4479
4480 STCX(stbcx_, DEF_MEMOP(MO_UB))
4481 STCX(sthcx_, DEF_MEMOP(MO_UW))
4482 STCX(stwcx_, DEF_MEMOP(MO_UL))
4483
4484 #if defined(TARGET_PPC64)
4485 /* ldarx */
4486 LARX(ldarx, DEF_MEMOP(MO_Q))
4487 /* stdcx. */
4488 STCX(stdcx_, DEF_MEMOP(MO_Q))
4489
4490 /* lqarx */
4491 static void gen_lqarx(DisasContext *ctx)
4492 {
4493 int rd = rD(ctx->opcode);
4494 TCGv EA, hi, lo;
4495
4496 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
4497 (rd == rB(ctx->opcode)))) {
4498 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4499 return;
4500 }
4501
4502 gen_set_access_type(ctx, ACCESS_RES);
4503 EA = tcg_temp_new();
4504 gen_addr_reg_index(ctx, EA);
4505
4506 /* Note that the low part is always in RD+1, even in LE mode. */
4507 lo = cpu_gpr[rd + 1];
4508 hi = cpu_gpr[rd];
4509
4510 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4511 if (HAVE_ATOMIC128) {
4512 TCGv_i32 oi = tcg_temp_new_i32();
4513 if (ctx->le_mode) {
4514 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
4515 ctx->mem_idx));
4516 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
4517 } else {
4518 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
4519 ctx->mem_idx));
4520 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
4521 }
4522 tcg_temp_free_i32(oi);
4523 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
4524 } else {
4525 /* Restart with exclusive lock. */
4526 gen_helper_exit_atomic(cpu_env);
4527 ctx->base.is_jmp = DISAS_NORETURN;
4528 tcg_temp_free(EA);
4529 return;
4530 }
4531 } else if (ctx->le_mode) {
4532 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
4533 tcg_gen_mov_tl(cpu_reserve, EA);
4534 gen_addr_add(ctx, EA, EA, 8);
4535 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
4536 } else {
4537 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
4538 tcg_gen_mov_tl(cpu_reserve, EA);
4539 gen_addr_add(ctx, EA, EA, 8);
4540 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
4541 }
4542 tcg_temp_free(EA);
4543
4544 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
4545 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
4546 }
4547
4548 /* stqcx. */
4549 static void gen_stqcx_(DisasContext *ctx)
4550 {
4551 int rs = rS(ctx->opcode);
4552 TCGv EA, hi, lo;
4553
4554 if (unlikely(rs & 1)) {
4555 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4556 return;
4557 }
4558
4559 gen_set_access_type(ctx, ACCESS_RES);
4560 EA = tcg_temp_new();
4561 gen_addr_reg_index(ctx, EA);
4562
4563 /* Note that the low part is always in RS+1, even in LE mode. */
4564 lo = cpu_gpr[rs + 1];
4565 hi = cpu_gpr[rs];
4566
4567 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4568 if (HAVE_CMPXCHG128) {
4569 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
4570 if (ctx->le_mode) {
4571 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
4572 EA, lo, hi, oi);
4573 } else {
4574 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
4575 EA, lo, hi, oi);
4576 }
4577 tcg_temp_free_i32(oi);
4578 } else {
4579 /* Restart with exclusive lock. */
4580 gen_helper_exit_atomic(cpu_env);
4581 ctx->base.is_jmp = DISAS_NORETURN;
4582 }
4583 tcg_temp_free(EA);
4584 } else {
4585 TCGLabel *lab_fail = gen_new_label();
4586 TCGLabel *lab_over = gen_new_label();
4587 TCGv_i64 t0 = tcg_temp_new_i64();
4588 TCGv_i64 t1 = tcg_temp_new_i64();
4589
4590 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
4591 tcg_temp_free(EA);
4592
4593 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
4594 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4595 ? offsetof(CPUPPCState, reserve_val2)
4596 : offsetof(CPUPPCState, reserve_val)));
4597 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4598
4599 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4600 gen_qemu_ld64_i64(ctx, t0, t0);
4601 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4602 ? offsetof(CPUPPCState, reserve_val)
4603 : offsetof(CPUPPCState, reserve_val2)));
4604 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4605
4606 /* Success */
4607 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
4608 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4609 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
4610
4611 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4612 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4613 tcg_gen_br(lab_over);
4614
4615 gen_set_label(lab_fail);
4616 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4617
4618 gen_set_label(lab_over);
4619 tcg_gen_movi_tl(cpu_reserve, -1);
4620 tcg_temp_free_i64(t0);
4621 tcg_temp_free_i64(t1);
4622 }
4623 }
4624 #endif /* defined(TARGET_PPC64) */
4625
4626 /* sync */
4627 static void gen_sync(DisasContext *ctx)
4628 {
4629 uint32_t l = (ctx->opcode >> 21) & 3;
4630
4631 /*
4632 * We may need to check for a pending TLB flush.
4633 *
4634 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
4635 *
4636 * Additionally, this can only happen in kernel mode however so
4637 * check MSR_PR as well.
4638 */
4639 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
4640 gen_check_tlb_flush(ctx, true);
4641 }
4642 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
4643 }
4644
4645 /* wait */
4646 static void gen_wait(DisasContext *ctx)
4647 {
4648 TCGv_i32 t0 = tcg_const_i32(1);
4649 tcg_gen_st_i32(t0, cpu_env,
4650 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
4651 tcg_temp_free_i32(t0);
4652 /* Stop translation, as the CPU is supposed to sleep from now */
4653 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4654 }
4655
4656 #if defined(TARGET_PPC64)
4657 static void gen_doze(DisasContext *ctx)
4658 {
4659 #if defined(CONFIG_USER_ONLY)
4660 GEN_PRIV;
4661 #else
4662 TCGv_i32 t;
4663
4664 CHK_HV;
4665 t = tcg_const_i32(PPC_PM_DOZE);
4666 gen_helper_pminsn(cpu_env, t);
4667 tcg_temp_free_i32(t);
4668 /* Stop translation, as the CPU is supposed to sleep from now */
4669 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4670 #endif /* defined(CONFIG_USER_ONLY) */
4671 }
4672
4673 static void gen_nap(DisasContext *ctx)
4674 {
4675 #if defined(CONFIG_USER_ONLY)
4676 GEN_PRIV;
4677 #else
4678 TCGv_i32 t;
4679
4680 CHK_HV;
4681 t = tcg_const_i32(PPC_PM_NAP);
4682 gen_helper_pminsn(cpu_env, t);
4683 tcg_temp_free_i32(t);
4684 /* Stop translation, as the CPU is supposed to sleep from now */
4685 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4686 #endif /* defined(CONFIG_USER_ONLY) */
4687 }
4688
4689 static void gen_stop(DisasContext *ctx)
4690 {
4691 #if defined(CONFIG_USER_ONLY)
4692 GEN_PRIV;
4693 #else
4694 TCGv_i32 t;
4695
4696 CHK_HV;
4697 t = tcg_const_i32(PPC_PM_STOP);
4698 gen_helper_pminsn(cpu_env, t);
4699 tcg_temp_free_i32(t);
4700 /* Stop translation, as the CPU is supposed to sleep from now */
4701 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4702 #endif /* defined(CONFIG_USER_ONLY) */
4703 }
4704
4705 static void gen_sleep(DisasContext *ctx)
4706 {
4707 #if defined(CONFIG_USER_ONLY)
4708 GEN_PRIV;
4709 #else
4710 TCGv_i32 t;
4711
4712 CHK_HV;
4713 t = tcg_const_i32(PPC_PM_SLEEP);
4714 gen_helper_pminsn(cpu_env, t);
4715 tcg_temp_free_i32(t);
4716 /* Stop translation, as the CPU is supposed to sleep from now */
4717 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4718 #endif /* defined(CONFIG_USER_ONLY) */
4719 }
4720
4721 static void gen_rvwinkle(DisasContext *ctx)
4722 {
4723 #if defined(CONFIG_USER_ONLY)
4724 GEN_PRIV;
4725 #else
4726 TCGv_i32 t;
4727
4728 CHK_HV;
4729 t = tcg_const_i32(PPC_PM_RVWINKLE);
4730 gen_helper_pminsn(cpu_env, t);
4731 tcg_temp_free_i32(t);
4732 /* Stop translation, as the CPU is supposed to sleep from now */
4733 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4734 #endif /* defined(CONFIG_USER_ONLY) */
4735 }
4736 #endif /* #if defined(TARGET_PPC64) */
4737
4738 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4739 {
4740 #if defined(TARGET_PPC64)
4741 if (ctx->has_cfar) {
4742 tcg_gen_movi_tl(cpu_cfar, nip);
4743 }
4744 #endif
4745 }
4746
4747 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4748 {
4749 if (unlikely(ctx->singlestep_enabled)) {
4750 return false;
4751 }
4752
4753 #ifndef CONFIG_USER_ONLY
4754 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
4755 #else
4756 return true;
4757 #endif
4758 }
4759
4760 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
4761 {
4762 int sse = ctx->singlestep_enabled;
4763 if (unlikely(sse)) {
4764 if (sse & GDBSTUB_SINGLE_STEP) {
4765 gen_debug_exception(ctx);
4766 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
4767 uint32_t excp = gen_prep_dbgex(ctx);
4768 gen_exception(ctx, excp);
4769 }
4770 tcg_gen_exit_tb(NULL, 0);
4771 } else {
4772 tcg_gen_lookup_and_goto_ptr();
4773 }
4774 }
4775
4776 /*** Branch ***/
4777 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4778 {
4779 if (NARROW_MODE(ctx)) {
4780 dest = (uint32_t) dest;
4781 }
4782 if (use_goto_tb(ctx, dest)) {
4783 tcg_gen_goto_tb(n);
4784 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4785 tcg_gen_exit_tb(ctx->base.tb, n);
4786 } else {
4787 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4788 gen_lookup_and_goto_ptr(ctx);
4789 }
4790 }
4791
4792 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4793 {
4794 if (NARROW_MODE(ctx)) {
4795 nip = (uint32_t)nip;
4796 }
4797 tcg_gen_movi_tl(cpu_lr, nip);
4798 }
4799
4800 /* b ba bl bla */
4801 static void gen_b(DisasContext *ctx)
4802 {
4803 target_ulong li, target;
4804
4805 ctx->exception = POWERPC_EXCP_BRANCH;
4806 /* sign extend LI */
4807 li = LI(ctx->opcode);
4808 li = (li ^ 0x02000000) - 0x02000000;
4809 if (likely(AA(ctx->opcode) == 0)) {
4810 target = ctx->cia + li;
4811 } else {
4812 target = li;
4813 }
4814 if (LK(ctx->opcode)) {
4815 gen_setlr(ctx, ctx->base.pc_next);
4816 }
4817 gen_update_cfar(ctx, ctx->cia);
4818 gen_goto_tb(ctx, 0, target);
4819 }
4820
4821 #define BCOND_IM 0
4822 #define BCOND_LR 1
4823 #define BCOND_CTR 2
4824 #define BCOND_TAR 3
4825
4826 static void gen_bcond(DisasContext *ctx, int type)
4827 {
4828 uint32_t bo = BO(ctx->opcode);
4829 TCGLabel *l1;
4830 TCGv target;
4831 ctx->exception = POWERPC_EXCP_BRANCH;
4832
4833 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4834 target = tcg_temp_local_new();
4835 if (type == BCOND_CTR) {
4836 tcg_gen_mov_tl(target, cpu_ctr);
4837 } else if (type == BCOND_TAR) {
4838 gen_load_spr(target, SPR_TAR);
4839 } else {
4840 tcg_gen_mov_tl(target, cpu_lr);
4841 }
4842 } else {
4843 target = NULL;
4844 }
4845 if (LK(ctx->opcode)) {
4846 gen_setlr(ctx, ctx->base.pc_next);
4847 }
4848 l1 = gen_new_label();
4849 if ((bo & 0x4) == 0) {
4850 /* Decrement and test CTR */
4851 TCGv temp = tcg_temp_new();
4852
4853 if (type == BCOND_CTR) {
4854 /*
4855 * All ISAs up to v3 describe this form of bcctr as invalid but
4856 * some processors, ie. 64-bit server processors compliant with
4857 * arch 2.x, do implement a "test and decrement" logic instead,
4858 * as described in their respective UMs. This logic involves CTR
4859 * to act as both the branch target and a counter, which makes
4860 * it basically useless and thus never used in real code.
4861 *
4862 * This form was hence chosen to trigger extra micro-architectural
4863 * side-effect on real HW needed for the Spectre v2 workaround.
4864 * It is up to guests that implement such workaround, ie. linux, to
4865 * use this form in a way it just triggers the side-effect without
4866 * doing anything else harmful.
4867 */
4868 if (unlikely(!is_book3s_arch2x(ctx))) {
4869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4870 tcg_temp_free(temp);
4871 tcg_temp_free(target);
4872 return;
4873 }
4874
4875 if (NARROW_MODE(ctx)) {
4876 tcg_gen_ext32u_tl(temp, cpu_ctr);
4877 } else {
4878 tcg_gen_mov_tl(temp, cpu_ctr);
4879 }
4880 if (bo & 0x2) {
4881 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4882 } else {
4883 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4884 }
4885 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4886 } else {
4887 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4888 if (NARROW_MODE(ctx)) {
4889 tcg_gen_ext32u_tl(temp, cpu_ctr);
4890 } else {
4891 tcg_gen_mov_tl(temp, cpu_ctr);
4892 }
4893 if (bo & 0x2) {
4894 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4895 } else {
4896 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4897 }
4898 }
4899 tcg_temp_free(temp);
4900 }
4901 if ((bo & 0x10) == 0) {
4902 /* Test CR */
4903 uint32_t bi = BI(ctx->opcode);
4904 uint32_t mask = 0x08 >> (bi & 0x03);
4905 TCGv_i32 temp = tcg_temp_new_i32();
4906
4907 if (bo & 0x8) {
4908 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4909 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4910 } else {
4911 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4912 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4913 }
4914 tcg_temp_free_i32(temp);
4915 }
4916 gen_update_cfar(ctx, ctx->cia);
4917 if (type == BCOND_IM) {
4918 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4919 if (likely(AA(ctx->opcode) == 0)) {
4920 gen_goto_tb(ctx, 0, ctx->cia + li);
4921 } else {
4922 gen_goto_tb(ctx, 0, li);
4923 }
4924 } else {
4925 if (NARROW_MODE(ctx)) {
4926 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4927 } else {
4928 tcg_gen_andi_tl(cpu_nip, target, ~3);
4929 }
4930 gen_lookup_and_goto_ptr(ctx);
4931 tcg_temp_free(target);
4932 }
4933 if ((bo & 0x14) != 0x14) {
4934 /* fallthrough case */
4935 gen_set_label(l1);
4936 gen_goto_tb(ctx, 1, ctx->base.pc_next);
4937 }
4938 }
4939
4940 static void gen_bc(DisasContext *ctx)
4941 {
4942 gen_bcond(ctx, BCOND_IM);
4943 }
4944
4945 static void gen_bcctr(DisasContext *ctx)
4946 {
4947 gen_bcond(ctx, BCOND_CTR);
4948 }
4949
4950 static void gen_bclr(DisasContext *ctx)
4951 {
4952 gen_bcond(ctx, BCOND_LR);
4953 }
4954
4955 static void gen_bctar(DisasContext *ctx)
4956 {
4957 gen_bcond(ctx, BCOND_TAR);
4958 }
4959
4960 /*** Condition register logical ***/
4961 #define GEN_CRLOGIC(name, tcg_op, opc) \
4962 static void glue(gen_, name)(DisasContext *ctx) \
4963 { \
4964 uint8_t bitmask; \
4965 int sh; \
4966 TCGv_i32 t0, t1; \
4967 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4968 t0 = tcg_temp_new_i32(); \
4969 if (sh > 0) \
4970 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4971 else if (sh < 0) \
4972 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4973 else \
4974 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4975 t1 = tcg_temp_new_i32(); \
4976 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4977 if (sh > 0) \
4978 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4979 else if (sh < 0) \
4980 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4981 else \
4982 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4983 tcg_op(t0, t0, t1); \
4984 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4985 tcg_gen_andi_i32(t0, t0, bitmask); \
4986 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4987 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4988 tcg_temp_free_i32(t0); \
4989 tcg_temp_free_i32(t1); \
4990 }
4991
4992 /* crand */
4993 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4994 /* crandc */
4995 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4996 /* creqv */
4997 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4998 /* crnand */
4999 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
5000 /* crnor */
5001 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
5002 /* cror */
5003 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
5004 /* crorc */
5005 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
5006 /* crxor */
5007 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
5008
5009 /* mcrf */
5010 static void gen_mcrf(DisasContext *ctx)
5011 {
5012 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
5013 }
5014
5015 /*** System linkage ***/
5016
5017 /* rfi (supervisor only) */
5018 static void gen_rfi(DisasContext *ctx)
5019 {
5020 #if defined(CONFIG_USER_ONLY)
5021 GEN_PRIV;
5022 #else
5023 /*
5024 * This instruction doesn't exist anymore on 64-bit server
5025 * processors compliant with arch 2.x
5026 */
5027 if (is_book3s_arch2x(ctx)) {
5028 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5029 return;
5030 }
5031 /* Restore CPU state */
5032 CHK_SV;
5033 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5034 gen_io_start();
5035 }
5036 gen_update_cfar(ctx, ctx->cia);
5037 gen_helper_rfi(cpu_env);
5038 gen_sync_exception(ctx);
5039 #endif
5040 }
5041
5042 #if defined(TARGET_PPC64)
5043 static void gen_rfid(DisasContext *ctx)
5044 {
5045 #if defined(CONFIG_USER_ONLY)
5046 GEN_PRIV;
5047 #else
5048 /* Restore CPU state */
5049 CHK_SV;
5050 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5051 gen_io_start();
5052 }
5053 gen_update_cfar(ctx, ctx->cia);
5054 gen_helper_rfid(cpu_env);
5055 gen_sync_exception(ctx);
5056 #endif
5057 }
5058
5059 #if !defined(CONFIG_USER_ONLY)
5060 static void gen_rfscv(DisasContext *ctx)
5061 {
5062 #if defined(CONFIG_USER_ONLY)
5063 GEN_PRIV;
5064 #else
5065 /* Restore CPU state */
5066 CHK_SV;
5067 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5068 gen_io_start();
5069 }
5070 gen_update_cfar(ctx, ctx->cia);
5071 gen_helper_rfscv(cpu_env);
5072 gen_sync_exception(ctx);
5073 #endif
5074 }
5075 #endif
5076
5077 static void gen_hrfid(DisasContext *ctx)
5078 {
5079 #if defined(CONFIG_USER_ONLY)
5080 GEN_PRIV;
5081 #else
5082 /* Restore CPU state */
5083 CHK_HV;
5084 gen_helper_hrfid(cpu_env);
5085 gen_sync_exception(ctx);
5086 #endif
5087 }
5088 #endif
5089
5090 /* sc */
5091 #if defined(CONFIG_USER_ONLY)
5092 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
5093 #else
5094 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
5095 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
5096 #endif
5097 static void gen_sc(DisasContext *ctx)
5098 {
5099 uint32_t lev;
5100
5101 lev = (ctx->opcode >> 5) & 0x7F;
5102 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
5103 }
5104
5105 #if defined(TARGET_PPC64)
5106 #if !defined(CONFIG_USER_ONLY)
5107 static void gen_scv(DisasContext *ctx)
5108 {
5109 uint32_t lev = (ctx->opcode >> 5) & 0x7F;
5110
5111 /* Set the PC back to the faulting instruction. */
5112 if (ctx->exception == POWERPC_EXCP_NONE) {
5113 gen_update_nip(ctx, ctx->cia);
5114 }
5115 gen_helper_scv(cpu_env, tcg_constant_i32(lev));
5116
5117 /* This need not be exact, just not POWERPC_EXCP_NONE */
5118 ctx->exception = POWERPC_SYSCALL_VECTORED;
5119 }
5120 #endif
5121 #endif
5122
5123 /*** Trap ***/
5124
5125 /* Check for unconditional traps (always or never) */
5126 static bool check_unconditional_trap(DisasContext *ctx)
5127 {
5128 /* Trap never */
5129 if (TO(ctx->opcode) == 0) {
5130 return true;
5131 }
5132 /* Trap always */
5133 if (TO(ctx->opcode) == 31) {
5134 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
5135 return true;
5136 }
5137 return false;
5138 }
5139
5140 /* tw */
5141 static void gen_tw(DisasContext *ctx)
5142 {
5143 TCGv_i32 t0;
5144
5145 if (check_unconditional_trap(ctx)) {
5146 return;
5147 }
5148 t0 = tcg_const_i32(TO(ctx->opcode));
5149 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5150 t0);
5151 tcg_temp_free_i32(t0);
5152 }
5153
5154 /* twi */
5155 static void gen_twi(DisasContext *ctx)
5156 {
5157 TCGv t0;
5158 TCGv_i32 t1;
5159
5160 if (check_unconditional_trap(ctx)) {
5161 return;
5162 }
5163 t0 = tcg_const_tl(SIMM(ctx->opcode));
5164 t1 = tcg_const_i32(TO(ctx->opcode));
5165 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
5166 tcg_temp_free(t0);
5167 tcg_temp_free_i32(t1);
5168 }
5169
5170 #if defined(TARGET_PPC64)
5171 /* td */
5172 static void gen_td(DisasContext *ctx)
5173 {
5174 TCGv_i32 t0;
5175
5176 if (check_unconditional_trap(ctx)) {
5177 return;
5178 }
5179 t0 = tcg_const_i32(TO(ctx->opcode));
5180 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5181 t0);
5182 tcg_temp_free_i32(t0);
5183 }
5184
5185 /* tdi */
5186 static void gen_tdi(DisasContext *ctx)
5187 {
5188 TCGv t0;
5189 TCGv_i32 t1;
5190
5191 if (check_unconditional_trap(ctx)) {
5192 return;
5193 }
5194 t0 = tcg_const_tl(SIMM(ctx->opcode));
5195 t1 = tcg_const_i32(TO(ctx->opcode));
5196 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
5197 tcg_temp_free(t0);
5198 tcg_temp_free_i32(t1);
5199 }
5200 #endif
5201
5202 /*** Processor control ***/
5203
5204 /* mcrxr */
5205 static void gen_mcrxr(DisasContext *ctx)
5206 {
5207 TCGv_i32 t0 = tcg_temp_new_i32();
5208 TCGv_i32 t1 = tcg_temp_new_i32();
5209 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
5210
5211 tcg_gen_trunc_tl_i32(t0, cpu_so);
5212 tcg_gen_trunc_tl_i32(t1, cpu_ov);
5213 tcg_gen_trunc_tl_i32(dst, cpu_ca);
5214 tcg_gen_shli_i32(t0, t0, 3);
5215 tcg_gen_shli_i32(t1, t1, 2);
5216 tcg_gen_shli_i32(dst, dst, 1);
5217 tcg_gen_or_i32(dst, dst, t0);
5218 tcg_gen_or_i32(dst, dst, t1);
5219 tcg_temp_free_i32(t0);
5220 tcg_temp_free_i32(t1);
5221
5222 tcg_gen_movi_tl(cpu_so, 0);
5223 tcg_gen_movi_tl(cpu_ov, 0);
5224 tcg_gen_movi_tl(cpu_ca, 0);
5225 }
5226
5227 #ifdef TARGET_PPC64
5228 /* mcrxrx */
5229 static void gen_mcrxrx(DisasContext *ctx)
5230 {
5231 TCGv t0 = tcg_temp_new();
5232 TCGv t1 = tcg_temp_new();
5233 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
5234
5235 /* copy OV and OV32 */
5236 tcg_gen_shli_tl(t0, cpu_ov, 1);
5237 tcg_gen_or_tl(t0, t0, cpu_ov32);
5238 tcg_gen_shli_tl(t0, t0, 2);
5239 /* copy CA and CA32 */
5240 tcg_gen_shli_tl(t1, cpu_ca, 1);
5241 tcg_gen_or_tl(t1, t1, cpu_ca32);
5242 tcg_gen_or_tl(t0, t0, t1);
5243 tcg_gen_trunc_tl_i32(dst, t0);
5244 tcg_temp_free(t0);
5245 tcg_temp_free(t1);
5246 }
5247 #endif
5248
5249 /* mfcr mfocrf */
5250 static void gen_mfcr(DisasContext *ctx)
5251 {
5252 uint32_t crm, crn;
5253
5254 if (likely(ctx->opcode & 0x00100000)) {
5255 crm = CRM(ctx->opcode);
5256 if (likely(crm && ((crm & (crm - 1)) == 0))) {
5257 crn = ctz32(crm);
5258 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
5259 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
5260 cpu_gpr[rD(ctx->opcode)], crn * 4);
5261 }
5262 } else {
5263 TCGv_i32 t0 = tcg_temp_new_i32();
5264 tcg_gen_mov_i32(t0, cpu_crf[0]);
5265 tcg_gen_shli_i32(t0, t0, 4);
5266 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
5267 tcg_gen_shli_i32(t0, t0, 4);
5268 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
5269 tcg_gen_shli_i32(t0, t0, 4);
5270 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
5271 tcg_gen_shli_i32(t0, t0, 4);
5272 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
5273 tcg_gen_shli_i32(t0, t0, 4);
5274 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
5275 tcg_gen_shli_i32(t0, t0, 4);
5276 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
5277 tcg_gen_shli_i32(t0, t0, 4);
5278 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
5279 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5280 tcg_temp_free_i32(t0);
5281 }
5282 }
5283
5284 /* mfmsr */
5285 static void gen_mfmsr(DisasContext *ctx)
5286 {
5287 CHK_SV;
5288 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
5289 }
5290
5291 /* mfspr */
5292 static inline void gen_op_mfspr(DisasContext *ctx)
5293 {
5294 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
5295 uint32_t sprn = SPR(ctx->opcode);
5296
5297 #if defined(CONFIG_USER_ONLY)
5298 read_cb = ctx->spr_cb[sprn].uea_read;
5299 #else
5300 if (ctx->pr) {
5301 read_cb = ctx->spr_cb[sprn].uea_read;
5302 } else if (ctx->hv) {
5303 read_cb = ctx->spr_cb[sprn].hea_read;
5304 } else {
5305 read_cb = ctx->spr_cb[sprn].oea_read;
5306 }
5307 #endif
5308 if (likely(read_cb != NULL)) {
5309 if (likely(read_cb != SPR_NOACCESS)) {
5310 (*read_cb)(ctx, rD(ctx->opcode), sprn);
5311 } else {
5312 /* Privilege exception */
5313 /*
5314 * This is a hack to avoid warnings when running Linux:
5315 * this OS breaks the PowerPC virtualisation model,
5316 * allowing userland application to read the PVR
5317 */
5318 if (sprn != SPR_PVR) {
5319 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
5320 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
5321 ctx->cia);
5322 }
5323 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
5324 }
5325 } else {
5326 /* ISA 2.07 defines these as no-ops */
5327 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
5328 (sprn >= 808 && sprn <= 811)) {
5329 /* This is a nop */
5330 return;
5331 }
5332 /* Not defined */
5333 qemu_log_mask(LOG_GUEST_ERROR,
5334 "Trying to read invalid spr %d (0x%03x) at "
5335 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
5336
5337 /*
5338 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5339 * generate a priv, a hv emu or a no-op
5340 */
5341 if (sprn & 0x10) {
5342 if (ctx->pr) {
5343 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5344 }
5345 } else {
5346 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
5347 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5348 }
5349 }
5350 }
5351 }
5352
5353 static void gen_mfspr(DisasContext *ctx)
5354 {
5355 gen_op_mfspr(ctx);
5356 }
5357
5358 /* mftb */
5359 static void gen_mftb(DisasContext *ctx)
5360 {
5361 gen_op_mfspr(ctx);
5362 }
5363
5364 /* mtcrf mtocrf*/
5365 static void gen_mtcrf(DisasContext *ctx)
5366 {
5367 uint32_t crm, crn;
5368
5369 crm = CRM(ctx->opcode);
5370 if (likely((ctx->opcode & 0x00100000))) {
5371 if (crm && ((crm & (crm - 1)) == 0)) {
5372 TCGv_i32 temp = tcg_temp_new_i32();
5373 crn = ctz32(crm);
5374 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
5375 tcg_gen_shri_i32(temp, temp, crn * 4);
5376 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
5377 tcg_temp_free_i32(temp);
5378 }
5379 } else {
5380 TCGv_i32 temp = tcg_temp_new_i32();
5381 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
5382 for (crn = 0 ; crn < 8 ; crn++) {
5383 if (crm & (1 << crn)) {
5384 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
5385 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
5386 }
5387 }
5388 tcg_temp_free_i32(temp);
5389 }
5390 }
5391
5392 /* mtmsr */
5393 #if defined(TARGET_PPC64)
5394 static void gen_mtmsrd(DisasContext *ctx)
5395 {
5396 CHK_SV;
5397
5398 #if !defined(CONFIG_USER_ONLY)
5399 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5400 gen_io_start();
5401 }
5402 if (ctx->opcode & 0x00010000) {
5403 /* L=1 form only updates EE and RI */
5404 TCGv t0 = tcg_temp_new();
5405 TCGv t1 = tcg_temp_new();
5406 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
5407 (1 << MSR_RI) | (1 << MSR_EE));
5408 tcg_gen_andi_tl(t1, cpu_msr,
5409 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
5410 tcg_gen_or_tl(t1, t1, t0);
5411
5412 gen_helper_store_msr(cpu_env, t1);
5413 tcg_temp_free(t0);
5414 tcg_temp_free(t1);
5415
5416 } else {
5417 /*
5418 * XXX: we need to update nip before the store if we enter
5419 * power saving mode, we will exit the loop directly from
5420 * ppc_store_msr
5421 */
5422 gen_update_nip(ctx, ctx->base.pc_next);
5423 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
5424 }
5425 /* Must stop the translation as machine state (may have) changed */
5426 gen_stop_exception(ctx);
5427 #endif /* !defined(CONFIG_USER_ONLY) */
5428 }
5429 #endif /* defined(TARGET_PPC64) */
5430
5431 static void gen_mtmsr(DisasContext *ctx)
5432 {
5433 CHK_SV;
5434
5435 #if !defined(CONFIG_USER_ONLY)
5436 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5437 gen_io_start();
5438 }
5439 if (ctx->opcode & 0x00010000) {
5440 /* L=1 form only updates EE and RI */
5441 TCGv t0 = tcg_temp_new();
5442 TCGv t1 = tcg_temp_new();
5443 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
5444 (1 << MSR_RI) | (1 << MSR_EE));
5445 tcg_gen_andi_tl(t1, cpu_msr,
5446 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
5447 tcg_gen_or_tl(t1, t1, t0);
5448
5449 gen_helper_store_msr(cpu_env, t1);
5450 tcg_temp_free(t0);
5451 tcg_temp_free(t1);
5452
5453 } else {
5454 TCGv msr = tcg_temp_new();
5455
5456 /*
5457 * XXX: we need to update nip before the store if we enter
5458 * power saving mode, we will exit the loop directly from
5459 * ppc_store_msr
5460 */
5461 gen_update_nip(ctx, ctx->base.pc_next);
5462 #if defined(TARGET_PPC64)
5463 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
5464 #else
5465 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
5466 #endif
5467 gen_helper_store_msr(cpu_env, msr);
5468 tcg_temp_free(msr);
5469 }
5470 /* Must stop the translation as machine state (may have) changed */
5471 gen_stop_exception(ctx);
5472 #endif
5473 }
5474
5475 /* mtspr */
5476 static void gen_mtspr(DisasContext *ctx)
5477 {
5478 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
5479 uint32_t sprn = SPR(ctx->opcode);
5480
5481 #if defined(CONFIG_USER_ONLY)
5482 write_cb = ctx->spr_cb[sprn].uea_write;
5483 #else
5484 if (ctx->pr) {
5485 write_cb = ctx->spr_cb[sprn].uea_write;
5486 } else if (ctx->hv) {
5487 write_cb = ctx->spr_cb[sprn].hea_write;
5488 } else {
5489 write_cb = ctx->spr_cb[sprn].oea_write;
5490 }
5491 #endif
5492 if (likely(write_cb != NULL)) {
5493 if (likely(write_cb != SPR_NOACCESS)) {
5494 (*write_cb)(ctx, sprn, rS(ctx->opcode));
5495 } else {
5496 /* Privilege exception */
5497 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
5498 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
5499 ctx->cia);
5500 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
5501 }
5502 } else {
5503 /* ISA 2.07 defines these as no-ops */
5504 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
5505 (sprn >= 808 && sprn <= 811)) {
5506 /* This is a nop */
5507 return;
5508 }
5509
5510 /* Not defined */
5511 qemu_log_mask(LOG_GUEST_ERROR,
5512 "Trying to write invalid spr %d (0x%03x) at "
5513 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
5514
5515
5516 /*
5517 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5518 * generate a priv, a hv emu or a no-op
5519 */
5520 if (sprn & 0x10) {
5521 if (ctx->pr) {
5522 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5523 }
5524 } else {
5525 if (ctx->pr || sprn == 0) {
5526 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5527 }
5528 }
5529 }
5530 }
5531
5532 #if defined(TARGET_PPC64)
5533 /* setb */
5534 static void gen_setb(DisasContext *ctx)
5535 {
5536 TCGv_i32 t0 = tcg_temp_new_i32();
5537 TCGv_i32 t8 = tcg_temp_new_i32();
5538 TCGv_i32 tm1 = tcg_temp_new_i32();
5539 int crf = crfS(ctx->opcode);
5540
5541 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
5542 tcg_gen_movi_i32(t8, 8);
5543 tcg_gen_movi_i32(tm1, -1);
5544 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
5545 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5546
5547 tcg_temp_free_i32(t0);
5548 tcg_temp_free_i32(t8);
5549 tcg_temp_free_i32(tm1);
5550 }
5551 #endif
5552
5553 /*** Cache management ***/
5554
5555 /* dcbf */
5556 static void gen_dcbf(DisasContext *ctx)
5557 {
5558 /* XXX: specification says this is treated as a load by the MMU */
5559 TCGv t0;
5560 gen_set_access_type(ctx, ACCESS_CACHE);
5561 t0 = tcg_temp_new();
5562 gen_addr_reg_index(ctx, t0);
5563 gen_qemu_ld8u(ctx, t0, t0);
5564 tcg_temp_free(t0);
5565 }
5566
5567 /* dcbfep (external PID dcbf) */
5568 static void gen_dcbfep(DisasContext *ctx)
5569 {
5570 /* XXX: specification says this is treated as a load by the MMU */
5571 TCGv t0;
5572 CHK_SV;
5573 gen_set_access_type(ctx, ACCESS_CACHE);
5574 t0 = tcg_temp_new();
5575 gen_addr_reg_index(ctx, t0);
5576 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5577 tcg_temp_free(t0);
5578 }
5579
5580 /* dcbi (Supervisor only) */
5581 static void gen_dcbi(DisasContext *ctx)
5582 {
5583 #if defined(CONFIG_USER_ONLY)
5584 GEN_PRIV;
5585 #else
5586 TCGv EA, val;
5587
5588 CHK_SV;
5589 EA = tcg_temp_new();
5590 gen_set_access_type(ctx, ACCESS_CACHE);
5591 gen_addr_reg_index(ctx, EA);
5592 val = tcg_temp_new();
5593 /* XXX: specification says this should be treated as a store by the MMU */
5594 gen_qemu_ld8u(ctx, val, EA);
5595 gen_qemu_st8(ctx, val, EA);
5596 tcg_temp_free(val);
5597 tcg_temp_free(EA);
5598 #endif /* defined(CONFIG_USER_ONLY) */
5599 }
5600
5601 /* dcdst */
5602 static void gen_dcbst(DisasContext *ctx)
5603 {
5604 /* XXX: specification say this is treated as a load by the MMU */
5605 TCGv t0;
5606 gen_set_access_type(ctx, ACCESS_CACHE);
5607 t0 = tcg_temp_new();
5608 gen_addr_reg_index(ctx, t0);
5609 gen_qemu_ld8u(ctx, t0, t0);
5610 tcg_temp_free(t0);
5611 }
5612
5613 /* dcbstep (dcbstep External PID version) */
5614 static void gen_dcbstep(DisasContext *ctx)
5615 {
5616 /* XXX: specification say this is treated as a load by the MMU */
5617 TCGv t0;
5618 gen_set_access_type(ctx, ACCESS_CACHE);
5619 t0 = tcg_temp_new();
5620 gen_addr_reg_index(ctx, t0);
5621 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5622 tcg_temp_free(t0);
5623 }
5624
5625 /* dcbt */
5626 static void gen_dcbt(DisasContext *ctx)
5627 {
5628 /*
5629 * interpreted as no-op
5630 * XXX: specification say this is treated as a load by the MMU but
5631 * does not generate any exception
5632 */
5633 }
5634
5635 /* dcbtep */
5636 static void gen_dcbtep(DisasContext *ctx)
5637 {
5638 /*
5639 * interpreted as no-op
5640 * XXX: specification say this is treated as a load by the MMU but
5641 * does not generate any exception
5642 */
5643 }
5644
5645 /* dcbtst */
5646 static void gen_dcbtst(DisasContext *ctx)
5647 {
5648 /*
5649 * interpreted as no-op
5650 * XXX: specification say this is treated as a load by the MMU but
5651 * does not generate any exception
5652 */
5653 }
5654
5655 /* dcbtstep */
5656 static void gen_dcbtstep(DisasContext *ctx)
5657 {
5658 /*
5659 * interpreted as no-op
5660 * XXX: specification say this is treated as a load by the MMU but
5661 * does not generate any exception
5662 */
5663 }
5664
5665 /* dcbtls */
5666 static void gen_dcbtls(DisasContext *ctx)
5667 {
5668 /* Always fails locking the cache */
5669 TCGv t0 = tcg_temp_new();
5670 gen_load_spr(t0, SPR_Exxx_L1CSR0);
5671 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
5672 gen_store_spr(SPR_Exxx_L1CSR0, t0);
5673 tcg_temp_free(t0);
5674 }
5675
5676 /* dcbz */
5677 static void gen_dcbz(DisasContext *ctx)
5678 {
5679 TCGv tcgv_addr;
5680 TCGv_i32 tcgv_op;
5681
5682 gen_set_access_type(ctx, ACCESS_CACHE);
5683 tcgv_addr = tcg_temp_new();
5684 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5685 gen_addr_reg_index(ctx, tcgv_addr);
5686 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
5687 tcg_temp_free(tcgv_addr);
5688 tcg_temp_free_i32(tcgv_op);
5689 }
5690
5691 /* dcbzep */
5692 static void gen_dcbzep(DisasContext *ctx)
5693 {
5694 TCGv tcgv_addr;
5695 TCGv_i32 tcgv_op;
5696
5697 gen_set_access_type(ctx, ACCESS_CACHE);
5698 tcgv_addr = tcg_temp_new();
5699 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5700 gen_addr_reg_index(ctx, tcgv_addr);
5701 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
5702 tcg_temp_free(tcgv_addr);
5703 tcg_temp_free_i32(tcgv_op);
5704 }
5705
5706 /* dst / dstt */
5707 static void gen_dst(DisasContext *ctx)
5708 {
5709 if (rA(ctx->opcode) == 0) {
5710 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5711 } else {
5712 /* interpreted as no-op */
5713 }
5714 }
5715
5716 /* dstst /dststt */
5717 static void gen_dstst(DisasContext *ctx)
5718 {
5719 if (rA(ctx->opcode) == 0) {
5720 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5721 } else {
5722 /* interpreted as no-op */
5723 }
5724
5725 }
5726
5727 /* dss / dssall */
5728 static void gen_dss(DisasContext *ctx)
5729 {
5730 /* interpreted as no-op */
5731 }
5732
5733 /* icbi */
5734 static void gen_icbi(DisasContext *ctx)
5735 {
5736 TCGv t0;
5737 gen_set_access_type(ctx, ACCESS_CACHE);
5738 t0 = tcg_temp_new();
5739 gen_addr_reg_index(ctx, t0);
5740 gen_helper_icbi(cpu_env, t0);
5741 tcg_temp_free(t0);
5742 }
5743
5744 /* icbiep */
5745 static void gen_icbiep(DisasContext *ctx)
5746 {
5747 TCGv t0;
5748 gen_set_access_type(ctx, ACCESS_CACHE);
5749 t0 = tcg_temp_new();
5750 gen_addr_reg_index(ctx, t0);
5751 gen_helper_icbiep(cpu_env, t0);
5752 tcg_temp_free(t0);
5753 }
5754
5755 /* Optional: */
5756 /* dcba */
5757 static void gen_dcba(DisasContext *ctx)
5758 {
5759 /*
5760 * interpreted as no-op
5761 * XXX: specification say this is treated as a store by the MMU
5762 * but does not generate any exception
5763 */
5764 }
5765
5766 /*** Segment register manipulation ***/
5767 /* Supervisor only: */
5768
5769 /* mfsr */
5770 static void gen_mfsr(DisasContext *ctx)
5771 {
5772 #if defined(CONFIG_USER_ONLY)
5773 GEN_PRIV;
5774 #else
5775 TCGv t0;
5776
5777 CHK_SV;
5778 t0 = tcg_const_tl(SR(ctx->opcode));
5779 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5780 tcg_temp_free(t0);
5781 #endif /* defined(CONFIG_USER_ONLY) */
5782 }
5783
5784 /* mfsrin */
5785 static void gen_mfsrin(DisasContext *ctx)
5786 {
5787 #if defined(CONFIG_USER_ONLY)
5788 GEN_PRIV;
5789 #else
5790 TCGv t0;
5791
5792 CHK_SV;
5793 t0 = tcg_temp_new();
5794 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5795 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5796 tcg_temp_free(t0);
5797 #endif /* defined(CONFIG_USER_ONLY) */
5798 }
5799
5800 /* mtsr */
5801 static void gen_mtsr(DisasContext *ctx)
5802 {
5803 #if defined(CONFIG_USER_ONLY)
5804 GEN_PRIV;
5805 #else
5806 TCGv t0;
5807
5808 CHK_SV;
5809 t0 = tcg_const_tl(SR(ctx->opcode));
5810 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5811 tcg_temp_free(t0);
5812 #endif /* defined(CONFIG_USER_ONLY) */
5813 }
5814
5815 /* mtsrin */
5816 static void gen_mtsrin(DisasContext *ctx)
5817 {
5818 #if defined(CONFIG_USER_ONLY)
5819 GEN_PRIV;
5820 #else
5821 TCGv t0;
5822 CHK_SV;
5823
5824 t0 = tcg_temp_new();
5825 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5826 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5827 tcg_temp_free(t0);
5828 #endif /* defined(CONFIG_USER_ONLY) */
5829 }
5830
5831 #if defined(TARGET_PPC64)
5832 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5833
5834 /* mfsr */
5835 static void gen_mfsr_64b(DisasContext *ctx)
5836 {
5837 #if defined(CONFIG_USER_ONLY)
5838 GEN_PRIV;
5839 #else
5840 TCGv t0;
5841
5842 CHK_SV;
5843 t0 = tcg_const_tl(SR(ctx->opcode));
5844 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5845 tcg_temp_free(t0);
5846 #endif /* defined(CONFIG_USER_ONLY) */
5847 }
5848
5849 /* mfsrin */
5850 static void gen_mfsrin_64b(DisasContext *ctx)
5851 {
5852 #if defined(CONFIG_USER_ONLY)
5853 GEN_PRIV;
5854 #else
5855 TCGv t0;
5856
5857 CHK_SV;
5858 t0 = tcg_temp_new();
5859 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5860 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5861 tcg_temp_free(t0);
5862 #endif /* defined(CONFIG_USER_ONLY) */
5863 }
5864
5865 /* mtsr */
5866 static void gen_mtsr_64b(DisasContext *ctx)
5867 {
5868 #if defined(CONFIG_USER_ONLY)
5869 GEN_PRIV;
5870 #else
5871 TCGv t0;
5872
5873 CHK_SV;
5874 t0 = tcg_const_tl(SR(ctx->opcode));
5875 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5876 tcg_temp_free(t0);
5877 #endif /* defined(CONFIG_USER_ONLY) */
5878 }
5879
5880 /* mtsrin */
5881 static void gen_mtsrin_64b(DisasContext *ctx)
5882 {
5883 #if defined(CONFIG_USER_ONLY)
5884 GEN_PRIV;
5885 #else
5886 TCGv t0;
5887
5888 CHK_SV;
5889 t0 = tcg_temp_new();
5890 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5891 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5892 tcg_temp_free(t0);
5893 #endif /* defined(CONFIG_USER_ONLY) */
5894 }
5895
5896 /* slbmte */
5897 static void gen_slbmte(DisasContext *ctx)
5898 {
5899 #if defined(CONFIG_USER_ONLY)
5900 GEN_PRIV;
5901 #else
5902 CHK_SV;
5903
5904 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
5905 cpu_gpr[rS(ctx->opcode)]);
5906 #endif /* defined(CONFIG_USER_ONLY) */
5907 }
5908
5909 static void gen_slbmfee(DisasContext *ctx)
5910 {
5911 #if defined(CONFIG_USER_ONLY)
5912 GEN_PRIV;
5913 #else
5914 CHK_SV;
5915
5916 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5917 cpu_gpr[rB(ctx->opcode)]);
5918 #endif /* defined(CONFIG_USER_ONLY) */
5919 }
5920
5921 static void gen_slbmfev(DisasContext *ctx)
5922 {
5923 #if defined(CONFIG_USER_ONLY)
5924 GEN_PRIV;
5925 #else
5926 CHK_SV;
5927
5928 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5929 cpu_gpr[rB(ctx->opcode)]);
5930 #endif /* defined(CONFIG_USER_ONLY) */
5931 }
5932
5933 static void gen_slbfee_(DisasContext *ctx)
5934 {
5935 #if defined(CONFIG_USER_ONLY)
5936 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5937 #else
5938 TCGLabel *l1, *l2;
5939
5940 if (unlikely(ctx->pr)) {
5941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5942 return;
5943 }
5944 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5945 cpu_gpr[rB(ctx->opcode)]);
5946 l1 = gen_new_label();
5947 l2 = gen_new_label();
5948 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5949 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
5950 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
5951 tcg_gen_br(l2);
5952 gen_set_label(l1);
5953 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5954 gen_set_label(l2);
5955 #endif
5956 }
5957 #endif /* defined(TARGET_PPC64) */
5958
5959 /*** Lookaside buffer management ***/
5960 /* Optional & supervisor only: */
5961
5962 /* tlbia */
5963 static void gen_tlbia(DisasContext *ctx)
5964 {
5965 #if defined(CONFIG_USER_ONLY)
5966 GEN_PRIV;
5967 #else
5968 CHK_HV;
5969
5970 gen_helper_tlbia(cpu_env);
5971 #endif /* defined(CONFIG_USER_ONLY) */
5972 }
5973
5974 /* tlbiel */
5975 static void gen_tlbiel(DisasContext *ctx)
5976 {
5977 #if defined(CONFIG_USER_ONLY)
5978 GEN_PRIV;
5979 #else
5980 CHK_SV;
5981
5982 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5983 #endif /* defined(CONFIG_USER_ONLY) */
5984 }
5985
5986 /* tlbie */
5987 static void gen_tlbie(DisasContext *ctx)
5988 {
5989 #if defined(CONFIG_USER_ONLY)
5990 GEN_PRIV;
5991 #else
5992 TCGv_i32 t1;
5993
5994 if (ctx->gtse) {
5995 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
5996 } else {
5997 CHK_HV; /* Else hypervisor privileged */
5998 }
5999
6000 if (NARROW_MODE(ctx)) {
6001 TCGv t0 = tcg_temp_new();
6002 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
6003 gen_helper_tlbie(cpu_env, t0);
6004 tcg_temp_free(t0);
6005 } else {
6006 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6007 }
6008 t1 = tcg_temp_new_i32();
6009 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
6010 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
6011 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
6012 tcg_temp_free_i32(t1);
6013 #endif /* defined(CONFIG_USER_ONLY) */
6014 }
6015
6016 /* tlbsync */
6017 static void gen_tlbsync(DisasContext *ctx)
6018 {
6019 #if defined(CONFIG_USER_ONLY)
6020 GEN_PRIV;
6021 #else
6022
6023 if (ctx->gtse) {
6024 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
6025 } else {
6026 CHK_HV; /* Else hypervisor privileged */
6027 }
6028
6029 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
6030 if (ctx->insns_flags & PPC_BOOKE) {
6031 gen_check_tlb_flush(ctx, true);
6032 }
6033 #endif /* defined(CONFIG_USER_ONLY) */
6034 }
6035
6036 #if defined(TARGET_PPC64)
6037 /* slbia */
6038 static void gen_slbia(DisasContext *ctx)
6039 {
6040 #if defined(CONFIG_USER_ONLY)
6041 GEN_PRIV;
6042 #else
6043 uint32_t ih = (ctx->opcode >> 21) & 0x7;
6044 TCGv_i32 t0 = tcg_const_i32(ih);
6045
6046 CHK_SV;
6047
6048 gen_helper_slbia(cpu_env, t0);
6049 tcg_temp_free_i32(t0);
6050 #endif /* defined(CONFIG_USER_ONLY) */
6051 }
6052
6053 /* slbie */
6054 static void gen_slbie(DisasContext *ctx)
6055 {
6056 #if defined(CONFIG_USER_ONLY)
6057 GEN_PRIV;
6058 #else
6059 CHK_SV;
6060
6061 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6062 #endif /* defined(CONFIG_USER_ONLY) */
6063 }
6064
6065 /* slbieg */
6066 static void gen_slbieg(DisasContext *ctx)
6067 {
6068 #if defined(CONFIG_USER_ONLY)
6069 GEN_PRIV;
6070 #else
6071 CHK_SV;
6072
6073 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6074 #endif /* defined(CONFIG_USER_ONLY) */
6075 }
6076
6077 /* slbsync */
6078 static void gen_slbsync(DisasContext *ctx)
6079 {
6080 #if defined(CONFIG_USER_ONLY)
6081 GEN_PRIV;
6082 #else
6083 CHK_SV;
6084 gen_check_tlb_flush(ctx, true);
6085 #endif /* defined(CONFIG_USER_ONLY) */
6086 }
6087
6088 #endif /* defined(TARGET_PPC64) */
6089
6090 /*** External control ***/
6091 /* Optional: */
6092
6093 /* eciwx */
6094 static void gen_eciwx(DisasContext *ctx)
6095 {
6096 TCGv t0;
6097 /* Should check EAR[E] ! */
6098 gen_set_access_type(ctx, ACCESS_EXT);
6099 t0 = tcg_temp_new();
6100 gen_addr_reg_index(ctx, t0);
6101 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
6102 DEF_MEMOP(MO_UL | MO_ALIGN));
6103 tcg_temp_free(t0);
6104 }
6105
6106 /* ecowx */
6107 static void gen_ecowx(DisasContext *ctx)
6108 {
6109 TCGv t0;
6110 /* Should check EAR[E] ! */
6111 gen_set_access_type(ctx, ACCESS_EXT);
6112 t0 = tcg_temp_new();
6113 gen_addr_reg_index(ctx, t0);
6114 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
6115 DEF_MEMOP(MO_UL | MO_ALIGN));
6116 tcg_temp_free(t0);
6117 }
6118
6119 /* PowerPC 601 specific instructions */
6120
6121 /* abs - abs. */
6122 static void gen_abs(DisasContext *ctx)
6123 {
6124 TCGv d = cpu_gpr[rD(ctx->opcode)];
6125 TCGv a = cpu_gpr[rA(ctx->opcode)];
6126
6127 tcg_gen_abs_tl(d, a);
6128 if (unlikely(Rc(ctx->opcode) != 0)) {
6129 gen_set_Rc0(ctx, d);
6130 }
6131 }
6132
6133 /* abso - abso. */
6134 static void gen_abso(DisasContext *ctx)
6135 {
6136 TCGv d = cpu_gpr[rD(ctx->opcode)];
6137 TCGv a = cpu_gpr[rA(ctx->opcode)];
6138
6139 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000);
6140 tcg_gen_abs_tl(d, a);
6141 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
6142 if (unlikely(Rc(ctx->opcode) != 0)) {
6143 gen_set_Rc0(ctx, d);
6144 }
6145 }
6146
6147 /* clcs */
6148 static void gen_clcs(DisasContext *ctx)
6149 {
6150 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
6151 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6152 tcg_temp_free_i32(t0);
6153 /* Rc=1 sets CR0 to an undefined state */
6154 }
6155
6156 /* div - div. */
6157 static void gen_div(DisasContext *ctx)
6158 {
6159 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6160 cpu_gpr[rB(ctx->opcode)]);
6161 if (unlikely(Rc(ctx->opcode) != 0)) {
6162 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6163 }
6164 }
6165
6166 /* divo - divo. */
6167 static void gen_divo(DisasContext *ctx)
6168 {
6169 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6170 cpu_gpr[rB(ctx->opcode)]);
6171 if (unlikely(Rc(ctx->opcode) != 0)) {
6172 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6173 }
6174 }
6175
6176 /* divs - divs. */
6177 static void gen_divs(DisasContext *ctx)
6178 {
6179 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6180 cpu_gpr[rB(ctx->opcode)]);
6181 if (unlikely(Rc(ctx->opcode) != 0)) {
6182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6183 }
6184 }
6185
6186 /* divso - divso. */
6187 static void gen_divso(DisasContext *ctx)
6188 {
6189 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
6190 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6191 if (unlikely(Rc(ctx->opcode) != 0)) {
6192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6193 }
6194 }
6195
6196 /* doz - doz. */
6197 static void gen_doz(DisasContext *ctx)
6198 {
6199 TCGLabel *l1 = gen_new_label();
6200 TCGLabel *l2 = gen_new_label();
6201 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
6202 cpu_gpr[rA(ctx->opcode)], l1);
6203 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
6204 cpu_gpr[rA(ctx->opcode)]);
6205 tcg_gen_br(l2);
6206 gen_set_label(l1);
6207 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6208 gen_set_label(l2);
6209 if (unlikely(Rc(ctx->opcode) != 0)) {
6210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6211 }
6212 }
6213
6214 /* dozo - dozo. */
6215 static void gen_dozo(DisasContext *ctx)
6216 {
6217 TCGLabel *l1 = gen_new_label();
6218 TCGLabel *l2 = gen_new_label();
6219 TCGv t0 = tcg_temp_new();
6220 TCGv t1 = tcg_temp_new();
6221 TCGv t2 = tcg_temp_new();
6222 /* Start with XER OV disabled, the most likely case */
6223 tcg_gen_movi_tl(cpu_ov, 0);
6224 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
6225 cpu_gpr[rA(ctx->opcode)], l1);
6226 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6227 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6228 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
6229 tcg_gen_andc_tl(t1, t1, t2);
6230 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6231 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
6232 tcg_gen_movi_tl(cpu_ov, 1);
6233 tcg_gen_movi_tl(cpu_so, 1);
6234 tcg_gen_br(l2);
6235 gen_set_label(l1);
6236 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6237 gen_set_label(l2);
6238 tcg_temp_free(t0);
6239 tcg_temp_free(t1);
6240 tcg_temp_free(t2);
6241 if (unlikely(Rc(ctx->opcode) != 0)) {
6242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6243 }
6244 }
6245
6246 /* dozi */
6247 static void gen_dozi(DisasContext *ctx)
6248 {
6249 target_long simm = SIMM(ctx->opcode);
6250 TCGLabel *l1 = gen_new_label();
6251 TCGLabel *l2 = gen_new_label();
6252 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
6253 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
6254 tcg_gen_br(l2);
6255 gen_set_label(l1);
6256 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6257 gen_set_label(l2);
6258 if (unlikely(Rc(ctx->opcode) != 0)) {
6259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6260 }
6261 }
6262
6263 /* lscbx - lscbx. */
6264 static void gen_lscbx(DisasContext *ctx)
6265 {
6266 TCGv t0 = tcg_temp_new();
6267 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
6268 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
6269 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
6270
6271 gen_addr_reg_index(ctx, t0);
6272 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
6273 tcg_temp_free_i32(t1);
6274 tcg_temp_free_i32(t2);
6275 tcg_temp_free_i32(t3);
6276 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
6277 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
6278 if (unlikely(Rc(ctx->opcode) != 0)) {
6279 gen_set_Rc0(ctx, t0);
6280 }
6281 tcg_temp_free(t0);
6282 }
6283
6284 /* maskg - maskg. */
6285 static void gen_maskg(DisasContext *ctx)
6286 {
6287 TCGLabel *l1 = gen_new_label();
6288 TCGv t0 = tcg_temp_new();
6289 TCGv t1 = tcg_temp_new();
6290 TCGv t2 = tcg_temp_new();
6291 TCGv t3 = tcg_temp_new();
6292 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
6293 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6294 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
6295 tcg_gen_addi_tl(t2, t0, 1);
6296 tcg_gen_shr_tl(t2, t3, t2);
6297 tcg_gen_shr_tl(t3, t3, t1);
6298 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
6299 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
6300 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6301 gen_set_label(l1);
6302 tcg_temp_free(t0);
6303 tcg_temp_free(t1);
6304 tcg_temp_free(t2);
6305 tcg_temp_free(t3);
6306 if (unlikely(Rc(ctx->opcode) != 0)) {
6307 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6308 }
6309 }
6310
6311 /* maskir - maskir. */
6312 static void gen_maskir(DisasContext *ctx)
6313 {
6314 TCGv t0 = tcg_temp_new();
6315 TCGv t1 = tcg_temp_new();
6316 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6317 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6318 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6319 tcg_temp_free(t0);
6320 tcg_temp_free(t1);
6321 if (unlikely(Rc(ctx->opcode) != 0)) {
6322 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6323 }
6324 }
6325
6326 /* mul - mul. */
6327 static void gen_mul(DisasContext *ctx)
6328 {
6329 TCGv_i64 t0 = tcg_temp_new_i64();
6330 TCGv_i64 t1 = tcg_temp_new_i64();
6331 TCGv t2 = tcg_temp_new();
6332 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
6333 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
6334 tcg_gen_mul_i64(t0, t0, t1);
6335 tcg_gen_trunc_i64_tl(t2, t0);
6336 gen_store_spr(SPR_MQ, t2);
6337 tcg_gen_shri_i64(t1, t0, 32);
6338 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
6339 tcg_temp_free_i64(t0);
6340 tcg_temp_free_i64(t1);
6341 tcg_temp_free(t2);
6342 if (unlikely(Rc(ctx->opcode) != 0)) {
6343 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6344 }
6345 }
6346
6347 /* mulo - mulo. */
6348 static void gen_mulo(DisasContext *ctx)
6349 {
6350 TCGLabel *l1 = gen_new_label();
6351 TCGv_i64 t0 = tcg_temp_new_i64();
6352 TCGv_i64 t1 = tcg_temp_new_i64();
6353 TCGv t2 = tcg_temp_new();
6354 /* Start with XER OV disabled, the most likely case */
6355 tcg_gen_movi_tl(cpu_ov, 0);
6356 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
6357 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
6358 tcg_gen_mul_i64(t0, t0, t1);
6359 tcg_gen_trunc_i64_tl(t2, t0);
6360 gen_store_spr(SPR_MQ, t2);
6361 tcg_gen_shri_i64(t1, t0, 32);
6362 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
6363 tcg_gen_ext32s_i64(t1, t0);
6364 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
6365 tcg_gen_movi_tl(cpu_ov, 1);
6366 tcg_gen_movi_tl(cpu_so, 1);
6367 gen_set_label(l1);
6368 tcg_temp_free_i64(t0);
6369 tcg_temp_free_i64(t1);
6370 tcg_temp_free(t2);
6371 if (unlikely(Rc(ctx->opcode) != 0)) {
6372 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6373 }
6374 }
6375
6376 /* nabs - nabs. */
6377 static void gen_nabs(DisasContext *ctx)
6378 {
6379 TCGv d = cpu_gpr[rD(ctx->opcode)];
6380 TCGv a = cpu_gpr[rA(ctx->opcode)];
6381
6382 tcg_gen_abs_tl(d, a);
6383 tcg_gen_neg_tl(d, d);
6384 if (unlikely(Rc(ctx->opcode) != 0)) {
6385 gen_set_Rc0(ctx, d);
6386 }
6387 }
6388
6389 /* nabso - nabso. */
6390 static void gen_nabso(DisasContext *ctx)
6391 {
6392 TCGv d = cpu_gpr[rD(ctx->opcode)];
6393 TCGv a = cpu_gpr[rA(ctx->opcode)];
6394
6395 tcg_gen_abs_tl(d, a);
6396 tcg_gen_neg_tl(d, d);
6397 /* nabs never overflows */
6398 tcg_gen_movi_tl(cpu_ov, 0);
6399 if (unlikely(Rc(ctx->opcode) != 0)) {
6400 gen_set_Rc0(ctx, d);
6401 }
6402 }
6403
6404 /* rlmi - rlmi. */
6405 static void gen_rlmi(DisasContext *ctx)
6406 {
6407 uint32_t mb = MB(ctx->opcode);
6408 uint32_t me = ME(ctx->opcode);
6409 TCGv t0 = tcg_temp_new();
6410 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6411 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6412 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
6413 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
6414 ~MASK(mb, me));
6415 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
6416 tcg_temp_free(t0);
6417 if (unlikely(Rc(ctx->opcode) != 0)) {
6418 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6419 }
6420 }
6421
6422 /* rrib - rrib. */
6423 static void gen_rrib(DisasContext *ctx)
6424 {
6425 TCGv t0 = tcg_temp_new();
6426 TCGv t1 = tcg_temp_new();
6427 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6428 tcg_gen_movi_tl(t1, 0x80000000);
6429 tcg_gen_shr_tl(t1, t1, t0);
6430 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6431 tcg_gen_and_tl(t0, t0, t1);
6432 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
6433 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6434 tcg_temp_free(t0);
6435 tcg_temp_free(t1);
6436 if (unlikely(Rc(ctx->opcode) != 0)) {
6437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6438 }
6439 }
6440
6441 /* sle - sle. */
6442 static void gen_sle(DisasContext *ctx)
6443 {
6444 TCGv t0 = tcg_temp_new();
6445 TCGv t1 = tcg_temp_new();
6446 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6447 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6448 tcg_gen_subfi_tl(t1, 32, t1);
6449 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6450 tcg_gen_or_tl(t1, t0, t1);
6451 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6452 gen_store_spr(SPR_MQ, t1);
6453 tcg_temp_free(t0);
6454 tcg_temp_free(t1);
6455 if (unlikely(Rc(ctx->opcode) != 0)) {
6456 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6457 }
6458 }
6459
6460 /* sleq - sleq. */
6461 static void gen_sleq(DisasContext *ctx)
6462 {
6463 TCGv t0 = tcg_temp_new();
6464 TCGv t1 = tcg_temp_new();
6465 TCGv t2 = tcg_temp_new();
6466 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6467 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
6468 tcg_gen_shl_tl(t2, t2, t0);
6469 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6470 gen_load_spr(t1, SPR_MQ);
6471 gen_store_spr(SPR_MQ, t0);
6472 tcg_gen_and_tl(t0, t0, t2);
6473 tcg_gen_andc_tl(t1, t1, t2);
6474 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6475 tcg_temp_free(t0);
6476 tcg_temp_free(t1);
6477 tcg_temp_free(t2);
6478 if (unlikely(Rc(ctx->opcode) != 0)) {
6479 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6480 }
6481 }
6482
6483 /* sliq - sliq. */
6484 static void gen_sliq(DisasContext *ctx)
6485 {
6486 int sh = SH(ctx->opcode);
6487 TCGv t0 = tcg_temp_new();
6488 TCGv t1 = tcg_temp_new();
6489 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6490 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6491 tcg_gen_or_tl(t1, t0, t1);
6492 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6493 gen_store_spr(SPR_MQ, t1);
6494 tcg_temp_free(t0);
6495 tcg_temp_free(t1);
6496 if (unlikely(Rc(ctx->opcode) != 0)) {
6497 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6498 }
6499 }
6500
6501 /* slliq - slliq. */
6502 static void gen_slliq(DisasContext *ctx)
6503 {
6504 int sh = SH(ctx->opcode);
6505 TCGv t0 = tcg_temp_new();
6506 TCGv t1 = tcg_temp_new();
6507 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6508 gen_load_spr(t1, SPR_MQ);
6509 gen_store_spr(SPR_MQ, t0);
6510 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
6511 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
6512 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6513 tcg_temp_free(t0);
6514 tcg_temp_free(t1);
6515 if (unlikely(Rc(ctx->opcode) != 0)) {
6516 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6517 }
6518 }
6519
6520 /* sllq - sllq. */
6521 static void gen_sllq(DisasContext *ctx)
6522 {
6523 TCGLabel *l1 = gen_new_label();
6524 TCGLabel *l2 = gen_new_label();
6525 TCGv t0 = tcg_temp_local_new();
6526 TCGv t1 = tcg_temp_local_new();
6527 TCGv t2 = tcg_temp_local_new();
6528 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6529 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6530 tcg_gen_shl_tl(t1, t1, t2);
6531 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6532 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6533 gen_load_spr(t0, SPR_MQ);
6534 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6535 tcg_gen_br(l2);
6536 gen_set_label(l1);
6537 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6538 gen_load_spr(t2, SPR_MQ);
6539 tcg_gen_andc_tl(t1, t2, t1);
6540 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6541 gen_set_label(l2);
6542 tcg_temp_free(t0);
6543 tcg_temp_free(t1);
6544 tcg_temp_free(t2);
6545 if (unlikely(Rc(ctx->opcode) != 0)) {
6546 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6547 }
6548 }
6549
6550 /* slq - slq. */
6551 static void gen_slq(DisasContext *ctx)
6552 {
6553 TCGLabel *l1 = gen_new_label();
6554 TCGv t0 = tcg_temp_new();
6555 TCGv t1 = tcg_temp_new();
6556 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6557 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6558 tcg_gen_subfi_tl(t1, 32, t1);
6559 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6560 tcg_gen_or_tl(t1, t0, t1);
6561 gen_store_spr(SPR_MQ, t1);
6562 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6563 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6564 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6565 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6566 gen_set_label(l1);
6567 tcg_temp_free(t0);
6568 tcg_temp_free(t1);
6569 if (unlikely(Rc(ctx->opcode) != 0)) {
6570 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6571 }
6572 }
6573
6574 /* sraiq - sraiq. */
6575 static void gen_sraiq(DisasContext *ctx)
6576 {
6577 int sh = SH(ctx->opcode);
6578 TCGLabel *l1 = gen_new_label();
6579 TCGv t0 = tcg_temp_new();
6580 TCGv t1 = tcg_temp_new();
6581 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6582 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6583 tcg_gen_or_tl(t0, t0, t1);
6584 gen_store_spr(SPR_MQ, t0);
6585 tcg_gen_movi_tl(cpu_ca, 0);
6586 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6587 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
6588 tcg_gen_movi_tl(cpu_ca, 1);
6589 gen_set_label(l1);
6590 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
6591 tcg_temp_free(t0);
6592 tcg_temp_free(t1);
6593 if (unlikely(Rc(ctx->opcode) != 0)) {
6594 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6595 }
6596 }
6597
6598 /* sraq - sraq. */
6599 static void gen_sraq(DisasContext *ctx)
6600 {
6601 TCGLabel *l1 = gen_new_label();
6602 TCGLabel *l2 = gen_new_label();
6603 TCGv t0 = tcg_temp_new();
6604 TCGv t1 = tcg_temp_local_new();
6605 TCGv t2 = tcg_temp_local_new();
6606 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6607 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6608 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
6609 tcg_gen_subfi_tl(t2, 32, t2);
6610 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
6611 tcg_gen_or_tl(t0, t0, t2);
6612 gen_store_spr(SPR_MQ, t0);
6613 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6614 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
6615 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
6616 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
6617 gen_set_label(l1);
6618 tcg_temp_free(t0);
6619 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
6620 tcg_gen_movi_tl(cpu_ca, 0);
6621 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
6622 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
6623 tcg_gen_movi_tl(cpu_ca, 1);
6624 gen_set_label(l2);
6625 tcg_temp_free(t1);
6626 tcg_temp_free(t2);
6627 if (unlikely(Rc(ctx->opcode) != 0)) {
6628 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6629 }
6630 }
6631
6632 /* sre - sre. */
6633 static void gen_sre(DisasContext *ctx)
6634 {
6635 TCGv t0 = tcg_temp_new();
6636 TCGv t1 = tcg_temp_new();
6637 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6638 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6639 tcg_gen_subfi_tl(t1, 32, t1);
6640 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6641 tcg_gen_or_tl(t1, t0, t1);
6642 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6643 gen_store_spr(SPR_MQ, t1);
6644 tcg_temp_free(t0);
6645 tcg_temp_free(t1);
6646 if (unlikely(Rc(ctx->opcode) != 0)) {
6647 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6648 }
6649 }
6650
6651 /* srea - srea. */
6652 static void gen_srea(DisasContext *ctx)
6653 {
6654 TCGv t0 = tcg_temp_new();
6655 TCGv t1 = tcg_temp_new();
6656 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6657 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6658 gen_store_spr(SPR_MQ, t0);
6659 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
6660 tcg_temp_free(t0);
6661 tcg_temp_free(t1);
6662 if (unlikely(Rc(ctx->opcode) != 0)) {
6663 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6664 }
6665 }
6666
6667 /* sreq */
6668 static void gen_sreq(DisasContext *ctx)
6669 {
6670 TCGv t0 = tcg_temp_new();
6671 TCGv t1 = tcg_temp_new();
6672 TCGv t2 = tcg_temp_new();
6673 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6674 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6675 tcg_gen_shr_tl(t1, t1, t0);
6676 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6677 gen_load_spr(t2, SPR_MQ);
6678 gen_store_spr(SPR_MQ, t0);
6679 tcg_gen_and_tl(t0, t0, t1);
6680 tcg_gen_andc_tl(t2, t2, t1);
6681 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6682 tcg_temp_free(t0);
6683 tcg_temp_free(t1);
6684 tcg_temp_free(t2);
6685 if (unlikely(Rc(ctx->opcode) != 0)) {
6686 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6687 }
6688 }
6689
6690 /* sriq */
6691 static void gen_sriq(DisasContext *ctx)
6692 {
6693 int sh = SH(ctx->opcode);
6694 TCGv t0 = tcg_temp_new();
6695 TCGv t1 = tcg_temp_new();
6696 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6697 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6698 tcg_gen_or_tl(t1, t0, t1);
6699 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6700 gen_store_spr(SPR_MQ, t1);
6701 tcg_temp_free(t0);
6702 tcg_temp_free(t1);
6703 if (unlikely(Rc(ctx->opcode) != 0)) {
6704 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6705 }
6706 }
6707
6708 /* srliq */
6709 static void gen_srliq(DisasContext *ctx)
6710 {
6711 int sh = SH(ctx->opcode);
6712 TCGv t0 = tcg_temp_new();
6713 TCGv t1 = tcg_temp_new();
6714 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6715 gen_load_spr(t1, SPR_MQ);
6716 gen_store_spr(SPR_MQ, t0);
6717 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
6718 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
6719 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6720 tcg_temp_free(t0);
6721 tcg_temp_free(t1);
6722 if (unlikely(Rc(ctx->opcode) != 0)) {
6723 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6724 }
6725 }
6726
6727 /* srlq */
6728 static void gen_srlq(DisasContext *ctx)
6729 {
6730 TCGLabel *l1 = gen_new_label();
6731 TCGLabel *l2 = gen_new_label();
6732 TCGv t0 = tcg_temp_local_new();
6733 TCGv t1 = tcg_temp_local_new();
6734 TCGv t2 = tcg_temp_local_new();
6735 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6736 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6737 tcg_gen_shr_tl(t2, t1, t2);
6738 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6739 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6740 gen_load_spr(t0, SPR_MQ);
6741 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6742 tcg_gen_br(l2);
6743 gen_set_label(l1);
6744 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6745 tcg_gen_and_tl(t0, t0, t2);
6746 gen_load_spr(t1, SPR_MQ);
6747 tcg_gen_andc_tl(t1, t1, t2);
6748 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6749 gen_set_label(l2);
6750 tcg_temp_free(t0);
6751 tcg_temp_free(t1);
6752 tcg_temp_free(t2);
6753 if (unlikely(Rc(ctx->opcode) != 0)) {
6754 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6755 }
6756 }
6757
6758 /* srq */
6759 static void gen_srq(DisasContext *ctx)
6760 {
6761 TCGLabel *l1 = gen_new_label();
6762 TCGv t0 = tcg_temp_new();
6763 TCGv t1 = tcg_temp_new();
6764 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6765 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6766 tcg_gen_subfi_tl(t1, 32, t1);
6767 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6768 tcg_gen_or_tl(t1, t0, t1);
6769 gen_store_spr(SPR_MQ, t1);
6770 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6772 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6773 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6774 gen_set_label(l1);
6775 tcg_temp_free(t0);
6776 tcg_temp_free(t1);
6777 if (unlikely(Rc(ctx->opcode) != 0)) {
6778 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6779 }
6780 }
6781
6782 /* PowerPC 602 specific instructions */
6783
6784 /* dsa */
6785 static void gen_dsa(DisasContext *ctx)
6786 {
6787 /* XXX: TODO */
6788 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6789 }
6790
6791 /* esa */
6792 static void gen_esa(DisasContext *ctx)
6793 {
6794 /* XXX: TODO */
6795 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6796 }
6797
6798 /* mfrom */
6799 static void gen_mfrom(DisasContext *ctx)
6800 {
6801 #if defined(CONFIG_USER_ONLY)
6802 GEN_PRIV;
6803 #else
6804 CHK_SV;
6805 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6806 #endif /* defined(CONFIG_USER_ONLY) */
6807 }
6808
6809 /* 602 - 603 - G2 TLB management */
6810
6811 /* tlbld */
6812 static void gen_tlbld_6xx(DisasContext *ctx)
6813 {
6814 #if defined(CONFIG_USER_ONLY)
6815 GEN_PRIV;
6816 #else
6817 CHK_SV;
6818 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6819 #endif /* defined(CONFIG_USER_ONLY) */
6820 }
6821
6822 /* tlbli */
6823 static void gen_tlbli_6xx(DisasContext *ctx)
6824 {
6825 #if defined(CONFIG_USER_ONLY)
6826 GEN_PRIV;
6827 #else
6828 CHK_SV;
6829 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6830 #endif /* defined(CONFIG_USER_ONLY) */
6831 }
6832
6833 /* 74xx TLB management */
6834
6835 /* tlbld */
6836 static void gen_tlbld_74xx(DisasContext *ctx)
6837 {
6838 #if defined(CONFIG_USER_ONLY)
6839 GEN_PRIV;
6840 #else
6841 CHK_SV;
6842 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6843 #endif /* defined(CONFIG_USER_ONLY) */
6844 }
6845
6846 /* tlbli */
6847 static void gen_tlbli_74xx(DisasContext *ctx)
6848 {
6849 #if defined(CONFIG_USER_ONLY)
6850 GEN_PRIV;
6851 #else
6852 CHK_SV;
6853 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6854 #endif /* defined(CONFIG_USER_ONLY) */
6855 }
6856
6857 /* POWER instructions not in PowerPC 601 */
6858
6859 /* clf */
6860 static void gen_clf(DisasContext *ctx)
6861 {
6862 /* Cache line flush: implemented as no-op */
6863 }
6864
6865 /* cli */
6866 static void gen_cli(DisasContext *ctx)
6867 {
6868 #if defined(CONFIG_USER_ONLY)
6869 GEN_PRIV;
6870 #else
6871 /* Cache line invalidate: privileged and treated as no-op */
6872 CHK_SV;
6873 #endif /* defined(CONFIG_USER_ONLY) */
6874 }
6875
6876 /* dclst */
6877 static void gen_dclst(DisasContext *ctx)
6878 {
6879 /* Data cache line store: treated as no-op */
6880 }
6881
6882 static void gen_mfsri(DisasContext *ctx)
6883 {
6884 #if defined(CONFIG_USER_ONLY)
6885 GEN_PRIV;
6886 #else
6887 int ra = rA(ctx->opcode);
6888 int rd = rD(ctx->opcode);
6889 TCGv t0;
6890
6891 CHK_SV;
6892 t0 = tcg_temp_new();
6893 gen_addr_reg_index(ctx, t0);
6894 tcg_gen_extract_tl(t0, t0, 28, 4);
6895 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
6896 tcg_temp_free(t0);
6897 if (ra != 0 && ra != rd) {
6898 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
6899 }
6900 #endif /* defined(CONFIG_USER_ONLY) */
6901 }
6902
6903 static void gen_rac(DisasContext *ctx)
6904 {
6905 #if defined(CONFIG_USER_ONLY)
6906 GEN_PRIV;
6907 #else
6908 TCGv t0;
6909
6910 CHK_SV;
6911 t0 = tcg_temp_new();
6912 gen_addr_reg_index(ctx, t0);
6913 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6914 tcg_temp_free(t0);
6915 #endif /* defined(CONFIG_USER_ONLY) */
6916 }
6917
6918 static void gen_rfsvc(DisasContext *ctx)
6919 {
6920 #if defined(CONFIG_USER_ONLY)
6921 GEN_PRIV;
6922 #else
6923 CHK_SV;
6924
6925 gen_helper_rfsvc(cpu_env);
6926 gen_sync_exception(ctx);
6927 #endif /* defined(CONFIG_USER_ONLY) */
6928 }
6929
6930 /* svc is not implemented for now */
6931
6932 /* BookE specific instructions */
6933
6934 /* XXX: not implemented on 440 ? */
6935 static void gen_mfapidi(DisasContext *ctx)
6936 {
6937 /* XXX: TODO */
6938 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6939 }
6940
6941 /* XXX: not implemented on 440 ? */
6942 static void gen_tlbiva(DisasContext *ctx)
6943 {
6944 #if defined(CONFIG_USER_ONLY)
6945 GEN_PRIV;
6946 #else
6947 TCGv t0;
6948
6949 CHK_SV;
6950 t0 = tcg_temp_new();
6951 gen_addr_reg_index(ctx, t0);
6952 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6953 tcg_temp_free(t0);
6954 #endif /* defined(CONFIG_USER_ONLY) */
6955 }
6956
6957 /* All 405 MAC instructions are translated here */
6958 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6959 int ra, int rb, int rt, int Rc)
6960 {
6961 TCGv t0, t1;
6962
6963 t0 = tcg_temp_local_new();
6964 t1 = tcg_temp_local_new();
6965
6966 switch (opc3 & 0x0D) {
6967 case 0x05:
6968 /* macchw - macchw. - macchwo - macchwo. */
6969 /* macchws - macchws. - macchwso - macchwso. */
6970 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6971 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6972 /* mulchw - mulchw. */
6973 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6974 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6975 tcg_gen_ext16s_tl(t1, t1);
6976 break;
6977 case 0x04:
6978 /* macchwu - macchwu. - macchwuo - macchwuo. */
6979 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6980 /* mulchwu - mulchwu. */
6981 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6982 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6983 tcg_gen_ext16u_tl(t1, t1);
6984 break;
6985 case 0x01:
6986 /* machhw - machhw. - machhwo - machhwo. */
6987 /* machhws - machhws. - machhwso - machhwso. */
6988 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6989 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6990 /* mulhhw - mulhhw. */
6991 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6992 tcg_gen_ext16s_tl(t0, t0);
6993 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6994 tcg_gen_ext16s_tl(t1, t1);
6995 break;
6996 case 0x00:
6997 /* machhwu - machhwu. - machhwuo - machhwuo. */
6998 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6999 /* mulhhwu - mulhhwu. */
7000 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
7001 tcg_gen_ext16u_tl(t0, t0);
7002 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
7003 tcg_gen_ext16u_tl(t1, t1);
7004 break;
7005 case 0x0D:
7006 /* maclhw - maclhw. - maclhwo - maclhwo. */
7007 /* maclhws - maclhws. - maclhwso - maclhwso. */
7008 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
7009 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
7010 /* mullhw - mullhw. */
7011 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
7012 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
7013 break;
7014 case 0x0C:
7015 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
7016 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
7017 /* mullhwu - mullhwu. */
7018 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
7019 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
7020 break;
7021 }
7022 if (opc2 & 0x04) {
7023 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
7024 tcg_gen_mul_tl(t1, t0, t1);
7025 if (opc2 & 0x02) {
7026 /* nmultiply-and-accumulate (0x0E) */
7027 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
7028 } else {
7029 /* multiply-and-accumulate (0x0C) */
7030 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
7031 }
7032
7033 if (opc3 & 0x12) {
7034 /* Check overflow and/or saturate */
7035 TCGLabel *l1 = gen_new_label();
7036
7037 if (opc3 & 0x10) {
7038 /* Start with XER OV disabled, the most likely case */
7039 tcg_gen_movi_tl(cpu_ov, 0);
7040 }
7041 if (opc3 & 0x01) {
7042 /* Signed */
7043 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
7044 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
7045 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
7046 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
7047 if (opc3 & 0x02) {
7048 /* Saturate */
7049 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
7050 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
7051 }
7052 } else {
7053 /* Unsigned */
7054 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
7055 if (opc3 & 0x02) {
7056 /* Saturate */
7057 tcg_gen_movi_tl(t0, UINT32_MAX);
7058 }
7059 }
7060 if (opc3 & 0x10) {
7061 /* Check overflow */
7062 tcg_gen_movi_tl(cpu_ov, 1);
7063 tcg_gen_movi_tl(cpu_so, 1);
7064 }
7065 gen_set_label(l1);
7066 tcg_gen_mov_tl(cpu_gpr[rt], t0);
7067 }
7068 } else {
7069 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
7070 }
7071 tcg_temp_free(t0);
7072 tcg_temp_free(t1);
7073 if (unlikely(Rc) != 0) {
7074 /* Update Rc0 */
7075 gen_set_Rc0(ctx, cpu_gpr[rt]);
7076 }
7077 }
7078
7079 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7080 static void glue(gen_, name)(DisasContext *ctx) \
7081 { \
7082 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
7083 rD(ctx->opcode), Rc(ctx->opcode)); \
7084 }
7085
7086 /* macchw - macchw. */
7087 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
7088 /* macchwo - macchwo. */
7089 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
7090 /* macchws - macchws. */
7091 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
7092 /* macchwso - macchwso. */
7093 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
7094 /* macchwsu - macchwsu. */
7095 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
7096 /* macchwsuo - macchwsuo. */
7097 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
7098 /* macchwu - macchwu. */
7099 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
7100 /* macchwuo - macchwuo. */
7101 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
7102 /* machhw - machhw. */
7103 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
7104 /* machhwo - machhwo. */
7105 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
7106 /* machhws - machhws. */
7107 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
7108 /* machhwso - machhwso. */
7109 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
7110 /* machhwsu - machhwsu. */
7111 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
7112 /* machhwsuo - machhwsuo. */
7113 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
7114 /* machhwu - machhwu. */
7115 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
7116 /* machhwuo - machhwuo. */
7117 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
7118 /* maclhw - maclhw. */
7119 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
7120 /* maclhwo - maclhwo. */
7121 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
7122 /* maclhws - maclhws. */
7123 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
7124 /* maclhwso - maclhwso. */
7125 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
7126 /* maclhwu - maclhwu. */
7127 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
7128 /* maclhwuo - maclhwuo. */
7129 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
7130 /* maclhwsu - maclhwsu. */
7131 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
7132 /* maclhwsuo - maclhwsuo. */
7133 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
7134 /* nmacchw - nmacchw. */
7135 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
7136 /* nmacchwo - nmacchwo. */
7137 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
7138 /* nmacchws - nmacchws. */
7139 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
7140 /* nmacchwso - nmacchwso. */
7141 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
7142 /* nmachhw - nmachhw. */
7143 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
7144 /* nmachhwo - nmachhwo. */
7145 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
7146 /* nmachhws - nmachhws. */
7147 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
7148 /* nmachhwso - nmachhwso. */
7149 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
7150 /* nmaclhw - nmaclhw. */
7151 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
7152 /* nmaclhwo - nmaclhwo. */
7153 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
7154 /* nmaclhws - nmaclhws. */
7155 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
7156 /* nmaclhwso - nmaclhwso. */
7157 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
7158
7159 /* mulchw - mulchw. */
7160 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
7161 /* mulchwu - mulchwu. */
7162 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
7163 /* mulhhw - mulhhw. */
7164 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
7165 /* mulhhwu - mulhhwu. */
7166 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
7167 /* mullhw - mullhw. */
7168 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
7169 /* mullhwu - mullhwu. */
7170 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
7171
7172 /* mfdcr */
7173 static void gen_mfdcr(DisasContext *ctx)
7174 {
7175 #if defined(CONFIG_USER_ONLY)
7176 GEN_PRIV;
7177 #else
7178 TCGv dcrn;
7179
7180 CHK_SV;
7181 dcrn = tcg_const_tl(SPR(ctx->opcode));
7182 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
7183 tcg_temp_free(dcrn);
7184 #endif /* defined(CONFIG_USER_ONLY) */
7185 }
7186
7187 /* mtdcr */
7188 static void gen_mtdcr(DisasContext *ctx)
7189 {
7190 #if defined(CONFIG_USER_ONLY)
7191 GEN_PRIV;
7192 #else
7193 TCGv dcrn;
7194
7195 CHK_SV;
7196 dcrn = tcg_const_tl(SPR(ctx->opcode));
7197 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
7198 tcg_temp_free(dcrn);
7199 #endif /* defined(CONFIG_USER_ONLY) */
7200 }
7201
7202 /* mfdcrx */
7203 /* XXX: not implemented on 440 ? */
7204 static void gen_mfdcrx(DisasContext *ctx)
7205 {
7206 #if defined(CONFIG_USER_ONLY)
7207 GEN_PRIV;
7208 #else
7209 CHK_SV;
7210 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
7211 cpu_gpr[rA(ctx->opcode)]);
7212 /* Note: Rc update flag set leads to undefined state of Rc0 */
7213 #endif /* defined(CONFIG_USER_ONLY) */
7214 }
7215
7216 /* mtdcrx */
7217 /* XXX: not implemented on 440 ? */
7218 static void gen_mtdcrx(DisasContext *ctx)
7219 {
7220 #if defined(CONFIG_USER_ONLY)
7221 GEN_PRIV;
7222 #else
7223 CHK_SV;
7224 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
7225 cpu_gpr[rS(ctx->opcode)]);
7226 /* Note: Rc update flag set leads to undefined state of Rc0 */
7227 #endif /* defined(CONFIG_USER_ONLY) */
7228 }
7229
7230 /* mfdcrux (PPC 460) : user-mode access to DCR */
7231 static void gen_mfdcrux(DisasContext *ctx)
7232 {
7233 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
7234 cpu_gpr[rA(ctx->opcode)]);
7235 /* Note: Rc update flag set leads to undefined state of Rc0 */
7236 }
7237
7238 /* mtdcrux (PPC 460) : user-mode access to DCR */
7239 static void gen_mtdcrux(DisasContext *ctx)
7240 {
7241 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
7242 cpu_gpr[rS(ctx->opcode)]);
7243 /* Note: Rc update flag set leads to undefined state of Rc0 */
7244 }
7245
7246 /* dccci */
7247 static void gen_dccci(DisasContext *ctx)
7248 {
7249 CHK_SV;
7250 /* interpreted as no-op */
7251 }
7252
7253 /* dcread */
7254 static void gen_dcread(DisasContext *ctx)
7255 {
7256 #if defined(CONFIG_USER_ONLY)
7257 GEN_PRIV;
7258 #else
7259 TCGv EA, val;
7260
7261 CHK_SV;
7262 gen_set_access_type(ctx, ACCESS_CACHE);
7263 EA = tcg_temp_new();
7264 gen_addr_reg_index(ctx, EA);
7265 val = tcg_temp_new();
7266 gen_qemu_ld32u(ctx, val, EA);
7267 tcg_temp_free(val);
7268 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
7269 tcg_temp_free(EA);
7270 #endif /* defined(CONFIG_USER_ONLY) */
7271 }
7272
7273 /* icbt */
7274 static void gen_icbt_40x(DisasContext *ctx)
7275 {
7276 /*
7277 * interpreted as no-op
7278 * XXX: specification say this is treated as a load by the MMU but
7279 * does not generate any exception
7280 */
7281 }
7282
7283 /* iccci */
7284 static void gen_iccci(DisasContext *ctx)
7285 {
7286 CHK_SV;
7287 /* interpreted as no-op */
7288 }
7289
7290 /* icread */
7291 static void gen_icread(DisasContext *ctx)
7292 {
7293 CHK_SV;
7294 /* interpreted as no-op */
7295 }
7296
7297 /* rfci (supervisor only) */
7298 static void gen_rfci_40x(DisasContext *ctx)
7299 {
7300 #if defined(CONFIG_USER_ONLY)
7301 GEN_PRIV;
7302 #else
7303 CHK_SV;
7304 /* Restore CPU state */
7305 gen_helper_40x_rfci(cpu_env);
7306 gen_sync_exception(ctx);
7307 #endif /* defined(CONFIG_USER_ONLY) */
7308 }
7309
7310 static void gen_rfci(DisasContext *ctx)
7311 {
7312 #if defined(CONFIG_USER_ONLY)
7313 GEN_PRIV;
7314 #else
7315 CHK_SV;
7316 /* Restore CPU state */
7317 gen_helper_rfci(cpu_env);
7318 gen_sync_exception(ctx);
7319 #endif /* defined(CONFIG_USER_ONLY) */
7320 }
7321
7322 /* BookE specific */
7323
7324 /* XXX: not implemented on 440 ? */
7325 static void gen_rfdi(DisasContext *ctx)
7326 {
7327 #if defined(CONFIG_USER_ONLY)
7328 GEN_PRIV;
7329 #else
7330 CHK_SV;
7331 /* Restore CPU state */
7332 gen_helper_rfdi(cpu_env);
7333 gen_sync_exception(ctx);
7334 #endif /* defined(CONFIG_USER_ONLY) */
7335 }
7336
7337 /* XXX: not implemented on 440 ? */
7338 static void gen_rfmci(DisasContext *ctx)
7339 {
7340 #if defined(CONFIG_USER_ONLY)
7341 GEN_PRIV;
7342 #else
7343 CHK_SV;
7344 /* Restore CPU state */
7345 gen_helper_rfmci(cpu_env);
7346 gen_sync_exception(ctx);
7347 #endif /* defined(CONFIG_USER_ONLY) */
7348 }
7349
7350 /* TLB management - PowerPC 405 implementation */
7351
7352 /* tlbre */
7353 static void gen_tlbre_40x(DisasContext *ctx)
7354 {
7355 #if defined(CONFIG_USER_ONLY)
7356 GEN_PRIV;
7357 #else
7358 CHK_SV;
7359 switch (rB(ctx->opcode)) {
7360 case 0:
7361 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
7362 cpu_gpr[rA(ctx->opcode)]);
7363 break;
7364 case 1:
7365 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
7366 cpu_gpr[rA(ctx->opcode)]);
7367 break;
7368 default:
7369 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7370 break;
7371 }
7372 #endif /* defined(CONFIG_USER_ONLY) */
7373 }
7374
7375 /* tlbsx - tlbsx. */
7376 static void gen_tlbsx_40x(DisasContext *ctx)
7377 {
7378 #if defined(CONFIG_USER_ONLY)
7379 GEN_PRIV;
7380 #else
7381 TCGv t0;
7382
7383 CHK_SV;
7384 t0 = tcg_temp_new();
7385 gen_addr_reg_index(ctx, t0);
7386 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
7387 tcg_temp_free(t0);
7388 if (Rc(ctx->opcode)) {
7389 TCGLabel *l1 = gen_new_label();
7390 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
7391 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
7392 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
7393 gen_set_label(l1);
7394 }
7395 #endif /* defined(CONFIG_USER_ONLY) */
7396 }
7397
7398 /* tlbwe */
7399 static void gen_tlbwe_40x(DisasContext *ctx)
7400 {
7401 #if defined(CONFIG_USER_ONLY)
7402 GEN_PRIV;
7403 #else
7404 CHK_SV;
7405
7406 switch (rB(ctx->opcode)) {
7407 case 0:
7408 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
7409 cpu_gpr[rS(ctx->opcode)]);
7410 break;
7411 case 1:
7412 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
7413 cpu_gpr[rS(ctx->opcode)]);
7414 break;
7415 default:
7416 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7417 break;
7418 }
7419 #endif /* defined(CONFIG_USER_ONLY) */
7420 }
7421
7422 /* TLB management - PowerPC 440 implementation */
7423
7424 /* tlbre */
7425 static void gen_tlbre_440(DisasContext *ctx)
7426 {
7427 #if defined(CONFIG_USER_ONLY)
7428 GEN_PRIV;
7429 #else
7430 CHK_SV;
7431
7432 switch (rB(ctx->opcode)) {
7433 case 0:
7434 case 1:
7435 case 2:
7436 {
7437 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
7438 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
7439 t0, cpu_gpr[rA(ctx->opcode)]);
7440 tcg_temp_free_i32(t0);
7441 }
7442 break;
7443 default:
7444 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7445 break;
7446 }
7447 #endif /* defined(CONFIG_USER_ONLY) */
7448 }
7449
7450 /* tlbsx - tlbsx. */
7451 static void gen_tlbsx_440(DisasContext *ctx)
7452 {
7453 #if defined(CONFIG_USER_ONLY)
7454 GEN_PRIV;
7455 #else
7456 TCGv t0;
7457
7458 CHK_SV;
7459 t0 = tcg_temp_new();
7460 gen_addr_reg_index(ctx, t0);
7461 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
7462 tcg_temp_free(t0);
7463 if (Rc(ctx->opcode)) {
7464 TCGLabel *l1 = gen_new_label();
7465 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
7466 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
7467 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
7468 gen_set_label(l1);
7469 }
7470 #endif /* defined(CONFIG_USER_ONLY) */
7471 }
7472
7473 /* tlbwe */
7474 static void gen_tlbwe_440(DisasContext *ctx)
7475 {
7476 #if defined(CONFIG_USER_ONLY)
7477 GEN_PRIV;
7478 #else
7479 CHK_SV;
7480 switch (rB(ctx->opcode)) {
7481 case 0:
7482 case 1:
7483 case 2:
7484 {
7485 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
7486 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
7487 cpu_gpr[rS(ctx->opcode)]);
7488 tcg_temp_free_i32(t0);
7489 }
7490 break;
7491 default:
7492 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7493 break;
7494 }
7495 #endif /* defined(CONFIG_USER_ONLY) */
7496 }
7497
7498 /* TLB management - PowerPC BookE 2.06 implementation */
7499
7500 /* tlbre */
7501 static void gen_tlbre_booke206(DisasContext *ctx)
7502 {
7503 #if defined(CONFIG_USER_ONLY)
7504 GEN_PRIV;
7505 #else
7506 CHK_SV;
7507 gen_helper_booke206_tlbre(cpu_env);
7508 #endif /* defined(CONFIG_USER_ONLY) */
7509 }
7510
7511 /* tlbsx - tlbsx. */
7512 static void gen_tlbsx_booke206(DisasContext *ctx)
7513 {
7514 #if defined(CONFIG_USER_ONLY)
7515 GEN_PRIV;
7516 #else
7517 TCGv t0;
7518
7519 CHK_SV;
7520 if (rA(ctx->opcode)) {
7521 t0 = tcg_temp_new();
7522 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
7523 } else {
7524 t0 = tcg_const_tl(0);
7525 }
7526
7527 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
7528 gen_helper_booke206_tlbsx(cpu_env, t0);
7529 tcg_temp_free(t0);
7530 #endif /* defined(CONFIG_USER_ONLY) */
7531 }
7532
7533 /* tlbwe */
7534 static void gen_tlbwe_booke206(DisasContext *ctx)
7535 {
7536 #if defined(CONFIG_USER_ONLY)
7537 GEN_PRIV;
7538 #else
7539 CHK_SV;
7540 gen_helper_booke206_tlbwe(cpu_env);
7541 #endif /* defined(CONFIG_USER_ONLY) */
7542 }
7543
7544 static void gen_tlbivax_booke206(DisasContext *ctx)
7545 {
7546 #if defined(CONFIG_USER_ONLY)
7547 GEN_PRIV;
7548 #else
7549 TCGv t0;
7550
7551 CHK_SV;
7552 t0 = tcg_temp_new();
7553 gen_addr_reg_index(ctx, t0);
7554 gen_helper_booke206_tlbivax(cpu_env, t0);
7555 tcg_temp_free(t0);
7556 #endif /* defined(CONFIG_USER_ONLY) */
7557 }
7558
7559 static void gen_tlbilx_booke206(DisasContext *ctx)
7560 {
7561 #if defined(CONFIG_USER_ONLY)
7562 GEN_PRIV;
7563 #else
7564 TCGv t0;
7565
7566 CHK_SV;
7567 t0 = tcg_temp_new();
7568 gen_addr_reg_index(ctx, t0);
7569
7570 switch ((ctx->opcode >> 21) & 0x3) {
7571 case 0:
7572 gen_helper_booke206_tlbilx0(cpu_env, t0);
7573 break;
7574 case 1:
7575 gen_helper_booke206_tlbilx1(cpu_env, t0);
7576 break;
7577 case 3:
7578 gen_helper_booke206_tlbilx3(cpu_env, t0);
7579 break;
7580 default:
7581 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7582 break;
7583 }
7584
7585 tcg_temp_free(t0);
7586 #endif /* defined(CONFIG_USER_ONLY) */
7587 }
7588
7589
7590 /* wrtee */
7591 static void gen_wrtee(DisasContext *ctx)
7592 {
7593 #if defined(CONFIG_USER_ONLY)
7594 GEN_PRIV;
7595 #else
7596 TCGv t0;
7597
7598 CHK_SV;
7599 t0 = tcg_temp_new();
7600 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
7601 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
7602 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
7603 tcg_temp_free(t0);
7604 /*
7605 * Stop translation to have a chance to raise an exception if we
7606 * just set msr_ee to 1
7607 */
7608 gen_stop_exception(ctx);
7609 #endif /* defined(CONFIG_USER_ONLY) */
7610 }
7611
7612 /* wrteei */
7613 static void gen_wrteei(DisasContext *ctx)
7614 {
7615 #if defined(CONFIG_USER_ONLY)
7616 GEN_PRIV;
7617 #else
7618 CHK_SV;
7619 if (ctx->opcode & 0x00008000) {
7620 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
7621 /* Stop translation to have a chance to raise an exception */
7622 gen_stop_exception(ctx);
7623 } else {
7624 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
7625 }
7626 #endif /* defined(CONFIG_USER_ONLY) */
7627 }
7628
7629 /* PowerPC 440 specific instructions */
7630
7631 /* dlmzb */
7632 static void gen_dlmzb(DisasContext *ctx)
7633 {
7634 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
7635 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
7636 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
7637 tcg_temp_free_i32(t0);
7638 }
7639
7640 /* mbar replaces eieio on 440 */
7641 static void gen_mbar(DisasContext *ctx)
7642 {
7643 /* interpreted as no-op */
7644 }
7645
7646 /* msync replaces sync on 440 */
7647 static void gen_msync_4xx(DisasContext *ctx)
7648 {
7649 /* Only e500 seems to treat reserved bits as invalid */
7650 if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
7651 (ctx->opcode & 0x03FFF801)) {
7652 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7653 }
7654 /* otherwise interpreted as no-op */
7655 }
7656
7657 /* icbt */
7658 static void gen_icbt_440(DisasContext *ctx)
7659 {
7660 /*
7661 * interpreted as no-op
7662 * XXX: specification say this is treated as a load by the MMU but
7663 * does not generate any exception
7664 */
7665 }
7666
7667 /* Embedded.Processor Control */
7668
7669 static void gen_msgclr(DisasContext *ctx)
7670 {
7671 #if defined(CONFIG_USER_ONLY)
7672 GEN_PRIV;
7673 #else
7674 CHK_HV;
7675 if (is_book3s_arch2x(ctx)) {
7676 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7677 } else {
7678 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7679 }
7680 #endif /* defined(CONFIG_USER_ONLY) */
7681 }
7682
7683 static void gen_msgsnd(DisasContext *ctx)
7684 {
7685 #if defined(CONFIG_USER_ONLY)
7686 GEN_PRIV;
7687 #else
7688 CHK_HV;
7689 if (is_book3s_arch2x(ctx)) {
7690 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7691 } else {
7692 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7693 }
7694 #endif /* defined(CONFIG_USER_ONLY) */
7695 }
7696
7697 #if defined(TARGET_PPC64)
7698 static void gen_msgclrp(DisasContext *ctx)
7699 {
7700 #if defined(CONFIG_USER_ONLY)
7701 GEN_PRIV;
7702 #else
7703 CHK_SV;
7704 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7705 #endif /* defined(CONFIG_USER_ONLY) */
7706 }
7707
7708 static void gen_msgsndp(DisasContext *ctx)
7709 {
7710 #if defined(CONFIG_USER_ONLY)
7711 GEN_PRIV;
7712 #else
7713 CHK_SV;
7714 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7715 #endif /* defined(CONFIG_USER_ONLY) */
7716 }
7717 #endif
7718
7719 static void gen_msgsync(DisasContext *ctx)
7720 {
7721 #if defined(CONFIG_USER_ONLY)
7722 GEN_PRIV;
7723 #else
7724 CHK_HV;
7725 #endif /* defined(CONFIG_USER_ONLY) */
7726 /* interpreted as no-op */
7727 }
7728
7729 #if defined(TARGET_PPC64)
7730 static void gen_maddld(DisasContext *ctx)
7731 {
7732 TCGv_i64 t1 = tcg_temp_new_i64();
7733
7734 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7735 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
7736 tcg_temp_free_i64(t1);
7737 }
7738
7739 /* maddhd maddhdu */
7740 static void gen_maddhd_maddhdu(DisasContext *ctx)
7741 {
7742 TCGv_i64 lo = tcg_temp_new_i64();
7743 TCGv_i64 hi = tcg_temp_new_i64();
7744 TCGv_i64 t1 = tcg_temp_new_i64();
7745
7746 if (Rc(ctx->opcode)) {
7747 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7748 cpu_gpr[rB(ctx->opcode)]);
7749 tcg_gen_movi_i64(t1, 0);
7750 } else {
7751 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7752 cpu_gpr[rB(ctx->opcode)]);
7753 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
7754 }
7755 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
7756 cpu_gpr[rC(ctx->opcode)], t1);
7757 tcg_temp_free_i64(lo);
7758 tcg_temp_free_i64(hi);
7759 tcg_temp_free_i64(t1);
7760 }
7761 #endif /* defined(TARGET_PPC64) */
7762
7763 static void gen_tbegin(DisasContext *ctx)
7764 {
7765 if (unlikely(!ctx->tm_enabled)) {
7766 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7767 return;
7768 }
7769 gen_helper_tbegin(cpu_env);
7770 }
7771
7772 #define GEN_TM_NOOP(name) \
7773 static inline void gen_##name(DisasContext *ctx) \
7774 { \
7775 if (unlikely(!ctx->tm_enabled)) { \
7776 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7777 return; \
7778 } \
7779 /* \
7780 * Because tbegin always fails in QEMU, these user \
7781 * space instructions all have a simple implementation: \
7782 * \
7783 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7784 * = 0b0 || 0b00 || 0b0 \
7785 */ \
7786 tcg_gen_movi_i32(cpu_crf[0], 0); \
7787 }
7788
7789 GEN_TM_NOOP(tend);
7790 GEN_TM_NOOP(tabort);
7791 GEN_TM_NOOP(tabortwc);
7792 GEN_TM_NOOP(tabortwci);
7793 GEN_TM_NOOP(tabortdc);
7794 GEN_TM_NOOP(tabortdci);
7795 GEN_TM_NOOP(tsr);
7796
7797 static inline void gen_cp_abort(DisasContext *ctx)
7798 {
7799 /* Do Nothing */
7800 }
7801
7802 #define GEN_CP_PASTE_NOOP(name) \
7803 static inline void gen_##name(DisasContext *ctx) \
7804 { \
7805 /* \
7806 * Generate invalid exception until we have an \
7807 * implementation of the copy paste facility \
7808 */ \
7809 gen_invalid(ctx); \
7810 }
7811
7812 GEN_CP_PASTE_NOOP(copy)
7813 GEN_CP_PASTE_NOOP(paste)
7814
7815 static void gen_tcheck(DisasContext *ctx)
7816 {
7817 if (unlikely(!ctx->tm_enabled)) {
7818 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7819 return;
7820 }
7821 /*
7822 * Because tbegin always fails, the tcheck implementation is
7823 * simple:
7824 *
7825 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
7826 * = 0b1 || 0b00 || 0b0
7827 */
7828 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
7829 }
7830
7831 #if defined(CONFIG_USER_ONLY)
7832 #define GEN_TM_PRIV_NOOP(name) \
7833 static inline void gen_##name(DisasContext *ctx) \
7834 { \
7835 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
7836 }
7837
7838 #else
7839
7840 #define GEN_TM_PRIV_NOOP(name) \
7841 static inline void gen_##name(DisasContext *ctx) \
7842 { \
7843 CHK_SV; \
7844 if (unlikely(!ctx->tm_enabled)) { \
7845 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7846 return; \
7847 } \
7848 /* \
7849 * Because tbegin always fails, the implementation is \
7850 * simple: \
7851 * \
7852 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7853 * = 0b0 || 0b00 | 0b0 \
7854 */ \
7855 tcg_gen_movi_i32(cpu_crf[0], 0); \
7856 }
7857
7858 #endif
7859
7860 GEN_TM_PRIV_NOOP(treclaim);
7861 GEN_TM_PRIV_NOOP(trechkpt);
7862
7863 static inline void get_fpr(TCGv_i64 dst, int regno)
7864 {
7865 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
7866 }
7867
7868 static inline void set_fpr(int regno, TCGv_i64 src)
7869 {
7870 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
7871 }
7872
7873 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
7874 {
7875 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
7876 }
7877
7878 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
7879 {
7880 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
7881 }
7882
7883 #include "translate/fp-impl.c.inc"
7884
7885 #include "translate/vmx-impl.c.inc"
7886
7887 #include "translate/vsx-impl.c.inc"
7888
7889 #include "translate/dfp-impl.c.inc"
7890
7891 #include "translate/spe-impl.c.inc"
7892
7893 /* Handles lfdp, lxsd, lxssp */
7894 static void gen_dform39(DisasContext *ctx)
7895 {
7896 switch (ctx->opcode & 0x3) {
7897 case 0: /* lfdp */
7898 if (ctx->insns_flags2 & PPC2_ISA205) {
7899 return gen_lfdp(ctx);
7900 }
7901 break;
7902 case 2: /* lxsd */
7903 if (ctx->insns_flags2 & PPC2_ISA300) {
7904 return gen_lxsd(ctx);
7905 }
7906 break;
7907 case 3: /* lxssp */
7908 if (ctx->insns_flags2 & PPC2_ISA300) {
7909 return gen_lxssp(ctx);
7910 }
7911 break;
7912 }
7913 return gen_invalid(ctx);
7914 }
7915
7916 /* handles stfdp, lxv, stxsd, stxssp lxvx */
7917 static void gen_dform3D(DisasContext *ctx)
7918 {
7919 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
7920 switch (ctx->opcode & 0x7) {
7921 case 1: /* lxv */
7922 if (ctx->insns_flags2 & PPC2_ISA300) {
7923 return gen_lxv(ctx);
7924 }
7925 break;
7926 case 5: /* stxv */
7927 if (ctx->insns_flags2 & PPC2_ISA300) {
7928 return gen_stxv(ctx);
7929 }
7930 break;
7931 }
7932 } else { /* DS-FORM */
7933 switch (ctx->opcode & 0x3) {
7934 case 0: /* stfdp */
7935 if (ctx->insns_flags2 & PPC2_ISA205) {
7936 return gen_stfdp(ctx);
7937 }
7938 break;
7939 case 2: /* stxsd */
7940 if (ctx->insns_flags2 & PPC2_ISA300) {
7941 return gen_stxsd(ctx);
7942 }
7943 break;
7944 case 3: /* stxssp */
7945 if (ctx->insns_flags2 & PPC2_ISA300) {
7946 return gen_stxssp(ctx);
7947 }
7948 break;
7949 }
7950 }
7951 return gen_invalid(ctx);
7952 }
7953
7954 #if defined(TARGET_PPC64)
7955 /* brd */
7956 static void gen_brd(DisasContext *ctx)
7957 {
7958 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7959 }
7960
7961 /* brw */
7962 static void gen_brw(DisasContext *ctx)
7963 {
7964 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7965 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
7966
7967 }
7968
7969 /* brh */
7970 static void gen_brh(DisasContext *ctx)
7971 {
7972 TCGv_i64 t0 = tcg_temp_new_i64();
7973 TCGv_i64 t1 = tcg_temp_new_i64();
7974 TCGv_i64 t2 = tcg_temp_new_i64();
7975
7976 tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
7977 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
7978 tcg_gen_and_i64(t2, t1, t0);
7979 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
7980 tcg_gen_shli_i64(t1, t1, 8);
7981 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
7982
7983 tcg_temp_free_i64(t0);
7984 tcg_temp_free_i64(t1);
7985 tcg_temp_free_i64(t2);
7986 }
7987 #endif
7988
7989 static opcode_t opcodes[] = {
7990 #if defined(TARGET_PPC64)
7991 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
7992 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
7993 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
7994 #endif
7995 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
7996 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
7997 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7998 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
7999 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8000 #if defined(TARGET_PPC64)
8001 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
8002 #endif
8003 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8004 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
8005 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8006 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8007 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8008 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8009 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8010 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
8011 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8012 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8013 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8014 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8015 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8016 #if defined(TARGET_PPC64)
8017 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8018 #endif
8019 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8020 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8021 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8022 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8023 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8024 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8025 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
8026 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
8027 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8028 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
8029 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8030 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8031 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8032 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8033 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8034 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8035 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
8036 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8037 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
8038 #if defined(TARGET_PPC64)
8039 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8040 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8041 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
8042 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
8043 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
8044 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
8045 #endif
8046 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8047 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8048 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8049 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8050 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8051 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8052 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8053 #if defined(TARGET_PPC64)
8054 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8055 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8056 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8057 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8058 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8059 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
8060 PPC_NONE, PPC2_ISA300),
8061 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
8062 PPC_NONE, PPC2_ISA300),
8063 #endif
8064 #if defined(TARGET_PPC64)
8065 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8066 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8067 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8068 #endif
8069 /* handles lfdp, lxsd, lxssp */
8070 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
8071 /* handles stfdp, lxv, stxsd, stxssp, stxv */
8072 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
8073 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8074 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8075 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8076 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8077 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8078 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8079 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
8080 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8081 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8082 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8083 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8084 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
8085 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
8086 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8087 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8088 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8089 #if defined(TARGET_PPC64)
8090 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
8091 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
8092 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8093 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
8094 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8095 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
8096 #endif
8097 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8098 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8099 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
8100 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8101 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8102 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8103 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8104 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
8105 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8106 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8107 #if defined(TARGET_PPC64)
8108 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8109 #if !defined(CONFIG_USER_ONLY)
8110 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
8111 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
8112 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
8113 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
8114 #endif
8115 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8116 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8117 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8118 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8119 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8120 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8121 #endif
8122 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
8123 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
8124 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
8125 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8126 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8127 #if defined(TARGET_PPC64)
8128 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8129 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8130 #endif
8131 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8132 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8133 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8134 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8135 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8136 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8137 #if defined(TARGET_PPC64)
8138 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8139 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
8140 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
8141 #endif
8142 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
8143 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
8144 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8145 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
8146 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8147 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8148 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
8149 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
8150 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
8151 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
8152 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
8153 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8154 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8155 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
8156 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8157 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
8158 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8159 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8160 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
8161 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8162 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8163 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8164 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8165 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8166 #if defined(TARGET_PPC64)
8167 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8168 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8169 PPC_SEGMENT_64B),
8170 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8171 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8172 PPC_SEGMENT_64B),
8173 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8174 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8175 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8176 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
8177 #endif
8178 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8179 /*
8180 * XXX Those instructions will need to be handled differently for
8181 * different ISA versions
8182 */
8183 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
8184 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
8185 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
8186 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
8187 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8188 #if defined(TARGET_PPC64)
8189 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
8190 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8191 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
8192 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8193 #endif
8194 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8195 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8196 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8197 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8198 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8199 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8200 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8201 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8202 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8203 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8204 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8205 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8206 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8207 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8208 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8209 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8210 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8211 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8212 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8213 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8214 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8215 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8216 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8217 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8218 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8219 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8220 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8221 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8222 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8223 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8224 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8225 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8226 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8227 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8228 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8229 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8230 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8231 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8232 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8233 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8234 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8235 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8236 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8237 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8238 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8239 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8240 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8241 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8242 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8243 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8244 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8245 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8246 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8247 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8248 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8249 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8250 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8251 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8252 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8253 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8254 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8255 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8256 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8257 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8258 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8259 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8260 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8261 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8262 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8263 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8264 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8265 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8266 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8267 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8268 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8269 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8270 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8271 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8272 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8273 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8274 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8275 PPC_NONE, PPC2_BOOKE206),
8276 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8277 PPC_NONE, PPC2_BOOKE206),
8278 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8279 PPC_NONE, PPC2_BOOKE206),
8280 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8281 PPC_NONE, PPC2_BOOKE206),
8282 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8283 PPC_NONE, PPC2_BOOKE206),
8284 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8285 PPC_NONE, PPC2_PRCNTL),
8286 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8287 PPC_NONE, PPC2_PRCNTL),
8288 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
8289 PPC_NONE, PPC2_PRCNTL),
8290 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8291 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8292 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8293 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8294 PPC_BOOKE, PPC2_BOOKE206),
8295 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
8296 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8297 PPC_BOOKE, PPC2_BOOKE206),
8298 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
8299 PPC_440_SPEC),
8300 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8301 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8302 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8303 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8304 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8305 #if defined(TARGET_PPC64)
8306 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
8307 PPC2_ISA300),
8308 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
8309 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
8310 PPC_NONE, PPC2_ISA207S),
8311 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
8312 PPC_NONE, PPC2_ISA207S),
8313 #endif
8314
8315 #undef GEN_INT_ARITH_ADD
8316 #undef GEN_INT_ARITH_ADD_CONST
8317 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8318 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8319 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8320 add_ca, compute_ca, compute_ov) \
8321 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8322 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8323 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8324 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8325 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8326 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8327 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8328 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8329 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8330 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
8331 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8332 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8333
8334 #undef GEN_INT_ARITH_DIVW
8335 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8336 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8337 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8338 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8339 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8340 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8341 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8342 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8343 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8344 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8345 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
8346 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
8347
8348 #if defined(TARGET_PPC64)
8349 #undef GEN_INT_ARITH_DIVD
8350 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8351 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8352 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8353 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8354 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8355 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8356
8357 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8358 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8359 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8360 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8361 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
8362 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
8363
8364 #undef GEN_INT_ARITH_MUL_HELPER
8365 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8366 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8367 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8368 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8369 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8370 #endif
8371
8372 #undef GEN_INT_ARITH_SUBF
8373 #undef GEN_INT_ARITH_SUBF_CONST
8374 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8375 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8376 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8377 add_ca, compute_ca, compute_ov) \
8378 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8379 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8380 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8381 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8382 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8383 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8384 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8385 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8386 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8387 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8388 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8389
8390 #undef GEN_LOGICAL1
8391 #undef GEN_LOGICAL2
8392 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8393 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8394 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8395 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8396 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8397 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8398 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8399 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8400 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8401 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8402 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8403 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8404 #if defined(TARGET_PPC64)
8405 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8406 #endif
8407
8408 #if defined(TARGET_PPC64)
8409 #undef GEN_PPC64_R2
8410 #undef GEN_PPC64_R4
8411 #define GEN_PPC64_R2(name, opc1, opc2) \
8412 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8413 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8414 PPC_64B)
8415 #define GEN_PPC64_R4(name, opc1, opc2) \
8416 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8417 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8418 PPC_64B), \
8419 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8420 PPC_64B), \
8421 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8422 PPC_64B)
8423 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8424 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8425 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8426 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8427 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8428 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8429 #endif
8430
8431 #undef GEN_LD
8432 #undef GEN_LDU
8433 #undef GEN_LDUX
8434 #undef GEN_LDX_E
8435 #undef GEN_LDS
8436 #define GEN_LD(name, ldop, opc, type) \
8437 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8438 #define GEN_LDU(name, ldop, opc, type) \
8439 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8440 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8441 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8442 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
8443 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8444 #define GEN_LDS(name, ldop, op, type) \
8445 GEN_LD(name, ldop, op | 0x20, type) \
8446 GEN_LDU(name, ldop, op | 0x21, type) \
8447 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8448 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8449
8450 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8451 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8452 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8453 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8454 #if defined(TARGET_PPC64)
8455 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8456 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8457 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
8458 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
8459 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
8460
8461 /* HV/P7 and later only */
8462 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
8463 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
8464 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
8465 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
8466 #endif
8467 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8468 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8469
8470 /* External PID based load */
8471 #undef GEN_LDEPX
8472 #define GEN_LDEPX(name, ldop, opc2, opc3) \
8473 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8474 0x00000001, PPC_NONE, PPC2_BOOKE206),
8475
8476 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
8477 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
8478 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
8479 #if defined(TARGET_PPC64)
8480 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
8481 #endif
8482
8483 #undef GEN_ST
8484 #undef GEN_STU
8485 #undef GEN_STUX
8486 #undef GEN_STX_E
8487 #undef GEN_STS
8488 #define GEN_ST(name, stop, opc, type) \
8489 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8490 #define GEN_STU(name, stop, opc, type) \
8491 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8492 #define GEN_STUX(name, stop, opc2, opc3, type) \
8493 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8494 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
8495 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
8496 #define GEN_STS(name, stop, op, type) \
8497 GEN_ST(name, stop, op | 0x20, type) \
8498 GEN_STU(name, stop, op | 0x21, type) \
8499 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8500 GEN_STX(name, stop, 0x17, op | 0x00, type)
8501
8502 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8503 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8504 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8505 #if defined(TARGET_PPC64)
8506 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
8507 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
8508 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
8509 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
8510 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
8511 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
8512 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
8513 #endif
8514 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8515 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8516
8517 #undef GEN_STEPX
8518 #define GEN_STEPX(name, ldop, opc2, opc3) \
8519 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8520 0x00000001, PPC_NONE, PPC2_BOOKE206),
8521
8522 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
8523 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
8524 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
8525 #if defined(TARGET_PPC64)
8526 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
8527 #endif
8528
8529 #undef GEN_CRLOGIC
8530 #define GEN_CRLOGIC(name, tcg_op, opc) \
8531 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8532 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8533 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8534 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8535 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8536 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8537 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8538 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8539 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8540
8541 #undef GEN_MAC_HANDLER
8542 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8543 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8544 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8545 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8546 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8547 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8548 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8549 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8550 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8551 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8552 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8553 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8554 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8555 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8556 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8557 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8558 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8559 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8560 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8561 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8562 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8563 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8564 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8565 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8566 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8567 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8568 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8569 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8570 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8571 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8572 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8573 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8574 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8575 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8576 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8577 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8578 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8579 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8580 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8581 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8582 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8583 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8584 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8585 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8586
8587 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
8588 PPC_NONE, PPC2_TM),
8589 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
8590 PPC_NONE, PPC2_TM),
8591 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
8592 PPC_NONE, PPC2_TM),
8593 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
8594 PPC_NONE, PPC2_TM),
8595 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
8596 PPC_NONE, PPC2_TM),
8597 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
8598 PPC_NONE, PPC2_TM),
8599 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
8600 PPC_NONE, PPC2_TM),
8601 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
8602 PPC_NONE, PPC2_TM),
8603 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
8604 PPC_NONE, PPC2_TM),
8605 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
8606 PPC_NONE, PPC2_TM),
8607 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
8608 PPC_NONE, PPC2_TM),
8609
8610 #include "translate/fp-ops.c.inc"
8611
8612 #include "translate/vmx-ops.c.inc"
8613
8614 #include "translate/vsx-ops.c.inc"
8615
8616 #include "translate/dfp-ops.c.inc"
8617
8618 #include "translate/spe-ops.c.inc"
8619 };
8620
8621 /*****************************************************************************/
8622 /* Opcode types */
8623 enum {
8624 PPC_DIRECT = 0, /* Opcode routine */
8625 PPC_INDIRECT = 1, /* Indirect opcode table */
8626 };
8627
8628 #define PPC_OPCODE_MASK 0x3
8629
8630 static inline int is_indirect_opcode(void *handler)
8631 {
8632 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8633 }
8634
8635 static inline opc_handler_t **ind_table(void *handler)
8636 {
8637 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8638 }
8639
8640 /* Instruction table creation */
8641 /* Opcodes tables creation */
8642 static void fill_new_table(opc_handler_t **table, int len)
8643 {
8644 int i;
8645
8646 for (i = 0; i < len; i++) {
8647 table[i] = &invalid_handler;
8648 }
8649 }
8650
8651 static int create_new_table(opc_handler_t **table, unsigned char idx)
8652 {
8653 opc_handler_t **tmp;
8654
8655 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8656 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8657 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8658
8659 return 0;
8660 }
8661
8662 static int insert_in_table(opc_handler_t **table, unsigned char idx,
8663 opc_handler_t *handler)
8664 {
8665 if (table[idx] != &invalid_handler) {
8666 return -1;
8667 }
8668 table[idx] = handler;
8669
8670 return 0;
8671 }
8672
8673 static int register_direct_insn(opc_handler_t **ppc_opcodes,
8674 unsigned char idx, opc_handler_t *handler)
8675 {
8676 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8677 printf("*** ERROR: opcode %02x already assigned in main "
8678 "opcode table\n", idx);
8679 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8680 printf(" Registered handler '%s' - new handler '%s'\n",
8681 ppc_opcodes[idx]->oname, handler->oname);
8682 #endif
8683 return -1;
8684 }
8685
8686 return 0;
8687 }
8688
8689 static int register_ind_in_table(opc_handler_t **table,
8690 unsigned char idx1, unsigned char idx2,
8691 opc_handler_t *handler)
8692 {
8693 if (table[idx1] == &invalid_handler) {
8694 if (create_new_table(table, idx1) < 0) {
8695 printf("*** ERROR: unable to create indirect table "
8696 "idx=%02x\n", idx1);
8697 return -1;
8698 }
8699 } else {
8700 if (!is_indirect_opcode(table[idx1])) {
8701 printf("*** ERROR: idx %02x already assigned to a direct "
8702 "opcode\n", idx1);
8703 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8704 printf(" Registered handler '%s' - new handler '%s'\n",
8705 ind_table(table[idx1])[idx2]->oname, handler->oname);
8706 #endif
8707 return -1;
8708 }
8709 }
8710 if (handler != NULL &&
8711 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8712 printf("*** ERROR: opcode %02x already assigned in "
8713 "opcode table %02x\n", idx2, idx1);
8714 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8715 printf(" Registered handler '%s' - new handler '%s'\n",
8716 ind_table(table[idx1])[idx2]->oname, handler->oname);
8717 #endif
8718 return -1;
8719 }
8720
8721 return 0;
8722 }
8723
8724 static int register_ind_insn(opc_handler_t **ppc_opcodes,
8725 unsigned char idx1, unsigned char idx2,
8726 opc_handler_t *handler)
8727 {
8728 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8729 }
8730
8731 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
8732 unsigned char idx1, unsigned char idx2,
8733 unsigned char idx3, opc_handler_t *handler)
8734 {
8735 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8736 printf("*** ERROR: unable to join indirect table idx "
8737 "[%02x-%02x]\n", idx1, idx2);
8738 return -1;
8739 }
8740 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8741 handler) < 0) {
8742 printf("*** ERROR: unable to insert opcode "
8743 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8744 return -1;
8745 }
8746
8747 return 0;
8748 }
8749
8750 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
8751 unsigned char idx1, unsigned char idx2,
8752 unsigned char idx3, unsigned char idx4,
8753 opc_handler_t *handler)
8754 {
8755 opc_handler_t **table;
8756
8757 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8758 printf("*** ERROR: unable to join indirect table idx "
8759 "[%02x-%02x]\n", idx1, idx2);
8760 return -1;
8761 }
8762 table = ind_table(ppc_opcodes[idx1]);
8763 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
8764 printf("*** ERROR: unable to join 2nd-level indirect table idx "
8765 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8766 return -1;
8767 }
8768 table = ind_table(table[idx2]);
8769 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
8770 printf("*** ERROR: unable to insert opcode "
8771 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
8772 return -1;
8773 }
8774 return 0;
8775 }
8776 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
8777 {
8778 if (insn->opc2 != 0xFF) {
8779 if (insn->opc3 != 0xFF) {
8780 if (insn->opc4 != 0xFF) {
8781 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8782 insn->opc3, insn->opc4,
8783 &insn->handler) < 0) {
8784 return -1;
8785 }
8786 } else {
8787 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8788 insn->opc3, &insn->handler) < 0) {
8789 return -1;
8790 }
8791 }
8792 } else {
8793 if (register_ind_insn(ppc_opcodes, insn->opc1,
8794 insn->opc2, &insn->handler) < 0) {
8795 return -1;
8796 }
8797 }
8798 } else {
8799 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
8800 return -1;
8801 }
8802 }
8803
8804 return 0;
8805 }
8806
8807 static int test_opcode_table(opc_handler_t **table, int len)
8808 {
8809 int i, count, tmp;
8810
8811 for (i = 0, count = 0; i < len; i++) {
8812 /* Consistency fixup */
8813 if (table[i] == NULL) {
8814 table[i] = &invalid_handler;
8815 }
8816 if (table[i] != &invalid_handler) {
8817 if (is_indirect_opcode(table[i])) {
8818 tmp = test_opcode_table(ind_table(table[i]),
8819 PPC_CPU_INDIRECT_OPCODES_LEN);
8820 if (tmp == 0) {
8821 free(table[i]);
8822 table[i] = &invalid_handler;
8823 } else {
8824 count++;
8825 }
8826 } else {
8827 count++;
8828 }
8829 }
8830 }
8831
8832 return count;
8833 }
8834
8835 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
8836 {
8837 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
8838 printf("*** WARNING: no opcode defined !\n");
8839 }
8840 }
8841
8842 /*****************************************************************************/
8843 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8844 {
8845 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8846 opcode_t *opc;
8847
8848 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
8849 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8850 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8851 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8852 if (register_insn(cpu->opcodes, opc) < 0) {
8853 error_setg(errp, "ERROR initializing PowerPC instruction "
8854 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8855 opc->opc3);
8856 return;
8857 }
8858 }
8859 }
8860 fix_opcode_tables(cpu->opcodes);
8861 fflush(stdout);
8862 fflush(stderr);
8863 }
8864
8865 void destroy_ppc_opcodes(PowerPCCPU *cpu)
8866 {
8867 opc_handler_t **table, **table_2;
8868 int i, j, k;
8869
8870 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8871 if (cpu->opcodes[i] == &invalid_handler) {
8872 continue;
8873 }
8874 if (is_indirect_opcode(cpu->opcodes[i])) {
8875 table = ind_table(cpu->opcodes[i]);
8876 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
8877 if (table[j] == &invalid_handler) {
8878 continue;
8879 }
8880 if (is_indirect_opcode(table[j])) {
8881 table_2 = ind_table(table[j]);
8882 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
8883 if (table_2[k] != &invalid_handler &&
8884 is_indirect_opcode(table_2[k])) {
8885 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
8886 ~PPC_INDIRECT));
8887 }
8888 }
8889 g_free((opc_handler_t *)((uintptr_t)table[j] &
8890 ~PPC_INDIRECT));
8891 }
8892 }
8893 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
8894 ~PPC_INDIRECT));
8895 }
8896 }
8897 }
8898
8899 #if defined(PPC_DUMP_CPU)
8900 static void dump_ppc_insns(CPUPPCState *env)
8901 {
8902 opc_handler_t **table, *handler;
8903 const char *p, *q;
8904 uint8_t opc1, opc2, opc3, opc4;
8905
8906 printf("Instructions set:\n");
8907 /* opc1 is 6 bits long */
8908 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
8909 table = env->opcodes;
8910 handler = table[opc1];
8911 if (is_indirect_opcode(handler)) {
8912 /* opc2 is 5 bits long */
8913 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
8914 table = env->opcodes;
8915 handler = env->opcodes[opc1];
8916 table = ind_table(handler);
8917 handler = table[opc2];
8918 if (is_indirect_opcode(handler)) {
8919 table = ind_table(handler);
8920 /* opc3 is 5 bits long */
8921 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
8922 opc3++) {
8923 handler = table[opc3];
8924 if (is_indirect_opcode(handler)) {
8925 table = ind_table(handler);
8926 /* opc4 is 5 bits long */
8927 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
8928 opc4++) {
8929 handler = table[opc4];
8930 if (handler->handler != &gen_invalid) {
8931 printf("INSN: %02x %02x %02x %02x -- "
8932 "(%02d %04d %02d) : %s\n",
8933 opc1, opc2, opc3, opc4,
8934 opc1, (opc3 << 5) | opc2, opc4,
8935 handler->oname);
8936 }
8937 }
8938 } else {
8939 if (handler->handler != &gen_invalid) {
8940 /* Special hack to properly dump SPE insns */
8941 p = strchr(handler->oname, '_');
8942 if (p == NULL) {
8943 printf("INSN: %02x %02x %02x (%02d %04d) : "
8944 "%s\n",
8945 opc1, opc2, opc3, opc1,
8946 (opc3 << 5) | opc2,
8947 handler->oname);
8948 } else {
8949 q = "speundef";
8950 if ((p - handler->oname) != strlen(q)
8951 || (memcmp(handler->oname, q, strlen(q))
8952 != 0)) {
8953 /* First instruction */
8954 printf("INSN: %02x %02x %02x"
8955 "(%02d %04d) : %.*s\n",
8956 opc1, opc2 << 1, opc3, opc1,
8957 (opc3 << 6) | (opc2 << 1),
8958 (int)(p - handler->oname),
8959 handler->oname);
8960 }
8961 if (strcmp(p + 1, q) != 0) {
8962 /* Second instruction */
8963 printf("INSN: %02x %02x %02x "
8964 "(%02d %04d) : %s\n", opc1,
8965 (opc2 << 1) | 1, opc3, opc1,
8966 (opc3 << 6) | (opc2 << 1) | 1,
8967 p + 1);
8968 }
8969 }
8970 }
8971 }
8972 }
8973 } else {
8974 if (handler->handler != &gen_invalid) {
8975 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8976 opc1, opc2, opc1, opc2, handler->oname);
8977 }
8978 }
8979 }
8980 } else {
8981 if (handler->handler != &gen_invalid) {
8982 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8983 opc1, opc1, handler->oname);
8984 }
8985 }
8986 }
8987 }
8988 #endif
8989 int ppc_fixup_cpu(PowerPCCPU *cpu)
8990 {
8991 CPUPPCState *env = &cpu->env;
8992
8993 /*
8994 * TCG doesn't (yet) emulate some groups of instructions that are
8995 * implemented on some otherwise supported CPUs (e.g. VSX and
8996 * decimal floating point instructions on POWER7). We remove
8997 * unsupported instruction groups from the cpu state's instruction
8998 * masks and hope the guest can cope. For at least the pseries
8999 * machine, the unavailability of these instructions can be
9000 * advertised to the guest via the device tree.
9001 */
9002 if ((env->insns_flags & ~PPC_TCG_INSNS)
9003 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9004 warn_report("Disabling some instructions which are not "
9005 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
9006 env->insns_flags & ~PPC_TCG_INSNS,
9007 env->insns_flags2 & ~PPC_TCG_INSNS2);
9008 }
9009 env->insns_flags &= PPC_TCG_INSNS;
9010 env->insns_flags2 &= PPC_TCG_INSNS2;
9011 return 0;
9012 }
9013
9014
9015 void ppc_cpu_dump_statistics(CPUState *cs, int flags)
9016 {
9017 #if defined(DO_PPC_STATISTICS)
9018 PowerPCCPU *cpu = POWERPC_CPU(cs);
9019 opc_handler_t **t1, **t2, **t3, *handler;
9020 int op1, op2, op3;
9021
9022 t1 = cpu->env.opcodes;
9023 for (op1 = 0; op1 < 64; op1++) {
9024 handler = t1[op1];
9025 if (is_indirect_opcode(handler)) {
9026 t2 = ind_table(handler);
9027 for (op2 = 0; op2 < 32; op2++) {
9028 handler = t2[op2];
9029 if (is_indirect_opcode(handler)) {
9030 t3 = ind_table(handler);
9031 for (op3 = 0; op3 < 32; op3++) {
9032 handler = t3[op3];
9033 if (handler->count == 0) {
9034 continue;
9035 }
9036 qemu_printf("%02x %02x %02x (%02x %04d) %16s: "
9037 "%016" PRIx64 " %" PRId64 "\n",
9038 op1, op2, op3, op1, (op3 << 5) | op2,
9039 handler->oname,
9040 handler->count, handler->count);
9041 }
9042 } else {
9043 if (handler->count == 0) {
9044 continue;
9045 }
9046 qemu_printf("%02x %02x (%02x %04d) %16s: "
9047 "%016" PRIx64 " %" PRId64 "\n",
9048 op1, op2, op1, op2, handler->oname,
9049 handler->count, handler->count);
9050 }
9051 }
9052 } else {
9053 if (handler->count == 0) {
9054 continue;
9055 }
9056 qemu_printf("%02x (%02x ) %16s: %016" PRIx64
9057 " %" PRId64 "\n",
9058 op1, op1, handler->oname,
9059 handler->count, handler->count);
9060 }
9061 }
9062 #endif
9063 }
9064
9065 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
9066 {
9067 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9068 CPUPPCState *env = cs->env_ptr;
9069 uint32_t hflags = ctx->base.tb->flags;
9070 int bound;
9071
9072 ctx->exception = POWERPC_EXCP_NONE;
9073 ctx->spr_cb = env->spr_cb;
9074 ctx->pr = (hflags >> HFLAGS_PR) & 1;
9075 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
9076 ctx->dr = (hflags >> HFLAGS_DR) & 1;
9077 ctx->hv = (hflags >> HFLAGS_HV) & 1;
9078 ctx->insns_flags = env->insns_flags;
9079 ctx->insns_flags2 = env->insns_flags2;
9080 ctx->access_type = -1;
9081 ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
9082 ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
9083 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
9084 ctx->flags = env->flags;
9085 #if defined(TARGET_PPC64)
9086 ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
9087 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9088 #endif
9089 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
9090 || env->mmu_model == POWERPC_MMU_601
9091 || env->mmu_model & POWERPC_MMU_64;
9092
9093 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
9094 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
9095 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
9096 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
9097 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
9098 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
9099
9100 ctx->singlestep_enabled = 0;
9101 if ((hflags >> HFLAGS_SE) & 1) {
9102 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
9103 }
9104 if ((hflags >> HFLAGS_BE) & 1) {
9105 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
9106 }
9107 if (unlikely(ctx->base.singlestep_enabled)) {
9108 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9109 }
9110
9111 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
9112 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
9113 }
9114
9115 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
9116 {
9117 }
9118
9119 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
9120 {
9121 tcg_gen_insn_start(dcbase->pc_next);
9122 }
9123
9124 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
9125 const CPUBreakpoint *bp)
9126 {
9127 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9128
9129 gen_debug_exception(ctx);
9130 dcbase->is_jmp = DISAS_NORETURN;
9131 /*
9132 * The address covered by the breakpoint must be included in
9133 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
9134 * cleared -- thus we increment the PC here so that the logic
9135 * setting tb->size below does the right thing.
9136 */
9137 ctx->base.pc_next += 4;
9138 return true;
9139 }
9140
9141 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
9142 {
9143 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9144 PowerPCCPU *cpu = POWERPC_CPU(cs);
9145 CPUPPCState *env = cs->env_ptr;
9146 opc_handler_t **table, *handler;
9147
9148 LOG_DISAS("----------------\n");
9149 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9150 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
9151
9152 ctx->cia = ctx->base.pc_next;
9153 ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
9154 need_byteswap(ctx));
9155
9156 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
9157 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
9158 opc3(ctx->opcode), opc4(ctx->opcode),
9159 ctx->le_mode ? "little" : "big");
9160 ctx->base.pc_next += 4;
9161 table = cpu->opcodes;
9162 handler = table[opc1(ctx->opcode)];
9163 if (is_indirect_opcode(handler)) {
9164 table = ind_table(handler);
9165 handler = table[opc2(ctx->opcode)];
9166 if (is_indirect_opcode(handler)) {
9167 table = ind_table(handler);
9168 handler = table[opc3(ctx->opcode)];
9169 if (is_indirect_opcode(handler)) {
9170 table = ind_table(handler);
9171 handler = table[opc4(ctx->opcode)];
9172 }
9173 }
9174 }
9175 /* Is opcode *REALLY* valid ? */
9176 if (unlikely(handler->handler == &gen_invalid)) {
9177 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
9178 "%02x - %02x - %02x - %02x (%08x) "
9179 TARGET_FMT_lx " %d\n",
9180 opc1(ctx->opcode), opc2(ctx->opcode),
9181 opc3(ctx->opcode), opc4(ctx->opcode),
9182 ctx->opcode, ctx->cia, (int)msr_ir);
9183 } else {
9184 uint32_t inval;
9185
9186 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
9187 && Rc(ctx->opcode))) {
9188 inval = handler->inval2;
9189 } else {
9190 inval = handler->inval1;
9191 }
9192
9193 if (unlikely((ctx->opcode & inval) != 0)) {
9194 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
9195 "%02x - %02x - %02x - %02x (%08x) "
9196 TARGET_FMT_lx "\n", ctx->opcode & inval,
9197 opc1(ctx->opcode), opc2(ctx->opcode),
9198 opc3(ctx->opcode), opc4(ctx->opcode),
9199 ctx->opcode, ctx->cia);
9200 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9201 ctx->base.is_jmp = DISAS_NORETURN;
9202 return;
9203 }
9204 }
9205 (*(handler->handler))(ctx);
9206 #if defined(DO_PPC_STATISTICS)
9207 handler->count++;
9208 #endif
9209 /* Check trace mode exceptions */
9210 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
9211 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
9212 ctx->exception != POWERPC_SYSCALL &&
9213 ctx->exception != POWERPC_EXCP_TRAP &&
9214 ctx->exception != POWERPC_EXCP_BRANCH)) {
9215 uint32_t excp = gen_prep_dbgex(ctx);
9216 gen_exception_nip(ctx, excp, ctx->base.pc_next);
9217 }
9218
9219 if (tcg_check_temp_count()) {
9220 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
9221 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
9222 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
9223 }
9224
9225 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
9226 DISAS_NEXT : DISAS_NORETURN;
9227 }
9228
9229 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
9230 {
9231 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9232
9233 if (ctx->exception == POWERPC_EXCP_NONE) {
9234 gen_goto_tb(ctx, 0, ctx->base.pc_next);
9235 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
9236 if (unlikely(ctx->base.singlestep_enabled)) {
9237 gen_debug_exception(ctx);
9238 }
9239 /* Generate the return instruction */
9240 tcg_gen_exit_tb(NULL, 0);
9241 }
9242 }
9243
9244 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
9245 {
9246 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
9247 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
9248 }
9249
9250 static const TranslatorOps ppc_tr_ops = {
9251 .init_disas_context = ppc_tr_init_disas_context,
9252 .tb_start = ppc_tr_tb_start,
9253 .insn_start = ppc_tr_insn_start,
9254 .breakpoint_check = ppc_tr_breakpoint_check,
9255 .translate_insn = ppc_tr_translate_insn,
9256 .tb_stop = ppc_tr_tb_stop,
9257 .disas_log = ppc_tr_disas_log,
9258 };
9259
9260 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
9261 {
9262 DisasContext ctx;
9263
9264 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
9265 }
9266
9267 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
9268 target_ulong *data)
9269 {
9270 env->nip = data[0];
9271 }
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