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pc-dimm: fix error messages if no slots were defined
[mirror_qemu.git] / target / ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/hw_accel.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/error.h"
33 #include "qapi/qmp/qnull.h"
34 #include "qapi/visitor.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/ppc/ppc.h"
37 #include "mmu-book3s-v3.h"
38 #include "sysemu/qtest.h"
39 #include "qemu/cutils.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
42
43 //#define PPC_DUMP_CPU
44 //#define PPC_DEBUG_SPR
45 //#define PPC_DUMP_SPR_ACCESSES
46 /* #define USE_APPLE_GDB */
47
48 /* Generic callbacks:
49 * do nothing but store/retrieve spr value
50 */
51 static void spr_load_dump_spr(int sprn)
52 {
53 #ifdef PPC_DUMP_SPR_ACCESSES
54 TCGv_i32 t0 = tcg_const_i32(sprn);
55 gen_helper_load_dump_spr(cpu_env, t0);
56 tcg_temp_free_i32(t0);
57 #endif
58 }
59
60 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
61 {
62 gen_load_spr(cpu_gpr[gprn], sprn);
63 spr_load_dump_spr(sprn);
64 }
65
66 static void spr_store_dump_spr(int sprn)
67 {
68 #ifdef PPC_DUMP_SPR_ACCESSES
69 TCGv_i32 t0 = tcg_const_i32(sprn);
70 gen_helper_store_dump_spr(cpu_env, t0);
71 tcg_temp_free_i32(t0);
72 #endif
73 }
74
75 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
76 {
77 gen_store_spr(sprn, cpu_gpr[gprn]);
78 spr_store_dump_spr(sprn);
79 }
80
81 #if !defined(CONFIG_USER_ONLY)
82 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
83 {
84 #ifdef TARGET_PPC64
85 TCGv t0 = tcg_temp_new();
86 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
87 gen_store_spr(sprn, t0);
88 tcg_temp_free(t0);
89 spr_store_dump_spr(sprn);
90 #else
91 spr_write_generic(ctx, sprn, gprn);
92 #endif
93 }
94
95 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
96 {
97 TCGv t0 = tcg_temp_new();
98 TCGv t1 = tcg_temp_new();
99 gen_load_spr(t0, sprn);
100 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
101 tcg_gen_and_tl(t0, t0, t1);
102 gen_store_spr(sprn, t0);
103 tcg_temp_free(t0);
104 tcg_temp_free(t1);
105 }
106
107 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
108 {
109 }
110
111 #endif
112
113 /* SPR common to all PowerPC */
114 /* XER */
115 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
116 {
117 gen_read_xer(ctx, cpu_gpr[gprn]);
118 }
119
120 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
121 {
122 gen_write_xer(cpu_gpr[gprn]);
123 }
124
125 /* LR */
126 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
127 {
128 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
129 }
130
131 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
132 {
133 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
134 }
135
136 /* CFAR */
137 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
138 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
139 {
140 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
141 }
142
143 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
144 {
145 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
146 }
147 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
148
149 /* CTR */
150 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
151 {
152 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
153 }
154
155 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
156 {
157 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
158 }
159
160 /* User read access to SPR */
161 /* USPRx */
162 /* UMMCRx */
163 /* UPMCx */
164 /* USIA */
165 /* UDECR */
166 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
167 {
168 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
169 }
170
171 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
172 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
173 {
174 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
175 }
176 #endif
177
178 /* SPR common to all non-embedded PowerPC */
179 /* DECR */
180 #if !defined(CONFIG_USER_ONLY)
181 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
182 {
183 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
184 gen_io_start();
185 }
186 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
187 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
188 gen_io_end();
189 gen_stop_exception(ctx);
190 }
191 }
192
193 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
194 {
195 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
196 gen_io_start();
197 }
198 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
199 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
200 gen_io_end();
201 gen_stop_exception(ctx);
202 }
203 }
204 #endif
205
206 /* SPR common to all non-embedded PowerPC, except 601 */
207 /* Time base */
208 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
209 {
210 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
211 gen_io_start();
212 }
213 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
214 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
215 gen_io_end();
216 gen_stop_exception(ctx);
217 }
218 }
219
220 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
221 {
222 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
223 gen_io_start();
224 }
225 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
226 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
227 gen_io_end();
228 gen_stop_exception(ctx);
229 }
230 }
231
232 __attribute__ (( unused ))
233 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
234 {
235 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
236 }
237
238 __attribute__ (( unused ))
239 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
240 {
241 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
242 }
243
244 #if !defined(CONFIG_USER_ONLY)
245 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
246 {
247 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
248 gen_io_start();
249 }
250 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
251 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
252 gen_io_end();
253 gen_stop_exception(ctx);
254 }
255 }
256
257 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
258 {
259 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
260 gen_io_start();
261 }
262 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
263 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
264 gen_io_end();
265 gen_stop_exception(ctx);
266 }
267 }
268
269 __attribute__ (( unused ))
270 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
271 {
272 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
273 }
274
275 __attribute__ (( unused ))
276 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
277 {
278 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
279 }
280
281 #if defined(TARGET_PPC64)
282 __attribute__ (( unused ))
283 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
284 {
285 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
286 }
287
288 /* HDECR */
289 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
290 {
291 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
292 gen_io_start();
293 }
294 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
295 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
296 gen_io_end();
297 gen_stop_exception(ctx);
298 }
299 }
300
301 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
302 {
303 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
304 gen_io_start();
305 }
306 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
307 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
308 gen_io_end();
309 gen_stop_exception(ctx);
310 }
311 }
312
313 #endif
314 #endif
315
316 #if !defined(CONFIG_USER_ONLY)
317 /* IBAT0U...IBAT0U */
318 /* IBAT0L...IBAT7L */
319 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
320 {
321 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
322 }
323
324 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
325 {
326 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
327 }
328
329 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
330 {
331 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
332 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
333 tcg_temp_free_i32(t0);
334 }
335
336 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
337 {
338 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
339 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
340 tcg_temp_free_i32(t0);
341 }
342
343 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
344 {
345 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
346 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
347 tcg_temp_free_i32(t0);
348 }
349
350 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
351 {
352 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
353 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
354 tcg_temp_free_i32(t0);
355 }
356
357 /* DBAT0U...DBAT7U */
358 /* DBAT0L...DBAT7L */
359 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
360 {
361 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
362 }
363
364 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
365 {
366 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
367 }
368
369 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
370 {
371 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
372 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
373 tcg_temp_free_i32(t0);
374 }
375
376 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
377 {
378 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
379 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
380 tcg_temp_free_i32(t0);
381 }
382
383 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
384 {
385 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
386 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
387 tcg_temp_free_i32(t0);
388 }
389
390 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
391 {
392 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
393 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
394 tcg_temp_free_i32(t0);
395 }
396
397 /* SDR1 */
398 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
399 {
400 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
401 }
402
403 #if defined(TARGET_PPC64)
404 /* 64 bits PowerPC specific SPRs */
405 /* PIDR */
406 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
407 {
408 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
409 }
410
411 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
412 {
413 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
414 }
415
416 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
417 {
418 TCGv t0 = tcg_temp_new();
419 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
420 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
421 tcg_temp_free(t0);
422 }
423 static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
424 {
425 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
426 }
427
428 #endif
429 #endif
430
431 /* PowerPC 601 specific registers */
432 /* RTC */
433 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
434 {
435 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
436 }
437
438 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
439 {
440 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
441 }
442
443 #if !defined(CONFIG_USER_ONLY)
444 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
445 {
446 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
447 }
448
449 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
450 {
451 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
452 }
453
454 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
455 {
456 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
457 /* Must stop the translation as endianness may have changed */
458 gen_stop_exception(ctx);
459 }
460 #endif
461
462 /* Unified bats */
463 #if !defined(CONFIG_USER_ONLY)
464 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
465 {
466 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
467 }
468
469 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
470 {
471 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
472 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
473 tcg_temp_free_i32(t0);
474 }
475
476 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
477 {
478 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
479 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
480 tcg_temp_free_i32(t0);
481 }
482 #endif
483
484 /* PowerPC 40x specific registers */
485 #if !defined(CONFIG_USER_ONLY)
486 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
487 {
488 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
489 }
490
491 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
492 {
493 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
494 }
495
496 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
497 {
498 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
499 /* We must stop translation as we may have rebooted */
500 gen_stop_exception(ctx);
501 }
502
503 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
504 {
505 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
506 }
507
508 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
509 {
510 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
511 }
512
513 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
514 {
515 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
516 }
517 #endif
518
519 /* PowerPC 403 specific registers */
520 /* PBL1 / PBU1 / PBL2 / PBU2 */
521 #if !defined(CONFIG_USER_ONLY)
522 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
523 {
524 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
525 }
526
527 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
528 {
529 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
530 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
531 tcg_temp_free_i32(t0);
532 }
533
534 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
535 {
536 TCGv t0 = tcg_temp_new();
537 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
538 gen_store_spr(SPR_PIR, t0);
539 tcg_temp_free(t0);
540 }
541 #endif
542
543 /* SPE specific registers */
544 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
545 {
546 TCGv_i32 t0 = tcg_temp_new_i32();
547 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
548 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
549 tcg_temp_free_i32(t0);
550 }
551
552 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
553 {
554 TCGv_i32 t0 = tcg_temp_new_i32();
555 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
556 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
557 tcg_temp_free_i32(t0);
558 }
559
560 #if !defined(CONFIG_USER_ONLY)
561 /* Callback used to write the exception vector base */
562 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
563 {
564 TCGv t0 = tcg_temp_new();
565 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
566 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
567 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
568 gen_store_spr(sprn, t0);
569 tcg_temp_free(t0);
570 }
571
572 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
573 {
574 int sprn_offs;
575
576 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
577 sprn_offs = sprn - SPR_BOOKE_IVOR0;
578 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
579 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
580 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
581 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
582 } else {
583 printf("Trying to write an unknown exception vector %d %03x\n",
584 sprn, sprn);
585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
586 return;
587 }
588
589 TCGv t0 = tcg_temp_new();
590 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
591 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
592 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
593 gen_store_spr(sprn, t0);
594 tcg_temp_free(t0);
595 }
596 #endif
597
598 static inline void vscr_init(CPUPPCState *env, uint32_t val)
599 {
600 env->vscr = val;
601 /* Altivec always uses round-to-nearest */
602 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
603 set_flush_to_zero(vscr_nj, &env->vec_status);
604 }
605
606 #ifdef CONFIG_USER_ONLY
607 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
608 oea_read, oea_write, one_reg_id, initial_value) \
609 _spr_register(env, num, name, uea_read, uea_write, initial_value)
610 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
611 oea_read, oea_write, hea_read, hea_write, \
612 one_reg_id, initial_value) \
613 _spr_register(env, num, name, uea_read, uea_write, initial_value)
614 #else
615 #if !defined(CONFIG_KVM)
616 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
617 oea_read, oea_write, one_reg_id, initial_value) \
618 _spr_register(env, num, name, uea_read, uea_write, \
619 oea_read, oea_write, oea_read, oea_write, initial_value)
620 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
621 oea_read, oea_write, hea_read, hea_write, \
622 one_reg_id, initial_value) \
623 _spr_register(env, num, name, uea_read, uea_write, \
624 oea_read, oea_write, hea_read, hea_write, initial_value)
625 #else
626 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
627 oea_read, oea_write, one_reg_id, initial_value) \
628 _spr_register(env, num, name, uea_read, uea_write, \
629 oea_read, oea_write, oea_read, oea_write, \
630 one_reg_id, initial_value)
631 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
632 oea_read, oea_write, hea_read, hea_write, \
633 one_reg_id, initial_value) \
634 _spr_register(env, num, name, uea_read, uea_write, \
635 oea_read, oea_write, hea_read, hea_write, \
636 one_reg_id, initial_value)
637 #endif
638 #endif
639
640 #define spr_register(env, num, name, uea_read, uea_write, \
641 oea_read, oea_write, initial_value) \
642 spr_register_kvm(env, num, name, uea_read, uea_write, \
643 oea_read, oea_write, 0, initial_value)
644
645 #define spr_register_hv(env, num, name, uea_read, uea_write, \
646 oea_read, oea_write, hea_read, hea_write, \
647 initial_value) \
648 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
649 oea_read, oea_write, hea_read, hea_write, \
650 0, initial_value)
651
652 static inline void _spr_register(CPUPPCState *env, int num,
653 const char *name,
654 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
655 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
656 #if !defined(CONFIG_USER_ONLY)
657
658 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
659 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
660 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
661 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
662 #endif
663 #if defined(CONFIG_KVM)
664 uint64_t one_reg_id,
665 #endif
666 target_ulong initial_value)
667 {
668 ppc_spr_t *spr;
669
670 spr = &env->spr_cb[num];
671 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
672 #if !defined(CONFIG_USER_ONLY)
673 spr->oea_read != NULL || spr->oea_write != NULL ||
674 #endif
675 spr->uea_read != NULL || spr->uea_write != NULL) {
676 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
677 exit(1);
678 }
679 #if defined(PPC_DEBUG_SPR)
680 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
681 name, initial_value);
682 #endif
683 spr->name = name;
684 spr->uea_read = uea_read;
685 spr->uea_write = uea_write;
686 #if !defined(CONFIG_USER_ONLY)
687 spr->oea_read = oea_read;
688 spr->oea_write = oea_write;
689 spr->hea_read = hea_read;
690 spr->hea_write = hea_write;
691 #endif
692 #if defined(CONFIG_KVM)
693 spr->one_reg_id = one_reg_id,
694 #endif
695 env->spr[num] = spr->default_value = initial_value;
696 }
697
698 /* Generic PowerPC SPRs */
699 static void gen_spr_generic(CPUPPCState *env)
700 {
701 /* Integer processing */
702 spr_register(env, SPR_XER, "XER",
703 &spr_read_xer, &spr_write_xer,
704 &spr_read_xer, &spr_write_xer,
705 0x00000000);
706 /* Branch contol */
707 spr_register(env, SPR_LR, "LR",
708 &spr_read_lr, &spr_write_lr,
709 &spr_read_lr, &spr_write_lr,
710 0x00000000);
711 spr_register(env, SPR_CTR, "CTR",
712 &spr_read_ctr, &spr_write_ctr,
713 &spr_read_ctr, &spr_write_ctr,
714 0x00000000);
715 /* Interrupt processing */
716 spr_register(env, SPR_SRR0, "SRR0",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, &spr_write_generic,
719 0x00000000);
720 spr_register(env, SPR_SRR1, "SRR1",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724 /* Processor control */
725 spr_register(env, SPR_SPRG0, "SPRG0",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729 spr_register(env, SPR_SPRG1, "SPRG1",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733 spr_register(env, SPR_SPRG2, "SPRG2",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_generic,
736 0x00000000);
737 spr_register(env, SPR_SPRG3, "SPRG3",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_generic, &spr_write_generic,
740 0x00000000);
741 }
742
743 /* SPR common to all non-embedded PowerPC, including 601 */
744 static void gen_spr_ne_601(CPUPPCState *env)
745 {
746 /* Exception processing */
747 spr_register_kvm(env, SPR_DSISR, "DSISR",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_generic, &spr_write_generic,
750 KVM_REG_PPC_DSISR, 0x00000000);
751 spr_register_kvm(env, SPR_DAR, "DAR",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 KVM_REG_PPC_DAR, 0x00000000);
755 /* Timer */
756 spr_register(env, SPR_DECR, "DECR",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_decr, &spr_write_decr,
759 0x00000000);
760 }
761
762 /* Storage Description Register 1 */
763 static void gen_spr_sdr1(CPUPPCState *env)
764 {
765 #ifndef CONFIG_USER_ONLY
766 if (env->has_hv_mode) {
767 /* SDR1 is a hypervisor resource on CPUs which have a
768 * hypervisor mode */
769 spr_register_hv(env, SPR_SDR1, "SDR1",
770 SPR_NOACCESS, SPR_NOACCESS,
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_sdr1,
773 0x00000000);
774 } else {
775 spr_register(env, SPR_SDR1, "SDR1",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_sdr1,
778 0x00000000);
779 }
780 #endif
781 }
782
783 /* BATs 0-3 */
784 static void gen_low_BATs(CPUPPCState *env)
785 {
786 #if !defined(CONFIG_USER_ONLY)
787 spr_register(env, SPR_IBAT0U, "IBAT0U",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_ibat, &spr_write_ibatu,
790 0x00000000);
791 spr_register(env, SPR_IBAT0L, "IBAT0L",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_ibat, &spr_write_ibatl,
794 0x00000000);
795 spr_register(env, SPR_IBAT1U, "IBAT1U",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_ibat, &spr_write_ibatu,
798 0x00000000);
799 spr_register(env, SPR_IBAT1L, "IBAT1L",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat, &spr_write_ibatl,
802 0x00000000);
803 spr_register(env, SPR_IBAT2U, "IBAT2U",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_ibat, &spr_write_ibatu,
806 0x00000000);
807 spr_register(env, SPR_IBAT2L, "IBAT2L",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_ibat, &spr_write_ibatl,
810 0x00000000);
811 spr_register(env, SPR_IBAT3U, "IBAT3U",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_ibat, &spr_write_ibatu,
814 0x00000000);
815 spr_register(env, SPR_IBAT3L, "IBAT3L",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_ibat, &spr_write_ibatl,
818 0x00000000);
819 spr_register(env, SPR_DBAT0U, "DBAT0U",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_dbat, &spr_write_dbatu,
822 0x00000000);
823 spr_register(env, SPR_DBAT0L, "DBAT0L",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_dbat, &spr_write_dbatl,
826 0x00000000);
827 spr_register(env, SPR_DBAT1U, "DBAT1U",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_dbat, &spr_write_dbatu,
830 0x00000000);
831 spr_register(env, SPR_DBAT1L, "DBAT1L",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat, &spr_write_dbatl,
834 0x00000000);
835 spr_register(env, SPR_DBAT2U, "DBAT2U",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_dbat, &spr_write_dbatu,
838 0x00000000);
839 spr_register(env, SPR_DBAT2L, "DBAT2L",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_dbat, &spr_write_dbatl,
842 0x00000000);
843 spr_register(env, SPR_DBAT3U, "DBAT3U",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_dbat, &spr_write_dbatu,
846 0x00000000);
847 spr_register(env, SPR_DBAT3L, "DBAT3L",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_dbat, &spr_write_dbatl,
850 0x00000000);
851 env->nb_BATs += 4;
852 #endif
853 }
854
855 /* BATs 4-7 */
856 static void gen_high_BATs(CPUPPCState *env)
857 {
858 #if !defined(CONFIG_USER_ONLY)
859 spr_register(env, SPR_IBAT4U, "IBAT4U",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_ibat_h, &spr_write_ibatu_h,
862 0x00000000);
863 spr_register(env, SPR_IBAT4L, "IBAT4L",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_ibat_h, &spr_write_ibatl_h,
866 0x00000000);
867 spr_register(env, SPR_IBAT5U, "IBAT5U",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_ibat_h, &spr_write_ibatu_h,
870 0x00000000);
871 spr_register(env, SPR_IBAT5L, "IBAT5L",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_ibat_h, &spr_write_ibatl_h,
874 0x00000000);
875 spr_register(env, SPR_IBAT6U, "IBAT6U",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_ibat_h, &spr_write_ibatu_h,
878 0x00000000);
879 spr_register(env, SPR_IBAT6L, "IBAT6L",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_ibat_h, &spr_write_ibatl_h,
882 0x00000000);
883 spr_register(env, SPR_IBAT7U, "IBAT7U",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_ibat_h, &spr_write_ibatu_h,
886 0x00000000);
887 spr_register(env, SPR_IBAT7L, "IBAT7L",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_ibat_h, &spr_write_ibatl_h,
890 0x00000000);
891 spr_register(env, SPR_DBAT4U, "DBAT4U",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_dbat_h, &spr_write_dbatu_h,
894 0x00000000);
895 spr_register(env, SPR_DBAT4L, "DBAT4L",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_dbat_h, &spr_write_dbatl_h,
898 0x00000000);
899 spr_register(env, SPR_DBAT5U, "DBAT5U",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_dbat_h, &spr_write_dbatu_h,
902 0x00000000);
903 spr_register(env, SPR_DBAT5L, "DBAT5L",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_dbat_h, &spr_write_dbatl_h,
906 0x00000000);
907 spr_register(env, SPR_DBAT6U, "DBAT6U",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_dbat_h, &spr_write_dbatu_h,
910 0x00000000);
911 spr_register(env, SPR_DBAT6L, "DBAT6L",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_dbat_h, &spr_write_dbatl_h,
914 0x00000000);
915 spr_register(env, SPR_DBAT7U, "DBAT7U",
916 SPR_NOACCESS, SPR_NOACCESS,
917 &spr_read_dbat_h, &spr_write_dbatu_h,
918 0x00000000);
919 spr_register(env, SPR_DBAT7L, "DBAT7L",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_dbat_h, &spr_write_dbatl_h,
922 0x00000000);
923 env->nb_BATs += 4;
924 #endif
925 }
926
927 /* Generic PowerPC time base */
928 static void gen_tbl(CPUPPCState *env)
929 {
930 spr_register(env, SPR_VTBL, "TBL",
931 &spr_read_tbl, SPR_NOACCESS,
932 &spr_read_tbl, SPR_NOACCESS,
933 0x00000000);
934 spr_register(env, SPR_TBL, "TBL",
935 &spr_read_tbl, SPR_NOACCESS,
936 &spr_read_tbl, &spr_write_tbl,
937 0x00000000);
938 spr_register(env, SPR_VTBU, "TBU",
939 &spr_read_tbu, SPR_NOACCESS,
940 &spr_read_tbu, SPR_NOACCESS,
941 0x00000000);
942 spr_register(env, SPR_TBU, "TBU",
943 &spr_read_tbu, SPR_NOACCESS,
944 &spr_read_tbu, &spr_write_tbu,
945 0x00000000);
946 }
947
948 /* Softare table search registers */
949 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
950 {
951 #if !defined(CONFIG_USER_ONLY)
952 env->nb_tlb = nb_tlbs;
953 env->nb_ways = nb_ways;
954 env->id_tlbs = 1;
955 env->tlb_type = TLB_6XX;
956 spr_register(env, SPR_DMISS, "DMISS",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, SPR_NOACCESS,
959 0x00000000);
960 spr_register(env, SPR_DCMP, "DCMP",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, SPR_NOACCESS,
963 0x00000000);
964 spr_register(env, SPR_HASH1, "HASH1",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, SPR_NOACCESS,
967 0x00000000);
968 spr_register(env, SPR_HASH2, "HASH2",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, SPR_NOACCESS,
971 0x00000000);
972 spr_register(env, SPR_IMISS, "IMISS",
973 SPR_NOACCESS, SPR_NOACCESS,
974 &spr_read_generic, SPR_NOACCESS,
975 0x00000000);
976 spr_register(env, SPR_ICMP, "ICMP",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, SPR_NOACCESS,
979 0x00000000);
980 spr_register(env, SPR_RPA, "RPA",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 0x00000000);
984 #endif
985 }
986
987 /* SPR common to MPC755 and G2 */
988 static void gen_spr_G2_755(CPUPPCState *env)
989 {
990 /* SGPRs */
991 spr_register(env, SPR_SPRG4, "SPRG4",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995 spr_register(env, SPR_SPRG5, "SPRG5",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 spr_register(env, SPR_SPRG6, "SPRG6",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003 spr_register(env, SPR_SPRG7, "SPRG7",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 }
1008
1009 /* SPR common to all 7xx PowerPC implementations */
1010 static void gen_spr_7xx(CPUPPCState *env)
1011 {
1012 /* Breakpoints */
1013 /* XXX : not implemented */
1014 spr_register_kvm(env, SPR_DABR, "DABR",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 KVM_REG_PPC_DABR, 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_IABR, "IABR",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 /* Cache management */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_ICTC, "ICTC",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* Performance monitors */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_7XX_PMC1, "PMC1",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_7XX_PMC2, "PMC2",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_7XX_PMC3, "PMC3",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_7XX_PMC4, "PMC4",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_7XX_SIAR, "SIAR",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, SPR_NOACCESS,
1064 0x00000000);
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1067 &spr_read_ureg, SPR_NOACCESS,
1068 &spr_read_ureg, SPR_NOACCESS,
1069 0x00000000);
1070 /* XXX : not implemented */
1071 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1072 &spr_read_ureg, SPR_NOACCESS,
1073 &spr_read_ureg, SPR_NOACCESS,
1074 0x00000000);
1075 /* XXX : not implemented */
1076 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1077 &spr_read_ureg, SPR_NOACCESS,
1078 &spr_read_ureg, SPR_NOACCESS,
1079 0x00000000);
1080 /* XXX : not implemented */
1081 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1082 &spr_read_ureg, SPR_NOACCESS,
1083 &spr_read_ureg, SPR_NOACCESS,
1084 0x00000000);
1085 /* XXX : not implemented */
1086 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1087 &spr_read_ureg, SPR_NOACCESS,
1088 &spr_read_ureg, SPR_NOACCESS,
1089 0x00000000);
1090 /* XXX : not implemented */
1091 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1092 &spr_read_ureg, SPR_NOACCESS,
1093 &spr_read_ureg, SPR_NOACCESS,
1094 0x00000000);
1095 /* XXX : not implemented */
1096 spr_register(env, SPR_7XX_USIAR, "USIAR",
1097 &spr_read_ureg, SPR_NOACCESS,
1098 &spr_read_ureg, SPR_NOACCESS,
1099 0x00000000);
1100 /* External access control */
1101 /* XXX : not implemented */
1102 spr_register(env, SPR_EAR, "EAR",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, &spr_write_generic,
1105 0x00000000);
1106 }
1107
1108 #ifdef TARGET_PPC64
1109 #ifndef CONFIG_USER_ONLY
1110 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1111 {
1112 TCGv t0 = tcg_temp_new();
1113 TCGv t1 = tcg_temp_new();
1114 TCGv t2 = tcg_temp_new();
1115
1116 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1117 * spr_write_generic for HV mode in the SPR table
1118 */
1119
1120 /* Build insertion mask into t1 based on context */
1121 if (ctx->pr) {
1122 gen_load_spr(t1, SPR_UAMOR);
1123 } else {
1124 gen_load_spr(t1, SPR_AMOR);
1125 }
1126
1127 /* Mask new bits into t2 */
1128 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1129
1130 /* Load AMR and clear new bits in t0 */
1131 gen_load_spr(t0, SPR_AMR);
1132 tcg_gen_andc_tl(t0, t0, t1);
1133
1134 /* Or'in new bits and write it out */
1135 tcg_gen_or_tl(t0, t0, t2);
1136 gen_store_spr(SPR_AMR, t0);
1137 spr_store_dump_spr(SPR_AMR);
1138
1139 tcg_temp_free(t0);
1140 tcg_temp_free(t1);
1141 tcg_temp_free(t2);
1142 }
1143
1144 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1145 {
1146 TCGv t0 = tcg_temp_new();
1147 TCGv t1 = tcg_temp_new();
1148 TCGv t2 = tcg_temp_new();
1149
1150 /* Note, the HV=1 case is handled earlier by simply using
1151 * spr_write_generic for HV mode in the SPR table
1152 */
1153
1154 /* Build insertion mask into t1 based on context */
1155 gen_load_spr(t1, SPR_AMOR);
1156
1157 /* Mask new bits into t2 */
1158 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1159
1160 /* Load AMR and clear new bits in t0 */
1161 gen_load_spr(t0, SPR_UAMOR);
1162 tcg_gen_andc_tl(t0, t0, t1);
1163
1164 /* Or'in new bits and write it out */
1165 tcg_gen_or_tl(t0, t0, t2);
1166 gen_store_spr(SPR_UAMOR, t0);
1167 spr_store_dump_spr(SPR_UAMOR);
1168
1169 tcg_temp_free(t0);
1170 tcg_temp_free(t1);
1171 tcg_temp_free(t2);
1172 }
1173
1174 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1175 {
1176 TCGv t0 = tcg_temp_new();
1177 TCGv t1 = tcg_temp_new();
1178 TCGv t2 = tcg_temp_new();
1179
1180 /* Note, the HV=1 case is handled earlier by simply using
1181 * spr_write_generic for HV mode in the SPR table
1182 */
1183
1184 /* Build insertion mask into t1 based on context */
1185 gen_load_spr(t1, SPR_AMOR);
1186
1187 /* Mask new bits into t2 */
1188 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1189
1190 /* Load AMR and clear new bits in t0 */
1191 gen_load_spr(t0, SPR_IAMR);
1192 tcg_gen_andc_tl(t0, t0, t1);
1193
1194 /* Or'in new bits and write it out */
1195 tcg_gen_or_tl(t0, t0, t2);
1196 gen_store_spr(SPR_IAMR, t0);
1197 spr_store_dump_spr(SPR_IAMR);
1198
1199 tcg_temp_free(t0);
1200 tcg_temp_free(t1);
1201 tcg_temp_free(t2);
1202 }
1203 #endif /* CONFIG_USER_ONLY */
1204
1205 static void gen_spr_amr(CPUPPCState *env)
1206 {
1207 #ifndef CONFIG_USER_ONLY
1208 /* Virtual Page Class Key protection */
1209 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1210 * userspace accessible, 29 is privileged. So we only need to set
1211 * the kvm ONE_REG id on one of them, we use 29 */
1212 spr_register(env, SPR_UAMR, "UAMR",
1213 &spr_read_generic, &spr_write_amr,
1214 &spr_read_generic, &spr_write_amr,
1215 0);
1216 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_amr,
1219 &spr_read_generic, &spr_write_generic,
1220 KVM_REG_PPC_AMR, 0);
1221 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_uamor,
1224 &spr_read_generic, &spr_write_generic,
1225 KVM_REG_PPC_UAMOR, 0);
1226 spr_register_hv(env, SPR_AMOR, "AMOR",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0);
1231 #endif /* !CONFIG_USER_ONLY */
1232 }
1233
1234 static void gen_spr_iamr(CPUPPCState *env)
1235 {
1236 #ifndef CONFIG_USER_ONLY
1237 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_iamr,
1240 &spr_read_generic, &spr_write_generic,
1241 KVM_REG_PPC_IAMR, 0);
1242 #endif /* !CONFIG_USER_ONLY */
1243 }
1244 #endif /* TARGET_PPC64 */
1245
1246 #ifndef CONFIG_USER_ONLY
1247 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1248 {
1249 gen_helper_fixup_thrm(cpu_env);
1250 gen_load_spr(cpu_gpr[gprn], sprn);
1251 spr_load_dump_spr(sprn);
1252 }
1253 #endif /* !CONFIG_USER_ONLY */
1254
1255 static void gen_spr_thrm(CPUPPCState *env)
1256 {
1257 /* Thermal management */
1258 /* XXX : not implemented */
1259 spr_register(env, SPR_THRM1, "THRM1",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_thrm, &spr_write_generic,
1262 0x00000000);
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_THRM2, "THRM2",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_thrm, &spr_write_generic,
1267 0x00000000);
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_THRM3, "THRM3",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_thrm, &spr_write_generic,
1272 0x00000000);
1273 }
1274
1275 /* SPR specific to PowerPC 604 implementation */
1276 static void gen_spr_604(CPUPPCState *env)
1277 {
1278 /* Processor identification */
1279 spr_register(env, SPR_PIR, "PIR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_pir,
1282 0x00000000);
1283 /* Breakpoints */
1284 /* XXX : not implemented */
1285 spr_register(env, SPR_IABR, "IABR",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 /* XXX : not implemented */
1290 spr_register_kvm(env, SPR_DABR, "DABR",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 KVM_REG_PPC_DABR, 0x00000000);
1294 /* Performance counters */
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300 /* XXX : not implemented */
1301 spr_register(env, SPR_7XX_PMC1, "PMC1",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_7XX_PMC2, "PMC2",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_7XX_SIAR, "SIAR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, SPR_NOACCESS,
1314 0x00000000);
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_SDA, "SDA",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, SPR_NOACCESS,
1319 0x00000000);
1320 /* External access control */
1321 /* XXX : not implemented */
1322 spr_register(env, SPR_EAR, "EAR",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
1326 }
1327
1328 /* SPR specific to PowerPC 603 implementation */
1329 static void gen_spr_603(CPUPPCState *env)
1330 {
1331 /* External access control */
1332 /* XXX : not implemented */
1333 spr_register(env, SPR_EAR, "EAR",
1334 SPR_NOACCESS, SPR_NOACCESS,
1335 &spr_read_generic, &spr_write_generic,
1336 0x00000000);
1337 /* Breakpoints */
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_IABR, "IABR",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343
1344 }
1345
1346 /* SPR specific to PowerPC G2 implementation */
1347 static void gen_spr_G2(CPUPPCState *env)
1348 {
1349 /* Memory base address */
1350 /* MBAR */
1351 /* XXX : not implemented */
1352 spr_register(env, SPR_MBAR, "MBAR",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
1356 /* Exception processing */
1357 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 0x00000000);
1361 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* Breakpoints */
1366 /* XXX : not implemented */
1367 spr_register(env, SPR_DABR, "DABR",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 /* XXX : not implemented */
1372 spr_register(env, SPR_DABR2, "DABR2",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 /* XXX : not implemented */
1377 spr_register(env, SPR_IABR, "IABR",
1378 SPR_NOACCESS, SPR_NOACCESS,
1379 &spr_read_generic, &spr_write_generic,
1380 0x00000000);
1381 /* XXX : not implemented */
1382 spr_register(env, SPR_IABR2, "IABR2",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, &spr_write_generic,
1385 0x00000000);
1386 /* XXX : not implemented */
1387 spr_register(env, SPR_IBCR, "IBCR",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391 /* XXX : not implemented */
1392 spr_register(env, SPR_DBCR, "DBCR",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396 }
1397
1398 /* SPR specific to PowerPC 602 implementation */
1399 static void gen_spr_602(CPUPPCState *env)
1400 {
1401 /* ESA registers */
1402 /* XXX : not implemented */
1403 spr_register(env, SPR_SER, "SER",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407 /* XXX : not implemented */
1408 spr_register(env, SPR_SEBR, "SEBR",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412 /* XXX : not implemented */
1413 spr_register(env, SPR_ESASRR, "ESASRR",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* Floating point status */
1418 /* XXX : not implemented */
1419 spr_register(env, SPR_SP, "SP",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 /* XXX : not implemented */
1424 spr_register(env, SPR_LT, "LT",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428 /* Watchdog timer */
1429 /* XXX : not implemented */
1430 spr_register(env, SPR_TCR, "TCR",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_generic, &spr_write_generic,
1433 0x00000000);
1434 /* Interrupt base */
1435 spr_register(env, SPR_IBR, "IBR",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_generic, &spr_write_generic,
1438 0x00000000);
1439 /* XXX : not implemented */
1440 spr_register(env, SPR_IABR, "IABR",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444 }
1445
1446 /* SPR specific to PowerPC 601 implementation */
1447 static void gen_spr_601(CPUPPCState *env)
1448 {
1449 /* Multiplication/division register */
1450 /* MQ */
1451 spr_register(env, SPR_MQ, "MQ",
1452 &spr_read_generic, &spr_write_generic,
1453 &spr_read_generic, &spr_write_generic,
1454 0x00000000);
1455 /* RTC registers */
1456 spr_register(env, SPR_601_RTCU, "RTCU",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 SPR_NOACCESS, &spr_write_601_rtcu,
1459 0x00000000);
1460 spr_register(env, SPR_601_VRTCU, "RTCU",
1461 &spr_read_601_rtcu, SPR_NOACCESS,
1462 &spr_read_601_rtcu, SPR_NOACCESS,
1463 0x00000000);
1464 spr_register(env, SPR_601_RTCL, "RTCL",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 SPR_NOACCESS, &spr_write_601_rtcl,
1467 0x00000000);
1468 spr_register(env, SPR_601_VRTCL, "RTCL",
1469 &spr_read_601_rtcl, SPR_NOACCESS,
1470 &spr_read_601_rtcl, SPR_NOACCESS,
1471 0x00000000);
1472 /* Timer */
1473 #if 0 /* ? */
1474 spr_register(env, SPR_601_UDECR, "UDECR",
1475 &spr_read_decr, SPR_NOACCESS,
1476 &spr_read_decr, SPR_NOACCESS,
1477 0x00000000);
1478 #endif
1479 /* External access control */
1480 /* XXX : not implemented */
1481 spr_register(env, SPR_EAR, "EAR",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 /* Memory management */
1486 #if !defined(CONFIG_USER_ONLY)
1487 spr_register(env, SPR_IBAT0U, "IBAT0U",
1488 SPR_NOACCESS, SPR_NOACCESS,
1489 &spr_read_601_ubat, &spr_write_601_ubatu,
1490 0x00000000);
1491 spr_register(env, SPR_IBAT0L, "IBAT0L",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_601_ubat, &spr_write_601_ubatl,
1494 0x00000000);
1495 spr_register(env, SPR_IBAT1U, "IBAT1U",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_601_ubat, &spr_write_601_ubatu,
1498 0x00000000);
1499 spr_register(env, SPR_IBAT1L, "IBAT1L",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_601_ubat, &spr_write_601_ubatl,
1502 0x00000000);
1503 spr_register(env, SPR_IBAT2U, "IBAT2U",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_601_ubat, &spr_write_601_ubatu,
1506 0x00000000);
1507 spr_register(env, SPR_IBAT2L, "IBAT2L",
1508 SPR_NOACCESS, SPR_NOACCESS,
1509 &spr_read_601_ubat, &spr_write_601_ubatl,
1510 0x00000000);
1511 spr_register(env, SPR_IBAT3U, "IBAT3U",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_601_ubat, &spr_write_601_ubatu,
1514 0x00000000);
1515 spr_register(env, SPR_IBAT3L, "IBAT3L",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_601_ubat, &spr_write_601_ubatl,
1518 0x00000000);
1519 env->nb_BATs = 4;
1520 #endif
1521 }
1522
1523 static void gen_spr_74xx(CPUPPCState *env)
1524 {
1525 /* Processor identification */
1526 spr_register(env, SPR_PIR, "PIR",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_pir,
1529 0x00000000);
1530 /* XXX : not implemented */
1531 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
1535 /* XXX : not implemented */
1536 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1537 &spr_read_ureg, SPR_NOACCESS,
1538 &spr_read_ureg, SPR_NOACCESS,
1539 0x00000000);
1540 /* XXX: not implemented */
1541 spr_register(env, SPR_BAMR, "BAMR",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_MSSCR0, "MSSCR0",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 /* Hardware implementation registers */
1551 /* XXX : not implemented */
1552 spr_register(env, SPR_HID0, "HID0",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556 /* XXX : not implemented */
1557 spr_register(env, SPR_HID1, "HID1",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561 /* Altivec */
1562 spr_register(env, SPR_VRSAVE, "VRSAVE",
1563 &spr_read_generic, &spr_write_generic,
1564 &spr_read_generic, &spr_write_generic,
1565 0x00000000);
1566 /* XXX : not implemented */
1567 spr_register(env, SPR_L2CR, "L2CR",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, spr_access_nop,
1570 0x00000000);
1571 /* Not strictly an SPR */
1572 vscr_init(env, 0x00010000);
1573 }
1574
1575 static void gen_l3_ctrl(CPUPPCState *env)
1576 {
1577 /* L3CR */
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_L3CR, "L3CR",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 /* L3ITCR0 */
1584 /* XXX : not implemented */
1585 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000);
1589 /* L3PM */
1590 /* XXX : not implemented */
1591 spr_register(env, SPR_L3PM, "L3PM",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595 }
1596
1597 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1598 {
1599 #if !defined(CONFIG_USER_ONLY)
1600 env->nb_tlb = nb_tlbs;
1601 env->nb_ways = nb_ways;
1602 env->id_tlbs = 1;
1603 env->tlb_type = TLB_6XX;
1604 /* XXX : not implemented */
1605 spr_register(env, SPR_PTEHI, "PTEHI",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609 /* XXX : not implemented */
1610 spr_register(env, SPR_PTELO, "PTELO",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_TLBMISS, "TLBMISS",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619 #endif
1620 }
1621
1622 #if !defined(CONFIG_USER_ONLY)
1623 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1624 {
1625 TCGv t0 = tcg_temp_new();
1626
1627 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1628 gen_store_spr(sprn, t0);
1629 tcg_temp_free(t0);
1630 }
1631
1632 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1633 {
1634 TCGv t0 = tcg_temp_new();
1635
1636 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1637 gen_store_spr(sprn, t0);
1638 tcg_temp_free(t0);
1639 }
1640
1641 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1642 {
1643 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1644 }
1645
1646 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1647 {
1648 TCGv_i32 t0 = tcg_const_i32(sprn);
1649 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1650 tcg_temp_free_i32(t0);
1651 }
1652 #endif
1653
1654 static void gen_spr_usprg3(CPUPPCState *env)
1655 {
1656 spr_register(env, SPR_USPRG3, "USPRG3",
1657 &spr_read_ureg, SPR_NOACCESS,
1658 &spr_read_ureg, SPR_NOACCESS,
1659 0x00000000);
1660 }
1661
1662 static void gen_spr_usprgh(CPUPPCState *env)
1663 {
1664 spr_register(env, SPR_USPRG4, "USPRG4",
1665 &spr_read_ureg, SPR_NOACCESS,
1666 &spr_read_ureg, SPR_NOACCESS,
1667 0x00000000);
1668 spr_register(env, SPR_USPRG5, "USPRG5",
1669 &spr_read_ureg, SPR_NOACCESS,
1670 &spr_read_ureg, SPR_NOACCESS,
1671 0x00000000);
1672 spr_register(env, SPR_USPRG6, "USPRG6",
1673 &spr_read_ureg, SPR_NOACCESS,
1674 &spr_read_ureg, SPR_NOACCESS,
1675 0x00000000);
1676 spr_register(env, SPR_USPRG7, "USPRG7",
1677 &spr_read_ureg, SPR_NOACCESS,
1678 &spr_read_ureg, SPR_NOACCESS,
1679 0x00000000);
1680 }
1681
1682 /* PowerPC BookE SPR */
1683 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1684 {
1685 const char *ivor_names[64] = {
1686 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1687 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1688 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1689 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1690 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1691 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1692 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1693 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1694 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1695 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1696 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1697 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1698 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1699 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1700 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1701 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1702 };
1703 #define SPR_BOOKE_IVORxx (-1)
1704 int ivor_sprn[64] = {
1705 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1706 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1707 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1708 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1709 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1710 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1711 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1712 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1713 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1714 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1715 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1716 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1717 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1718 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1719 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1720 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1721 };
1722 int i;
1723
1724 /* Interrupt processing */
1725 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, &spr_write_generic,
1728 0x00000000);
1729 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* Debug */
1734 /* XXX : not implemented */
1735 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
1739 /* XXX : not implemented */
1740 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744 /* XXX : not implemented */
1745 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749 /* XXX : not implemented */
1750 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
1754 /* XXX : not implemented */
1755 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_40x_dbcr0,
1758 0x00000000);
1759 /* XXX : not implemented */
1760 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764 /* XXX : not implemented */
1765 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769 /* XXX : not implemented */
1770 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_clear,
1773 0x00000000);
1774 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 spr_register(env, SPR_BOOKE_ESR, "ESR",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_excp_prefix,
1785 0x00000000);
1786 /* Exception vectors */
1787 for (i = 0; i < 64; i++) {
1788 if (ivor_mask & (1ULL << i)) {
1789 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1790 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1791 exit(1);
1792 }
1793 spr_register(env, ivor_sprn[i], ivor_names[i],
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_excp_vector,
1796 0x00000000);
1797 }
1798 }
1799 spr_register(env, SPR_BOOKE_PID, "PID",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_booke_pid,
1802 0x00000000);
1803 spr_register(env, SPR_BOOKE_TCR, "TCR",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_booke_tcr,
1806 0x00000000);
1807 spr_register(env, SPR_BOOKE_TSR, "TSR",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_booke_tsr,
1810 0x00000000);
1811 /* Timer */
1812 spr_register(env, SPR_DECR, "DECR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_decr, &spr_write_decr,
1815 0x00000000);
1816 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1817 SPR_NOACCESS, SPR_NOACCESS,
1818 SPR_NOACCESS, &spr_write_generic,
1819 0x00000000);
1820 /* SPRGs */
1821 spr_register(env, SPR_USPRG0, "USPRG0",
1822 &spr_read_generic, &spr_write_generic,
1823 &spr_read_generic, &spr_write_generic,
1824 0x00000000);
1825 spr_register(env, SPR_SPRG4, "SPRG4",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829 spr_register(env, SPR_SPRG5, "SPRG5",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1832 0x00000000);
1833 spr_register(env, SPR_SPRG6, "SPRG6",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 spr_register(env, SPR_SPRG7, "SPRG7",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 }
1842
1843 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1844 uint32_t maxsize, uint32_t flags,
1845 uint32_t nentries)
1846 {
1847 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1848 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1849 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1850 flags | nentries;
1851 }
1852
1853 /* BookE 2.06 storage control registers */
1854 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1855 uint32_t *tlbncfg, uint32_t mmucfg)
1856 {
1857 #if !defined(CONFIG_USER_ONLY)
1858 const char *mas_names[8] = {
1859 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1860 };
1861 int mas_sprn[8] = {
1862 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1863 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1864 };
1865 int i;
1866
1867 /* TLB assist registers */
1868 /* XXX : not implemented */
1869 for (i = 0; i < 8; i++) {
1870 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1871 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1872 uea_write = &spr_write_generic;
1873 }
1874 if (mas_mask & (1 << i)) {
1875 spr_register(env, mas_sprn[i], mas_names[i],
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_generic, uea_write,
1878 0x00000000);
1879 }
1880 }
1881 if (env->nb_pids > 1) {
1882 /* XXX : not implemented */
1883 spr_register(env, SPR_BOOKE_PID1, "PID1",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_booke_pid,
1886 0x00000000);
1887 }
1888 if (env->nb_pids > 2) {
1889 /* XXX : not implemented */
1890 spr_register(env, SPR_BOOKE_PID2, "PID2",
1891 SPR_NOACCESS, SPR_NOACCESS,
1892 &spr_read_generic, &spr_write_booke_pid,
1893 0x00000000);
1894 }
1895 /* XXX : not implemented */
1896 spr_register(env, SPR_MMUCFG, "MMUCFG",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, SPR_NOACCESS,
1899 mmucfg);
1900 switch (env->nb_ways) {
1901 case 4:
1902 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, SPR_NOACCESS,
1905 tlbncfg[3]);
1906 /* Fallthru */
1907 case 3:
1908 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, SPR_NOACCESS,
1911 tlbncfg[2]);
1912 /* Fallthru */
1913 case 2:
1914 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, SPR_NOACCESS,
1917 tlbncfg[1]);
1918 /* Fallthru */
1919 case 1:
1920 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, SPR_NOACCESS,
1923 tlbncfg[0]);
1924 /* Fallthru */
1925 case 0:
1926 default:
1927 break;
1928 }
1929 #endif
1930
1931 gen_spr_usprgh(env);
1932 }
1933
1934 /* SPR specific to PowerPC 440 implementation */
1935 static void gen_spr_440(CPUPPCState *env)
1936 {
1937 /* Cache control */
1938 /* XXX : not implemented */
1939 spr_register(env, SPR_440_DNV0, "DNV0",
1940 SPR_NOACCESS, SPR_NOACCESS,
1941 &spr_read_generic, &spr_write_generic,
1942 0x00000000);
1943 /* XXX : not implemented */
1944 spr_register(env, SPR_440_DNV1, "DNV1",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 &spr_read_generic, &spr_write_generic,
1947 0x00000000);
1948 /* XXX : not implemented */
1949 spr_register(env, SPR_440_DNV2, "DNV2",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953 /* XXX : not implemented */
1954 spr_register(env, SPR_440_DNV3, "DNV3",
1955 SPR_NOACCESS, SPR_NOACCESS,
1956 &spr_read_generic, &spr_write_generic,
1957 0x00000000);
1958 /* XXX : not implemented */
1959 spr_register(env, SPR_440_DTV0, "DTV0",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 &spr_read_generic, &spr_write_generic,
1962 0x00000000);
1963 /* XXX : not implemented */
1964 spr_register(env, SPR_440_DTV1, "DTV1",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_generic, &spr_write_generic,
1967 0x00000000);
1968 /* XXX : not implemented */
1969 spr_register(env, SPR_440_DTV2, "DTV2",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, &spr_write_generic,
1972 0x00000000);
1973 /* XXX : not implemented */
1974 spr_register(env, SPR_440_DTV3, "DTV3",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 /* XXX : not implemented */
1979 spr_register(env, SPR_440_DVLIM, "DVLIM",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_generic, &spr_write_generic,
1982 0x00000000);
1983 /* XXX : not implemented */
1984 spr_register(env, SPR_440_INV0, "INV0",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, &spr_write_generic,
1987 0x00000000);
1988 /* XXX : not implemented */
1989 spr_register(env, SPR_440_INV1, "INV1",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_generic,
1992 0x00000000);
1993 /* XXX : not implemented */
1994 spr_register(env, SPR_440_INV2, "INV2",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_generic,
1997 0x00000000);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_440_INV3, "INV3",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_440_ITV0, "ITV0",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* XXX : not implemented */
2009 spr_register(env, SPR_440_ITV1, "ITV1",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, &spr_write_generic,
2012 0x00000000);
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_440_ITV2, "ITV2",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_440_ITV3, "ITV3",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, &spr_write_generic,
2022 0x00000000);
2023 /* XXX : not implemented */
2024 spr_register(env, SPR_440_IVLIM, "IVLIM",
2025 SPR_NOACCESS, SPR_NOACCESS,
2026 &spr_read_generic, &spr_write_generic,
2027 0x00000000);
2028 /* Cache debug */
2029 /* XXX : not implemented */
2030 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, SPR_NOACCESS,
2033 0x00000000);
2034 /* XXX : not implemented */
2035 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, SPR_NOACCESS,
2038 0x00000000);
2039 /* XXX : not implemented */
2040 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, SPR_NOACCESS,
2043 0x00000000);
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, SPR_NOACCESS,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, SPR_NOACCESS,
2053 0x00000000);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_440_DBDR, "DBDR",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 /* Processor control */
2060 spr_register(env, SPR_4xx_CCR0, "CCR0",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, SPR_NOACCESS,
2067 0x00000000);
2068 /* Storage control */
2069 spr_register(env, SPR_440_MMUCR, "MMUCR",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_generic,
2072 0x00000000);
2073 }
2074
2075 /* SPR shared between PowerPC 40x implementations */
2076 static void gen_spr_40x(CPUPPCState *env)
2077 {
2078 /* Cache */
2079 /* not emulated, as QEMU do not emulate caches */
2080 spr_register(env, SPR_40x_DCCR, "DCCR",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 /* not emulated, as QEMU do not emulate caches */
2085 spr_register(env, SPR_40x_ICCR, "ICCR",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089 /* not emulated, as QEMU do not emulate caches */
2090 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, SPR_NOACCESS,
2093 0x00000000);
2094 /* Exception */
2095 spr_register(env, SPR_40x_DEAR, "DEAR",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
2099 spr_register(env, SPR_40x_ESR, "ESR",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2103 spr_register(env, SPR_40x_EVPR, "EVPR",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_excp_prefix,
2106 0x00000000);
2107 spr_register(env, SPR_40x_SRR2, "SRR2",
2108 &spr_read_generic, &spr_write_generic,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 spr_register(env, SPR_40x_SRR3, "SRR3",
2112 &spr_read_generic, &spr_write_generic,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115 /* Timers */
2116 spr_register(env, SPR_40x_PIT, "PIT",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_40x_pit, &spr_write_40x_pit,
2119 0x00000000);
2120 spr_register(env, SPR_40x_TCR, "TCR",
2121 SPR_NOACCESS, SPR_NOACCESS,
2122 &spr_read_generic, &spr_write_booke_tcr,
2123 0x00000000);
2124 spr_register(env, SPR_40x_TSR, "TSR",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_booke_tsr,
2127 0x00000000);
2128 }
2129
2130 /* SPR specific to PowerPC 405 implementation */
2131 static void gen_spr_405(CPUPPCState *env)
2132 {
2133 /* MMU */
2134 spr_register(env, SPR_40x_PID, "PID",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 spr_register(env, SPR_4xx_CCR0, "CCR0",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00700000);
2142 /* Debug interface */
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, &spr_write_40x_dbcr0,
2147 0x00000000);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_405_DBCR1, "DBCR1",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_generic,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_40x_DBSR, "DBSR",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_clear,
2157 /* Last reset was system reset */
2158 0x00000300);
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_40x_DAC1, "DAC1",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 spr_register(env, SPR_40x_DAC2, "DAC2",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_405_DVC1, "DVC1",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_405_DVC2, "DVC2",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_40x_IAC1, "IAC1",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183 spr_register(env, SPR_40x_IAC2, "IAC2",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_405_IAC3, "IAC3",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_405_IAC4, "IAC4",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 /* Storage control */
2198 /* XXX: TODO: not implemented */
2199 spr_register(env, SPR_405_SLER, "SLER",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_40x_sler,
2202 0x00000000);
2203 spr_register(env, SPR_40x_ZPR, "ZPR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_405_SU0R, "SU0R",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* SPRG */
2213 spr_register(env, SPR_USPRG0, "USPRG0",
2214 &spr_read_ureg, SPR_NOACCESS,
2215 &spr_read_ureg, SPR_NOACCESS,
2216 0x00000000);
2217 spr_register(env, SPR_SPRG4, "SPRG4",
2218 SPR_NOACCESS, SPR_NOACCESS,
2219 &spr_read_generic, &spr_write_generic,
2220 0x00000000);
2221 spr_register(env, SPR_SPRG5, "SPRG5",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 spr_read_generic, &spr_write_generic,
2224 0x00000000);
2225 spr_register(env, SPR_SPRG6, "SPRG6",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 spr_read_generic, &spr_write_generic,
2228 0x00000000);
2229 spr_register(env, SPR_SPRG7, "SPRG7",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 gen_spr_usprgh(env);
2234 }
2235
2236 /* SPR shared between PowerPC 401 & 403 implementations */
2237 static void gen_spr_401_403(CPUPPCState *env)
2238 {
2239 /* Time base */
2240 spr_register(env, SPR_403_VTBL, "TBL",
2241 &spr_read_tbl, SPR_NOACCESS,
2242 &spr_read_tbl, SPR_NOACCESS,
2243 0x00000000);
2244 spr_register(env, SPR_403_TBL, "TBL",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 SPR_NOACCESS, &spr_write_tbl,
2247 0x00000000);
2248 spr_register(env, SPR_403_VTBU, "TBU",
2249 &spr_read_tbu, SPR_NOACCESS,
2250 &spr_read_tbu, SPR_NOACCESS,
2251 0x00000000);
2252 spr_register(env, SPR_403_TBU, "TBU",
2253 SPR_NOACCESS, SPR_NOACCESS,
2254 SPR_NOACCESS, &spr_write_tbu,
2255 0x00000000);
2256 /* Debug */
2257 /* not emulated, as QEMU do not emulate caches */
2258 spr_register(env, SPR_403_CDBCR, "CDBCR",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 }
2263
2264 /* SPR specific to PowerPC 401 implementation */
2265 static void gen_spr_401(CPUPPCState *env)
2266 {
2267 /* Debug interface */
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_40x_DBCR0, "DBCR",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_40x_dbcr0,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_40x_DBSR, "DBSR",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_clear,
2277 /* Last reset was system reset */
2278 0x00000300);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_40x_DAC1, "DAC",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_40x_IAC1, "IAC",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* Storage control */
2290 /* XXX: TODO: not implemented */
2291 spr_register(env, SPR_405_SLER, "SLER",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_40x_sler,
2294 0x00000000);
2295 /* not emulated, as QEMU never does speculative access */
2296 spr_register(env, SPR_40x_SGR, "SGR",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_generic, &spr_write_generic,
2299 0xFFFFFFFF);
2300 /* not emulated, as QEMU do not emulate caches */
2301 spr_register(env, SPR_40x_DCWR, "DCWR",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 }
2306
2307 static void gen_spr_401x2(CPUPPCState *env)
2308 {
2309 gen_spr_401(env);
2310 spr_register(env, SPR_40x_PID, "PID",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 spr_register(env, SPR_40x_ZPR, "ZPR",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 }
2319
2320 /* SPR specific to PowerPC 403 implementation */
2321 static void gen_spr_403(CPUPPCState *env)
2322 {
2323 /* Debug interface */
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_40x_dbcr0,
2328 0x00000000);
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_40x_DBSR, "DBSR",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_clear,
2333 /* Last reset was system reset */
2334 0x00000300);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_40x_DAC1, "DAC1",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_40x_DAC2, "DAC2",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_40x_IAC1, "IAC1",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_40x_IAC2, "IAC2",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 }
2356
2357 static void gen_spr_403_real(CPUPPCState *env)
2358 {
2359 spr_register(env, SPR_403_PBL1, "PBL1",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_403_pbr, &spr_write_403_pbr,
2362 0x00000000);
2363 spr_register(env, SPR_403_PBU1, "PBU1",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_403_pbr, &spr_write_403_pbr,
2366 0x00000000);
2367 spr_register(env, SPR_403_PBL2, "PBL2",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_403_pbr, &spr_write_403_pbr,
2370 0x00000000);
2371 spr_register(env, SPR_403_PBU2, "PBU2",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_403_pbr, &spr_write_403_pbr,
2374 0x00000000);
2375 }
2376
2377 static void gen_spr_403_mmu(CPUPPCState *env)
2378 {
2379 /* MMU */
2380 spr_register(env, SPR_40x_PID, "PID",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 spr_register(env, SPR_40x_ZPR, "ZPR",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 }
2389
2390 /* SPR specific to PowerPC compression coprocessor extension */
2391 static void gen_spr_compress(CPUPPCState *env)
2392 {
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_401_SKR, "SKR",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 }
2399
2400 static void gen_spr_5xx_8xx(CPUPPCState *env)
2401 {
2402 /* Exception processing */
2403 spr_register_kvm(env, SPR_DSISR, "DSISR",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 KVM_REG_PPC_DSISR, 0x00000000);
2407 spr_register_kvm(env, SPR_DAR, "DAR",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 KVM_REG_PPC_DAR, 0x00000000);
2411 /* Timer */
2412 spr_register(env, SPR_DECR, "DECR",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_decr, &spr_write_decr,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_MPC_EIE, "EIE",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_MPC_EID, "EID",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_MPC_NRI, "NRI",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_MPC_CMPA, "CMPA",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_MPC_CMPB, "CMPB",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_MPC_CMPC, "CMPC",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_MPC_CMPD, "CMPD",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_MPC_ECR, "ECR",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_MPC_DER, "DER",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_MPC_CMPE, "CMPE",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_MPC_CMPF, "CMPF",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_MPC_CMPG, "CMPG",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_MPC_CMPH, "CMPH",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_MPC_BAR, "BAR",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_MPC_DPDR, "DPDR",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_MPC_IMMR, "IMMR",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 }
2517
2518 static void gen_spr_5xx(CPUPPCState *env)
2519 {
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 }
2626
2627 static void gen_spr_8xx(CPUPPCState *env)
2628 {
2629 /* XXX : not implemented */
2630 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2631 SPR_NOACCESS, SPR_NOACCESS,
2632 &spr_read_generic, &spr_write_generic,
2633 0x00000000);
2634 /* XXX : not implemented */
2635 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2636 SPR_NOACCESS, SPR_NOACCESS,
2637 &spr_read_generic, &spr_write_generic,
2638 0x00000000);
2639 /* XXX : not implemented */
2640 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2641 SPR_NOACCESS, SPR_NOACCESS,
2642 &spr_read_generic, &spr_write_generic,
2643 0x00000000);
2644 /* XXX : not implemented */
2645 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2646 SPR_NOACCESS, SPR_NOACCESS,
2647 &spr_read_generic, &spr_write_generic,
2648 0x00000000);
2649 /* XXX : not implemented */
2650 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2651 SPR_NOACCESS, SPR_NOACCESS,
2652 &spr_read_generic, &spr_write_generic,
2653 0x00000000);
2654 /* XXX : not implemented */
2655 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2656 SPR_NOACCESS, SPR_NOACCESS,
2657 &spr_read_generic, &spr_write_generic,
2658 0x00000000);
2659 /* XXX : not implemented */
2660 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2661 SPR_NOACCESS, SPR_NOACCESS,
2662 &spr_read_generic, &spr_write_generic,
2663 0x00000000);
2664 /* XXX : not implemented */
2665 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2666 SPR_NOACCESS, SPR_NOACCESS,
2667 &spr_read_generic, &spr_write_generic,
2668 0x00000000);
2669 /* XXX : not implemented */
2670 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2671 SPR_NOACCESS, SPR_NOACCESS,
2672 &spr_read_generic, &spr_write_generic,
2673 0x00000000);
2674 /* XXX : not implemented */
2675 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2676 SPR_NOACCESS, SPR_NOACCESS,
2677 &spr_read_generic, &spr_write_generic,
2678 0x00000000);
2679 /* XXX : not implemented */
2680 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2681 SPR_NOACCESS, SPR_NOACCESS,
2682 &spr_read_generic, &spr_write_generic,
2683 0x00000000);
2684 /* XXX : not implemented */
2685 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2686 SPR_NOACCESS, SPR_NOACCESS,
2687 &spr_read_generic, &spr_write_generic,
2688 0x00000000);
2689 /* XXX : not implemented */
2690 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2691 SPR_NOACCESS, SPR_NOACCESS,
2692 &spr_read_generic, &spr_write_generic,
2693 0x00000000);
2694 /* XXX : not implemented */
2695 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2696 SPR_NOACCESS, SPR_NOACCESS,
2697 &spr_read_generic, &spr_write_generic,
2698 0x00000000);
2699 /* XXX : not implemented */
2700 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2701 SPR_NOACCESS, SPR_NOACCESS,
2702 &spr_read_generic, &spr_write_generic,
2703 0x00000000);
2704 /* XXX : not implemented */
2705 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2706 SPR_NOACCESS, SPR_NOACCESS,
2707 &spr_read_generic, &spr_write_generic,
2708 0x00000000);
2709 /* XXX : not implemented */
2710 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2711 SPR_NOACCESS, SPR_NOACCESS,
2712 &spr_read_generic, &spr_write_generic,
2713 0x00000000);
2714 /* XXX : not implemented */
2715 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2716 SPR_NOACCESS, SPR_NOACCESS,
2717 &spr_read_generic, &spr_write_generic,
2718 0x00000000);
2719 /* XXX : not implemented */
2720 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2721 SPR_NOACCESS, SPR_NOACCESS,
2722 &spr_read_generic, &spr_write_generic,
2723 0x00000000);
2724 /* XXX : not implemented */
2725 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2726 SPR_NOACCESS, SPR_NOACCESS,
2727 &spr_read_generic, &spr_write_generic,
2728 0x00000000);
2729 /* XXX : not implemented */
2730 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2731 SPR_NOACCESS, SPR_NOACCESS,
2732 &spr_read_generic, &spr_write_generic,
2733 0x00000000);
2734 /* XXX : not implemented */
2735 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2736 SPR_NOACCESS, SPR_NOACCESS,
2737 &spr_read_generic, &spr_write_generic,
2738 0x00000000);
2739 /* XXX : not implemented */
2740 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2741 SPR_NOACCESS, SPR_NOACCESS,
2742 &spr_read_generic, &spr_write_generic,
2743 0x00000000);
2744 /* XXX : not implemented */
2745 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2746 SPR_NOACCESS, SPR_NOACCESS,
2747 &spr_read_generic, &spr_write_generic,
2748 0x00000000);
2749 /* XXX : not implemented */
2750 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2751 SPR_NOACCESS, SPR_NOACCESS,
2752 &spr_read_generic, &spr_write_generic,
2753 0x00000000);
2754 }
2755
2756 // XXX: TODO
2757 /*
2758 * AMR => SPR 29 (Power 2.04)
2759 * CTRL => SPR 136 (Power 2.04)
2760 * CTRL => SPR 152 (Power 2.04)
2761 * SCOMC => SPR 276 (64 bits ?)
2762 * SCOMD => SPR 277 (64 bits ?)
2763 * TBU40 => SPR 286 (Power 2.04 hypv)
2764 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2765 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2766 * HDSISR => SPR 306 (Power 2.04 hypv)
2767 * HDAR => SPR 307 (Power 2.04 hypv)
2768 * PURR => SPR 309 (Power 2.04 hypv)
2769 * HDEC => SPR 310 (Power 2.04 hypv)
2770 * HIOR => SPR 311 (hypv)
2771 * RMOR => SPR 312 (970)
2772 * HRMOR => SPR 313 (Power 2.04 hypv)
2773 * HSRR0 => SPR 314 (Power 2.04 hypv)
2774 * HSRR1 => SPR 315 (Power 2.04 hypv)
2775 * LPIDR => SPR 317 (970)
2776 * EPR => SPR 702 (Power 2.04 emb)
2777 * perf => 768-783 (Power 2.04)
2778 * perf => 784-799 (Power 2.04)
2779 * PPR => SPR 896 (Power 2.04)
2780 * EPLC => SPR 947 (Power 2.04 emb)
2781 * EPSC => SPR 948 (Power 2.04 emb)
2782 * DABRX => 1015 (Power 2.04 hypv)
2783 * FPECR => SPR 1022 (?)
2784 * ... and more (thermal management, performance counters, ...)
2785 */
2786
2787 /*****************************************************************************/
2788 /* Exception vectors models */
2789 static void init_excp_4xx_real(CPUPPCState *env)
2790 {
2791 #if !defined(CONFIG_USER_ONLY)
2792 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2793 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2794 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2795 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2796 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2797 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2798 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2799 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2800 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2801 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2802 env->ivor_mask = 0x0000FFF0UL;
2803 env->ivpr_mask = 0xFFFF0000UL;
2804 /* Hardware reset vector */
2805 env->hreset_vector = 0xFFFFFFFCUL;
2806 #endif
2807 }
2808
2809 static void init_excp_4xx_softmmu(CPUPPCState *env)
2810 {
2811 #if !defined(CONFIG_USER_ONLY)
2812 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2813 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2814 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2815 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2816 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2817 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2818 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2820 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2821 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2822 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2823 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2824 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2825 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2826 env->ivor_mask = 0x0000FFF0UL;
2827 env->ivpr_mask = 0xFFFF0000UL;
2828 /* Hardware reset vector */
2829 env->hreset_vector = 0xFFFFFFFCUL;
2830 #endif
2831 }
2832
2833 static void init_excp_MPC5xx(CPUPPCState *env)
2834 {
2835 #if !defined(CONFIG_USER_ONLY)
2836 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2837 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2838 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2839 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2840 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2841 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2842 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2844 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2845 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2846 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2847 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2848 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2849 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2850 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2851 env->ivor_mask = 0x0000FFF0UL;
2852 env->ivpr_mask = 0xFFFF0000UL;
2853 /* Hardware reset vector */
2854 env->hreset_vector = 0x00000100UL;
2855 #endif
2856 }
2857
2858 static void init_excp_MPC8xx(CPUPPCState *env)
2859 {
2860 #if !defined(CONFIG_USER_ONLY)
2861 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2862 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2863 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2864 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2865 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2866 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2867 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2868 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2869 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2870 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2871 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2872 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2873 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2874 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2875 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2876 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2877 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2878 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2879 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2880 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2881 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2882 env->ivor_mask = 0x0000FFF0UL;
2883 env->ivpr_mask = 0xFFFF0000UL;
2884 /* Hardware reset vector */
2885 env->hreset_vector = 0x00000100UL;
2886 #endif
2887 }
2888
2889 static void init_excp_G2(CPUPPCState *env)
2890 {
2891 #if !defined(CONFIG_USER_ONLY)
2892 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2893 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2894 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2895 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2896 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2897 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2898 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2899 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2900 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2901 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2902 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2903 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2904 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2905 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2906 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2907 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2908 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2909 /* Hardware reset vector */
2910 env->hreset_vector = 0x00000100UL;
2911 #endif
2912 }
2913
2914 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2915 {
2916 #if !defined(CONFIG_USER_ONLY)
2917 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2918 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2919 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2920 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2921 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2922 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2923 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2924 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2925 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2926 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2927 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2928 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2929 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2930 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2931 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2932 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2933 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2934 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2935 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2936 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2937 env->ivor_mask = 0x0000FFF7UL;
2938 env->ivpr_mask = ivpr_mask;
2939 /* Hardware reset vector */
2940 env->hreset_vector = 0xFFFFFFFCUL;
2941 #endif
2942 }
2943
2944 static void init_excp_BookE(CPUPPCState *env)
2945 {
2946 #if !defined(CONFIG_USER_ONLY)
2947 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2948 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2949 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2950 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2951 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2952 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2953 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2954 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2955 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2956 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2957 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2958 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2959 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2960 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2961 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2962 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2963 env->ivor_mask = 0x0000FFF0UL;
2964 env->ivpr_mask = 0xFFFF0000UL;
2965 /* Hardware reset vector */
2966 env->hreset_vector = 0xFFFFFFFCUL;
2967 #endif
2968 }
2969
2970 static void init_excp_601(CPUPPCState *env)
2971 {
2972 #if !defined(CONFIG_USER_ONLY)
2973 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2974 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2975 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2976 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2977 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2978 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2979 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2980 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2981 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2982 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2983 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2984 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2985 /* Hardware reset vector */
2986 env->hreset_vector = 0x00000100UL;
2987 #endif
2988 }
2989
2990 static void init_excp_602(CPUPPCState *env)
2991 {
2992 #if !defined(CONFIG_USER_ONLY)
2993 /* XXX: exception prefix has a special behavior on 602 */
2994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3005 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3006 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3007 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3008 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3009 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3010 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
3011 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
3012 /* Hardware reset vector */
3013 env->hreset_vector = 0x00000100UL;
3014 #endif
3015 }
3016
3017 static void init_excp_603(CPUPPCState *env)
3018 {
3019 #if !defined(CONFIG_USER_ONLY)
3020 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3021 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3022 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3023 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3024 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3025 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3026 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3027 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3028 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3029 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3030 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3031 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3032 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3033 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3034 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3035 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3036 /* Hardware reset vector */
3037 env->hreset_vector = 0x00000100UL;
3038 #endif
3039 }
3040
3041 static void init_excp_604(CPUPPCState *env)
3042 {
3043 #if !defined(CONFIG_USER_ONLY)
3044 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3045 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3046 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3047 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3048 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3049 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3050 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3051 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3052 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3053 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3054 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3055 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3056 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3057 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3058 /* Hardware reset vector */
3059 env->hreset_vector = 0x00000100UL;
3060 #endif
3061 }
3062
3063 static void init_excp_7x0(CPUPPCState *env)
3064 {
3065 #if !defined(CONFIG_USER_ONLY)
3066 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3067 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3068 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3069 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3070 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3071 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3072 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3073 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3074 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3075 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3076 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3077 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3078 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3079 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3080 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3081 /* Hardware reset vector */
3082 env->hreset_vector = 0x00000100UL;
3083 #endif
3084 }
3085
3086 static void init_excp_750cl(CPUPPCState *env)
3087 {
3088 #if !defined(CONFIG_USER_ONLY)
3089 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3090 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3091 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3092 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3093 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3094 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3095 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3096 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3097 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3098 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3099 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3100 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 /* Hardware reset vector */
3104 env->hreset_vector = 0x00000100UL;
3105 #endif
3106 }
3107
3108 static void init_excp_750cx(CPUPPCState *env)
3109 {
3110 #if !defined(CONFIG_USER_ONLY)
3111 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3112 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3113 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3114 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3115 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3116 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3117 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3118 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3119 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3120 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3121 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3122 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3123 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3124 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3125 /* Hardware reset vector */
3126 env->hreset_vector = 0x00000100UL;
3127 #endif
3128 }
3129
3130 /* XXX: Check if this is correct */
3131 static void init_excp_7x5(CPUPPCState *env)
3132 {
3133 #if !defined(CONFIG_USER_ONLY)
3134 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3135 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3136 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3137 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3138 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3139 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3140 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3141 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3142 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3143 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3144 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3145 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3146 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3147 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3148 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3149 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3150 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3151 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3152 /* Hardware reset vector */
3153 env->hreset_vector = 0x00000100UL;
3154 #endif
3155 }
3156
3157 static void init_excp_7400(CPUPPCState *env)
3158 {
3159 #if !defined(CONFIG_USER_ONLY)
3160 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3161 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3162 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3163 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3164 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3165 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3166 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3167 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3168 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3169 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3170 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3171 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3172 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3173 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3174 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3175 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3176 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3177 /* Hardware reset vector */
3178 env->hreset_vector = 0x00000100UL;
3179 #endif
3180 }
3181
3182 static void init_excp_7450(CPUPPCState *env)
3183 {
3184 #if !defined(CONFIG_USER_ONLY)
3185 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3186 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3187 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3188 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3189 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3190 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3191 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3192 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3193 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3194 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3195 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3196 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3197 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3198 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3199 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3200 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3201 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3202 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3203 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3204 /* Hardware reset vector */
3205 env->hreset_vector = 0x00000100UL;
3206 #endif
3207 }
3208
3209 #if defined(TARGET_PPC64)
3210 static void init_excp_970(CPUPPCState *env)
3211 {
3212 #if !defined(CONFIG_USER_ONLY)
3213 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3214 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3215 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3216 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3217 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3218 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3219 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3220 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3221 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3222 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3223 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3224 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3225 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3226 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3227 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3228 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3229 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3230 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3231 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3232 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3233 /* Hardware reset vector */
3234 env->hreset_vector = 0x0000000000000100ULL;
3235 #endif
3236 }
3237
3238 static void init_excp_POWER7(CPUPPCState *env)
3239 {
3240 #if !defined(CONFIG_USER_ONLY)
3241 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3242 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3243 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3244 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3245 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3246 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3247 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3248 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3249 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3250 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3251 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3252 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3253 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3254 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3255 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
3256 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
3257 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
3258 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3259 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3260 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3261 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3262 /* Hardware reset vector */
3263 env->hreset_vector = 0x0000000000000100ULL;
3264 #endif
3265 }
3266
3267 static void init_excp_POWER8(CPUPPCState *env)
3268 {
3269 init_excp_POWER7(env);
3270
3271 #if !defined(CONFIG_USER_ONLY)
3272 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
3273 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3274 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
3275 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3276 #endif
3277 }
3278
3279 #endif
3280
3281 /*****************************************************************************/
3282 /* Power management enable checks */
3283 static int check_pow_none(CPUPPCState *env)
3284 {
3285 return 0;
3286 }
3287
3288 static int check_pow_nocheck(CPUPPCState *env)
3289 {
3290 return 1;
3291 }
3292
3293 static int check_pow_hid0(CPUPPCState *env)
3294 {
3295 if (env->spr[SPR_HID0] & 0x00E00000)
3296 return 1;
3297
3298 return 0;
3299 }
3300
3301 static int check_pow_hid0_74xx(CPUPPCState *env)
3302 {
3303 if (env->spr[SPR_HID0] & 0x00600000)
3304 return 1;
3305
3306 return 0;
3307 }
3308
3309 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3310 {
3311 return true;
3312 }
3313
3314 #ifdef TARGET_PPC64
3315 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3316 {
3317 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3318 }
3319 #endif
3320
3321 /*****************************************************************************/
3322 /* PowerPC implementations definitions */
3323
3324 #define POWERPC_FAMILY(_name) \
3325 static void \
3326 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3327 \
3328 static const TypeInfo \
3329 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3330 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3331 .parent = TYPE_POWERPC_CPU, \
3332 .abstract = true, \
3333 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3334 }; \
3335 \
3336 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3337 { \
3338 type_register_static( \
3339 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3340 } \
3341 \
3342 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3343 \
3344 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3345
3346 static void init_proc_401(CPUPPCState *env)
3347 {
3348 gen_spr_40x(env);
3349 gen_spr_401_403(env);
3350 gen_spr_401(env);
3351 init_excp_4xx_real(env);
3352 env->dcache_line_size = 32;
3353 env->icache_line_size = 32;
3354 /* Allocate hardware IRQ controller */
3355 ppc40x_irq_init(ppc_env_get_cpu(env));
3356
3357 SET_FIT_PERIOD(12, 16, 20, 24);
3358 SET_WDT_PERIOD(16, 20, 24, 28);
3359 }
3360
3361 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3362 {
3363 DeviceClass *dc = DEVICE_CLASS(oc);
3364 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3365
3366 dc->desc = "PowerPC 401";
3367 pcc->init_proc = init_proc_401;
3368 pcc->check_pow = check_pow_nocheck;
3369 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3370 PPC_WRTEE | PPC_DCR |
3371 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3372 PPC_CACHE_DCBZ |
3373 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3374 PPC_4xx_COMMON | PPC_40x_EXCP;
3375 pcc->msr_mask = (1ull << MSR_KEY) |
3376 (1ull << MSR_POW) |
3377 (1ull << MSR_CE) |
3378 (1ull << MSR_ILE) |
3379 (1ull << MSR_EE) |
3380 (1ull << MSR_PR) |
3381 (1ull << MSR_ME) |
3382 (1ull << MSR_DE) |
3383 (1ull << MSR_LE);
3384 pcc->mmu_model = POWERPC_MMU_REAL;
3385 pcc->excp_model = POWERPC_EXCP_40x;
3386 pcc->bus_model = PPC_FLAGS_INPUT_401;
3387 pcc->bfd_mach = bfd_mach_ppc_403;
3388 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3389 POWERPC_FLAG_BUS_CLK;
3390 }
3391
3392 static void init_proc_401x2(CPUPPCState *env)
3393 {
3394 gen_spr_40x(env);
3395 gen_spr_401_403(env);
3396 gen_spr_401x2(env);
3397 gen_spr_compress(env);
3398 /* Memory management */
3399 #if !defined(CONFIG_USER_ONLY)
3400 env->nb_tlb = 64;
3401 env->nb_ways = 1;
3402 env->id_tlbs = 0;
3403 env->tlb_type = TLB_EMB;
3404 #endif
3405 init_excp_4xx_softmmu(env);
3406 env->dcache_line_size = 32;
3407 env->icache_line_size = 32;
3408 /* Allocate hardware IRQ controller */
3409 ppc40x_irq_init(ppc_env_get_cpu(env));
3410
3411 SET_FIT_PERIOD(12, 16, 20, 24);
3412 SET_WDT_PERIOD(16, 20, 24, 28);
3413 }
3414
3415 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3416 {
3417 DeviceClass *dc = DEVICE_CLASS(oc);
3418 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3419
3420 dc->desc = "PowerPC 401x2";
3421 pcc->init_proc = init_proc_401x2;
3422 pcc->check_pow = check_pow_nocheck;
3423 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3424 PPC_DCR | PPC_WRTEE |
3425 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3426 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3427 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3428 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3429 PPC_4xx_COMMON | PPC_40x_EXCP;
3430 pcc->msr_mask = (1ull << 20) |
3431 (1ull << MSR_KEY) |
3432 (1ull << MSR_POW) |
3433 (1ull << MSR_CE) |
3434 (1ull << MSR_ILE) |
3435 (1ull << MSR_EE) |
3436 (1ull << MSR_PR) |
3437 (1ull << MSR_ME) |
3438 (1ull << MSR_DE) |
3439 (1ull << MSR_IR) |
3440 (1ull << MSR_DR) |
3441 (1ull << MSR_LE);
3442 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3443 pcc->excp_model = POWERPC_EXCP_40x;
3444 pcc->bus_model = PPC_FLAGS_INPUT_401;
3445 pcc->bfd_mach = bfd_mach_ppc_403;
3446 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3447 POWERPC_FLAG_BUS_CLK;
3448 }
3449
3450 static void init_proc_401x3(CPUPPCState *env)
3451 {
3452 gen_spr_40x(env);
3453 gen_spr_401_403(env);
3454 gen_spr_401(env);
3455 gen_spr_401x2(env);
3456 gen_spr_compress(env);
3457 init_excp_4xx_softmmu(env);
3458 env->dcache_line_size = 32;
3459 env->icache_line_size = 32;
3460 /* Allocate hardware IRQ controller */
3461 ppc40x_irq_init(ppc_env_get_cpu(env));
3462
3463 SET_FIT_PERIOD(12, 16, 20, 24);
3464 SET_WDT_PERIOD(16, 20, 24, 28);
3465 }
3466
3467 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3468 {
3469 DeviceClass *dc = DEVICE_CLASS(oc);
3470 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3471
3472 dc->desc = "PowerPC 401x3";
3473 pcc->init_proc = init_proc_401x3;
3474 pcc->check_pow = check_pow_nocheck;
3475 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3476 PPC_DCR | PPC_WRTEE |
3477 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3478 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3479 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3480 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3481 PPC_4xx_COMMON | PPC_40x_EXCP;
3482 pcc->msr_mask = (1ull << 20) |
3483 (1ull << MSR_KEY) |
3484 (1ull << MSR_POW) |
3485 (1ull << MSR_CE) |
3486 (1ull << MSR_ILE) |
3487 (1ull << MSR_EE) |
3488 (1ull << MSR_PR) |
3489 (1ull << MSR_ME) |
3490 (1ull << MSR_DWE) |
3491 (1ull << MSR_DE) |
3492 (1ull << MSR_IR) |
3493 (1ull << MSR_DR) |
3494 (1ull << MSR_LE);
3495 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3496 pcc->excp_model = POWERPC_EXCP_40x;
3497 pcc->bus_model = PPC_FLAGS_INPUT_401;
3498 pcc->bfd_mach = bfd_mach_ppc_403;
3499 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3500 POWERPC_FLAG_BUS_CLK;
3501 }
3502
3503 static void init_proc_IOP480(CPUPPCState *env)
3504 {
3505 gen_spr_40x(env);
3506 gen_spr_401_403(env);
3507 gen_spr_401x2(env);
3508 gen_spr_compress(env);
3509 /* Memory management */
3510 #if !defined(CONFIG_USER_ONLY)
3511 env->nb_tlb = 64;
3512 env->nb_ways = 1;
3513 env->id_tlbs = 0;
3514 env->tlb_type = TLB_EMB;
3515 #endif
3516 init_excp_4xx_softmmu(env);
3517 env->dcache_line_size = 32;
3518 env->icache_line_size = 32;
3519 /* Allocate hardware IRQ controller */
3520 ppc40x_irq_init(ppc_env_get_cpu(env));
3521
3522 SET_FIT_PERIOD(8, 12, 16, 20);
3523 SET_WDT_PERIOD(16, 20, 24, 28);
3524 }
3525
3526 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3527 {
3528 DeviceClass *dc = DEVICE_CLASS(oc);
3529 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3530
3531 dc->desc = "IOP480";
3532 pcc->init_proc = init_proc_IOP480;
3533 pcc->check_pow = check_pow_nocheck;
3534 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3535 PPC_DCR | PPC_WRTEE |
3536 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3537 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3538 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3539 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3540 PPC_4xx_COMMON | PPC_40x_EXCP;
3541 pcc->msr_mask = (1ull << 20) |
3542 (1ull << MSR_KEY) |
3543 (1ull << MSR_POW) |
3544 (1ull << MSR_CE) |
3545 (1ull << MSR_ILE) |
3546 (1ull << MSR_EE) |
3547 (1ull << MSR_PR) |
3548 (1ull << MSR_ME) |
3549 (1ull << MSR_DE) |
3550 (1ull << MSR_IR) |
3551 (1ull << MSR_DR) |
3552 (1ull << MSR_LE);
3553 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3554 pcc->excp_model = POWERPC_EXCP_40x;
3555 pcc->bus_model = PPC_FLAGS_INPUT_401;
3556 pcc->bfd_mach = bfd_mach_ppc_403;
3557 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3558 POWERPC_FLAG_BUS_CLK;
3559 }
3560
3561 static void init_proc_403(CPUPPCState *env)
3562 {
3563 gen_spr_40x(env);
3564 gen_spr_401_403(env);
3565 gen_spr_403(env);
3566 gen_spr_403_real(env);
3567 init_excp_4xx_real(env);
3568 env->dcache_line_size = 32;
3569 env->icache_line_size = 32;
3570 /* Allocate hardware IRQ controller */
3571 ppc40x_irq_init(ppc_env_get_cpu(env));
3572
3573 SET_FIT_PERIOD(8, 12, 16, 20);
3574 SET_WDT_PERIOD(16, 20, 24, 28);
3575 }
3576
3577 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3578 {
3579 DeviceClass *dc = DEVICE_CLASS(oc);
3580 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3581
3582 dc->desc = "PowerPC 403";
3583 pcc->init_proc = init_proc_403;
3584 pcc->check_pow = check_pow_nocheck;
3585 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3586 PPC_DCR | PPC_WRTEE |
3587 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3588 PPC_CACHE_DCBZ |
3589 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3590 PPC_4xx_COMMON | PPC_40x_EXCP;
3591 pcc->msr_mask = (1ull << MSR_POW) |
3592 (1ull << MSR_CE) |
3593 (1ull << MSR_ILE) |
3594 (1ull << MSR_EE) |
3595 (1ull << MSR_PR) |
3596 (1ull << MSR_ME) |
3597 (1ull << MSR_PE) |
3598 (1ull << MSR_PX) |
3599 (1ull << MSR_LE);
3600 pcc->mmu_model = POWERPC_MMU_REAL;
3601 pcc->excp_model = POWERPC_EXCP_40x;
3602 pcc->bus_model = PPC_FLAGS_INPUT_401;
3603 pcc->bfd_mach = bfd_mach_ppc_403;
3604 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3605 POWERPC_FLAG_BUS_CLK;
3606 }
3607
3608 static void init_proc_403GCX(CPUPPCState *env)
3609 {
3610 gen_spr_40x(env);
3611 gen_spr_401_403(env);
3612 gen_spr_403(env);
3613 gen_spr_403_real(env);
3614 gen_spr_403_mmu(env);
3615 /* Bus access control */
3616 /* not emulated, as QEMU never does speculative access */
3617 spr_register(env, SPR_40x_SGR, "SGR",
3618 SPR_NOACCESS, SPR_NOACCESS,
3619 &spr_read_generic, &spr_write_generic,
3620 0xFFFFFFFF);
3621 /* not emulated, as QEMU do not emulate caches */
3622 spr_register(env, SPR_40x_DCWR, "DCWR",
3623 SPR_NOACCESS, SPR_NOACCESS,
3624 &spr_read_generic, &spr_write_generic,
3625 0x00000000);
3626 /* Memory management */
3627 #if !defined(CONFIG_USER_ONLY)
3628 env->nb_tlb = 64;
3629 env->nb_ways = 1;
3630 env->id_tlbs = 0;
3631 env->tlb_type = TLB_EMB;
3632 #endif
3633 init_excp_4xx_softmmu(env);
3634 env->dcache_line_size = 32;
3635 env->icache_line_size = 32;
3636 /* Allocate hardware IRQ controller */
3637 ppc40x_irq_init(ppc_env_get_cpu(env));
3638
3639 SET_FIT_PERIOD(8, 12, 16, 20);
3640 SET_WDT_PERIOD(16, 20, 24, 28);
3641 }
3642
3643 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3644 {
3645 DeviceClass *dc = DEVICE_CLASS(oc);
3646 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3647
3648 dc->desc = "PowerPC 403 GCX";
3649 pcc->init_proc = init_proc_403GCX;
3650 pcc->check_pow = check_pow_nocheck;
3651 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3652 PPC_DCR | PPC_WRTEE |
3653 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3654 PPC_CACHE_DCBZ |
3655 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3656 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3657 PPC_4xx_COMMON | PPC_40x_EXCP;
3658 pcc->msr_mask = (1ull << MSR_POW) |
3659 (1ull << MSR_CE) |
3660 (1ull << MSR_ILE) |
3661 (1ull << MSR_EE) |
3662 (1ull << MSR_PR) |
3663 (1ull << MSR_ME) |
3664 (1ull << MSR_PE) |
3665 (1ull << MSR_PX) |
3666 (1ull << MSR_LE);
3667 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3668 pcc->excp_model = POWERPC_EXCP_40x;
3669 pcc->bus_model = PPC_FLAGS_INPUT_401;
3670 pcc->bfd_mach = bfd_mach_ppc_403;
3671 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3672 POWERPC_FLAG_BUS_CLK;
3673 }
3674
3675 static void init_proc_405(CPUPPCState *env)
3676 {
3677 /* Time base */
3678 gen_tbl(env);
3679 gen_spr_40x(env);
3680 gen_spr_405(env);
3681 /* Bus access control */
3682 /* not emulated, as QEMU never does speculative access */
3683 spr_register(env, SPR_40x_SGR, "SGR",
3684 SPR_NOACCESS, SPR_NOACCESS,
3685 &spr_read_generic, &spr_write_generic,
3686 0xFFFFFFFF);
3687 /* not emulated, as QEMU do not emulate caches */
3688 spr_register(env, SPR_40x_DCWR, "DCWR",
3689 SPR_NOACCESS, SPR_NOACCESS,
3690 &spr_read_generic, &spr_write_generic,
3691 0x00000000);
3692 /* Memory management */
3693 #if !defined(CONFIG_USER_ONLY)
3694 env->nb_tlb = 64;
3695 env->nb_ways = 1;
3696 env->id_tlbs = 0;
3697 env->tlb_type = TLB_EMB;
3698 #endif
3699 init_excp_4xx_softmmu(env);
3700 env->dcache_line_size = 32;
3701 env->icache_line_size = 32;
3702 /* Allocate hardware IRQ controller */
3703 ppc40x_irq_init(ppc_env_get_cpu(env));
3704
3705 SET_FIT_PERIOD(8, 12, 16, 20);
3706 SET_WDT_PERIOD(16, 20, 24, 28);
3707 }
3708
3709 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3710 {
3711 DeviceClass *dc = DEVICE_CLASS(oc);
3712 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3713
3714 dc->desc = "PowerPC 405";
3715 pcc->init_proc = init_proc_405;
3716 pcc->check_pow = check_pow_nocheck;
3717 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3718 PPC_DCR | PPC_WRTEE |
3719 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3720 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3721 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3722 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3723 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3724 pcc->msr_mask = (1ull << MSR_POW) |
3725 (1ull << MSR_CE) |
3726 (1ull << MSR_EE) |
3727 (1ull << MSR_PR) |
3728 (1ull << MSR_FP) |
3729 (1ull << MSR_DWE) |
3730 (1ull << MSR_DE) |
3731 (1ull << MSR_IR) |
3732 (1ull << MSR_DR);
3733 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3734 pcc->excp_model = POWERPC_EXCP_40x;
3735 pcc->bus_model = PPC_FLAGS_INPUT_405;
3736 pcc->bfd_mach = bfd_mach_ppc_403;
3737 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3738 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3739 }
3740
3741 static void init_proc_440EP(CPUPPCState *env)
3742 {
3743 /* Time base */
3744 gen_tbl(env);
3745 gen_spr_BookE(env, 0x000000000000FFFFULL);
3746 gen_spr_440(env);
3747 gen_spr_usprgh(env);
3748 /* Processor identification */
3749 spr_register(env, SPR_BOOKE_PIR, "PIR",
3750 SPR_NOACCESS, SPR_NOACCESS,
3751 &spr_read_generic, &spr_write_pir,
3752 0x00000000);
3753 /* XXX : not implemented */
3754 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3755 SPR_NOACCESS, SPR_NOACCESS,
3756 &spr_read_generic, &spr_write_generic,
3757 0x00000000);
3758 /* XXX : not implemented */
3759 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3760 SPR_NOACCESS, SPR_NOACCESS,
3761 &spr_read_generic, &spr_write_generic,
3762 0x00000000);
3763 /* XXX : not implemented */
3764 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3765 SPR_NOACCESS, SPR_NOACCESS,
3766 &spr_read_generic, &spr_write_generic,
3767 0x00000000);
3768 /* XXX : not implemented */
3769 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3770 SPR_NOACCESS, SPR_NOACCESS,
3771 &spr_read_generic, &spr_write_generic,
3772 0x00000000);
3773 /* XXX : not implemented */
3774 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3775 SPR_NOACCESS, SPR_NOACCESS,
3776 &spr_read_generic, &spr_write_generic,
3777 0x00000000);
3778 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3781 0x00000000);
3782 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3783 SPR_NOACCESS, SPR_NOACCESS,
3784 &spr_read_generic, &spr_write_generic,
3785 0x00000000);
3786 /* XXX : not implemented */
3787 spr_register(env, SPR_440_CCR1, "CCR1",
3788 SPR_NOACCESS, SPR_NOACCESS,
3789 &spr_read_generic, &spr_write_generic,
3790 0x00000000);
3791 /* Memory management */
3792 #if !defined(CONFIG_USER_ONLY)
3793 env->nb_tlb = 64;
3794 env->nb_ways = 1;
3795 env->id_tlbs = 0;
3796 env->tlb_type = TLB_EMB;
3797 #endif
3798 init_excp_BookE(env);
3799 env->dcache_line_size = 32;
3800 env->icache_line_size = 32;
3801 ppc40x_irq_init(ppc_env_get_cpu(env));
3802
3803 SET_FIT_PERIOD(12, 16, 20, 24);
3804 SET_WDT_PERIOD(20, 24, 28, 32);
3805 }
3806
3807 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3808 {
3809 DeviceClass *dc = DEVICE_CLASS(oc);
3810 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3811
3812 dc->desc = "PowerPC 440 EP";
3813 pcc->init_proc = init_proc_440EP;
3814 pcc->check_pow = check_pow_nocheck;
3815 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3816 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3817 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3818 PPC_FLOAT_STFIWX |
3819 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3820 PPC_CACHE | PPC_CACHE_ICBI |
3821 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3822 PPC_MEM_TLBSYNC | PPC_MFTB |
3823 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3824 PPC_440_SPEC;
3825 pcc->msr_mask = (1ull << MSR_POW) |
3826 (1ull << MSR_CE) |
3827 (1ull << MSR_EE) |
3828 (1ull << MSR_PR) |
3829 (1ull << MSR_FP) |
3830 (1ull << MSR_ME) |
3831 (1ull << MSR_FE0) |
3832 (1ull << MSR_DWE) |
3833 (1ull << MSR_DE) |
3834 (1ull << MSR_FE1) |
3835 (1ull << MSR_IR) |
3836 (1ull << MSR_DR);
3837 pcc->mmu_model = POWERPC_MMU_BOOKE;
3838 pcc->excp_model = POWERPC_EXCP_BOOKE;
3839 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3840 pcc->bfd_mach = bfd_mach_ppc_403;
3841 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3842 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3843 }
3844
3845 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3846 {
3847 DeviceClass *dc = DEVICE_CLASS(oc);
3848 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3849
3850 dc->desc = "PowerPC 460 EX";
3851 pcc->init_proc = init_proc_440EP;
3852 pcc->check_pow = check_pow_nocheck;
3853 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3854 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3855 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3856 PPC_FLOAT_STFIWX |
3857 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3858 PPC_CACHE | PPC_CACHE_ICBI |
3859 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3860 PPC_MEM_TLBSYNC | PPC_MFTB |
3861 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3862 PPC_440_SPEC;
3863 pcc->msr_mask = (1ull << MSR_POW) |
3864 (1ull << MSR_CE) |
3865 (1ull << MSR_EE) |
3866 (1ull << MSR_PR) |
3867 (1ull << MSR_FP) |
3868 (1ull << MSR_ME) |
3869 (1ull << MSR_FE0) |
3870 (1ull << MSR_DWE) |
3871 (1ull << MSR_DE) |
3872 (1ull << MSR_FE1) |
3873 (1ull << MSR_IR) |
3874 (1ull << MSR_DR);
3875 pcc->mmu_model = POWERPC_MMU_BOOKE;
3876 pcc->excp_model = POWERPC_EXCP_BOOKE;
3877 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3878 pcc->bfd_mach = bfd_mach_ppc_403;
3879 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3880 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3881 }
3882
3883 static void init_proc_440GP(CPUPPCState *env)
3884 {
3885 /* Time base */
3886 gen_tbl(env);
3887 gen_spr_BookE(env, 0x000000000000FFFFULL);
3888 gen_spr_440(env);
3889 gen_spr_usprgh(env);
3890 /* Processor identification */
3891 spr_register(env, SPR_BOOKE_PIR, "PIR",
3892 SPR_NOACCESS, SPR_NOACCESS,
3893 &spr_read_generic, &spr_write_pir,
3894 0x00000000);
3895 /* XXX : not implemented */
3896 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3897 SPR_NOACCESS, SPR_NOACCESS,
3898 &spr_read_generic, &spr_write_generic,
3899 0x00000000);
3900 /* XXX : not implemented */
3901 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3902 SPR_NOACCESS, SPR_NOACCESS,
3903 &spr_read_generic, &spr_write_generic,
3904 0x00000000);
3905 /* XXX : not implemented */
3906 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3907 SPR_NOACCESS, SPR_NOACCESS,
3908 &spr_read_generic, &spr_write_generic,
3909 0x00000000);
3910 /* XXX : not implemented */
3911 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3912 SPR_NOACCESS, SPR_NOACCESS,
3913 &spr_read_generic, &spr_write_generic,
3914 0x00000000);
3915 /* Memory management */
3916 #if !defined(CONFIG_USER_ONLY)
3917 env->nb_tlb = 64;
3918 env->nb_ways = 1;
3919 env->id_tlbs = 0;
3920 env->tlb_type = TLB_EMB;
3921 #endif
3922 init_excp_BookE(env);
3923 env->dcache_line_size = 32;
3924 env->icache_line_size = 32;
3925 /* XXX: TODO: allocate internal IRQ controller */
3926
3927 SET_FIT_PERIOD(12, 16, 20, 24);
3928 SET_WDT_PERIOD(20, 24, 28, 32);
3929 }
3930
3931 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3932 {
3933 DeviceClass *dc = DEVICE_CLASS(oc);
3934 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3935
3936 dc->desc = "PowerPC 440 GP";
3937 pcc->init_proc = init_proc_440GP;
3938 pcc->check_pow = check_pow_nocheck;
3939 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3940 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3941 PPC_CACHE | PPC_CACHE_ICBI |
3942 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3943 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3944 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3945 PPC_440_SPEC;
3946 pcc->msr_mask = (1ull << MSR_POW) |
3947 (1ull << MSR_CE) |
3948 (1ull << MSR_EE) |
3949 (1ull << MSR_PR) |
3950 (1ull << MSR_FP) |
3951 (1ull << MSR_ME) |
3952 (1ull << MSR_FE0) |
3953 (1ull << MSR_DWE) |
3954 (1ull << MSR_DE) |
3955 (1ull << MSR_FE1) |
3956 (1ull << MSR_IR) |
3957 (1ull << MSR_DR);
3958 pcc->mmu_model = POWERPC_MMU_BOOKE;
3959 pcc->excp_model = POWERPC_EXCP_BOOKE;
3960 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3961 pcc->bfd_mach = bfd_mach_ppc_403;
3962 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3963 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3964 }
3965
3966 static void init_proc_440x4(CPUPPCState *env)
3967 {
3968 /* Time base */
3969 gen_tbl(env);
3970 gen_spr_BookE(env, 0x000000000000FFFFULL);
3971 gen_spr_440(env);
3972 gen_spr_usprgh(env);
3973 /* Processor identification */
3974 spr_register(env, SPR_BOOKE_PIR, "PIR",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_pir,
3977 0x00000000);
3978 /* XXX : not implemented */
3979 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, &spr_write_generic,
3982 0x00000000);
3983 /* XXX : not implemented */
3984 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 /* XXX : not implemented */
3989 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 /* XXX : not implemented */
3994 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3995 SPR_NOACCESS, SPR_NOACCESS,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
3998 /* Memory management */
3999 #if !defined(CONFIG_USER_ONLY)
4000 env->nb_tlb = 64;
4001 env->nb_ways = 1;
4002 env->id_tlbs = 0;
4003 env->tlb_type = TLB_EMB;
4004 #endif
4005 init_excp_BookE(env);
4006 env->dcache_line_size = 32;
4007 env->icache_line_size = 32;
4008 /* XXX: TODO: allocate internal IRQ controller */
4009
4010 SET_FIT_PERIOD(12, 16, 20, 24);
4011 SET_WDT_PERIOD(20, 24, 28, 32);
4012 }
4013
4014 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
4015 {
4016 DeviceClass *dc = DEVICE_CLASS(oc);
4017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4018
4019 dc->desc = "PowerPC 440x4";
4020 pcc->init_proc = init_proc_440x4;
4021 pcc->check_pow = check_pow_nocheck;
4022 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4023 PPC_DCR | PPC_WRTEE |
4024 PPC_CACHE | PPC_CACHE_ICBI |
4025 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4026 PPC_MEM_TLBSYNC | PPC_MFTB |
4027 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4028 PPC_440_SPEC;
4029 pcc->msr_mask = (1ull << MSR_POW) |
4030 (1ull << MSR_CE) |
4031 (1ull << MSR_EE) |
4032 (1ull << MSR_PR) |
4033 (1ull << MSR_FP) |
4034 (1ull << MSR_ME) |
4035 (1ull << MSR_FE0) |
4036 (1ull << MSR_DWE) |
4037 (1ull << MSR_DE) |
4038 (1ull << MSR_FE1) |
4039 (1ull << MSR_IR) |
4040 (1ull << MSR_DR);
4041 pcc->mmu_model = POWERPC_MMU_BOOKE;
4042 pcc->excp_model = POWERPC_EXCP_BOOKE;
4043 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4044 pcc->bfd_mach = bfd_mach_ppc_403;
4045 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4046 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4047 }
4048
4049 static void init_proc_440x5(CPUPPCState *env)
4050 {
4051 /* Time base */
4052 gen_tbl(env);
4053 gen_spr_BookE(env, 0x000000000000FFFFULL);
4054 gen_spr_440(env);
4055 gen_spr_usprgh(env);
4056 /* Processor identification */
4057 spr_register(env, SPR_BOOKE_PIR, "PIR",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_pir,
4060 0x00000000);
4061 /* XXX : not implemented */
4062 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4063 SPR_NOACCESS, SPR_NOACCESS,
4064 &spr_read_generic, &spr_write_generic,
4065 0x00000000);
4066 /* XXX : not implemented */
4067 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4068 SPR_NOACCESS, SPR_NOACCESS,
4069 &spr_read_generic, &spr_write_generic,
4070 0x00000000);
4071 /* XXX : not implemented */
4072 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4073 SPR_NOACCESS, SPR_NOACCESS,
4074 &spr_read_generic, &spr_write_generic,
4075 0x00000000);
4076 /* XXX : not implemented */
4077 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4078 SPR_NOACCESS, SPR_NOACCESS,
4079 &spr_read_generic, &spr_write_generic,
4080 0x00000000);
4081 /* XXX : not implemented */
4082 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4083 SPR_NOACCESS, SPR_NOACCESS,
4084 &spr_read_generic, &spr_write_generic,
4085 0x00000000);
4086 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_generic,
4089 0x00000000);
4090 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4091 SPR_NOACCESS, SPR_NOACCESS,
4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
4094 /* XXX : not implemented */
4095 spr_register(env, SPR_440_CCR1, "CCR1",
4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, &spr_write_generic,
4098 0x00000000);
4099 /* Memory management */
4100 #if !defined(CONFIG_USER_ONLY)
4101 env->nb_tlb = 64;
4102 env->nb_ways = 1;
4103 env->id_tlbs = 0;
4104 env->tlb_type = TLB_EMB;
4105 #endif
4106 init_excp_BookE(env);
4107 env->dcache_line_size = 32;
4108 env->icache_line_size = 32;
4109 ppc40x_irq_init(ppc_env_get_cpu(env));
4110
4111 SET_FIT_PERIOD(12, 16, 20, 24);
4112 SET_WDT_PERIOD(20, 24, 28, 32);
4113 }
4114
4115 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4116 {
4117 DeviceClass *dc = DEVICE_CLASS(oc);
4118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4119
4120 dc->desc = "PowerPC 440x5";
4121 pcc->init_proc = init_proc_440x5;
4122 pcc->check_pow = check_pow_nocheck;
4123 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4124 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4125 PPC_CACHE | PPC_CACHE_ICBI |
4126 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4127 PPC_MEM_TLBSYNC | PPC_MFTB |
4128 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4129 PPC_440_SPEC;
4130 pcc->msr_mask = (1ull << MSR_POW) |
4131 (1ull << MSR_CE) |
4132 (1ull << MSR_EE) |
4133 (1ull << MSR_PR) |
4134 (1ull << MSR_FP) |
4135 (1ull << MSR_ME) |
4136 (1ull << MSR_FE0) |
4137 (1ull << MSR_DWE) |
4138 (1ull << MSR_DE) |
4139 (1ull << MSR_FE1) |
4140 (1ull << MSR_IR) |
4141 (1ull << MSR_DR);
4142 pcc->mmu_model = POWERPC_MMU_BOOKE;
4143 pcc->excp_model = POWERPC_EXCP_BOOKE;
4144 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4145 pcc->bfd_mach = bfd_mach_ppc_403;
4146 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4147 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4148 }
4149
4150 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4151 {
4152 DeviceClass *dc = DEVICE_CLASS(oc);
4153 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4154
4155 dc->desc = "PowerPC 440x5 with double precision FPU";
4156 pcc->init_proc = init_proc_440x5;
4157 pcc->check_pow = check_pow_nocheck;
4158 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4159 PPC_FLOAT | PPC_FLOAT_FSQRT |
4160 PPC_FLOAT_STFIWX |
4161 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4162 PPC_CACHE | PPC_CACHE_ICBI |
4163 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4164 PPC_MEM_TLBSYNC | PPC_MFTB |
4165 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4166 PPC_440_SPEC;
4167 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4168 pcc->msr_mask = (1ull << MSR_POW) |
4169 (1ull << MSR_CE) |
4170 (1ull << MSR_EE) |
4171 (1ull << MSR_PR) |
4172 (1ull << MSR_FP) |
4173 (1ull << MSR_ME) |
4174 (1ull << MSR_FE0) |
4175 (1ull << MSR_DWE) |
4176 (1ull << MSR_DE) |
4177 (1ull << MSR_FE1) |
4178 (1ull << MSR_IR) |
4179 (1ull << MSR_DR);
4180 pcc->mmu_model = POWERPC_MMU_BOOKE;
4181 pcc->excp_model = POWERPC_EXCP_BOOKE;
4182 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4183 pcc->bfd_mach = bfd_mach_ppc_403;
4184 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4185 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4186 }
4187
4188 static void init_proc_MPC5xx(CPUPPCState *env)
4189 {
4190 /* Time base */
4191 gen_tbl(env);
4192 gen_spr_5xx_8xx(env);
4193 gen_spr_5xx(env);
4194 init_excp_MPC5xx(env);
4195 env->dcache_line_size = 32;
4196 env->icache_line_size = 32;
4197 /* XXX: TODO: allocate internal IRQ controller */
4198 }
4199
4200 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4201 {
4202 DeviceClass *dc = DEVICE_CLASS(oc);
4203 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4204
4205 dc->desc = "Freescale 5xx cores (aka RCPU)";
4206 pcc->init_proc = init_proc_MPC5xx;
4207 pcc->check_pow = check_pow_none;
4208 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4209 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4210 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4211 PPC_MFTB;
4212 pcc->msr_mask = (1ull << MSR_ILE) |
4213 (1ull << MSR_EE) |
4214 (1ull << MSR_PR) |
4215 (1ull << MSR_FP) |
4216 (1ull << MSR_ME) |
4217 (1ull << MSR_FE0) |
4218 (1ull << MSR_SE) |
4219 (1ull << MSR_DE) |
4220 (1ull << MSR_FE1) |
4221 (1ull << MSR_EP) |
4222 (1ull << MSR_RI) |
4223 (1ull << MSR_LE);
4224 pcc->mmu_model = POWERPC_MMU_REAL;
4225 pcc->excp_model = POWERPC_EXCP_603;
4226 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4227 pcc->bfd_mach = bfd_mach_ppc_505;
4228 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4229 POWERPC_FLAG_BUS_CLK;
4230 }
4231
4232 static void init_proc_MPC8xx(CPUPPCState *env)
4233 {
4234 /* Time base */
4235 gen_tbl(env);
4236 gen_spr_5xx_8xx(env);
4237 gen_spr_8xx(env);
4238 init_excp_MPC8xx(env);
4239 env->dcache_line_size = 32;
4240 env->icache_line_size = 32;
4241 /* XXX: TODO: allocate internal IRQ controller */
4242 }
4243
4244 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4245 {
4246 DeviceClass *dc = DEVICE_CLASS(oc);
4247 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4248
4249 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4250 pcc->init_proc = init_proc_MPC8xx;
4251 pcc->check_pow = check_pow_none;
4252 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4253 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4254 PPC_CACHE_ICBI | PPC_MFTB;
4255 pcc->msr_mask = (1ull << MSR_ILE) |
4256 (1ull << MSR_EE) |
4257 (1ull << MSR_PR) |
4258 (1ull << MSR_FP) |
4259 (1ull << MSR_ME) |
4260 (1ull << MSR_SE) |
4261 (1ull << MSR_DE) |
4262 (1ull << MSR_EP) |
4263 (1ull << MSR_IR) |
4264 (1ull << MSR_DR) |
4265 (1ull << MSR_RI) |
4266 (1ull << MSR_LE);
4267 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4268 pcc->excp_model = POWERPC_EXCP_603;
4269 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4270 pcc->bfd_mach = bfd_mach_ppc_860;
4271 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4272 POWERPC_FLAG_BUS_CLK;
4273 }
4274
4275 /* Freescale 82xx cores (aka PowerQUICC-II) */
4276
4277 static void init_proc_G2(CPUPPCState *env)
4278 {
4279 gen_spr_ne_601(env);
4280 gen_spr_sdr1(env);
4281 gen_spr_G2_755(env);
4282 gen_spr_G2(env);
4283 /* Time base */
4284 gen_tbl(env);
4285 /* External access control */
4286 /* XXX : not implemented */
4287 spr_register(env, SPR_EAR, "EAR",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 /* Hardware implementation register */
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_HID0, "HID0",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
4297 /* XXX : not implemented */
4298 spr_register(env, SPR_HID1, "HID1",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
4302 /* XXX : not implemented */
4303 spr_register(env, SPR_HID2, "HID2",
4304 SPR_NOACCESS, SPR_NOACCESS,
4305 &spr_read_generic, &spr_write_generic,
4306 0x00000000);
4307 /* Memory management */
4308 gen_low_BATs(env);
4309 gen_high_BATs(env);
4310 gen_6xx_7xx_soft_tlb(env, 64, 2);
4311 init_excp_G2(env);
4312 env->dcache_line_size = 32;
4313 env->icache_line_size = 32;
4314 /* Allocate hardware IRQ controller */
4315 ppc6xx_irq_init(ppc_env_get_cpu(env));
4316 }
4317
4318 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4319 {
4320 DeviceClass *dc = DEVICE_CLASS(oc);
4321 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4322
4323 dc->desc = "PowerPC G2";
4324 pcc->init_proc = init_proc_G2;
4325 pcc->check_pow = check_pow_hid0;
4326 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4327 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4328 PPC_FLOAT_STFIWX |
4329 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4330 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4331 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4332 PPC_SEGMENT | PPC_EXTERN;
4333 pcc->msr_mask = (1ull << MSR_POW) |
4334 (1ull << MSR_TGPR) |
4335 (1ull << MSR_EE) |
4336 (1ull << MSR_PR) |
4337 (1ull << MSR_FP) |
4338 (1ull << MSR_ME) |
4339 (1ull << MSR_FE0) |
4340 (1ull << MSR_SE) |
4341 (1ull << MSR_DE) |
4342 (1ull << MSR_FE1) |
4343 (1ull << MSR_AL) |
4344 (1ull << MSR_EP) |
4345 (1ull << MSR_IR) |
4346 (1ull << MSR_DR) |
4347 (1ull << MSR_RI);
4348 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4349 pcc->excp_model = POWERPC_EXCP_G2;
4350 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4351 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4352 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4353 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4354 }
4355
4356 static void init_proc_G2LE(CPUPPCState *env)
4357 {
4358 gen_spr_ne_601(env);
4359 gen_spr_sdr1(env);
4360 gen_spr_G2_755(env);
4361 gen_spr_G2(env);
4362 /* Time base */
4363 gen_tbl(env);
4364 /* External access control */
4365 /* XXX : not implemented */
4366 spr_register(env, SPR_EAR, "EAR",
4367 SPR_NOACCESS, SPR_NOACCESS,
4368 &spr_read_generic, &spr_write_generic,
4369 0x00000000);
4370 /* Hardware implementation register */
4371 /* XXX : not implemented */
4372 spr_register(env, SPR_HID0, "HID0",
4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
4376 /* XXX : not implemented */
4377 spr_register(env, SPR_HID1, "HID1",
4378 SPR_NOACCESS, SPR_NOACCESS,
4379 &spr_read_generic, &spr_write_generic,
4380 0x00000000);
4381 /* XXX : not implemented */
4382 spr_register(env, SPR_HID2, "HID2",
4383 SPR_NOACCESS, SPR_NOACCESS,
4384 &spr_read_generic, &spr_write_generic,
4385 0x00000000);
4386
4387 /* Memory management */
4388 gen_low_BATs(env);
4389 gen_high_BATs(env);
4390 gen_6xx_7xx_soft_tlb(env, 64, 2);
4391 init_excp_G2(env);
4392 env->dcache_line_size = 32;
4393 env->icache_line_size = 32;
4394 /* Allocate hardware IRQ controller */
4395 ppc6xx_irq_init(ppc_env_get_cpu(env));
4396 }
4397
4398 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4399 {
4400 DeviceClass *dc = DEVICE_CLASS(oc);
4401 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4402
4403 dc->desc = "PowerPC G2LE";
4404 pcc->init_proc = init_proc_G2LE;
4405 pcc->check_pow = check_pow_hid0;
4406 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4407 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4408 PPC_FLOAT_STFIWX |
4409 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4410 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4411 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4412 PPC_SEGMENT | PPC_EXTERN;
4413 pcc->msr_mask = (1ull << MSR_POW) |
4414 (1ull << MSR_TGPR) |
4415 (1ull << MSR_ILE) |
4416 (1ull << MSR_EE) |
4417 (1ull << MSR_PR) |
4418 (1ull << MSR_FP) |
4419 (1ull << MSR_ME) |
4420 (1ull << MSR_FE0) |
4421 (1ull << MSR_SE) |
4422 (1ull << MSR_DE) |
4423 (1ull << MSR_FE1) |
4424 (1ull << MSR_AL) |
4425 (1ull << MSR_EP) |
4426 (1ull << MSR_IR) |
4427 (1ull << MSR_DR) |
4428 (1ull << MSR_RI) |
4429 (1ull << MSR_LE);
4430 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4431 pcc->excp_model = POWERPC_EXCP_G2;
4432 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4433 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4434 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4435 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4436 }
4437
4438 static void init_proc_e200(CPUPPCState *env)
4439 {
4440 /* Time base */
4441 gen_tbl(env);
4442 gen_spr_BookE(env, 0x000000070000FFFFULL);
4443 /* XXX : not implemented */
4444 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4445 &spr_read_spefscr, &spr_write_spefscr,
4446 &spr_read_spefscr, &spr_write_spefscr,
4447 0x00000000);
4448 /* Memory management */
4449 gen_spr_BookE206(env, 0x0000005D, NULL, 0);
4450 /* XXX : not implemented */
4451 spr_register(env, SPR_HID0, "HID0",
4452 SPR_NOACCESS, SPR_NOACCESS,
4453 &spr_read_generic, &spr_write_generic,
4454 0x00000000);
4455 /* XXX : not implemented */
4456 spr_register(env, SPR_HID1, "HID1",
4457 SPR_NOACCESS, SPR_NOACCESS,
4458 &spr_read_generic, &spr_write_generic,
4459 0x00000000);
4460 /* XXX : not implemented */
4461 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4462 SPR_NOACCESS, SPR_NOACCESS,
4463 &spr_read_generic, &spr_write_generic,
4464 0x00000000);
4465 /* XXX : not implemented */
4466 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4467 SPR_NOACCESS, SPR_NOACCESS,
4468 &spr_read_generic, &spr_write_generic,
4469 0x00000000);
4470 /* XXX : not implemented */
4471 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4472 SPR_NOACCESS, SPR_NOACCESS,
4473 &spr_read_generic, &spr_write_generic,
4474 0x00000000);
4475 /* XXX : not implemented */
4476 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4477 SPR_NOACCESS, SPR_NOACCESS,
4478 &spr_read_generic, &spr_write_generic,
4479 0x00000000);
4480 /* XXX : not implemented */
4481 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4482 SPR_NOACCESS, SPR_NOACCESS,
4483 &spr_read_generic, &spr_write_generic,
4484 0x00000000);
4485 /* XXX : not implemented */
4486 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4487 &spr_read_generic, SPR_NOACCESS,
4488 &spr_read_generic, SPR_NOACCESS,
4489 0x00000000);
4490 /* XXX : not implemented */
4491 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4492 SPR_NOACCESS, SPR_NOACCESS,
4493 &spr_read_generic, &spr_write_generic,
4494 0x00000000);
4495 /* XXX : not implemented */
4496 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4497 SPR_NOACCESS, SPR_NOACCESS,
4498 &spr_read_generic, &spr_write_generic,
4499 0x00000000);
4500 /* XXX : not implemented */
4501 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4502 SPR_NOACCESS, SPR_NOACCESS,
4503 &spr_read_generic, &spr_write_generic,
4504 0x00000000);
4505 /* XXX : not implemented */
4506 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4507 SPR_NOACCESS, SPR_NOACCESS,
4508 &spr_read_generic, &spr_write_generic,
4509 0x00000000);
4510 /* XXX : not implemented */
4511 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4512 SPR_NOACCESS, SPR_NOACCESS,
4513 &spr_read_generic, &spr_write_generic,
4514 0x00000000);
4515 /* XXX : not implemented */
4516 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4517 SPR_NOACCESS, SPR_NOACCESS,
4518 &spr_read_generic, &spr_write_generic,
4519 0x00000000);
4520 /* XXX : not implemented */
4521 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4522 SPR_NOACCESS, SPR_NOACCESS,
4523 &spr_read_generic, &spr_write_generic,
4524 0x00000000); /* TOFIX */
4525 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4530 SPR_NOACCESS, SPR_NOACCESS,
4531 &spr_read_generic, &spr_write_generic,
4532 0x00000000);
4533 #if !defined(CONFIG_USER_ONLY)
4534 env->nb_tlb = 64;
4535 env->nb_ways = 1;
4536 env->id_tlbs = 0;
4537 env->tlb_type = TLB_EMB;
4538 #endif
4539 init_excp_e200(env, 0xFFFF0000UL);
4540 env->dcache_line_size = 32;
4541 env->icache_line_size = 32;
4542 /* XXX: TODO: allocate internal IRQ controller */
4543 }
4544
4545 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4546 {
4547 DeviceClass *dc = DEVICE_CLASS(oc);
4548 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4549
4550 dc->desc = "e200 core";
4551 pcc->init_proc = init_proc_e200;
4552 pcc->check_pow = check_pow_hid0;
4553 /* XXX: unimplemented instructions:
4554 * dcblc
4555 * dcbtlst
4556 * dcbtstls
4557 * icblc
4558 * icbtls
4559 * tlbivax
4560 * all SPE multiply-accumulate instructions
4561 */
4562 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4563 PPC_SPE | PPC_SPE_SINGLE |
4564 PPC_WRTEE | PPC_RFDI |
4565 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4566 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4567 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4568 PPC_BOOKE;
4569 pcc->msr_mask = (1ull << MSR_UCLE) |
4570 (1ull << MSR_SPE) |
4571 (1ull << MSR_POW) |
4572 (1ull << MSR_CE) |
4573 (1ull << MSR_EE) |
4574 (1ull << MSR_PR) |
4575 (1ull << MSR_FP) |
4576 (1ull << MSR_ME) |
4577 (1ull << MSR_FE0) |
4578 (1ull << MSR_DWE) |
4579 (1ull << MSR_DE) |
4580 (1ull << MSR_FE1) |
4581 (1ull << MSR_IR) |
4582 (1ull << MSR_DR);
4583 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4584 pcc->excp_model = POWERPC_EXCP_BOOKE;
4585 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4586 pcc->bfd_mach = bfd_mach_ppc_860;
4587 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4588 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4589 POWERPC_FLAG_BUS_CLK;
4590 }
4591
4592 static void init_proc_e300(CPUPPCState *env)
4593 {
4594 gen_spr_ne_601(env);
4595 gen_spr_sdr1(env);
4596 gen_spr_603(env);
4597 /* Time base */
4598 gen_tbl(env);
4599 /* hardware implementation registers */
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_HID0, "HID0",
4602 SPR_NOACCESS, SPR_NOACCESS,
4603 &spr_read_generic, &spr_write_generic,
4604 0x00000000);
4605 /* XXX : not implemented */
4606 spr_register(env, SPR_HID1, "HID1",
4607 SPR_NOACCESS, SPR_NOACCESS,
4608 &spr_read_generic, &spr_write_generic,
4609 0x00000000);
4610 /* XXX : not implemented */
4611 spr_register(env, SPR_HID2, "HID2",
4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
4615 /* Breakpoints */
4616 /* XXX : not implemented */
4617 spr_register(env, SPR_DABR, "DABR",
4618 SPR_NOACCESS, SPR_NOACCESS,
4619 &spr_read_generic, &spr_write_generic,
4620 0x00000000);
4621 /* XXX : not implemented */
4622 spr_register(env, SPR_DABR2, "DABR2",
4623 SPR_NOACCESS, SPR_NOACCESS,
4624 &spr_read_generic, &spr_write_generic,
4625 0x00000000);
4626 /* XXX : not implemented */
4627 spr_register(env, SPR_IABR2, "IABR2",
4628 SPR_NOACCESS, SPR_NOACCESS,
4629 &spr_read_generic, &spr_write_generic,
4630 0x00000000);
4631 /* XXX : not implemented */
4632 spr_register(env, SPR_IBCR, "IBCR",
4633 SPR_NOACCESS, SPR_NOACCESS,
4634 &spr_read_generic, &spr_write_generic,
4635 0x00000000);
4636 /* XXX : not implemented */
4637 spr_register(env, SPR_DBCR, "DBCR",
4638 SPR_NOACCESS, SPR_NOACCESS,
4639 &spr_read_generic, &spr_write_generic,
4640 0x00000000);
4641 /* Memory management */
4642 gen_low_BATs(env);
4643 gen_high_BATs(env);
4644 gen_6xx_7xx_soft_tlb(env, 64, 2);
4645 init_excp_603(env);
4646 env->dcache_line_size = 32;
4647 env->icache_line_size = 32;
4648 /* Allocate hardware IRQ controller */
4649 ppc6xx_irq_init(ppc_env_get_cpu(env));
4650 }
4651
4652 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4653 {
4654 DeviceClass *dc = DEVICE_CLASS(oc);
4655 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4656
4657 dc->desc = "e300 core";
4658 pcc->init_proc = init_proc_e300;
4659 pcc->check_pow = check_pow_hid0;
4660 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4661 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4662 PPC_FLOAT_STFIWX |
4663 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4664 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4665 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4666 PPC_SEGMENT | PPC_EXTERN;
4667 pcc->msr_mask = (1ull << MSR_POW) |
4668 (1ull << MSR_TGPR) |
4669 (1ull << MSR_ILE) |
4670 (1ull << MSR_EE) |
4671 (1ull << MSR_PR) |
4672 (1ull << MSR_FP) |
4673 (1ull << MSR_ME) |
4674 (1ull << MSR_FE0) |
4675 (1ull << MSR_SE) |
4676 (1ull << MSR_DE) |
4677 (1ull << MSR_FE1) |
4678 (1ull << MSR_AL) |
4679 (1ull << MSR_EP) |
4680 (1ull << MSR_IR) |
4681 (1ull << MSR_DR) |
4682 (1ull << MSR_RI) |
4683 (1ull << MSR_LE);
4684 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4685 pcc->excp_model = POWERPC_EXCP_603;
4686 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4687 pcc->bfd_mach = bfd_mach_ppc_603;
4688 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4689 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4690 }
4691
4692 #if !defined(CONFIG_USER_ONLY)
4693 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4694 {
4695 TCGv val = tcg_temp_new();
4696 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4697 gen_store_spr(SPR_BOOKE_MAS3, val);
4698 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4699 gen_store_spr(SPR_BOOKE_MAS7, val);
4700 tcg_temp_free(val);
4701 }
4702
4703 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4704 {
4705 TCGv mas7 = tcg_temp_new();
4706 TCGv mas3 = tcg_temp_new();
4707 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4708 tcg_gen_shli_tl(mas7, mas7, 32);
4709 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4710 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4711 tcg_temp_free(mas3);
4712 tcg_temp_free(mas7);
4713 }
4714
4715 #endif
4716
4717 enum fsl_e500_version {
4718 fsl_e500v1,
4719 fsl_e500v2,
4720 fsl_e500mc,
4721 fsl_e5500,
4722 fsl_e6500,
4723 };
4724
4725 static void init_proc_e500(CPUPPCState *env, int version)
4726 {
4727 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4728 uint32_t tlbncfg[2];
4729 uint64_t ivor_mask;
4730 uint64_t ivpr_mask = 0xFFFF0000ULL;
4731 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4732 | 0x0020; /* 32 kb */
4733 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4734 | 0x0020; /* 32 kb */
4735 uint32_t mmucfg = 0;
4736 #if !defined(CONFIG_USER_ONLY)
4737 int i;
4738 #endif
4739
4740 /* Time base */
4741 gen_tbl(env);
4742 /*
4743 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4744 * complain when accessing them.
4745 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4746 */
4747 switch (version) {
4748 case fsl_e500v1:
4749 case fsl_e500v2:
4750 default:
4751 ivor_mask = 0x0000000F0000FFFFULL;
4752 break;
4753 case fsl_e500mc:
4754 case fsl_e5500:
4755 ivor_mask = 0x000003FE0000FFFFULL;
4756 break;
4757 case fsl_e6500:
4758 ivor_mask = 0x000003FF0000FFFFULL;
4759 break;
4760 }
4761 gen_spr_BookE(env, ivor_mask);
4762 gen_spr_usprg3(env);
4763 /* Processor identification */
4764 spr_register(env, SPR_BOOKE_PIR, "PIR",
4765 SPR_NOACCESS, SPR_NOACCESS,
4766 &spr_read_generic, &spr_write_pir,
4767 0x00000000);
4768 /* XXX : not implemented */
4769 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4770 &spr_read_spefscr, &spr_write_spefscr,
4771 &spr_read_spefscr, &spr_write_spefscr,
4772 0x00000000);
4773 #if !defined(CONFIG_USER_ONLY)
4774 /* Memory management */
4775 env->nb_pids = 3;
4776 env->nb_ways = 2;
4777 env->id_tlbs = 0;
4778 switch (version) {
4779 case fsl_e500v1:
4780 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4781 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4782 break;
4783 case fsl_e500v2:
4784 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4785 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4786 break;
4787 case fsl_e500mc:
4788 case fsl_e5500:
4789 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4790 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4791 break;
4792 case fsl_e6500:
4793 mmucfg = 0x6510B45;
4794 env->nb_pids = 1;
4795 tlbncfg[0] = 0x08052400;
4796 tlbncfg[1] = 0x40028040;
4797 break;
4798 default:
4799 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4800 }
4801 #endif
4802 /* Cache sizes */
4803 switch (version) {
4804 case fsl_e500v1:
4805 case fsl_e500v2:
4806 env->dcache_line_size = 32;
4807 env->icache_line_size = 32;
4808 break;
4809 case fsl_e500mc:
4810 case fsl_e5500:
4811 env->dcache_line_size = 64;
4812 env->icache_line_size = 64;
4813 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4814 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4815 break;
4816 case fsl_e6500:
4817 env->dcache_line_size = 32;
4818 env->icache_line_size = 32;
4819 l1cfg0 |= 0x0F83820;
4820 l1cfg1 |= 0x0B83820;
4821 break;
4822 default:
4823 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4824 }
4825 gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
4826 /* XXX : not implemented */
4827 spr_register(env, SPR_HID0, "HID0",
4828 SPR_NOACCESS, SPR_NOACCESS,
4829 &spr_read_generic, &spr_write_generic,
4830 0x00000000);
4831 /* XXX : not implemented */
4832 spr_register(env, SPR_HID1, "HID1",
4833 SPR_NOACCESS, SPR_NOACCESS,
4834 &spr_read_generic, &spr_write_generic,
4835 0x00000000);
4836 /* XXX : not implemented */
4837 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4838 SPR_NOACCESS, SPR_NOACCESS,
4839 &spr_read_generic, &spr_write_generic,
4840 0x00000000);
4841 /* XXX : not implemented */
4842 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4843 SPR_NOACCESS, SPR_NOACCESS,
4844 &spr_read_generic, &spr_write_generic,
4845 0x00000000);
4846 /* XXX : not implemented */
4847 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4848 SPR_NOACCESS, SPR_NOACCESS,
4849 &spr_read_generic, &spr_write_generic,
4850 0x00000000);
4851 /* XXX : not implemented */
4852 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4853 SPR_NOACCESS, SPR_NOACCESS,
4854 &spr_read_generic, &spr_write_generic,
4855 0x00000000);
4856 /* XXX : not implemented */
4857 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4858 SPR_NOACCESS, SPR_NOACCESS,
4859 &spr_read_generic, &spr_write_generic,
4860 0x00000000);
4861 /* XXX : not implemented */
4862 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4863 SPR_NOACCESS, SPR_NOACCESS,
4864 &spr_read_generic, &spr_write_generic,
4865 0x00000000);
4866 /* XXX : not implemented */
4867 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4868 &spr_read_generic, SPR_NOACCESS,
4869 &spr_read_generic, SPR_NOACCESS,
4870 l1cfg0);
4871 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4872 &spr_read_generic, SPR_NOACCESS,
4873 &spr_read_generic, SPR_NOACCESS,
4874 l1cfg1);
4875 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4876 SPR_NOACCESS, SPR_NOACCESS,
4877 &spr_read_generic, &spr_write_e500_l1csr0,
4878 0x00000000);
4879 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4880 SPR_NOACCESS, SPR_NOACCESS,
4881 &spr_read_generic, &spr_write_e500_l1csr1,
4882 0x00000000);
4883 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4884 SPR_NOACCESS, SPR_NOACCESS,
4885 &spr_read_generic, &spr_write_generic,
4886 0x00000000);
4887 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4888 SPR_NOACCESS, SPR_NOACCESS,
4889 &spr_read_generic, &spr_write_generic,
4890 0x00000000);
4891 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4892 SPR_NOACCESS, SPR_NOACCESS,
4893 &spr_read_generic, &spr_write_booke206_mmucsr0,
4894 0x00000000);
4895 spr_register(env, SPR_BOOKE_EPR, "EPR",
4896 SPR_NOACCESS, SPR_NOACCESS,
4897 &spr_read_generic, SPR_NOACCESS,
4898 0x00000000);
4899 /* XXX better abstract into Emb.xxx features */
4900 if ((version == fsl_e5500) || (version == fsl_e6500)) {
4901 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4902 SPR_NOACCESS, SPR_NOACCESS,
4903 &spr_read_generic, &spr_write_generic,
4904 0x00000000);
4905 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4906 SPR_NOACCESS, SPR_NOACCESS,
4907 &spr_read_mas73, &spr_write_mas73,
4908 0x00000000);
4909 ivpr_mask = (target_ulong)~0xFFFFULL;
4910 }
4911
4912 if (version == fsl_e6500) {
4913 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
4914 SPR_NOACCESS, SPR_NOACCESS,
4915 &spr_read_generic, &spr_write_generic,
4916 0x00000000);
4917 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921 /* Thread identification */
4922 spr_register(env, SPR_TIR, "TIR",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, SPR_NOACCESS,
4925 0x00000000);
4926 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
4927 SPR_NOACCESS, SPR_NOACCESS,
4928 &spr_read_generic, SPR_NOACCESS,
4929 0x00000004);
4930 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
4931 SPR_NOACCESS, SPR_NOACCESS,
4932 &spr_read_generic, SPR_NOACCESS,
4933 0x7FFFFFFC);
4934 }
4935
4936 #if !defined(CONFIG_USER_ONLY)
4937 env->nb_tlb = 0;
4938 env->tlb_type = TLB_MAS;
4939 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4940 env->nb_tlb += booke206_tlb_size(env, i);
4941 }
4942 #endif
4943
4944 init_excp_e200(env, ivpr_mask);
4945 /* Allocate hardware IRQ controller */
4946 ppce500_irq_init(ppc_env_get_cpu(env));
4947 }
4948
4949 static void init_proc_e500v1(CPUPPCState *env)
4950 {
4951 init_proc_e500(env, fsl_e500v1);
4952 }
4953
4954 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4955 {
4956 DeviceClass *dc = DEVICE_CLASS(oc);
4957 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4958
4959 dc->desc = "e500v1 core";
4960 pcc->init_proc = init_proc_e500v1;
4961 pcc->check_pow = check_pow_hid0;
4962 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4963 PPC_SPE | PPC_SPE_SINGLE |
4964 PPC_WRTEE | PPC_RFDI |
4965 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4966 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4967 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4968 pcc->insns_flags2 = PPC2_BOOKE206;
4969 pcc->msr_mask = (1ull << MSR_UCLE) |
4970 (1ull << MSR_SPE) |
4971 (1ull << MSR_POW) |
4972 (1ull << MSR_CE) |
4973 (1ull << MSR_EE) |
4974 (1ull << MSR_PR) |
4975 (1ull << MSR_FP) |
4976 (1ull << MSR_ME) |
4977 (1ull << MSR_FE0) |
4978 (1ull << MSR_DWE) |
4979 (1ull << MSR_DE) |
4980 (1ull << MSR_FE1) |
4981 (1ull << MSR_IR) |
4982 (1ull << MSR_DR);
4983 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4984 pcc->excp_model = POWERPC_EXCP_BOOKE;
4985 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4986 pcc->bfd_mach = bfd_mach_ppc_860;
4987 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4988 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4989 POWERPC_FLAG_BUS_CLK;
4990 }
4991
4992 static void init_proc_e500v2(CPUPPCState *env)
4993 {
4994 init_proc_e500(env, fsl_e500v2);
4995 }
4996
4997 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4998 {
4999 DeviceClass *dc = DEVICE_CLASS(oc);
5000 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5001
5002 dc->desc = "e500v2 core";
5003 pcc->init_proc = init_proc_e500v2;
5004 pcc->check_pow = check_pow_hid0;
5005 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5006 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5007 PPC_WRTEE | PPC_RFDI |
5008 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5009 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5010 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5011 pcc->insns_flags2 = PPC2_BOOKE206;
5012 pcc->msr_mask = (1ull << MSR_UCLE) |
5013 (1ull << MSR_SPE) |
5014 (1ull << MSR_POW) |
5015 (1ull << MSR_CE) |
5016 (1ull << MSR_EE) |
5017 (1ull << MSR_PR) |
5018 (1ull << MSR_FP) |
5019 (1ull << MSR_ME) |
5020 (1ull << MSR_FE0) |
5021 (1ull << MSR_DWE) |
5022 (1ull << MSR_DE) |
5023 (1ull << MSR_FE1) |
5024 (1ull << MSR_IR) |
5025 (1ull << MSR_DR);
5026 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5027 pcc->excp_model = POWERPC_EXCP_BOOKE;
5028 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5029 pcc->bfd_mach = bfd_mach_ppc_860;
5030 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5031 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5032 POWERPC_FLAG_BUS_CLK;
5033 }
5034
5035 static void init_proc_e500mc(CPUPPCState *env)
5036 {
5037 init_proc_e500(env, fsl_e500mc);
5038 }
5039
5040 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5041 {
5042 DeviceClass *dc = DEVICE_CLASS(oc);
5043 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5044
5045 dc->desc = "e500mc core";
5046 pcc->init_proc = init_proc_e500mc;
5047 pcc->check_pow = check_pow_none;
5048 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5049 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5050 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5051 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5052 PPC_FLOAT | PPC_FLOAT_FRES |
5053 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5054 PPC_FLOAT_STFIWX | PPC_WAIT |
5055 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5056 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5057 pcc->msr_mask = (1ull << MSR_GS) |
5058 (1ull << MSR_UCLE) |
5059 (1ull << MSR_CE) |
5060 (1ull << MSR_EE) |
5061 (1ull << MSR_PR) |
5062 (1ull << MSR_FP) |
5063 (1ull << MSR_ME) |
5064 (1ull << MSR_FE0) |
5065 (1ull << MSR_DE) |
5066 (1ull << MSR_FE1) |
5067 (1ull << MSR_IR) |
5068 (1ull << MSR_DR) |
5069 (1ull << MSR_PX) |
5070 (1ull << MSR_RI);
5071 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5072 pcc->excp_model = POWERPC_EXCP_BOOKE;
5073 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5074 /* FIXME: figure out the correct flag for e500mc */
5075 pcc->bfd_mach = bfd_mach_ppc_e500;
5076 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5077 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5078 }
5079
5080 #ifdef TARGET_PPC64
5081 static void init_proc_e5500(CPUPPCState *env)
5082 {
5083 init_proc_e500(env, fsl_e5500);
5084 }
5085
5086 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5087 {
5088 DeviceClass *dc = DEVICE_CLASS(oc);
5089 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5090
5091 dc->desc = "e5500 core";
5092 pcc->init_proc = init_proc_e5500;
5093 pcc->check_pow = check_pow_none;
5094 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5095 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5096 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5097 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5098 PPC_FLOAT | PPC_FLOAT_FRES |
5099 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5100 PPC_FLOAT_STFIWX | PPC_WAIT |
5101 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5102 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5103 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5104 PPC2_FP_CVT_S64;
5105 pcc->msr_mask = (1ull << MSR_CM) |
5106 (1ull << MSR_GS) |
5107 (1ull << MSR_UCLE) |
5108 (1ull << MSR_CE) |
5109 (1ull << MSR_EE) |
5110 (1ull << MSR_PR) |
5111 (1ull << MSR_FP) |
5112 (1ull << MSR_ME) |
5113 (1ull << MSR_FE0) |
5114 (1ull << MSR_DE) |
5115 (1ull << MSR_FE1) |
5116 (1ull << MSR_IR) |
5117 (1ull << MSR_DR) |
5118 (1ull << MSR_PX) |
5119 (1ull << MSR_RI);
5120 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5121 pcc->excp_model = POWERPC_EXCP_BOOKE;
5122 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5123 /* FIXME: figure out the correct flag for e5500 */
5124 pcc->bfd_mach = bfd_mach_ppc_e500;
5125 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5126 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5127 }
5128
5129 static void init_proc_e6500(CPUPPCState *env)
5130 {
5131 init_proc_e500(env, fsl_e6500);
5132 }
5133
5134 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
5135 {
5136 DeviceClass *dc = DEVICE_CLASS(oc);
5137 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5138
5139 dc->desc = "e6500 core";
5140 pcc->init_proc = init_proc_e6500;
5141 pcc->check_pow = check_pow_none;
5142 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5143 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5144 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5145 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5146 PPC_FLOAT | PPC_FLOAT_FRES |
5147 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5148 PPC_FLOAT_STFIWX | PPC_WAIT |
5149 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5150 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
5151 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5152 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
5153 pcc->msr_mask = (1ull << MSR_CM) |
5154 (1ull << MSR_GS) |
5155 (1ull << MSR_UCLE) |
5156 (1ull << MSR_CE) |
5157 (1ull << MSR_EE) |
5158 (1ull << MSR_PR) |
5159 (1ull << MSR_FP) |
5160 (1ull << MSR_ME) |
5161 (1ull << MSR_FE0) |
5162 (1ull << MSR_DE) |
5163 (1ull << MSR_FE1) |
5164 (1ull << MSR_IS) |
5165 (1ull << MSR_DS) |
5166 (1ull << MSR_PX) |
5167 (1ull << MSR_RI) |
5168 (1ull << MSR_VR);
5169 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5170 pcc->excp_model = POWERPC_EXCP_BOOKE;
5171 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5172 pcc->bfd_mach = bfd_mach_ppc_e500;
5173 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5174 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
5175 }
5176
5177 #endif
5178
5179 /* Non-embedded PowerPC */
5180
5181 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5182
5183 static void init_proc_601(CPUPPCState *env)
5184 {
5185 gen_spr_ne_601(env);
5186 gen_spr_sdr1(env);
5187 gen_spr_601(env);
5188 /* Hardware implementation registers */
5189 /* XXX : not implemented */
5190 spr_register(env, SPR_HID0, "HID0",
5191 SPR_NOACCESS, SPR_NOACCESS,
5192 &spr_read_generic, &spr_write_hid0_601,
5193 0x80010080);
5194 /* XXX : not implemented */
5195 spr_register(env, SPR_HID1, "HID1",
5196 SPR_NOACCESS, SPR_NOACCESS,
5197 &spr_read_generic, &spr_write_generic,
5198 0x00000000);
5199 /* XXX : not implemented */
5200 spr_register(env, SPR_601_HID2, "HID2",
5201 SPR_NOACCESS, SPR_NOACCESS,
5202 &spr_read_generic, &spr_write_generic,
5203 0x00000000);
5204 /* XXX : not implemented */
5205 spr_register(env, SPR_601_HID5, "HID5",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 /* Memory management */
5210 init_excp_601(env);
5211 /* XXX: beware that dcache line size is 64
5212 * but dcbz uses 32 bytes "sectors"
5213 * XXX: this breaks clcs instruction !
5214 */
5215 env->dcache_line_size = 32;
5216 env->icache_line_size = 64;
5217 /* Allocate hardware IRQ controller */
5218 ppc6xx_irq_init(ppc_env_get_cpu(env));
5219 }
5220
5221 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5222 {
5223 DeviceClass *dc = DEVICE_CLASS(oc);
5224 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5225
5226 dc->desc = "PowerPC 601";
5227 pcc->init_proc = init_proc_601;
5228 pcc->check_pow = check_pow_none;
5229 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5230 PPC_FLOAT |
5231 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5232 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5233 PPC_SEGMENT | PPC_EXTERN;
5234 pcc->msr_mask = (1ull << MSR_EE) |
5235 (1ull << MSR_PR) |
5236 (1ull << MSR_FP) |
5237 (1ull << MSR_ME) |
5238 (1ull << MSR_FE0) |
5239 (1ull << MSR_SE) |
5240 (1ull << MSR_FE1) |
5241 (1ull << MSR_EP) |
5242 (1ull << MSR_IR) |
5243 (1ull << MSR_DR);
5244 pcc->mmu_model = POWERPC_MMU_601;
5245 #if defined(CONFIG_SOFTMMU)
5246 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5247 #endif
5248 pcc->excp_model = POWERPC_EXCP_601;
5249 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5250 pcc->bfd_mach = bfd_mach_ppc_601;
5251 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5252 }
5253
5254 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5255
5256 static void init_proc_601v(CPUPPCState *env)
5257 {
5258 init_proc_601(env);
5259 /* XXX : not implemented */
5260 spr_register(env, SPR_601_HID15, "HID15",
5261 SPR_NOACCESS, SPR_NOACCESS,
5262 &spr_read_generic, &spr_write_generic,
5263 0x00000000);
5264 }
5265
5266 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5267 {
5268 DeviceClass *dc = DEVICE_CLASS(oc);
5269 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5270
5271 dc->desc = "PowerPC 601v";
5272 pcc->init_proc = init_proc_601v;
5273 pcc->check_pow = check_pow_none;
5274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5275 PPC_FLOAT |
5276 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5277 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5278 PPC_SEGMENT | PPC_EXTERN;
5279 pcc->msr_mask = (1ull << MSR_EE) |
5280 (1ull << MSR_PR) |
5281 (1ull << MSR_FP) |
5282 (1ull << MSR_ME) |
5283 (1ull << MSR_FE0) |
5284 (1ull << MSR_SE) |
5285 (1ull << MSR_FE1) |
5286 (1ull << MSR_EP) |
5287 (1ull << MSR_IR) |
5288 (1ull << MSR_DR);
5289 pcc->mmu_model = POWERPC_MMU_601;
5290 #if defined(CONFIG_SOFTMMU)
5291 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5292 #endif
5293 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5294 pcc->bfd_mach = bfd_mach_ppc_601;
5295 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5296 }
5297
5298 static void init_proc_602(CPUPPCState *env)
5299 {
5300 gen_spr_ne_601(env);
5301 gen_spr_sdr1(env);
5302 gen_spr_602(env);
5303 /* Time base */
5304 gen_tbl(env);
5305 /* hardware implementation registers */
5306 /* XXX : not implemented */
5307 spr_register(env, SPR_HID0, "HID0",
5308 SPR_NOACCESS, SPR_NOACCESS,
5309 &spr_read_generic, &spr_write_generic,
5310 0x00000000);
5311 /* XXX : not implemented */
5312 spr_register(env, SPR_HID1, "HID1",
5313 SPR_NOACCESS, SPR_NOACCESS,
5314 &spr_read_generic, &spr_write_generic,
5315 0x00000000);
5316 /* Memory management */
5317 gen_low_BATs(env);
5318 gen_6xx_7xx_soft_tlb(env, 64, 2);
5319 init_excp_602(env);
5320 env->dcache_line_size = 32;
5321 env->icache_line_size = 32;
5322 /* Allocate hardware IRQ controller */
5323 ppc6xx_irq_init(ppc_env_get_cpu(env));
5324 }
5325
5326 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5327 {
5328 DeviceClass *dc = DEVICE_CLASS(oc);
5329 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5330
5331 dc->desc = "PowerPC 602";
5332 pcc->init_proc = init_proc_602;
5333 pcc->check_pow = check_pow_hid0;
5334 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5335 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5336 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5337 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5338 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5339 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5340 PPC_SEGMENT | PPC_602_SPEC;
5341 pcc->msr_mask = (1ull << MSR_VSX) |
5342 (1ull << MSR_SA) |
5343 (1ull << MSR_POW) |
5344 (1ull << MSR_TGPR) |
5345 (1ull << MSR_ILE) |
5346 (1ull << MSR_EE) |
5347 (1ull << MSR_PR) |
5348 (1ull << MSR_FP) |
5349 (1ull << MSR_ME) |
5350 (1ull << MSR_FE0) |
5351 (1ull << MSR_SE) |
5352 (1ull << MSR_DE) |
5353 (1ull << MSR_FE1) |
5354 (1ull << MSR_EP) |
5355 (1ull << MSR_IR) |
5356 (1ull << MSR_DR) |
5357 (1ull << MSR_RI) |
5358 (1ull << MSR_LE);
5359 /* XXX: 602 MMU is quite specific. Should add a special case */
5360 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5361 pcc->excp_model = POWERPC_EXCP_602;
5362 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5363 pcc->bfd_mach = bfd_mach_ppc_602;
5364 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5365 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5366 }
5367
5368 static void init_proc_603(CPUPPCState *env)
5369 {
5370 gen_spr_ne_601(env);
5371 gen_spr_sdr1(env);
5372 gen_spr_603(env);
5373 /* Time base */
5374 gen_tbl(env);
5375 /* hardware implementation registers */
5376 /* XXX : not implemented */
5377 spr_register(env, SPR_HID0, "HID0",
5378 SPR_NOACCESS, SPR_NOACCESS,
5379 &spr_read_generic, &spr_write_generic,
5380 0x00000000);
5381 /* XXX : not implemented */
5382 spr_register(env, SPR_HID1, "HID1",
5383 SPR_NOACCESS, SPR_NOACCESS,
5384 &spr_read_generic, &spr_write_generic,
5385 0x00000000);
5386 /* Memory management */
5387 gen_low_BATs(env);
5388 gen_6xx_7xx_soft_tlb(env, 64, 2);
5389 init_excp_603(env);
5390 env->dcache_line_size = 32;
5391 env->icache_line_size = 32;
5392 /* Allocate hardware IRQ controller */
5393 ppc6xx_irq_init(ppc_env_get_cpu(env));
5394 }
5395
5396 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5397 {
5398 DeviceClass *dc = DEVICE_CLASS(oc);
5399 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5400
5401 dc->desc = "PowerPC 603";
5402 pcc->init_proc = init_proc_603;
5403 pcc->check_pow = check_pow_hid0;
5404 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5405 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5406 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5407 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5408 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5409 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5410 PPC_SEGMENT | PPC_EXTERN;
5411 pcc->msr_mask = (1ull << MSR_POW) |
5412 (1ull << MSR_TGPR) |
5413 (1ull << MSR_ILE) |
5414 (1ull << MSR_EE) |
5415 (1ull << MSR_PR) |
5416 (1ull << MSR_FP) |
5417 (1ull << MSR_ME) |
5418 (1ull << MSR_FE0) |
5419 (1ull << MSR_SE) |
5420 (1ull << MSR_DE) |
5421 (1ull << MSR_FE1) |
5422 (1ull << MSR_EP) |
5423 (1ull << MSR_IR) |
5424 (1ull << MSR_DR) |
5425 (1ull << MSR_RI) |
5426 (1ull << MSR_LE);
5427 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5428 pcc->excp_model = POWERPC_EXCP_603;
5429 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5430 pcc->bfd_mach = bfd_mach_ppc_603;
5431 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5432 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5433 }
5434
5435 static void init_proc_603E(CPUPPCState *env)
5436 {
5437 gen_spr_ne_601(env);
5438 gen_spr_sdr1(env);
5439 gen_spr_603(env);
5440 /* Time base */
5441 gen_tbl(env);
5442 /* hardware implementation registers */
5443 /* XXX : not implemented */
5444 spr_register(env, SPR_HID0, "HID0",
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448 /* XXX : not implemented */
5449 spr_register(env, SPR_HID1, "HID1",
5450 SPR_NOACCESS, SPR_NOACCESS,
5451 &spr_read_generic, &spr_write_generic,
5452 0x00000000);
5453 /* Memory management */
5454 gen_low_BATs(env);
5455 gen_6xx_7xx_soft_tlb(env, 64, 2);
5456 init_excp_603(env);
5457 env->dcache_line_size = 32;
5458 env->icache_line_size = 32;
5459 /* Allocate hardware IRQ controller */
5460 ppc6xx_irq_init(ppc_env_get_cpu(env));
5461 }
5462
5463 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5464 {
5465 DeviceClass *dc = DEVICE_CLASS(oc);
5466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5467
5468 dc->desc = "PowerPC 603e";
5469 pcc->init_proc = init_proc_603E;
5470 pcc->check_pow = check_pow_hid0;
5471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5473 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5474 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5475 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5476 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5477 PPC_SEGMENT | PPC_EXTERN;
5478 pcc->msr_mask = (1ull << MSR_POW) |
5479 (1ull << MSR_TGPR) |
5480 (1ull << MSR_ILE) |
5481 (1ull << MSR_EE) |
5482 (1ull << MSR_PR) |
5483 (1ull << MSR_FP) |
5484 (1ull << MSR_ME) |
5485 (1ull << MSR_FE0) |
5486 (1ull << MSR_SE) |
5487 (1ull << MSR_DE) |
5488 (1ull << MSR_FE1) |
5489 (1ull << MSR_EP) |
5490 (1ull << MSR_IR) |
5491 (1ull << MSR_DR) |
5492 (1ull << MSR_RI) |
5493 (1ull << MSR_LE);
5494 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5495 pcc->excp_model = POWERPC_EXCP_603E;
5496 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5497 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5498 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5499 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5500 }
5501
5502 static void init_proc_604(CPUPPCState *env)
5503 {
5504 gen_spr_ne_601(env);
5505 gen_spr_sdr1(env);
5506 gen_spr_604(env);
5507 /* Time base */
5508 gen_tbl(env);
5509 /* Hardware implementation registers */
5510 /* XXX : not implemented */
5511 spr_register(env, SPR_HID0, "HID0",
5512 SPR_NOACCESS, SPR_NOACCESS,
5513 &spr_read_generic, &spr_write_generic,
5514 0x00000000);
5515 /* Memory management */
5516 gen_low_BATs(env);
5517 init_excp_604(env);
5518 env->dcache_line_size = 32;
5519 env->icache_line_size = 32;
5520 /* Allocate hardware IRQ controller */
5521 ppc6xx_irq_init(ppc_env_get_cpu(env));
5522 }
5523
5524 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5525 {
5526 DeviceClass *dc = DEVICE_CLASS(oc);
5527 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5528
5529 dc->desc = "PowerPC 604";
5530 pcc->init_proc = init_proc_604;
5531 pcc->check_pow = check_pow_nocheck;
5532 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5533 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5534 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5535 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5536 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5537 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5538 PPC_SEGMENT | PPC_EXTERN;
5539 pcc->msr_mask = (1ull << MSR_POW) |
5540 (1ull << MSR_ILE) |
5541 (1ull << MSR_EE) |
5542 (1ull << MSR_PR) |
5543 (1ull << MSR_FP) |
5544 (1ull << MSR_ME) |
5545 (1ull << MSR_FE0) |
5546 (1ull << MSR_SE) |
5547 (1ull << MSR_DE) |
5548 (1ull << MSR_FE1) |
5549 (1ull << MSR_EP) |
5550 (1ull << MSR_IR) |
5551 (1ull << MSR_DR) |
5552 (1ull << MSR_PMM) |
5553 (1ull << MSR_RI) |
5554 (1ull << MSR_LE);
5555 pcc->mmu_model = POWERPC_MMU_32B;
5556 #if defined(CONFIG_SOFTMMU)
5557 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5558 #endif
5559 pcc->excp_model = POWERPC_EXCP_604;
5560 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5561 pcc->bfd_mach = bfd_mach_ppc_604;
5562 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5563 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5564 }
5565
5566 static void init_proc_604E(CPUPPCState *env)
5567 {
5568 gen_spr_ne_601(env);
5569 gen_spr_sdr1(env);
5570 gen_spr_604(env);
5571 /* XXX : not implemented */
5572 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5573 SPR_NOACCESS, SPR_NOACCESS,
5574 &spr_read_generic, &spr_write_generic,
5575 0x00000000);
5576 /* XXX : not implemented */
5577 spr_register(env, SPR_7XX_PMC3, "PMC3",
5578 SPR_NOACCESS, SPR_NOACCESS,
5579 &spr_read_generic, &spr_write_generic,
5580 0x00000000);
5581 /* XXX : not implemented */
5582 spr_register(env, SPR_7XX_PMC4, "PMC4",
5583 SPR_NOACCESS, SPR_NOACCESS,
5584 &spr_read_generic, &spr_write_generic,
5585 0x00000000);
5586 /* Time base */
5587 gen_tbl(env);
5588 /* Hardware implementation registers */
5589 /* XXX : not implemented */
5590 spr_register(env, SPR_HID0, "HID0",
5591 SPR_NOACCESS, SPR_NOACCESS,
5592 &spr_read_generic, &spr_write_generic,
5593 0x00000000);
5594 /* XXX : not implemented */
5595 spr_register(env, SPR_HID1, "HID1",
5596 SPR_NOACCESS, SPR_NOACCESS,
5597 &spr_read_generic, &spr_write_generic,
5598 0x00000000);
5599 /* Memory management */
5600 gen_low_BATs(env);
5601 init_excp_604(env);
5602 env->dcache_line_size = 32;
5603 env->icache_line_size = 32;
5604 /* Allocate hardware IRQ controller */
5605 ppc6xx_irq_init(ppc_env_get_cpu(env));
5606 }
5607
5608 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5609 {
5610 DeviceClass *dc = DEVICE_CLASS(oc);
5611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5612
5613 dc->desc = "PowerPC 604E";
5614 pcc->init_proc = init_proc_604E;
5615 pcc->check_pow = check_pow_nocheck;
5616 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5617 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5618 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5619 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5620 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5621 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5622 PPC_SEGMENT | PPC_EXTERN;
5623 pcc->msr_mask = (1ull << MSR_POW) |
5624 (1ull << MSR_ILE) |
5625 (1ull << MSR_EE) |
5626 (1ull << MSR_PR) |
5627 (1ull << MSR_FP) |
5628 (1ull << MSR_ME) |
5629 (1ull << MSR_FE0) |
5630 (1ull << MSR_SE) |
5631 (1ull << MSR_DE) |
5632 (1ull << MSR_FE1) |
5633 (1ull << MSR_EP) |
5634 (1ull << MSR_IR) |
5635 (1ull << MSR_DR) |
5636 (1ull << MSR_PMM) |
5637 (1ull << MSR_RI) |
5638 (1ull << MSR_LE);
5639 pcc->mmu_model = POWERPC_MMU_32B;
5640 #if defined(CONFIG_SOFTMMU)
5641 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5642 #endif
5643 pcc->excp_model = POWERPC_EXCP_604;
5644 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5645 pcc->bfd_mach = bfd_mach_ppc_604;
5646 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5647 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5648 }
5649
5650 static void init_proc_740(CPUPPCState *env)
5651 {
5652 gen_spr_ne_601(env);
5653 gen_spr_sdr1(env);
5654 gen_spr_7xx(env);
5655 /* Time base */
5656 gen_tbl(env);
5657 /* Thermal management */
5658 gen_spr_thrm(env);
5659 /* Hardware implementation registers */
5660 /* XXX : not implemented */
5661 spr_register(env, SPR_HID0, "HID0",
5662 SPR_NOACCESS, SPR_NOACCESS,
5663 &spr_read_generic, &spr_write_generic,
5664 0x00000000);
5665 /* XXX : not implemented */
5666 spr_register(env, SPR_HID1, "HID1",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_generic, &spr_write_generic,
5669 0x00000000);
5670 /* Memory management */
5671 gen_low_BATs(env);
5672 init_excp_7x0(env);
5673 env->dcache_line_size = 32;
5674 env->icache_line_size = 32;
5675 /* Allocate hardware IRQ controller */
5676 ppc6xx_irq_init(ppc_env_get_cpu(env));
5677 }
5678
5679 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5680 {
5681 DeviceClass *dc = DEVICE_CLASS(oc);
5682 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5683
5684 dc->desc = "PowerPC 740";
5685 pcc->init_proc = init_proc_740;
5686 pcc->check_pow = check_pow_hid0;
5687 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5688 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5689 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5690 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5691 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5692 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5693 PPC_SEGMENT | PPC_EXTERN;
5694 pcc->msr_mask = (1ull << MSR_POW) |
5695 (1ull << MSR_ILE) |
5696 (1ull << MSR_EE) |
5697 (1ull << MSR_PR) |
5698 (1ull << MSR_FP) |
5699 (1ull << MSR_ME) |
5700 (1ull << MSR_FE0) |
5701 (1ull << MSR_SE) |
5702 (1ull << MSR_DE) |
5703 (1ull << MSR_FE1) |
5704 (1ull << MSR_EP) |
5705 (1ull << MSR_IR) |
5706 (1ull << MSR_DR) |
5707 (1ull << MSR_PMM) |
5708 (1ull << MSR_RI) |
5709 (1ull << MSR_LE);
5710 pcc->mmu_model = POWERPC_MMU_32B;
5711 #if defined(CONFIG_SOFTMMU)
5712 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5713 #endif
5714 pcc->excp_model = POWERPC_EXCP_7x0;
5715 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5716 pcc->bfd_mach = bfd_mach_ppc_750;
5717 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5718 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5719 }
5720
5721 static void init_proc_750(CPUPPCState *env)
5722 {
5723 gen_spr_ne_601(env);
5724 gen_spr_sdr1(env);
5725 gen_spr_7xx(env);
5726 /* XXX : not implemented */
5727 spr_register(env, SPR_L2CR, "L2CR",
5728 SPR_NOACCESS, SPR_NOACCESS,
5729 &spr_read_generic, spr_access_nop,
5730 0x00000000);
5731 /* Time base */
5732 gen_tbl(env);
5733 /* Thermal management */
5734 gen_spr_thrm(env);
5735 /* Hardware implementation registers */
5736 /* XXX : not implemented */
5737 spr_register(env, SPR_HID0, "HID0",
5738 SPR_NOACCESS, SPR_NOACCESS,
5739 &spr_read_generic, &spr_write_generic,
5740 0x00000000);
5741 /* XXX : not implemented */
5742 spr_register(env, SPR_HID1, "HID1",
5743 SPR_NOACCESS, SPR_NOACCESS,
5744 &spr_read_generic, &spr_write_generic,
5745 0x00000000);
5746 /* Memory management */
5747 gen_low_BATs(env);
5748 /* XXX: high BATs are also present but are known to be bugged on
5749 * die version 1.x
5750 */
5751 init_excp_7x0(env);
5752 env->dcache_line_size = 32;
5753 env->icache_line_size = 32;
5754 /* Allocate hardware IRQ controller */
5755 ppc6xx_irq_init(ppc_env_get_cpu(env));
5756 }
5757
5758 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5759 {
5760 DeviceClass *dc = DEVICE_CLASS(oc);
5761 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5762
5763 dc->desc = "PowerPC 750";
5764 pcc->init_proc = init_proc_750;
5765 pcc->check_pow = check_pow_hid0;
5766 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5767 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5768 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5769 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5770 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5771 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5772 PPC_SEGMENT | PPC_EXTERN;
5773 pcc->msr_mask = (1ull << MSR_POW) |
5774 (1ull << MSR_ILE) |
5775 (1ull << MSR_EE) |
5776 (1ull << MSR_PR) |
5777 (1ull << MSR_FP) |
5778 (1ull << MSR_ME) |
5779 (1ull << MSR_FE0) |
5780 (1ull << MSR_SE) |
5781 (1ull << MSR_DE) |
5782 (1ull << MSR_FE1) |
5783 (1ull << MSR_EP) |
5784 (1ull << MSR_IR) |
5785 (1ull << MSR_DR) |
5786 (1ull << MSR_PMM) |
5787 (1ull << MSR_RI) |
5788 (1ull << MSR_LE);
5789 pcc->mmu_model = POWERPC_MMU_32B;
5790 #if defined(CONFIG_SOFTMMU)
5791 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5792 #endif
5793 pcc->excp_model = POWERPC_EXCP_7x0;
5794 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5795 pcc->bfd_mach = bfd_mach_ppc_750;
5796 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5797 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5798 }
5799
5800 static void init_proc_750cl(CPUPPCState *env)
5801 {
5802 gen_spr_ne_601(env);
5803 gen_spr_sdr1(env);
5804 gen_spr_7xx(env);
5805 /* XXX : not implemented */
5806 spr_register(env, SPR_L2CR, "L2CR",
5807 SPR_NOACCESS, SPR_NOACCESS,
5808 &spr_read_generic, spr_access_nop,
5809 0x00000000);
5810 /* Time base */
5811 gen_tbl(env);
5812 /* Thermal management */
5813 /* Those registers are fake on 750CL */
5814 spr_register(env, SPR_THRM1, "THRM1",
5815 SPR_NOACCESS, SPR_NOACCESS,
5816 &spr_read_generic, &spr_write_generic,
5817 0x00000000);
5818 spr_register(env, SPR_THRM2, "THRM2",
5819 SPR_NOACCESS, SPR_NOACCESS,
5820 &spr_read_generic, &spr_write_generic,
5821 0x00000000);
5822 spr_register(env, SPR_THRM3, "THRM3",
5823 SPR_NOACCESS, SPR_NOACCESS,
5824 &spr_read_generic, &spr_write_generic,
5825 0x00000000);
5826 /* XXX: not implemented */
5827 spr_register(env, SPR_750_TDCL, "TDCL",
5828 SPR_NOACCESS, SPR_NOACCESS,
5829 &spr_read_generic, &spr_write_generic,
5830 0x00000000);
5831 spr_register(env, SPR_750_TDCH, "TDCH",
5832 SPR_NOACCESS, SPR_NOACCESS,
5833 &spr_read_generic, &spr_write_generic,
5834 0x00000000);
5835 /* DMA */
5836 /* XXX : not implemented */
5837 spr_register(env, SPR_750_WPAR, "WPAR",
5838 SPR_NOACCESS, SPR_NOACCESS,
5839 &spr_read_generic, &spr_write_generic,
5840 0x00000000);
5841 spr_register(env, SPR_750_DMAL, "DMAL",
5842 SPR_NOACCESS, SPR_NOACCESS,
5843 &spr_read_generic, &spr_write_generic,
5844 0x00000000);
5845 spr_register(env, SPR_750_DMAU, "DMAU",
5846 SPR_NOACCESS, SPR_NOACCESS,
5847 &spr_read_generic, &spr_write_generic,
5848 0x00000000);
5849 /* Hardware implementation registers */
5850 /* XXX : not implemented */
5851 spr_register(env, SPR_HID0, "HID0",
5852 SPR_NOACCESS, SPR_NOACCESS,
5853 &spr_read_generic, &spr_write_generic,
5854 0x00000000);
5855 /* XXX : not implemented */
5856 spr_register(env, SPR_HID1, "HID1",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 &spr_read_generic, &spr_write_generic,
5859 0x00000000);
5860 /* XXX : not implemented */
5861 spr_register(env, SPR_750CL_HID2, "HID2",
5862 SPR_NOACCESS, SPR_NOACCESS,
5863 &spr_read_generic, &spr_write_generic,
5864 0x00000000);
5865 /* XXX : not implemented */
5866 spr_register(env, SPR_750CL_HID4, "HID4",
5867 SPR_NOACCESS, SPR_NOACCESS,
5868 &spr_read_generic, &spr_write_generic,
5869 0x00000000);
5870 /* Quantization registers */
5871 /* XXX : not implemented */
5872 spr_register(env, SPR_750_GQR0, "GQR0",
5873 SPR_NOACCESS, SPR_NOACCESS,
5874 &spr_read_generic, &spr_write_generic,
5875 0x00000000);
5876 /* XXX : not implemented */
5877 spr_register(env, SPR_750_GQR1, "GQR1",
5878 SPR_NOACCESS, SPR_NOACCESS,
5879 &spr_read_generic, &spr_write_generic,
5880 0x00000000);
5881 /* XXX : not implemented */
5882 spr_register(env, SPR_750_GQR2, "GQR2",
5883 SPR_NOACCESS, SPR_NOACCESS,
5884 &spr_read_generic, &spr_write_generic,
5885 0x00000000);
5886 /* XXX : not implemented */
5887 spr_register(env, SPR_750_GQR3, "GQR3",
5888 SPR_NOACCESS, SPR_NOACCESS,
5889 &spr_read_generic, &spr_write_generic,
5890 0x00000000);
5891 /* XXX : not implemented */
5892 spr_register(env, SPR_750_GQR4, "GQR4",
5893 SPR_NOACCESS, SPR_NOACCESS,
5894 &spr_read_generic, &spr_write_generic,
5895 0x00000000);
5896 /* XXX : not implemented */
5897 spr_register(env, SPR_750_GQR5, "GQR5",
5898 SPR_NOACCESS, SPR_NOACCESS,
5899 &spr_read_generic, &spr_write_generic,
5900 0x00000000);
5901 /* XXX : not implemented */
5902 spr_register(env, SPR_750_GQR6, "GQR6",
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0x00000000);
5906 /* XXX : not implemented */
5907 spr_register(env, SPR_750_GQR7, "GQR7",
5908 SPR_NOACCESS, SPR_NOACCESS,
5909 &spr_read_generic, &spr_write_generic,
5910 0x00000000);
5911 /* Memory management */
5912 gen_low_BATs(env);
5913 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5914 gen_high_BATs(env);
5915 init_excp_750cl(env);
5916 env->dcache_line_size = 32;
5917 env->icache_line_size = 32;
5918 /* Allocate hardware IRQ controller */
5919 ppc6xx_irq_init(ppc_env_get_cpu(env));
5920 }
5921
5922 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5923 {
5924 DeviceClass *dc = DEVICE_CLASS(oc);
5925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5926
5927 dc->desc = "PowerPC 750 CL";
5928 pcc->init_proc = init_proc_750cl;
5929 pcc->check_pow = check_pow_hid0;
5930 /* XXX: not implemented:
5931 * cache lock instructions:
5932 * dcbz_l
5933 * floating point paired instructions
5934 * psq_lux
5935 * psq_lx
5936 * psq_stux
5937 * psq_stx
5938 * ps_abs
5939 * ps_add
5940 * ps_cmpo0
5941 * ps_cmpo1
5942 * ps_cmpu0
5943 * ps_cmpu1
5944 * ps_div
5945 * ps_madd
5946 * ps_madds0
5947 * ps_madds1
5948 * ps_merge00
5949 * ps_merge01
5950 * ps_merge10
5951 * ps_merge11
5952 * ps_mr
5953 * ps_msub
5954 * ps_mul
5955 * ps_muls0
5956 * ps_muls1
5957 * ps_nabs
5958 * ps_neg
5959 * ps_nmadd
5960 * ps_nmsub
5961 * ps_res
5962 * ps_rsqrte
5963 * ps_sel
5964 * ps_sub
5965 * ps_sum0
5966 * ps_sum1
5967 */
5968 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5969 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5970 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5971 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5972 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5973 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5974 PPC_SEGMENT | PPC_EXTERN;
5975 pcc->msr_mask = (1ull << MSR_POW) |
5976 (1ull << MSR_ILE) |
5977 (1ull << MSR_EE) |
5978 (1ull << MSR_PR) |
5979 (1ull << MSR_FP) |
5980 (1ull << MSR_ME) |
5981 (1ull << MSR_FE0) |
5982 (1ull << MSR_SE) |
5983 (1ull << MSR_DE) |
5984 (1ull << MSR_FE1) |
5985 (1ull << MSR_EP) |
5986 (1ull << MSR_IR) |
5987 (1ull << MSR_DR) |
5988 (1ull << MSR_PMM) |
5989 (1ull << MSR_RI) |
5990 (1ull << MSR_LE);
5991 pcc->mmu_model = POWERPC_MMU_32B;
5992 #if defined(CONFIG_SOFTMMU)
5993 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5994 #endif
5995 pcc->excp_model = POWERPC_EXCP_7x0;
5996 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5997 pcc->bfd_mach = bfd_mach_ppc_750;
5998 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5999 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6000 }
6001
6002 static void init_proc_750cx(CPUPPCState *env)
6003 {
6004 gen_spr_ne_601(env);
6005 gen_spr_sdr1(env);
6006 gen_spr_7xx(env);
6007 /* XXX : not implemented */
6008 spr_register(env, SPR_L2CR, "L2CR",
6009 SPR_NOACCESS, SPR_NOACCESS,
6010 &spr_read_generic, spr_access_nop,
6011 0x00000000);
6012 /* Time base */
6013 gen_tbl(env);
6014 /* Thermal management */
6015 gen_spr_thrm(env);
6016 /* This register is not implemented but is present for compatibility */
6017 spr_register(env, SPR_SDA, "SDA",
6018 SPR_NOACCESS, SPR_NOACCESS,
6019 &spr_read_generic, &spr_write_generic,
6020 0x00000000);
6021 /* Hardware implementation registers */
6022 /* XXX : not implemented */
6023 spr_register(env, SPR_HID0, "HID0",
6024 SPR_NOACCESS, SPR_NOACCESS,
6025 &spr_read_generic, &spr_write_generic,
6026 0x00000000);
6027 /* XXX : not implemented */
6028 spr_register(env, SPR_HID1, "HID1",
6029 SPR_NOACCESS, SPR_NOACCESS,
6030 &spr_read_generic, &spr_write_generic,
6031 0x00000000);
6032 /* Memory management */
6033 gen_low_BATs(env);
6034 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6035 gen_high_BATs(env);
6036 init_excp_750cx(env);
6037 env->dcache_line_size = 32;
6038 env->icache_line_size = 32;
6039 /* Allocate hardware IRQ controller */
6040 ppc6xx_irq_init(ppc_env_get_cpu(env));
6041 }
6042
6043 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6044 {
6045 DeviceClass *dc = DEVICE_CLASS(oc);
6046 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6047
6048 dc->desc = "PowerPC 750CX";
6049 pcc->init_proc = init_proc_750cx;
6050 pcc->check_pow = check_pow_hid0;
6051 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6052 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6053 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6054 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6055 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6056 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6057 PPC_SEGMENT | PPC_EXTERN;
6058 pcc->msr_mask = (1ull << MSR_POW) |
6059 (1ull << MSR_ILE) |
6060 (1ull << MSR_EE) |
6061 (1ull << MSR_PR) |
6062 (1ull << MSR_FP) |
6063 (1ull << MSR_ME) |
6064 (1ull << MSR_FE0) |
6065 (1ull << MSR_SE) |
6066 (1ull << MSR_DE) |
6067 (1ull << MSR_FE1) |
6068 (1ull << MSR_EP) |
6069 (1ull << MSR_IR) |
6070 (1ull << MSR_DR) |
6071 (1ull << MSR_PMM) |
6072 (1ull << MSR_RI) |
6073 (1ull << MSR_LE);
6074 pcc->mmu_model = POWERPC_MMU_32B;
6075 #if defined(CONFIG_SOFTMMU)
6076 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6077 #endif
6078 pcc->excp_model = POWERPC_EXCP_7x0;
6079 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6080 pcc->bfd_mach = bfd_mach_ppc_750;
6081 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6082 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6083 }
6084
6085 static void init_proc_750fx(CPUPPCState *env)
6086 {
6087 gen_spr_ne_601(env);
6088 gen_spr_sdr1(env);
6089 gen_spr_7xx(env);
6090 /* XXX : not implemented */
6091 spr_register(env, SPR_L2CR, "L2CR",
6092 SPR_NOACCESS, SPR_NOACCESS,
6093 &spr_read_generic, spr_access_nop,
6094 0x00000000);
6095 /* Time base */
6096 gen_tbl(env);
6097 /* Thermal management */
6098 gen_spr_thrm(env);
6099 /* XXX : not implemented */
6100 spr_register(env, SPR_750_THRM4, "THRM4",
6101 SPR_NOACCESS, SPR_NOACCESS,
6102 &spr_read_generic, &spr_write_generic,
6103 0x00000000);
6104 /* Hardware implementation registers */
6105 /* XXX : not implemented */
6106 spr_register(env, SPR_HID0, "HID0",
6107 SPR_NOACCESS, SPR_NOACCESS,
6108 &spr_read_generic, &spr_write_generic,
6109 0x00000000);
6110 /* XXX : not implemented */
6111 spr_register(env, SPR_HID1, "HID1",
6112 SPR_NOACCESS, SPR_NOACCESS,
6113 &spr_read_generic, &spr_write_generic,
6114 0x00000000);
6115 /* XXX : not implemented */
6116 spr_register(env, SPR_750FX_HID2, "HID2",
6117 SPR_NOACCESS, SPR_NOACCESS,
6118 &spr_read_generic, &spr_write_generic,
6119 0x00000000);
6120 /* Memory management */
6121 gen_low_BATs(env);
6122 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6123 gen_high_BATs(env);
6124 init_excp_7x0(env);
6125 env->dcache_line_size = 32;
6126 env->icache_line_size = 32;
6127 /* Allocate hardware IRQ controller */
6128 ppc6xx_irq_init(ppc_env_get_cpu(env));
6129 }
6130
6131 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6132 {
6133 DeviceClass *dc = DEVICE_CLASS(oc);
6134 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6135
6136 dc->desc = "PowerPC 750FX";
6137 pcc->init_proc = init_proc_750fx;
6138 pcc->check_pow = check_pow_hid0;
6139 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6140 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6141 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6142 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6143 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6144 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6145 PPC_SEGMENT | PPC_EXTERN;
6146 pcc->msr_mask = (1ull << MSR_POW) |
6147 (1ull << MSR_ILE) |
6148 (1ull << MSR_EE) |
6149 (1ull << MSR_PR) |
6150 (1ull << MSR_FP) |
6151 (1ull << MSR_ME) |
6152 (1ull << MSR_FE0) |
6153 (1ull << MSR_SE) |
6154 (1ull << MSR_DE) |
6155 (1ull << MSR_FE1) |
6156 (1ull << MSR_EP) |
6157 (1ull << MSR_IR) |
6158 (1ull << MSR_DR) |
6159 (1ull << MSR_PMM) |
6160 (1ull << MSR_RI) |
6161 (1ull << MSR_LE);
6162 pcc->mmu_model = POWERPC_MMU_32B;
6163 #if defined(CONFIG_SOFTMMU)
6164 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6165 #endif
6166 pcc->excp_model = POWERPC_EXCP_7x0;
6167 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6168 pcc->bfd_mach = bfd_mach_ppc_750;
6169 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6170 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6171 }
6172
6173 static void init_proc_750gx(CPUPPCState *env)
6174 {
6175 gen_spr_ne_601(env);
6176 gen_spr_sdr1(env);
6177 gen_spr_7xx(env);
6178 /* XXX : not implemented (XXX: different from 750fx) */
6179 spr_register(env, SPR_L2CR, "L2CR",
6180 SPR_NOACCESS, SPR_NOACCESS,
6181 &spr_read_generic, spr_access_nop,
6182 0x00000000);
6183 /* Time base */
6184 gen_tbl(env);
6185 /* Thermal management */
6186 gen_spr_thrm(env);
6187 /* XXX : not implemented */
6188 spr_register(env, SPR_750_THRM4, "THRM4",
6189 SPR_NOACCESS, SPR_NOACCESS,
6190 &spr_read_generic, &spr_write_generic,
6191 0x00000000);
6192 /* Hardware implementation registers */
6193 /* XXX : not implemented (XXX: different from 750fx) */
6194 spr_register(env, SPR_HID0, "HID0",
6195 SPR_NOACCESS, SPR_NOACCESS,
6196 &spr_read_generic, &spr_write_generic,
6197 0x00000000);
6198 /* XXX : not implemented */
6199 spr_register(env, SPR_HID1, "HID1",
6200 SPR_NOACCESS, SPR_NOACCESS,
6201 &spr_read_generic, &spr_write_generic,
6202 0x00000000);
6203 /* XXX : not implemented (XXX: different from 750fx) */
6204 spr_register(env, SPR_750FX_HID2, "HID2",
6205 SPR_NOACCESS, SPR_NOACCESS,
6206 &spr_read_generic, &spr_write_generic,
6207 0x00000000);
6208 /* Memory management */
6209 gen_low_BATs(env);
6210 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6211 gen_high_BATs(env);
6212 init_excp_7x0(env);
6213 env->dcache_line_size = 32;
6214 env->icache_line_size = 32;
6215 /* Allocate hardware IRQ controller */
6216 ppc6xx_irq_init(ppc_env_get_cpu(env));
6217 }
6218
6219 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6220 {
6221 DeviceClass *dc = DEVICE_CLASS(oc);
6222 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6223
6224 dc->desc = "PowerPC 750GX";
6225 pcc->init_proc = init_proc_750gx;
6226 pcc->check_pow = check_pow_hid0;
6227 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6228 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6229 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6230 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6231 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6232 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6233 PPC_SEGMENT | PPC_EXTERN;
6234 pcc->msr_mask = (1ull << MSR_POW) |
6235 (1ull << MSR_ILE) |
6236 (1ull << MSR_EE) |
6237 (1ull << MSR_PR) |
6238 (1ull << MSR_FP) |
6239 (1ull << MSR_ME) |
6240 (1ull << MSR_FE0) |
6241 (1ull << MSR_SE) |
6242 (1ull << MSR_DE) |
6243 (1ull << MSR_FE1) |
6244 (1ull << MSR_EP) |
6245 (1ull << MSR_IR) |
6246 (1ull << MSR_DR) |
6247 (1ull << MSR_PMM) |
6248 (1ull << MSR_RI) |
6249 (1ull << MSR_LE);
6250 pcc->mmu_model = POWERPC_MMU_32B;
6251 #if defined(CONFIG_SOFTMMU)
6252 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6253 #endif
6254 pcc->excp_model = POWERPC_EXCP_7x0;
6255 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6256 pcc->bfd_mach = bfd_mach_ppc_750;
6257 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6258 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6259 }
6260
6261 static void init_proc_745(CPUPPCState *env)
6262 {
6263 gen_spr_ne_601(env);
6264 gen_spr_sdr1(env);
6265 gen_spr_7xx(env);
6266 gen_spr_G2_755(env);
6267 /* Time base */
6268 gen_tbl(env);
6269 /* Thermal management */
6270 gen_spr_thrm(env);
6271 /* Hardware implementation registers */
6272 /* XXX : not implemented */
6273 spr_register(env, SPR_HID0, "HID0",
6274 SPR_NOACCESS, SPR_NOACCESS,
6275 &spr_read_generic, &spr_write_generic,
6276 0x00000000);
6277 /* XXX : not implemented */
6278 spr_register(env, SPR_HID1, "HID1",
6279 SPR_NOACCESS, SPR_NOACCESS,
6280 &spr_read_generic, &spr_write_generic,
6281 0x00000000);
6282 /* XXX : not implemented */
6283 spr_register(env, SPR_HID2, "HID2",
6284 SPR_NOACCESS, SPR_NOACCESS,
6285 &spr_read_generic, &spr_write_generic,
6286 0x00000000);
6287 /* Memory management */
6288 gen_low_BATs(env);
6289 gen_high_BATs(env);
6290 gen_6xx_7xx_soft_tlb(env, 64, 2);
6291 init_excp_7x5(env);
6292 env->dcache_line_size = 32;
6293 env->icache_line_size = 32;
6294 /* Allocate hardware IRQ controller */
6295 ppc6xx_irq_init(ppc_env_get_cpu(env));
6296 }
6297
6298 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6299 {
6300 DeviceClass *dc = DEVICE_CLASS(oc);
6301 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6302
6303 dc->desc = "PowerPC 745";
6304 pcc->init_proc = init_proc_745;
6305 pcc->check_pow = check_pow_hid0;
6306 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6307 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6308 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6309 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6310 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6311 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6312 PPC_SEGMENT | PPC_EXTERN;
6313 pcc->msr_mask = (1ull << MSR_POW) |
6314 (1ull << MSR_ILE) |
6315 (1ull << MSR_EE) |
6316 (1ull << MSR_PR) |
6317 (1ull << MSR_FP) |
6318 (1ull << MSR_ME) |
6319 (1ull << MSR_FE0) |
6320 (1ull << MSR_SE) |
6321 (1ull << MSR_DE) |
6322 (1ull << MSR_FE1) |
6323 (1ull << MSR_EP) |
6324 (1ull << MSR_IR) |
6325 (1ull << MSR_DR) |
6326 (1ull << MSR_PMM) |
6327 (1ull << MSR_RI) |
6328 (1ull << MSR_LE);
6329 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6330 pcc->excp_model = POWERPC_EXCP_7x5;
6331 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6332 pcc->bfd_mach = bfd_mach_ppc_750;
6333 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6334 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6335 }
6336
6337 static void init_proc_755(CPUPPCState *env)
6338 {
6339 gen_spr_ne_601(env);
6340 gen_spr_sdr1(env);
6341 gen_spr_7xx(env);
6342 gen_spr_G2_755(env);
6343 /* Time base */
6344 gen_tbl(env);
6345 /* L2 cache control */
6346 /* XXX : not implemented */
6347 spr_register(env, SPR_L2CR, "L2CR",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, spr_access_nop,
6350 0x00000000);
6351 /* XXX : not implemented */
6352 spr_register(env, SPR_L2PMCR, "L2PMCR",
6353 SPR_NOACCESS, SPR_NOACCESS,
6354 &spr_read_generic, &spr_write_generic,
6355 0x00000000);
6356 /* Thermal management */
6357 gen_spr_thrm(env);
6358 /* Hardware implementation registers */
6359 /* XXX : not implemented */
6360 spr_register(env, SPR_HID0, "HID0",
6361 SPR_NOACCESS, SPR_NOACCESS,
6362 &spr_read_generic, &spr_write_generic,
6363 0x00000000);
6364 /* XXX : not implemented */
6365 spr_register(env, SPR_HID1, "HID1",
6366 SPR_NOACCESS, SPR_NOACCESS,
6367 &spr_read_generic, &spr_write_generic,
6368 0x00000000);
6369 /* XXX : not implemented */
6370 spr_register(env, SPR_HID2, "HID2",
6371 SPR_NOACCESS, SPR_NOACCESS,
6372 &spr_read_generic, &spr_write_generic,
6373 0x00000000);
6374 /* Memory management */
6375 gen_low_BATs(env);
6376 gen_high_BATs(env);
6377 gen_6xx_7xx_soft_tlb(env, 64, 2);
6378 init_excp_7x5(env);
6379 env->dcache_line_size = 32;
6380 env->icache_line_size = 32;
6381 /* Allocate hardware IRQ controller */
6382 ppc6xx_irq_init(ppc_env_get_cpu(env));
6383 }
6384
6385 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6386 {
6387 DeviceClass *dc = DEVICE_CLASS(oc);
6388 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6389
6390 dc->desc = "PowerPC 755";
6391 pcc->init_proc = init_proc_755;
6392 pcc->check_pow = check_pow_hid0;
6393 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6394 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6395 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6396 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6397 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6398 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6399 PPC_SEGMENT | PPC_EXTERN;
6400 pcc->msr_mask = (1ull << MSR_POW) |
6401 (1ull << MSR_ILE) |
6402 (1ull << MSR_EE) |
6403 (1ull << MSR_PR) |
6404 (1ull << MSR_FP) |
6405 (1ull << MSR_ME) |
6406 (1ull << MSR_FE0) |
6407 (1ull << MSR_SE) |
6408 (1ull << MSR_DE) |
6409 (1ull << MSR_FE1) |
6410 (1ull << MSR_EP) |
6411 (1ull << MSR_IR) |
6412 (1ull << MSR_DR) |
6413 (1ull << MSR_PMM) |
6414 (1ull << MSR_RI) |
6415 (1ull << MSR_LE);
6416 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6417 pcc->excp_model = POWERPC_EXCP_7x5;
6418 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6419 pcc->bfd_mach = bfd_mach_ppc_750;
6420 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6421 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6422 }
6423
6424 static void init_proc_7400(CPUPPCState *env)
6425 {
6426 gen_spr_ne_601(env);
6427 gen_spr_sdr1(env);
6428 gen_spr_7xx(env);
6429 /* Time base */
6430 gen_tbl(env);
6431 /* 74xx specific SPR */
6432 gen_spr_74xx(env);
6433 /* XXX : not implemented */
6434 spr_register(env, SPR_UBAMR, "UBAMR",
6435 &spr_read_ureg, SPR_NOACCESS,
6436 &spr_read_ureg, SPR_NOACCESS,
6437 0x00000000);
6438 /* XXX: this seems not implemented on all revisions. */
6439 /* XXX : not implemented */
6440 spr_register(env, SPR_MSSCR1, "MSSCR1",
6441 SPR_NOACCESS, SPR_NOACCESS,
6442 &spr_read_generic, &spr_write_generic,
6443 0x00000000);
6444 /* Thermal management */
6445 gen_spr_thrm(env);
6446 /* Memory management */
6447 gen_low_BATs(env);
6448 init_excp_7400(env);
6449 env->dcache_line_size = 32;
6450 env->icache_line_size = 32;
6451 /* Allocate hardware IRQ controller */
6452 ppc6xx_irq_init(ppc_env_get_cpu(env));
6453 }
6454
6455 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6456 {
6457 DeviceClass *dc = DEVICE_CLASS(oc);
6458 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6459
6460 dc->desc = "PowerPC 7400 (aka G4)";
6461 pcc->init_proc = init_proc_7400;
6462 pcc->check_pow = check_pow_hid0;
6463 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6464 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6465 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6466 PPC_FLOAT_STFIWX |
6467 PPC_CACHE | PPC_CACHE_ICBI |
6468 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6469 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6470 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6471 PPC_MEM_TLBIA |
6472 PPC_SEGMENT | PPC_EXTERN |
6473 PPC_ALTIVEC;
6474 pcc->msr_mask = (1ull << MSR_VR) |
6475 (1ull << MSR_POW) |
6476 (1ull << MSR_ILE) |
6477 (1ull << MSR_EE) |
6478 (1ull << MSR_PR) |
6479 (1ull << MSR_FP) |
6480 (1ull << MSR_ME) |
6481 (1ull << MSR_FE0) |
6482 (1ull << MSR_SE) |
6483 (1ull << MSR_DE) |
6484 (1ull << MSR_FE1) |
6485 (1ull << MSR_EP) |
6486 (1ull << MSR_IR) |
6487 (1ull << MSR_DR) |
6488 (1ull << MSR_PMM) |
6489 (1ull << MSR_RI) |
6490 (1ull << MSR_LE);
6491 pcc->mmu_model = POWERPC_MMU_32B;
6492 #if defined(CONFIG_SOFTMMU)
6493 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6494 #endif
6495 pcc->excp_model = POWERPC_EXCP_74xx;
6496 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6497 pcc->bfd_mach = bfd_mach_ppc_7400;
6498 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6499 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6500 POWERPC_FLAG_BUS_CLK;
6501 }
6502
6503 static void init_proc_7410(CPUPPCState *env)
6504 {
6505 gen_spr_ne_601(env);
6506 gen_spr_sdr1(env);
6507 gen_spr_7xx(env);
6508 /* Time base */
6509 gen_tbl(env);
6510 /* 74xx specific SPR */
6511 gen_spr_74xx(env);
6512 /* XXX : not implemented */
6513 spr_register(env, SPR_UBAMR, "UBAMR",
6514 &spr_read_ureg, SPR_NOACCESS,
6515 &spr_read_ureg, SPR_NOACCESS,
6516 0x00000000);
6517 /* Thermal management */
6518 gen_spr_thrm(env);
6519 /* L2PMCR */
6520 /* XXX : not implemented */
6521 spr_register(env, SPR_L2PMCR, "L2PMCR",
6522 SPR_NOACCESS, SPR_NOACCESS,
6523 &spr_read_generic, &spr_write_generic,
6524 0x00000000);
6525 /* LDSTDB */
6526 /* XXX : not implemented */
6527 spr_register(env, SPR_LDSTDB, "LDSTDB",
6528 SPR_NOACCESS, SPR_NOACCESS,
6529 &spr_read_generic, &spr_write_generic,
6530 0x00000000);
6531 /* Memory management */
6532 gen_low_BATs(env);
6533 init_excp_7400(env);
6534 env->dcache_line_size = 32;
6535 env->icache_line_size = 32;
6536 /* Allocate hardware IRQ controller */
6537 ppc6xx_irq_init(ppc_env_get_cpu(env));
6538 }
6539
6540 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6541 {
6542 DeviceClass *dc = DEVICE_CLASS(oc);
6543 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6544
6545 dc->desc = "PowerPC 7410 (aka G4)";
6546 pcc->init_proc = init_proc_7410;
6547 pcc->check_pow = check_pow_hid0;
6548 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6549 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6550 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6551 PPC_FLOAT_STFIWX |
6552 PPC_CACHE | PPC_CACHE_ICBI |
6553 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6554 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6555 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6556 PPC_MEM_TLBIA |
6557 PPC_SEGMENT | PPC_EXTERN |
6558 PPC_ALTIVEC;
6559 pcc->msr_mask = (1ull << MSR_VR) |
6560 (1ull << MSR_POW) |
6561 (1ull << MSR_ILE) |
6562 (1ull << MSR_EE) |
6563 (1ull << MSR_PR) |
6564 (1ull << MSR_FP) |
6565 (1ull << MSR_ME) |
6566 (1ull << MSR_FE0) |
6567 (1ull << MSR_SE) |
6568 (1ull << MSR_DE) |
6569 (1ull << MSR_FE1) |
6570 (1ull << MSR_EP) |
6571 (1ull << MSR_IR) |
6572 (1ull << MSR_DR) |
6573 (1ull << MSR_PMM) |
6574 (1ull << MSR_RI) |
6575 (1ull << MSR_LE);
6576 pcc->mmu_model = POWERPC_MMU_32B;
6577 #if defined(CONFIG_SOFTMMU)
6578 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6579 #endif
6580 pcc->excp_model = POWERPC_EXCP_74xx;
6581 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6582 pcc->bfd_mach = bfd_mach_ppc_7400;
6583 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6584 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6585 POWERPC_FLAG_BUS_CLK;
6586 }
6587
6588 static void init_proc_7440(CPUPPCState *env)
6589 {
6590 gen_spr_ne_601(env);
6591 gen_spr_sdr1(env);
6592 gen_spr_7xx(env);
6593 /* Time base */
6594 gen_tbl(env);
6595 /* 74xx specific SPR */
6596 gen_spr_74xx(env);
6597 /* XXX : not implemented */
6598 spr_register(env, SPR_UBAMR, "UBAMR",
6599 &spr_read_ureg, SPR_NOACCESS,
6600 &spr_read_ureg, SPR_NOACCESS,
6601 0x00000000);
6602 /* LDSTCR */
6603 /* XXX : not implemented */
6604 spr_register(env, SPR_LDSTCR, "LDSTCR",
6605 SPR_NOACCESS, SPR_NOACCESS,
6606 &spr_read_generic, &spr_write_generic,
6607 0x00000000);
6608 /* ICTRL */
6609 /* XXX : not implemented */
6610 spr_register(env, SPR_ICTRL, "ICTRL",
6611 SPR_NOACCESS, SPR_NOACCESS,
6612 &spr_read_generic, &spr_write_generic,
6613 0x00000000);
6614 /* MSSSR0 */
6615 /* XXX : not implemented */
6616 spr_register(env, SPR_MSSSR0, "MSSSR0",
6617 SPR_NOACCESS, SPR_NOACCESS,
6618 &spr_read_generic, &spr_write_generic,
6619 0x00000000);
6620 /* PMC */
6621 /* XXX : not implemented */
6622 spr_register(env, SPR_7XX_PMC5, "PMC5",
6623 SPR_NOACCESS, SPR_NOACCESS,
6624 &spr_read_generic, &spr_write_generic,
6625 0x00000000);
6626 /* XXX : not implemented */
6627 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6628 &spr_read_ureg, SPR_NOACCESS,
6629 &spr_read_ureg, SPR_NOACCESS,
6630 0x00000000);
6631 /* XXX : not implemented */
6632 spr_register(env, SPR_7XX_PMC6, "PMC6",
6633 SPR_NOACCESS, SPR_NOACCESS,
6634 &spr_read_generic, &spr_write_generic,
6635 0x00000000);
6636 /* XXX : not implemented */
6637 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6638 &spr_read_ureg, SPR_NOACCESS,
6639 &spr_read_ureg, SPR_NOACCESS,
6640 0x00000000);
6641 /* Memory management */
6642 gen_low_BATs(env);
6643 gen_74xx_soft_tlb(env, 128, 2);
6644 init_excp_7450(env);
6645 env->dcache_line_size = 32;
6646 env->icache_line_size = 32;
6647 /* Allocate hardware IRQ controller */
6648 ppc6xx_irq_init(ppc_env_get_cpu(env));
6649 }
6650
6651 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6652 {
6653 DeviceClass *dc = DEVICE_CLASS(oc);
6654 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6655
6656 dc->desc = "PowerPC 7440 (aka G4)";
6657 pcc->init_proc = init_proc_7440;
6658 pcc->check_pow = check_pow_hid0_74xx;
6659 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6660 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6661 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6662 PPC_FLOAT_STFIWX |
6663 PPC_CACHE | PPC_CACHE_ICBI |
6664 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6665 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6666 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6667 PPC_MEM_TLBIA | PPC_74xx_TLB |
6668 PPC_SEGMENT | PPC_EXTERN |
6669 PPC_ALTIVEC;
6670 pcc->msr_mask = (1ull << MSR_VR) |
6671 (1ull << MSR_POW) |
6672 (1ull << MSR_ILE) |
6673 (1ull << MSR_EE) |
6674 (1ull << MSR_PR) |
6675 (1ull << MSR_FP) |
6676 (1ull << MSR_ME) |
6677 (1ull << MSR_FE0) |
6678 (1ull << MSR_SE) |
6679 (1ull << MSR_DE) |
6680 (1ull << MSR_FE1) |
6681 (1ull << MSR_EP) |
6682 (1ull << MSR_IR) |
6683 (1ull << MSR_DR) |
6684 (1ull << MSR_PMM) |
6685 (1ull << MSR_RI) |
6686 (1ull << MSR_LE);
6687 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6688 pcc->excp_model = POWERPC_EXCP_74xx;
6689 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6690 pcc->bfd_mach = bfd_mach_ppc_7400;
6691 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6692 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6693 POWERPC_FLAG_BUS_CLK;
6694 }
6695
6696 static void init_proc_7450(CPUPPCState *env)
6697 {
6698 gen_spr_ne_601(env);
6699 gen_spr_sdr1(env);
6700 gen_spr_7xx(env);
6701 /* Time base */
6702 gen_tbl(env);
6703 /* 74xx specific SPR */
6704 gen_spr_74xx(env);
6705 /* Level 3 cache control */
6706 gen_l3_ctrl(env);
6707 /* L3ITCR1 */
6708 /* XXX : not implemented */
6709 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6710 SPR_NOACCESS, SPR_NOACCESS,
6711 &spr_read_generic, &spr_write_generic,
6712 0x00000000);
6713 /* L3ITCR2 */
6714 /* XXX : not implemented */
6715 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6716 SPR_NOACCESS, SPR_NOACCESS,
6717 &spr_read_generic, &spr_write_generic,
6718 0x00000000);
6719 /* L3ITCR3 */
6720 /* XXX : not implemented */
6721 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6722 SPR_NOACCESS, SPR_NOACCESS,
6723 &spr_read_generic, &spr_write_generic,
6724 0x00000000);
6725 /* L3OHCR */
6726 /* XXX : not implemented */
6727 spr_register(env, SPR_L3OHCR, "L3OHCR",
6728 SPR_NOACCESS, SPR_NOACCESS,
6729 &spr_read_generic, &spr_write_generic,
6730 0x00000000);
6731 /* XXX : not implemented */
6732 spr_register(env, SPR_UBAMR, "UBAMR",
6733 &spr_read_ureg, SPR_NOACCESS,
6734 &spr_read_ureg, SPR_NOACCESS,
6735 0x00000000);
6736 /* LDSTCR */
6737 /* XXX : not implemented */
6738 spr_register(env, SPR_LDSTCR, "LDSTCR",
6739 SPR_NOACCESS, SPR_NOACCESS,
6740 &spr_read_generic, &spr_write_generic,
6741 0x00000000);
6742 /* ICTRL */
6743 /* XXX : not implemented */
6744 spr_register(env, SPR_ICTRL, "ICTRL",
6745 SPR_NOACCESS, SPR_NOACCESS,
6746 &spr_read_generic, &spr_write_generic,
6747 0x00000000);
6748 /* MSSSR0 */
6749 /* XXX : not implemented */
6750 spr_register(env, SPR_MSSSR0, "MSSSR0",
6751 SPR_NOACCESS, SPR_NOACCESS,
6752 &spr_read_generic, &spr_write_generic,
6753 0x00000000);
6754 /* PMC */
6755 /* XXX : not implemented */
6756 spr_register(env, SPR_7XX_PMC5, "PMC5",
6757 SPR_NOACCESS, SPR_NOACCESS,
6758 &spr_read_generic, &spr_write_generic,
6759 0x00000000);
6760 /* XXX : not implemented */
6761 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6762 &spr_read_ureg, SPR_NOACCESS,
6763 &spr_read_ureg, SPR_NOACCESS,
6764 0x00000000);
6765 /* XXX : not implemented */
6766 spr_register(env, SPR_7XX_PMC6, "PMC6",
6767 SPR_NOACCESS, SPR_NOACCESS,
6768 &spr_read_generic, &spr_write_generic,
6769 0x00000000);
6770 /* XXX : not implemented */
6771 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6772 &spr_read_ureg, SPR_NOACCESS,
6773 &spr_read_ureg, SPR_NOACCESS,
6774 0x00000000);
6775 /* Memory management */
6776 gen_low_BATs(env);
6777 gen_74xx_soft_tlb(env, 128, 2);
6778 init_excp_7450(env);
6779 env->dcache_line_size = 32;
6780 env->icache_line_size = 32;
6781 /* Allocate hardware IRQ controller */
6782 ppc6xx_irq_init(ppc_env_get_cpu(env));
6783 }
6784
6785 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6786 {
6787 DeviceClass *dc = DEVICE_CLASS(oc);
6788 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6789
6790 dc->desc = "PowerPC 7450 (aka G4)";
6791 pcc->init_proc = init_proc_7450;
6792 pcc->check_pow = check_pow_hid0_74xx;
6793 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6794 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6795 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6796 PPC_FLOAT_STFIWX |
6797 PPC_CACHE | PPC_CACHE_ICBI |
6798 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6799 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6800 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6801 PPC_MEM_TLBIA | PPC_74xx_TLB |
6802 PPC_SEGMENT | PPC_EXTERN |
6803 PPC_ALTIVEC;
6804 pcc->msr_mask = (1ull << MSR_VR) |
6805 (1ull << MSR_POW) |
6806 (1ull << MSR_ILE) |
6807 (1ull << MSR_EE) |
6808 (1ull << MSR_PR) |
6809 (1ull << MSR_FP) |
6810 (1ull << MSR_ME) |
6811 (1ull << MSR_FE0) |
6812 (1ull << MSR_SE) |
6813 (1ull << MSR_DE) |
6814 (1ull << MSR_FE1) |
6815 (1ull << MSR_EP) |
6816 (1ull << MSR_IR) |
6817 (1ull << MSR_DR) |
6818 (1ull << MSR_PMM) |
6819 (1ull << MSR_RI) |
6820 (1ull << MSR_LE);
6821 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6822 pcc->excp_model = POWERPC_EXCP_74xx;
6823 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6824 pcc->bfd_mach = bfd_mach_ppc_7400;
6825 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6826 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6827 POWERPC_FLAG_BUS_CLK;
6828 }
6829
6830 static void init_proc_7445(CPUPPCState *env)
6831 {
6832 gen_spr_ne_601(env);
6833 gen_spr_sdr1(env);
6834 gen_spr_7xx(env);
6835 /* Time base */
6836 gen_tbl(env);
6837 /* 74xx specific SPR */
6838 gen_spr_74xx(env);
6839 /* LDSTCR */
6840 /* XXX : not implemented */
6841 spr_register(env, SPR_LDSTCR, "LDSTCR",
6842 SPR_NOACCESS, SPR_NOACCESS,
6843 &spr_read_generic, &spr_write_generic,
6844 0x00000000);
6845 /* ICTRL */
6846 /* XXX : not implemented */
6847 spr_register(env, SPR_ICTRL, "ICTRL",
6848 SPR_NOACCESS, SPR_NOACCESS,
6849 &spr_read_generic, &spr_write_generic,
6850 0x00000000);
6851 /* MSSSR0 */
6852 /* XXX : not implemented */
6853 spr_register(env, SPR_MSSSR0, "MSSSR0",
6854 SPR_NOACCESS, SPR_NOACCESS,
6855 &spr_read_generic, &spr_write_generic,
6856 0x00000000);
6857 /* PMC */
6858 /* XXX : not implemented */
6859 spr_register(env, SPR_7XX_PMC5, "PMC5",
6860 SPR_NOACCESS, SPR_NOACCESS,
6861 &spr_read_generic, &spr_write_generic,
6862 0x00000000);
6863 /* XXX : not implemented */
6864 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6865 &spr_read_ureg, SPR_NOACCESS,
6866 &spr_read_ureg, SPR_NOACCESS,
6867 0x00000000);
6868 /* XXX : not implemented */
6869 spr_register(env, SPR_7XX_PMC6, "PMC6",
6870 SPR_NOACCESS, SPR_NOACCESS,
6871 &spr_read_generic, &spr_write_generic,
6872 0x00000000);
6873 /* XXX : not implemented */
6874 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6875 &spr_read_ureg, SPR_NOACCESS,
6876 &spr_read_ureg, SPR_NOACCESS,
6877 0x00000000);
6878 /* SPRGs */
6879 spr_register(env, SPR_SPRG4, "SPRG4",
6880 SPR_NOACCESS, SPR_NOACCESS,
6881 &spr_read_generic, &spr_write_generic,
6882 0x00000000);
6883 spr_register(env, SPR_USPRG4, "USPRG4",
6884 &spr_read_ureg, SPR_NOACCESS,
6885 &spr_read_ureg, SPR_NOACCESS,
6886 0x00000000);
6887 spr_register(env, SPR_SPRG5, "SPRG5",
6888 SPR_NOACCESS, SPR_NOACCESS,
6889 &spr_read_generic, &spr_write_generic,
6890 0x00000000);
6891 spr_register(env, SPR_USPRG5, "USPRG5",
6892 &spr_read_ureg, SPR_NOACCESS,
6893 &spr_read_ureg, SPR_NOACCESS,
6894 0x00000000);
6895 spr_register(env, SPR_SPRG6, "SPRG6",
6896 SPR_NOACCESS, SPR_NOACCESS,
6897 &spr_read_generic, &spr_write_generic,
6898 0x00000000);
6899 spr_register(env, SPR_USPRG6, "USPRG6",
6900 &spr_read_ureg, SPR_NOACCESS,
6901 &spr_read_ureg, SPR_NOACCESS,
6902 0x00000000);
6903 spr_register(env, SPR_SPRG7, "SPRG7",
6904 SPR_NOACCESS, SPR_NOACCESS,
6905 &spr_read_generic, &spr_write_generic,
6906 0x00000000);
6907 spr_register(env, SPR_USPRG7, "USPRG7",
6908 &spr_read_ureg, SPR_NOACCESS,
6909 &spr_read_ureg, SPR_NOACCESS,
6910 0x00000000);
6911 /* Memory management */
6912 gen_low_BATs(env);
6913 gen_high_BATs(env);
6914 gen_74xx_soft_tlb(env, 128, 2);
6915 init_excp_7450(env);
6916 env->dcache_line_size = 32;
6917 env->icache_line_size = 32;
6918 /* Allocate hardware IRQ controller */
6919 ppc6xx_irq_init(ppc_env_get_cpu(env));
6920 }
6921
6922 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6923 {
6924 DeviceClass *dc = DEVICE_CLASS(oc);
6925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6926
6927 dc->desc = "PowerPC 7445 (aka G4)";
6928 pcc->init_proc = init_proc_7445;
6929 pcc->check_pow = check_pow_hid0_74xx;
6930 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6931 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6932 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6933 PPC_FLOAT_STFIWX |
6934 PPC_CACHE | PPC_CACHE_ICBI |
6935 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6936 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6937 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6938 PPC_MEM_TLBIA | PPC_74xx_TLB |
6939 PPC_SEGMENT | PPC_EXTERN |
6940 PPC_ALTIVEC;
6941 pcc->msr_mask = (1ull << MSR_VR) |
6942 (1ull << MSR_POW) |
6943 (1ull << MSR_ILE) |
6944 (1ull << MSR_EE) |
6945 (1ull << MSR_PR) |
6946 (1ull << MSR_FP) |
6947 (1ull << MSR_ME) |
6948 (1ull << MSR_FE0) |
6949 (1ull << MSR_SE) |
6950 (1ull << MSR_DE) |
6951 (1ull << MSR_FE1) |
6952 (1ull << MSR_EP) |
6953 (1ull << MSR_IR) |
6954 (1ull << MSR_DR) |
6955 (1ull << MSR_PMM) |
6956 (1ull << MSR_RI) |
6957 (1ull << MSR_LE);
6958 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6959 pcc->excp_model = POWERPC_EXCP_74xx;
6960 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6961 pcc->bfd_mach = bfd_mach_ppc_7400;
6962 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6963 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6964 POWERPC_FLAG_BUS_CLK;
6965 }
6966
6967 static void init_proc_7455(CPUPPCState *env)
6968 {
6969 gen_spr_ne_601(env);
6970 gen_spr_sdr1(env);
6971 gen_spr_7xx(env);
6972 /* Time base */
6973 gen_tbl(env);
6974 /* 74xx specific SPR */
6975 gen_spr_74xx(env);
6976 /* Level 3 cache control */
6977 gen_l3_ctrl(env);
6978 /* LDSTCR */
6979 /* XXX : not implemented */
6980 spr_register(env, SPR_LDSTCR, "LDSTCR",
6981 SPR_NOACCESS, SPR_NOACCESS,
6982 &spr_read_generic, &spr_write_generic,
6983 0x00000000);
6984 /* ICTRL */
6985 /* XXX : not implemented */
6986 spr_register(env, SPR_ICTRL, "ICTRL",
6987 SPR_NOACCESS, SPR_NOACCESS,
6988 &spr_read_generic, &spr_write_generic,
6989 0x00000000);
6990 /* MSSSR0 */
6991 /* XXX : not implemented */
6992 spr_register(env, SPR_MSSSR0, "MSSSR0",
6993 SPR_NOACCESS, SPR_NOACCESS,
6994 &spr_read_generic, &spr_write_generic,
6995 0x00000000);
6996 /* PMC */
6997 /* XXX : not implemented */
6998 spr_register(env, SPR_7XX_PMC5, "PMC5",
6999 SPR_NOACCESS, SPR_NOACCESS,
7000 &spr_read_generic, &spr_write_generic,
7001 0x00000000);
7002 /* XXX : not implemented */
7003 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7004 &spr_read_ureg, SPR_NOACCESS,
7005 &spr_read_ureg, SPR_NOACCESS,
7006 0x00000000);
7007 /* XXX : not implemented */
7008 spr_register(env, SPR_7XX_PMC6, "PMC6",
7009 SPR_NOACCESS, SPR_NOACCESS,
7010 &spr_read_generic, &spr_write_generic,
7011 0x00000000);
7012 /* XXX : not implemented */
7013 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7014 &spr_read_ureg, SPR_NOACCESS,
7015 &spr_read_ureg, SPR_NOACCESS,
7016 0x00000000);
7017 /* SPRGs */
7018 spr_register(env, SPR_SPRG4, "SPRG4",
7019 SPR_NOACCESS, SPR_NOACCESS,
7020 &spr_read_generic, &spr_write_generic,
7021 0x00000000);
7022 spr_register(env, SPR_USPRG4, "USPRG4",
7023 &spr_read_ureg, SPR_NOACCESS,
7024 &spr_read_ureg, SPR_NOACCESS,
7025 0x00000000);
7026 spr_register(env, SPR_SPRG5, "SPRG5",
7027 SPR_NOACCESS, SPR_NOACCESS,
7028 &spr_read_generic, &spr_write_generic,
7029 0x00000000);
7030 spr_register(env, SPR_USPRG5, "USPRG5",
7031 &spr_read_ureg, SPR_NOACCESS,
7032 &spr_read_ureg, SPR_NOACCESS,
7033 0x00000000);
7034 spr_register(env, SPR_SPRG6, "SPRG6",
7035 SPR_NOACCESS, SPR_NOACCESS,
7036 &spr_read_generic, &spr_write_generic,
7037 0x00000000);
7038 spr_register(env, SPR_USPRG6, "USPRG6",
7039 &spr_read_ureg, SPR_NOACCESS,
7040 &spr_read_ureg, SPR_NOACCESS,
7041 0x00000000);
7042 spr_register(env, SPR_SPRG7, "SPRG7",
7043 SPR_NOACCESS, SPR_NOACCESS,
7044 &spr_read_generic, &spr_write_generic,
7045 0x00000000);
7046 spr_register(env, SPR_USPRG7, "USPRG7",
7047 &spr_read_ureg, SPR_NOACCESS,
7048 &spr_read_ureg, SPR_NOACCESS,
7049 0x00000000);
7050 /* Memory management */
7051 gen_low_BATs(env);
7052 gen_high_BATs(env);
7053 gen_74xx_soft_tlb(env, 128, 2);
7054 init_excp_7450(env);
7055 env->dcache_line_size = 32;
7056 env->icache_line_size = 32;
7057 /* Allocate hardware IRQ controller */
7058 ppc6xx_irq_init(ppc_env_get_cpu(env));
7059 }
7060
7061 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7062 {
7063 DeviceClass *dc = DEVICE_CLASS(oc);
7064 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7065
7066 dc->desc = "PowerPC 7455 (aka G4)";
7067 pcc->init_proc = init_proc_7455;
7068 pcc->check_pow = check_pow_hid0_74xx;
7069 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7070 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7071 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7072 PPC_FLOAT_STFIWX |
7073 PPC_CACHE | PPC_CACHE_ICBI |
7074 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7075 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7076 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7077 PPC_MEM_TLBIA | PPC_74xx_TLB |
7078 PPC_SEGMENT | PPC_EXTERN |
7079 PPC_ALTIVEC;
7080 pcc->msr_mask = (1ull << MSR_VR) |
7081 (1ull << MSR_POW) |
7082 (1ull << MSR_ILE) |
7083 (1ull << MSR_EE) |
7084 (1ull << MSR_PR) |
7085 (1ull << MSR_FP) |
7086 (1ull << MSR_ME) |
7087 (1ull << MSR_FE0) |
7088 (1ull << MSR_SE) |
7089 (1ull << MSR_DE) |
7090 (1ull << MSR_FE1) |
7091 (1ull << MSR_EP) |
7092 (1ull << MSR_IR) |
7093 (1ull << MSR_DR) |
7094 (1ull << MSR_PMM) |
7095 (1ull << MSR_RI) |
7096 (1ull << MSR_LE);
7097 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7098 pcc->excp_model = POWERPC_EXCP_74xx;
7099 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7100 pcc->bfd_mach = bfd_mach_ppc_7400;
7101 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7102 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7103 POWERPC_FLAG_BUS_CLK;
7104 }
7105
7106 static void init_proc_7457(CPUPPCState *env)
7107 {
7108 gen_spr_ne_601(env);
7109 gen_spr_sdr1(env);
7110 gen_spr_7xx(env);
7111 /* Time base */
7112 gen_tbl(env);
7113 /* 74xx specific SPR */
7114 gen_spr_74xx(env);
7115 /* Level 3 cache control */
7116 gen_l3_ctrl(env);
7117 /* L3ITCR1 */
7118 /* XXX : not implemented */
7119 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7120 SPR_NOACCESS, SPR_NOACCESS,
7121 &spr_read_generic, &spr_write_generic,
7122 0x00000000);
7123 /* L3ITCR2 */
7124 /* XXX : not implemented */
7125 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7126 SPR_NOACCESS, SPR_NOACCESS,
7127 &spr_read_generic, &spr_write_generic,
7128 0x00000000);
7129 /* L3ITCR3 */
7130 /* XXX : not implemented */
7131 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7132 SPR_NOACCESS, SPR_NOACCESS,
7133 &spr_read_generic, &spr_write_generic,
7134 0x00000000);
7135 /* L3OHCR */
7136 /* XXX : not implemented */
7137 spr_register(env, SPR_L3OHCR, "L3OHCR",
7138 SPR_NOACCESS, SPR_NOACCESS,
7139 &spr_read_generic, &spr_write_generic,
7140 0x00000000);
7141 /* LDSTCR */
7142 /* XXX : not implemented */
7143 spr_register(env, SPR_LDSTCR, "LDSTCR",
7144 SPR_NOACCESS, SPR_NOACCESS,
7145 &spr_read_generic, &spr_write_generic,
7146 0x00000000);
7147 /* ICTRL */
7148 /* XXX : not implemented */
7149 spr_register(env, SPR_ICTRL, "ICTRL",
7150 SPR_NOACCESS, SPR_NOACCESS,
7151 &spr_read_generic, &spr_write_generic,
7152 0x00000000);
7153 /* MSSSR0 */
7154 /* XXX : not implemented */
7155 spr_register(env, SPR_MSSSR0, "MSSSR0",
7156 SPR_NOACCESS, SPR_NOACCESS,
7157 &spr_read_generic, &spr_write_generic,
7158 0x00000000);
7159 /* PMC */
7160 /* XXX : not implemented */
7161 spr_register(env, SPR_7XX_PMC5, "PMC5",
7162 SPR_NOACCESS, SPR_NOACCESS,
7163 &spr_read_generic, &spr_write_generic,
7164 0x00000000);
7165 /* XXX : not implemented */
7166 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7167 &spr_read_ureg, SPR_NOACCESS,
7168 &spr_read_ureg, SPR_NOACCESS,
7169 0x00000000);
7170 /* XXX : not implemented */
7171 spr_register(env, SPR_7XX_PMC6, "PMC6",
7172 SPR_NOACCESS, SPR_NOACCESS,
7173 &spr_read_generic, &spr_write_generic,
7174 0x00000000);
7175 /* XXX : not implemented */
7176 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7177 &spr_read_ureg, SPR_NOACCESS,
7178 &spr_read_ureg, SPR_NOACCESS,
7179 0x00000000);
7180 /* SPRGs */
7181 spr_register(env, SPR_SPRG4, "SPRG4",
7182 SPR_NOACCESS, SPR_NOACCESS,
7183 &spr_read_generic, &spr_write_generic,
7184 0x00000000);
7185 spr_register(env, SPR_USPRG4, "USPRG4",
7186 &spr_read_ureg, SPR_NOACCESS,
7187 &spr_read_ureg, SPR_NOACCESS,
7188 0x00000000);
7189 spr_register(env, SPR_SPRG5, "SPRG5",
7190 SPR_NOACCESS, SPR_NOACCESS,
7191 &spr_read_generic, &spr_write_generic,
7192 0x00000000);
7193 spr_register(env, SPR_USPRG5, "USPRG5",
7194 &spr_read_ureg, SPR_NOACCESS,
7195 &spr_read_ureg, SPR_NOACCESS,
7196 0x00000000);
7197 spr_register(env, SPR_SPRG6, "SPRG6",
7198 SPR_NOACCESS, SPR_NOACCESS,
7199 &spr_read_generic, &spr_write_generic,
7200 0x00000000);
7201 spr_register(env, SPR_USPRG6, "USPRG6",
7202 &spr_read_ureg, SPR_NOACCESS,
7203 &spr_read_ureg, SPR_NOACCESS,
7204 0x00000000);
7205 spr_register(env, SPR_SPRG7, "SPRG7",
7206 SPR_NOACCESS, SPR_NOACCESS,
7207 &spr_read_generic, &spr_write_generic,
7208 0x00000000);
7209 spr_register(env, SPR_USPRG7, "USPRG7",
7210 &spr_read_ureg, SPR_NOACCESS,
7211 &spr_read_ureg, SPR_NOACCESS,
7212 0x00000000);
7213 /* Memory management */
7214 gen_low_BATs(env);
7215 gen_high_BATs(env);
7216 gen_74xx_soft_tlb(env, 128, 2);
7217 init_excp_7450(env);
7218 env->dcache_line_size = 32;
7219 env->icache_line_size = 32;
7220 /* Allocate hardware IRQ controller */
7221 ppc6xx_irq_init(ppc_env_get_cpu(env));
7222 }
7223
7224 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7225 {
7226 DeviceClass *dc = DEVICE_CLASS(oc);
7227 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7228
7229 dc->desc = "PowerPC 7457 (aka G4)";
7230 pcc->init_proc = init_proc_7457;
7231 pcc->check_pow = check_pow_hid0_74xx;
7232 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7233 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7234 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7235 PPC_FLOAT_STFIWX |
7236 PPC_CACHE | PPC_CACHE_ICBI |
7237 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7238 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7239 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7240 PPC_MEM_TLBIA | PPC_74xx_TLB |
7241 PPC_SEGMENT | PPC_EXTERN |
7242 PPC_ALTIVEC;
7243 pcc->msr_mask = (1ull << MSR_VR) |
7244 (1ull << MSR_POW) |
7245 (1ull << MSR_ILE) |
7246 (1ull << MSR_EE) |
7247 (1ull << MSR_PR) |
7248 (1ull << MSR_FP) |
7249 (1ull << MSR_ME) |
7250 (1ull << MSR_FE0) |
7251 (1ull << MSR_SE) |
7252 (1ull << MSR_DE) |
7253 (1ull << MSR_FE1) |
7254 (1ull << MSR_EP) |
7255 (1ull << MSR_IR) |
7256 (1ull << MSR_DR) |
7257 (1ull << MSR_PMM) |
7258 (1ull << MSR_RI) |
7259 (1ull << MSR_LE);
7260 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7261 pcc->excp_model = POWERPC_EXCP_74xx;
7262 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7263 pcc->bfd_mach = bfd_mach_ppc_7400;
7264 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7265 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7266 POWERPC_FLAG_BUS_CLK;
7267 }
7268
7269 static void init_proc_e600(CPUPPCState *env)
7270 {
7271 gen_spr_ne_601(env);
7272 gen_spr_sdr1(env);
7273 gen_spr_7xx(env);
7274 /* Time base */
7275 gen_tbl(env);
7276 /* 74xx specific SPR */
7277 gen_spr_74xx(env);
7278 /* XXX : not implemented */
7279 spr_register(env, SPR_UBAMR, "UBAMR",
7280 &spr_read_ureg, SPR_NOACCESS,
7281 &spr_read_ureg, SPR_NOACCESS,
7282 0x00000000);
7283 /* XXX : not implemented */
7284 spr_register(env, SPR_LDSTCR, "LDSTCR",
7285 SPR_NOACCESS, SPR_NOACCESS,
7286 &spr_read_generic, &spr_write_generic,
7287 0x00000000);
7288 /* XXX : not implemented */
7289 spr_register(env, SPR_ICTRL, "ICTRL",
7290 SPR_NOACCESS, SPR_NOACCESS,
7291 &spr_read_generic, &spr_write_generic,
7292 0x00000000);
7293 /* XXX : not implemented */
7294 spr_register(env, SPR_MSSSR0, "MSSSR0",
7295 SPR_NOACCESS, SPR_NOACCESS,
7296 &spr_read_generic, &spr_write_generic,
7297 0x00000000);
7298 /* XXX : not implemented */
7299 spr_register(env, SPR_7XX_PMC5, "PMC5",
7300 SPR_NOACCESS, SPR_NOACCESS,
7301 &spr_read_generic, &spr_write_generic,
7302 0x00000000);
7303 /* XXX : not implemented */
7304 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7305 &spr_read_ureg, SPR_NOACCESS,
7306 &spr_read_ureg, SPR_NOACCESS,
7307 0x00000000);
7308 /* XXX : not implemented */
7309 spr_register(env, SPR_7XX_PMC6, "PMC6",
7310 SPR_NOACCESS, SPR_NOACCESS,
7311 &spr_read_generic, &spr_write_generic,
7312 0x00000000);
7313 /* XXX : not implemented */
7314 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7315 &spr_read_ureg, SPR_NOACCESS,
7316 &spr_read_ureg, SPR_NOACCESS,
7317 0x00000000);
7318 /* SPRGs */
7319 spr_register(env, SPR_SPRG4, "SPRG4",
7320 SPR_NOACCESS, SPR_NOACCESS,
7321 &spr_read_generic, &spr_write_generic,
7322 0x00000000);
7323 spr_register(env, SPR_USPRG4, "USPRG4",
7324 &spr_read_ureg, SPR_NOACCESS,
7325 &spr_read_ureg, SPR_NOACCESS,
7326 0x00000000);
7327 spr_register(env, SPR_SPRG5, "SPRG5",
7328 SPR_NOACCESS, SPR_NOACCESS,
7329 &spr_read_generic, &spr_write_generic,
7330 0x00000000);
7331 spr_register(env, SPR_USPRG5, "USPRG5",
7332 &spr_read_ureg, SPR_NOACCESS,
7333 &spr_read_ureg, SPR_NOACCESS,
7334 0x00000000);
7335 spr_register(env, SPR_SPRG6, "SPRG6",
7336 SPR_NOACCESS, SPR_NOACCESS,
7337 &spr_read_generic, &spr_write_generic,
7338 0x00000000);
7339 spr_register(env, SPR_USPRG6, "USPRG6",
7340 &spr_read_ureg, SPR_NOACCESS,
7341 &spr_read_ureg, SPR_NOACCESS,
7342 0x00000000);
7343 spr_register(env, SPR_SPRG7, "SPRG7",
7344 SPR_NOACCESS, SPR_NOACCESS,
7345 &spr_read_generic, &spr_write_generic,
7346 0x00000000);
7347 spr_register(env, SPR_USPRG7, "USPRG7",
7348 &spr_read_ureg, SPR_NOACCESS,
7349 &spr_read_ureg, SPR_NOACCESS,
7350 0x00000000);
7351 /* Memory management */
7352 gen_low_BATs(env);
7353 gen_high_BATs(env);
7354 gen_74xx_soft_tlb(env, 128, 2);
7355 init_excp_7450(env);
7356 env->dcache_line_size = 32;
7357 env->icache_line_size = 32;
7358 /* Allocate hardware IRQ controller */
7359 ppc6xx_irq_init(ppc_env_get_cpu(env));
7360 }
7361
7362 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7363 {
7364 DeviceClass *dc = DEVICE_CLASS(oc);
7365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7366
7367 dc->desc = "PowerPC e600";
7368 pcc->init_proc = init_proc_e600;
7369 pcc->check_pow = check_pow_hid0_74xx;
7370 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7371 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7372 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7373 PPC_FLOAT_STFIWX |
7374 PPC_CACHE | PPC_CACHE_ICBI |
7375 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7376 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7377 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7378 PPC_MEM_TLBIA | PPC_74xx_TLB |
7379 PPC_SEGMENT | PPC_EXTERN |
7380 PPC_ALTIVEC;
7381 pcc->insns_flags2 = PPC_NONE;
7382 pcc->msr_mask = (1ull << MSR_VR) |
7383 (1ull << MSR_POW) |
7384 (1ull << MSR_ILE) |
7385 (1ull << MSR_EE) |
7386 (1ull << MSR_PR) |
7387 (1ull << MSR_FP) |
7388 (1ull << MSR_ME) |
7389 (1ull << MSR_FE0) |
7390 (1ull << MSR_SE) |
7391 (1ull << MSR_DE) |
7392 (1ull << MSR_FE1) |
7393 (1ull << MSR_EP) |
7394 (1ull << MSR_IR) |
7395 (1ull << MSR_DR) |
7396 (1ull << MSR_PMM) |
7397 (1ull << MSR_RI) |
7398 (1ull << MSR_LE);
7399 pcc->mmu_model = POWERPC_MMU_32B;
7400 #if defined(CONFIG_SOFTMMU)
7401 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7402 #endif
7403 pcc->excp_model = POWERPC_EXCP_74xx;
7404 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7405 pcc->bfd_mach = bfd_mach_ppc_7400;
7406 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7407 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7408 POWERPC_FLAG_BUS_CLK;
7409 }
7410
7411 #if defined(TARGET_PPC64)
7412 #if defined(CONFIG_USER_ONLY)
7413 #define POWERPC970_HID5_INIT 0x00000080
7414 #else
7415 #define POWERPC970_HID5_INIT 0x00000000
7416 #endif
7417
7418 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7419 int bit, int sprn, int cause)
7420 {
7421 TCGv_i32 t1 = tcg_const_i32(bit);
7422 TCGv_i32 t2 = tcg_const_i32(sprn);
7423 TCGv_i32 t3 = tcg_const_i32(cause);
7424
7425 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7426
7427 tcg_temp_free_i32(t3);
7428 tcg_temp_free_i32(t2);
7429 tcg_temp_free_i32(t1);
7430 }
7431
7432 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7433 int bit, int sprn, int cause)
7434 {
7435 TCGv_i32 t1 = tcg_const_i32(bit);
7436 TCGv_i32 t2 = tcg_const_i32(sprn);
7437 TCGv_i32 t3 = tcg_const_i32(cause);
7438
7439 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7440
7441 tcg_temp_free_i32(t3);
7442 tcg_temp_free_i32(t2);
7443 tcg_temp_free_i32(t1);
7444 }
7445
7446 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7447 {
7448 TCGv spr_up = tcg_temp_new();
7449 TCGv spr = tcg_temp_new();
7450
7451 gen_load_spr(spr, sprn - 1);
7452 tcg_gen_shri_tl(spr_up, spr, 32);
7453 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7454
7455 tcg_temp_free(spr);
7456 tcg_temp_free(spr_up);
7457 }
7458
7459 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7460 {
7461 TCGv spr = tcg_temp_new();
7462
7463 gen_load_spr(spr, sprn - 1);
7464 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7465 gen_store_spr(sprn - 1, spr);
7466
7467 tcg_temp_free(spr);
7468 }
7469
7470 static int check_pow_970(CPUPPCState *env)
7471 {
7472 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7473 return 1;
7474 }
7475
7476 return 0;
7477 }
7478
7479 static void gen_spr_970_hid(CPUPPCState *env)
7480 {
7481 /* Hardware implementation registers */
7482 /* XXX : not implemented */
7483 spr_register(env, SPR_HID0, "HID0",
7484 SPR_NOACCESS, SPR_NOACCESS,
7485 &spr_read_generic, &spr_write_clear,
7486 0x60000000);
7487 spr_register(env, SPR_HID1, "HID1",
7488 SPR_NOACCESS, SPR_NOACCESS,
7489 &spr_read_generic, &spr_write_generic,
7490 0x00000000);
7491 spr_register(env, SPR_970_HID5, "HID5",
7492 SPR_NOACCESS, SPR_NOACCESS,
7493 &spr_read_generic, &spr_write_generic,
7494 POWERPC970_HID5_INIT);
7495 }
7496
7497 static void gen_spr_970_hior(CPUPPCState *env)
7498 {
7499 spr_register(env, SPR_HIOR, "SPR_HIOR",
7500 SPR_NOACCESS, SPR_NOACCESS,
7501 &spr_read_hior, &spr_write_hior,
7502 0x00000000);
7503 }
7504
7505 static void gen_spr_book3s_ctrl(CPUPPCState *env)
7506 {
7507 spr_register(env, SPR_CTRL, "SPR_CTRL",
7508 SPR_NOACCESS, SPR_NOACCESS,
7509 SPR_NOACCESS, &spr_write_generic,
7510 0x00000000);
7511 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7512 &spr_read_ureg, SPR_NOACCESS,
7513 &spr_read_ureg, SPR_NOACCESS,
7514 0x00000000);
7515 }
7516
7517 static void gen_spr_book3s_altivec(CPUPPCState *env)
7518 {
7519 if (!(env->insns_flags & PPC_ALTIVEC)) {
7520 return;
7521 }
7522
7523 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7524 &spr_read_generic, &spr_write_generic,
7525 &spr_read_generic, &spr_write_generic,
7526 KVM_REG_PPC_VRSAVE, 0x00000000);
7527
7528 /* Can't find information on what this should be on reset. This
7529 * value is the one used by 74xx processors. */
7530 vscr_init(env, 0x00010000);
7531 }
7532
7533 static void gen_spr_book3s_dbg(CPUPPCState *env)
7534 {
7535 /*
7536 * TODO: different specs define different scopes for these,
7537 * will have to address this:
7538 * 970: super/write and super/read
7539 * powerisa 2.03..2.04: hypv/write and super/read.
7540 * powerisa 2.05 and newer: hypv/write and hypv/read.
7541 */
7542 spr_register_kvm(env, SPR_DABR, "DABR",
7543 SPR_NOACCESS, SPR_NOACCESS,
7544 &spr_read_generic, &spr_write_generic,
7545 KVM_REG_PPC_DABR, 0x00000000);
7546 spr_register_kvm(env, SPR_DABRX, "DABRX",
7547 SPR_NOACCESS, SPR_NOACCESS,
7548 &spr_read_generic, &spr_write_generic,
7549 KVM_REG_PPC_DABRX, 0x00000000);
7550 }
7551
7552 static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7553 {
7554 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7555 SPR_NOACCESS, SPR_NOACCESS,
7556 SPR_NOACCESS, SPR_NOACCESS,
7557 &spr_read_generic, &spr_write_generic,
7558 KVM_REG_PPC_DAWR, 0x00000000);
7559 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7560 SPR_NOACCESS, SPR_NOACCESS,
7561 SPR_NOACCESS, SPR_NOACCESS,
7562 &spr_read_generic, &spr_write_generic,
7563 KVM_REG_PPC_DAWRX, 0x00000000);
7564 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7565 SPR_NOACCESS, SPR_NOACCESS,
7566 SPR_NOACCESS, SPR_NOACCESS,
7567 &spr_read_generic, &spr_write_generic,
7568 KVM_REG_PPC_CIABR, 0x00000000);
7569 }
7570
7571 static void gen_spr_970_dbg(CPUPPCState *env)
7572 {
7573 /* Breakpoints */
7574 spr_register(env, SPR_IABR, "IABR",
7575 SPR_NOACCESS, SPR_NOACCESS,
7576 &spr_read_generic, &spr_write_generic,
7577 0x00000000);
7578 }
7579
7580 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7581 {
7582 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7583 SPR_NOACCESS, SPR_NOACCESS,
7584 &spr_read_generic, &spr_write_generic,
7585 KVM_REG_PPC_MMCR0, 0x00000000);
7586 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7587 SPR_NOACCESS, SPR_NOACCESS,
7588 &spr_read_generic, &spr_write_generic,
7589 KVM_REG_PPC_MMCR1, 0x00000000);
7590 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7591 SPR_NOACCESS, SPR_NOACCESS,
7592 &spr_read_generic, &spr_write_generic,
7593 KVM_REG_PPC_MMCRA, 0x00000000);
7594 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7595 SPR_NOACCESS, SPR_NOACCESS,
7596 &spr_read_generic, &spr_write_generic,
7597 KVM_REG_PPC_PMC1, 0x00000000);
7598 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7599 SPR_NOACCESS, SPR_NOACCESS,
7600 &spr_read_generic, &spr_write_generic,
7601 KVM_REG_PPC_PMC2, 0x00000000);
7602 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7603 SPR_NOACCESS, SPR_NOACCESS,
7604 &spr_read_generic, &spr_write_generic,
7605 KVM_REG_PPC_PMC3, 0x00000000);
7606 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7607 SPR_NOACCESS, SPR_NOACCESS,
7608 &spr_read_generic, &spr_write_generic,
7609 KVM_REG_PPC_PMC4, 0x00000000);
7610 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7611 SPR_NOACCESS, SPR_NOACCESS,
7612 &spr_read_generic, &spr_write_generic,
7613 KVM_REG_PPC_PMC5, 0x00000000);
7614 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7615 SPR_NOACCESS, SPR_NOACCESS,
7616 &spr_read_generic, &spr_write_generic,
7617 KVM_REG_PPC_PMC6, 0x00000000);
7618 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7619 SPR_NOACCESS, SPR_NOACCESS,
7620 &spr_read_generic, &spr_write_generic,
7621 KVM_REG_PPC_SIAR, 0x00000000);
7622 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7623 SPR_NOACCESS, SPR_NOACCESS,
7624 &spr_read_generic, &spr_write_generic,
7625 KVM_REG_PPC_SDAR, 0x00000000);
7626 }
7627
7628 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7629 {
7630 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7631 &spr_read_ureg, SPR_NOACCESS,
7632 &spr_read_ureg, &spr_write_ureg,
7633 0x00000000);
7634 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7635 &spr_read_ureg, SPR_NOACCESS,
7636 &spr_read_ureg, &spr_write_ureg,
7637 0x00000000);
7638 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7639 &spr_read_ureg, SPR_NOACCESS,
7640 &spr_read_ureg, &spr_write_ureg,
7641 0x00000000);
7642 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7643 &spr_read_ureg, SPR_NOACCESS,
7644 &spr_read_ureg, &spr_write_ureg,
7645 0x00000000);
7646 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7647 &spr_read_ureg, SPR_NOACCESS,
7648 &spr_read_ureg, &spr_write_ureg,
7649 0x00000000);
7650 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7651 &spr_read_ureg, SPR_NOACCESS,
7652 &spr_read_ureg, &spr_write_ureg,
7653 0x00000000);
7654 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7655 &spr_read_ureg, SPR_NOACCESS,
7656 &spr_read_ureg, &spr_write_ureg,
7657 0x00000000);
7658 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7659 &spr_read_ureg, SPR_NOACCESS,
7660 &spr_read_ureg, &spr_write_ureg,
7661 0x00000000);
7662 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7663 &spr_read_ureg, SPR_NOACCESS,
7664 &spr_read_ureg, &spr_write_ureg,
7665 0x00000000);
7666 spr_register(env, SPR_POWER_USIAR, "USIAR",
7667 &spr_read_ureg, SPR_NOACCESS,
7668 &spr_read_ureg, &spr_write_ureg,
7669 0x00000000);
7670 spr_register(env, SPR_POWER_USDAR, "USDAR",
7671 &spr_read_ureg, SPR_NOACCESS,
7672 &spr_read_ureg, &spr_write_ureg,
7673 0x00000000);
7674 }
7675
7676 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7677 {
7678 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7679 SPR_NOACCESS, SPR_NOACCESS,
7680 &spr_read_generic, &spr_write_generic,
7681 KVM_REG_PPC_PMC7, 0x00000000);
7682 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7683 SPR_NOACCESS, SPR_NOACCESS,
7684 &spr_read_generic, &spr_write_generic,
7685 KVM_REG_PPC_PMC8, 0x00000000);
7686 }
7687
7688 static void gen_spr_970_pmu_user(CPUPPCState *env)
7689 {
7690 spr_register(env, SPR_970_UPMC7, "UPMC7",
7691 &spr_read_ureg, SPR_NOACCESS,
7692 &spr_read_ureg, &spr_write_ureg,
7693 0x00000000);
7694 spr_register(env, SPR_970_UPMC8, "UPMC8",
7695 &spr_read_ureg, SPR_NOACCESS,
7696 &spr_read_ureg, &spr_write_ureg,
7697 0x00000000);
7698 }
7699
7700 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7701 {
7702 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7703 SPR_NOACCESS, SPR_NOACCESS,
7704 &spr_read_generic, &spr_write_generic,
7705 KVM_REG_PPC_MMCR2, 0x00000000);
7706 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7707 SPR_NOACCESS, SPR_NOACCESS,
7708 &spr_read_generic, &spr_write_generic,
7709 KVM_REG_PPC_MMCRS, 0x00000000);
7710 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7711 SPR_NOACCESS, SPR_NOACCESS,
7712 &spr_read_generic, &spr_write_generic,
7713 KVM_REG_PPC_SIER, 0x00000000);
7714 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7715 SPR_NOACCESS, SPR_NOACCESS,
7716 &spr_read_generic, &spr_write_generic,
7717 KVM_REG_PPC_SPMC1, 0x00000000);
7718 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7719 SPR_NOACCESS, SPR_NOACCESS,
7720 &spr_read_generic, &spr_write_generic,
7721 KVM_REG_PPC_SPMC2, 0x00000000);
7722 spr_register_kvm(env, SPR_TACR, "TACR",
7723 SPR_NOACCESS, SPR_NOACCESS,
7724 &spr_read_generic, &spr_write_generic,
7725 KVM_REG_PPC_TACR, 0x00000000);
7726 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7727 SPR_NOACCESS, SPR_NOACCESS,
7728 &spr_read_generic, &spr_write_generic,
7729 KVM_REG_PPC_TCSCR, 0x00000000);
7730 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7731 SPR_NOACCESS, SPR_NOACCESS,
7732 &spr_read_generic, &spr_write_generic,
7733 KVM_REG_PPC_CSIGR, 0x00000000);
7734 }
7735
7736 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7737 {
7738 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7739 &spr_read_ureg, SPR_NOACCESS,
7740 &spr_read_ureg, &spr_write_ureg,
7741 0x00000000);
7742 spr_register(env, SPR_POWER_USIER, "USIER",
7743 &spr_read_generic, SPR_NOACCESS,
7744 &spr_read_generic, &spr_write_generic,
7745 0x00000000);
7746 }
7747
7748 static void gen_spr_power5p_ear(CPUPPCState *env)
7749 {
7750 /* External access control */
7751 spr_register(env, SPR_EAR, "EAR",
7752 SPR_NOACCESS, SPR_NOACCESS,
7753 &spr_read_generic, &spr_write_generic,
7754 0x00000000);
7755 }
7756
7757 #if !defined(CONFIG_USER_ONLY)
7758 static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
7759 {
7760 TCGv hmer = tcg_temp_new();
7761
7762 gen_load_spr(hmer, sprn);
7763 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
7764 gen_store_spr(sprn, hmer);
7765 spr_store_dump_spr(sprn);
7766 tcg_temp_free(hmer);
7767 }
7768
7769 static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
7770 {
7771 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7772 }
7773
7774 static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
7775 {
7776 #if defined(TARGET_PPC64)
7777 spr_write_generic(ctx, sprn, gprn);
7778 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7779 #endif
7780 }
7781
7782 #endif /* !defined(CONFIG_USER_ONLY) */
7783
7784 static void gen_spr_970_lpar(CPUPPCState *env)
7785 {
7786 #if !defined(CONFIG_USER_ONLY)
7787 /* Logical partitionning */
7788 /* PPC970: HID4 is effectively the LPCR */
7789 spr_register(env, SPR_970_HID4, "HID4",
7790 SPR_NOACCESS, SPR_NOACCESS,
7791 &spr_read_generic, &spr_write_970_hid4,
7792 0x00000000);
7793 #endif
7794 }
7795
7796 static void gen_spr_power5p_lpar(CPUPPCState *env)
7797 {
7798 #if !defined(CONFIG_USER_ONLY)
7799 /* Logical partitionning */
7800 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7801 SPR_NOACCESS, SPR_NOACCESS,
7802 SPR_NOACCESS, SPR_NOACCESS,
7803 &spr_read_generic, &spr_write_lpcr,
7804 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7805 spr_register_hv(env, SPR_HDEC, "HDEC",
7806 SPR_NOACCESS, SPR_NOACCESS,
7807 SPR_NOACCESS, SPR_NOACCESS,
7808 &spr_read_hdecr, &spr_write_hdecr, 0);
7809 #endif
7810 }
7811
7812 static void gen_spr_book3s_ids(CPUPPCState *env)
7813 {
7814 /* FIXME: Will need to deal with thread vs core only SPRs */
7815
7816 /* Processor identification */
7817 spr_register_hv(env, SPR_PIR, "PIR",
7818 SPR_NOACCESS, SPR_NOACCESS,
7819 SPR_NOACCESS, SPR_NOACCESS,
7820 &spr_read_generic, NULL,
7821 0x00000000);
7822 spr_register_hv(env, SPR_HID0, "HID0",
7823 SPR_NOACCESS, SPR_NOACCESS,
7824 SPR_NOACCESS, SPR_NOACCESS,
7825 &spr_read_generic, &spr_write_generic,
7826 0x00000000);
7827 spr_register_hv(env, SPR_TSCR, "TSCR",
7828 SPR_NOACCESS, SPR_NOACCESS,
7829 SPR_NOACCESS, SPR_NOACCESS,
7830 &spr_read_generic, &spr_write_generic,
7831 0x00000000);
7832 spr_register_hv(env, SPR_HMER, "HMER",
7833 SPR_NOACCESS, SPR_NOACCESS,
7834 SPR_NOACCESS, SPR_NOACCESS,
7835 &spr_read_generic, &spr_write_hmer,
7836 0x00000000);
7837 spr_register_hv(env, SPR_HMEER, "HMEER",
7838 SPR_NOACCESS, SPR_NOACCESS,
7839 SPR_NOACCESS, SPR_NOACCESS,
7840 &spr_read_generic, &spr_write_generic,
7841 0x00000000);
7842 spr_register_hv(env, SPR_TFMR, "TFMR",
7843 SPR_NOACCESS, SPR_NOACCESS,
7844 SPR_NOACCESS, SPR_NOACCESS,
7845 &spr_read_generic, &spr_write_generic,
7846 0x00000000);
7847 spr_register_hv(env, SPR_LPIDR, "LPIDR",
7848 SPR_NOACCESS, SPR_NOACCESS,
7849 SPR_NOACCESS, SPR_NOACCESS,
7850 &spr_read_generic, &spr_write_generic,
7851 0x00000000);
7852 spr_register_hv(env, SPR_HFSCR, "HFSCR",
7853 SPR_NOACCESS, SPR_NOACCESS,
7854 SPR_NOACCESS, SPR_NOACCESS,
7855 &spr_read_generic, &spr_write_generic,
7856 0x00000000);
7857 spr_register_hv(env, SPR_MMCRC, "MMCRC",
7858 SPR_NOACCESS, SPR_NOACCESS,
7859 SPR_NOACCESS, SPR_NOACCESS,
7860 &spr_read_generic, &spr_write_generic,
7861 0x00000000);
7862 spr_register_hv(env, SPR_MMCRH, "MMCRH",
7863 SPR_NOACCESS, SPR_NOACCESS,
7864 SPR_NOACCESS, SPR_NOACCESS,
7865 &spr_read_generic, &spr_write_generic,
7866 0x00000000);
7867 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7868 SPR_NOACCESS, SPR_NOACCESS,
7869 SPR_NOACCESS, SPR_NOACCESS,
7870 &spr_read_generic, &spr_write_generic,
7871 0x00000000);
7872 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7873 SPR_NOACCESS, SPR_NOACCESS,
7874 SPR_NOACCESS, SPR_NOACCESS,
7875 &spr_read_generic, &spr_write_generic,
7876 0x00000000);
7877 spr_register_hv(env, SPR_HSRR0, "HSRR0",
7878 SPR_NOACCESS, SPR_NOACCESS,
7879 SPR_NOACCESS, SPR_NOACCESS,
7880 &spr_read_generic, &spr_write_generic,
7881 0x00000000);
7882 spr_register_hv(env, SPR_HSRR1, "HSRR1",
7883 SPR_NOACCESS, SPR_NOACCESS,
7884 SPR_NOACCESS, SPR_NOACCESS,
7885 &spr_read_generic, &spr_write_generic,
7886 0x00000000);
7887 spr_register_hv(env, SPR_HDAR, "HDAR",
7888 SPR_NOACCESS, SPR_NOACCESS,
7889 SPR_NOACCESS, SPR_NOACCESS,
7890 &spr_read_generic, &spr_write_generic,
7891 0x00000000);
7892 spr_register_hv(env, SPR_HDSISR, "HDSISR",
7893 SPR_NOACCESS, SPR_NOACCESS,
7894 SPR_NOACCESS, SPR_NOACCESS,
7895 &spr_read_generic, &spr_write_generic,
7896 0x00000000);
7897 spr_register_hv(env, SPR_RMOR, "RMOR",
7898 SPR_NOACCESS, SPR_NOACCESS,
7899 SPR_NOACCESS, SPR_NOACCESS,
7900 &spr_read_generic, &spr_write_generic,
7901 0x00000000);
7902 spr_register_hv(env, SPR_HRMOR, "HRMOR",
7903 SPR_NOACCESS, SPR_NOACCESS,
7904 SPR_NOACCESS, SPR_NOACCESS,
7905 &spr_read_generic, &spr_write_generic,
7906 0x00000000);
7907 }
7908
7909 static void gen_spr_power8_ids(CPUPPCState *env)
7910 {
7911 /* Thread identification */
7912 spr_register(env, SPR_TIR, "TIR",
7913 SPR_NOACCESS, SPR_NOACCESS,
7914 &spr_read_generic, SPR_NOACCESS,
7915 0x00000000);
7916 }
7917
7918 static void gen_spr_book3s_purr(CPUPPCState *env)
7919 {
7920 #if !defined(CONFIG_USER_ONLY)
7921 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7922 spr_register_kvm(env, SPR_PURR, "PURR",
7923 &spr_read_purr, SPR_NOACCESS,
7924 &spr_read_purr, SPR_NOACCESS,
7925 KVM_REG_PPC_PURR, 0x00000000);
7926 spr_register_kvm(env, SPR_SPURR, "SPURR",
7927 &spr_read_purr, SPR_NOACCESS,
7928 &spr_read_purr, SPR_NOACCESS,
7929 KVM_REG_PPC_SPURR, 0x00000000);
7930 #endif
7931 }
7932
7933 static void gen_spr_power6_dbg(CPUPPCState *env)
7934 {
7935 #if !defined(CONFIG_USER_ONLY)
7936 spr_register(env, SPR_CFAR, "SPR_CFAR",
7937 SPR_NOACCESS, SPR_NOACCESS,
7938 &spr_read_cfar, &spr_write_cfar,
7939 0x00000000);
7940 #endif
7941 }
7942
7943 static void gen_spr_power5p_common(CPUPPCState *env)
7944 {
7945 spr_register_kvm(env, SPR_PPR, "PPR",
7946 &spr_read_generic, &spr_write_generic,
7947 &spr_read_generic, &spr_write_generic,
7948 KVM_REG_PPC_PPR, 0x00000000);
7949 }
7950
7951 static void gen_spr_power6_common(CPUPPCState *env)
7952 {
7953 #if !defined(CONFIG_USER_ONLY)
7954 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7955 SPR_NOACCESS, SPR_NOACCESS,
7956 &spr_read_generic, &spr_write_generic,
7957 KVM_REG_PPC_DSCR, 0x00000000);
7958 #endif
7959 /*
7960 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7961 * POWERPC_EXCP_INVAL_SPR.
7962 */
7963 spr_register(env, SPR_PCR, "PCR",
7964 SPR_NOACCESS, SPR_NOACCESS,
7965 SPR_NOACCESS, SPR_NOACCESS,
7966 0x00000000);
7967 }
7968
7969 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
7970 {
7971 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7972 spr_read_generic(ctx, gprn, sprn);
7973 }
7974
7975 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
7976 {
7977 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7978 spr_write_generic(ctx, sprn, gprn);
7979 }
7980
7981 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
7982 {
7983 spr_register_kvm(env, SPR_TAR, "TAR",
7984 &spr_read_tar, &spr_write_tar,
7985 &spr_read_generic, &spr_write_generic,
7986 KVM_REG_PPC_TAR, 0x00000000);
7987 }
7988
7989 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
7990 {
7991 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7992 spr_read_generic(ctx, gprn, sprn);
7993 }
7994
7995 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
7996 {
7997 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7998 spr_write_generic(ctx, sprn, gprn);
7999 }
8000
8001 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
8002 {
8003 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8004 spr_read_prev_upper32(ctx, gprn, sprn);
8005 }
8006
8007 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
8008 {
8009 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8010 spr_write_prev_upper32(ctx, sprn, gprn);
8011 }
8012
8013 static void gen_spr_power8_tm(CPUPPCState *env)
8014 {
8015 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
8016 &spr_read_tm, &spr_write_tm,
8017 &spr_read_tm, &spr_write_tm,
8018 KVM_REG_PPC_TFHAR, 0x00000000);
8019 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
8020 &spr_read_tm, &spr_write_tm,
8021 &spr_read_tm, &spr_write_tm,
8022 KVM_REG_PPC_TFIAR, 0x00000000);
8023 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
8024 &spr_read_tm, &spr_write_tm,
8025 &spr_read_tm, &spr_write_tm,
8026 KVM_REG_PPC_TEXASR, 0x00000000);
8027 spr_register(env, SPR_TEXASRU, "TEXASRU",
8028 &spr_read_tm_upper32, &spr_write_tm_upper32,
8029 &spr_read_tm_upper32, &spr_write_tm_upper32,
8030 0x00000000);
8031 }
8032
8033 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
8034 {
8035 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8036 spr_read_generic(ctx, gprn, sprn);
8037 }
8038
8039 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
8040 {
8041 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8042 spr_write_generic(ctx, sprn, gprn);
8043 }
8044
8045 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
8046 {
8047 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8048 spr_read_prev_upper32(ctx, gprn, sprn);
8049 }
8050
8051 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
8052 {
8053 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8054 spr_write_prev_upper32(ctx, sprn, gprn);
8055 }
8056
8057 static void gen_spr_power8_ebb(CPUPPCState *env)
8058 {
8059 spr_register(env, SPR_BESCRS, "BESCRS",
8060 &spr_read_ebb, &spr_write_ebb,
8061 &spr_read_generic, &spr_write_generic,
8062 0x00000000);
8063 spr_register(env, SPR_BESCRSU, "BESCRSU",
8064 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8065 &spr_read_prev_upper32, &spr_write_prev_upper32,
8066 0x00000000);
8067 spr_register(env, SPR_BESCRR, "BESCRR",
8068 &spr_read_ebb, &spr_write_ebb,
8069 &spr_read_generic, &spr_write_generic,
8070 0x00000000);
8071 spr_register(env, SPR_BESCRRU, "BESCRRU",
8072 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8073 &spr_read_prev_upper32, &spr_write_prev_upper32,
8074 0x00000000);
8075 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
8076 &spr_read_ebb, &spr_write_ebb,
8077 &spr_read_generic, &spr_write_generic,
8078 KVM_REG_PPC_EBBHR, 0x00000000);
8079 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
8080 &spr_read_ebb, &spr_write_ebb,
8081 &spr_read_generic, &spr_write_generic,
8082 KVM_REG_PPC_EBBRR, 0x00000000);
8083 spr_register_kvm(env, SPR_BESCR, "BESCR",
8084 &spr_read_ebb, &spr_write_ebb,
8085 &spr_read_generic, &spr_write_generic,
8086 KVM_REG_PPC_BESCR, 0x00000000);
8087 }
8088
8089 /* Virtual Time Base */
8090 static void gen_spr_vtb(CPUPPCState *env)
8091 {
8092 spr_register_kvm(env, SPR_VTB, "VTB",
8093 SPR_NOACCESS, SPR_NOACCESS,
8094 &spr_read_tbl, SPR_NOACCESS,
8095 KVM_REG_PPC_VTB, 0x00000000);
8096 }
8097
8098 static void gen_spr_power8_fscr(CPUPPCState *env)
8099 {
8100 #if defined(CONFIG_USER_ONLY)
8101 target_ulong initval = 1ULL << FSCR_TAR;
8102 #else
8103 target_ulong initval = 0;
8104 #endif
8105 spr_register_kvm(env, SPR_FSCR, "FSCR",
8106 SPR_NOACCESS, SPR_NOACCESS,
8107 &spr_read_generic, &spr_write_generic,
8108 KVM_REG_PPC_FSCR, initval);
8109 }
8110
8111 static void gen_spr_power8_pspb(CPUPPCState *env)
8112 {
8113 spr_register_kvm(env, SPR_PSPB, "PSPB",
8114 SPR_NOACCESS, SPR_NOACCESS,
8115 &spr_read_generic, &spr_write_generic32,
8116 KVM_REG_PPC_PSPB, 0);
8117 }
8118
8119 static void gen_spr_power8_ic(CPUPPCState *env)
8120 {
8121 #if !defined(CONFIG_USER_ONLY)
8122 spr_register_hv(env, SPR_IC, "IC",
8123 SPR_NOACCESS, SPR_NOACCESS,
8124 &spr_read_generic, SPR_NOACCESS,
8125 &spr_read_generic, &spr_write_generic,
8126 0);
8127 #endif
8128 }
8129
8130 static void gen_spr_power8_book4(CPUPPCState *env)
8131 {
8132 /* Add a number of P8 book4 registers */
8133 #if !defined(CONFIG_USER_ONLY)
8134 spr_register_kvm(env, SPR_ACOP, "ACOP",
8135 SPR_NOACCESS, SPR_NOACCESS,
8136 &spr_read_generic, &spr_write_generic,
8137 KVM_REG_PPC_ACOP, 0);
8138 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8139 SPR_NOACCESS, SPR_NOACCESS,
8140 &spr_read_generic, &spr_write_pidr,
8141 KVM_REG_PPC_PID, 0);
8142 spr_register_kvm(env, SPR_WORT, "WORT",
8143 SPR_NOACCESS, SPR_NOACCESS,
8144 &spr_read_generic, &spr_write_generic,
8145 KVM_REG_PPC_WORT, 0);
8146 #endif
8147 }
8148
8149 static void gen_spr_power7_book4(CPUPPCState *env)
8150 {
8151 /* Add a number of P7 book4 registers */
8152 #if !defined(CONFIG_USER_ONLY)
8153 spr_register_kvm(env, SPR_ACOP, "ACOP",
8154 SPR_NOACCESS, SPR_NOACCESS,
8155 &spr_read_generic, &spr_write_generic,
8156 KVM_REG_PPC_ACOP, 0);
8157 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8158 SPR_NOACCESS, SPR_NOACCESS,
8159 &spr_read_generic, &spr_write_generic,
8160 KVM_REG_PPC_PID, 0);
8161 #endif
8162 }
8163
8164 static void gen_spr_power8_rpr(CPUPPCState *env)
8165 {
8166 #if !defined(CONFIG_USER_ONLY)
8167 spr_register_hv(env, SPR_RPR, "RPR",
8168 SPR_NOACCESS, SPR_NOACCESS,
8169 SPR_NOACCESS, SPR_NOACCESS,
8170 &spr_read_generic, &spr_write_generic,
8171 0x00000103070F1F3F);
8172 #endif
8173 }
8174
8175 static void gen_spr_power9_mmu(CPUPPCState *env)
8176 {
8177 #if !defined(CONFIG_USER_ONLY)
8178 /* Partition Table Control */
8179 spr_register_hv(env, SPR_PTCR, "PTCR",
8180 SPR_NOACCESS, SPR_NOACCESS,
8181 SPR_NOACCESS, SPR_NOACCESS,
8182 &spr_read_generic, &spr_write_ptcr,
8183 0x00000000);
8184 #endif
8185 }
8186
8187 static void init_proc_book3s_common(CPUPPCState *env)
8188 {
8189 gen_spr_ne_601(env);
8190 gen_tbl(env);
8191 gen_spr_usprg3(env);
8192 gen_spr_book3s_altivec(env);
8193 gen_spr_book3s_pmu_sup(env);
8194 gen_spr_book3s_pmu_user(env);
8195 gen_spr_book3s_ctrl(env);
8196 }
8197
8198 static void init_proc_970(CPUPPCState *env)
8199 {
8200 /* Common Registers */
8201 init_proc_book3s_common(env);
8202 gen_spr_sdr1(env);
8203 gen_spr_book3s_dbg(env);
8204
8205 /* 970 Specific Registers */
8206 gen_spr_970_hid(env);
8207 gen_spr_970_hior(env);
8208 gen_low_BATs(env);
8209 gen_spr_970_pmu_sup(env);
8210 gen_spr_970_pmu_user(env);
8211 gen_spr_970_lpar(env);
8212 gen_spr_970_dbg(env);
8213
8214 /* env variables */
8215 env->dcache_line_size = 128;
8216 env->icache_line_size = 128;
8217
8218 /* Allocate hardware IRQ controller */
8219 init_excp_970(env);
8220 ppc970_irq_init(ppc_env_get_cpu(env));
8221 }
8222
8223 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8224 {
8225 DeviceClass *dc = DEVICE_CLASS(oc);
8226 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8227
8228 dc->desc = "PowerPC 970";
8229 pcc->init_proc = init_proc_970;
8230 pcc->check_pow = check_pow_970;
8231 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8232 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8233 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8234 PPC_FLOAT_STFIWX |
8235 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8236 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8237 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8238 PPC_64B | PPC_ALTIVEC |
8239 PPC_SEGMENT_64B | PPC_SLBI;
8240 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8241 pcc->msr_mask = (1ull << MSR_SF) |
8242 (1ull << MSR_VR) |
8243 (1ull << MSR_POW) |
8244 (1ull << MSR_EE) |
8245 (1ull << MSR_PR) |
8246 (1ull << MSR_FP) |
8247 (1ull << MSR_ME) |
8248 (1ull << MSR_FE0) |
8249 (1ull << MSR_SE) |
8250 (1ull << MSR_DE) |
8251 (1ull << MSR_FE1) |
8252 (1ull << MSR_IR) |
8253 (1ull << MSR_DR) |
8254 (1ull << MSR_PMM) |
8255 (1ull << MSR_RI);
8256 pcc->mmu_model = POWERPC_MMU_64B;
8257 #if defined(CONFIG_SOFTMMU)
8258 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8259 pcc->hash64_opts = &ppc_hash64_opts_basic;
8260 #endif
8261 pcc->excp_model = POWERPC_EXCP_970;
8262 pcc->bus_model = PPC_FLAGS_INPUT_970;
8263 pcc->bfd_mach = bfd_mach_ppc64;
8264 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8265 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8266 POWERPC_FLAG_BUS_CLK;
8267 pcc->l1_dcache_size = 0x8000;
8268 pcc->l1_icache_size = 0x10000;
8269 }
8270
8271 static void init_proc_power5plus(CPUPPCState *env)
8272 {
8273 /* Common Registers */
8274 init_proc_book3s_common(env);
8275 gen_spr_sdr1(env);
8276 gen_spr_book3s_dbg(env);
8277
8278 /* POWER5+ Specific Registers */
8279 gen_spr_970_hid(env);
8280 gen_spr_970_hior(env);
8281 gen_low_BATs(env);
8282 gen_spr_970_pmu_sup(env);
8283 gen_spr_970_pmu_user(env);
8284 gen_spr_power5p_common(env);
8285 gen_spr_power5p_lpar(env);
8286 gen_spr_power5p_ear(env);
8287
8288 /* env variables */
8289 env->dcache_line_size = 128;
8290 env->icache_line_size = 128;
8291
8292 /* Allocate hardware IRQ controller */
8293 init_excp_970(env);
8294 ppc970_irq_init(ppc_env_get_cpu(env));
8295 }
8296
8297 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8298 {
8299 DeviceClass *dc = DEVICE_CLASS(oc);
8300 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8301
8302 dc->fw_name = "PowerPC,POWER5";
8303 dc->desc = "POWER5+";
8304 pcc->init_proc = init_proc_power5plus;
8305 pcc->check_pow = check_pow_970;
8306 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8307 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8308 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8309 PPC_FLOAT_STFIWX |
8310 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8311 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8312 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8313 PPC_64B |
8314 PPC_SEGMENT_64B | PPC_SLBI;
8315 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8316 pcc->msr_mask = (1ull << MSR_SF) |
8317 (1ull << MSR_VR) |
8318 (1ull << MSR_POW) |
8319 (1ull << MSR_EE) |
8320 (1ull << MSR_PR) |
8321 (1ull << MSR_FP) |
8322 (1ull << MSR_ME) |
8323 (1ull << MSR_FE0) |
8324 (1ull << MSR_SE) |
8325 (1ull << MSR_DE) |
8326 (1ull << MSR_FE1) |
8327 (1ull << MSR_IR) |
8328 (1ull << MSR_DR) |
8329 (1ull << MSR_PMM) |
8330 (1ull << MSR_RI);
8331 pcc->mmu_model = POWERPC_MMU_2_03;
8332 #if defined(CONFIG_SOFTMMU)
8333 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8334 pcc->hash64_opts = &ppc_hash64_opts_basic;
8335 #endif
8336 pcc->excp_model = POWERPC_EXCP_970;
8337 pcc->bus_model = PPC_FLAGS_INPUT_970;
8338 pcc->bfd_mach = bfd_mach_ppc64;
8339 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8340 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8341 POWERPC_FLAG_BUS_CLK;
8342 pcc->l1_dcache_size = 0x8000;
8343 pcc->l1_icache_size = 0x10000;
8344 }
8345
8346 /*
8347 * The CPU used to have a "compat" property which set the
8348 * compatibility mode PVR. However, this was conceptually broken - it
8349 * only makes sense on the pseries machine type (otherwise the guest
8350 * owns the PCR and can control the compatibility mode itself). It's
8351 * been replaced with the 'max-cpu-compat' property on the pseries
8352 * machine type. For backwards compatibility, pseries specially
8353 * parses the -cpu parameter and converts old compat= parameters into
8354 * the appropriate machine parameters. This stub implementation of
8355 * the parameter catches any uses on explicitly created CPUs.
8356 */
8357 static void getset_compat_deprecated(Object *obj, Visitor *v, const char *name,
8358 void *opaque, Error **errp)
8359 {
8360 QNull *null = NULL;
8361
8362 if (!qtest_enabled()) {
8363 error_report("CPU 'compat' property is deprecated and has no effect; "
8364 "use max-cpu-compat machine property instead");
8365 }
8366 visit_type_null(v, name, &null, NULL);
8367 qobject_unref(null);
8368 }
8369
8370 static const PropertyInfo ppc_compat_deprecated_propinfo = {
8371 .name = "str",
8372 .description = "compatibility mode (deprecated)",
8373 .get = getset_compat_deprecated,
8374 .set = getset_compat_deprecated,
8375 };
8376 static Property powerpc_servercpu_properties[] = {
8377 {
8378 .name = "compat",
8379 .info = &ppc_compat_deprecated_propinfo,
8380 },
8381 DEFINE_PROP_END_OF_LIST(),
8382 };
8383
8384 static void init_proc_POWER7(CPUPPCState *env)
8385 {
8386 /* Common Registers */
8387 init_proc_book3s_common(env);
8388 gen_spr_sdr1(env);
8389 gen_spr_book3s_dbg(env);
8390
8391 /* POWER7 Specific Registers */
8392 gen_spr_book3s_ids(env);
8393 gen_spr_amr(env);
8394 gen_spr_book3s_purr(env);
8395 gen_spr_power5p_common(env);
8396 gen_spr_power5p_lpar(env);
8397 gen_spr_power5p_ear(env);
8398 gen_spr_power6_common(env);
8399 gen_spr_power6_dbg(env);
8400 gen_spr_power7_book4(env);
8401
8402 /* env variables */
8403 env->dcache_line_size = 128;
8404 env->icache_line_size = 128;
8405
8406 /* Allocate hardware IRQ controller */
8407 init_excp_POWER7(env);
8408 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8409 }
8410
8411 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8412 {
8413 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8414 return true;
8415 }
8416 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8417 return true;
8418 }
8419 return false;
8420 }
8421
8422 static bool cpu_has_work_POWER7(CPUState *cs)
8423 {
8424 PowerPCCPU *cpu = POWERPC_CPU(cs);
8425 CPUPPCState *env = &cpu->env;
8426
8427 if (cs->halted) {
8428 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8429 return false;
8430 }
8431 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8432 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
8433 return true;
8434 }
8435 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8436 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
8437 return true;
8438 }
8439 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8440 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8441 return true;
8442 }
8443 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8444 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8445 return true;
8446 }
8447 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8448 return true;
8449 }
8450 return false;
8451 } else {
8452 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8453 }
8454 }
8455
8456 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8457 {
8458 DeviceClass *dc = DEVICE_CLASS(oc);
8459 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8460 CPUClass *cc = CPU_CLASS(oc);
8461
8462 dc->fw_name = "PowerPC,POWER7";
8463 dc->desc = "POWER7";
8464 dc->props = powerpc_servercpu_properties;
8465 pcc->pvr_match = ppc_pvr_match_power7;
8466 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8467 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8468 pcc->init_proc = init_proc_POWER7;
8469 pcc->check_pow = check_pow_nocheck;
8470 cc->has_work = cpu_has_work_POWER7;
8471 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8473 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8474 PPC_FLOAT_FRSQRTES |
8475 PPC_FLOAT_STFIWX |
8476 PPC_FLOAT_EXT |
8477 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8478 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8479 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8480 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8481 PPC_SEGMENT_64B | PPC_SLBI |
8482 PPC_POPCNTB | PPC_POPCNTWD |
8483 PPC_CILDST;
8484 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8485 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8486 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8487 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
8488 PPC2_PM_ISA206;
8489 pcc->msr_mask = (1ull << MSR_SF) |
8490 (1ull << MSR_VR) |
8491 (1ull << MSR_VSX) |
8492 (1ull << MSR_EE) |
8493 (1ull << MSR_PR) |
8494 (1ull << MSR_FP) |
8495 (1ull << MSR_ME) |
8496 (1ull << MSR_FE0) |
8497 (1ull << MSR_SE) |
8498 (1ull << MSR_DE) |
8499 (1ull << MSR_FE1) |
8500 (1ull << MSR_IR) |
8501 (1ull << MSR_DR) |
8502 (1ull << MSR_PMM) |
8503 (1ull << MSR_RI) |
8504 (1ull << MSR_LE);
8505 pcc->mmu_model = POWERPC_MMU_2_06;
8506 #if defined(CONFIG_SOFTMMU)
8507 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8508 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8509 #endif
8510 pcc->excp_model = POWERPC_EXCP_POWER7;
8511 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8512 pcc->bfd_mach = bfd_mach_ppc64;
8513 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8514 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8515 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8516 POWERPC_FLAG_VSX;
8517 pcc->l1_dcache_size = 0x8000;
8518 pcc->l1_icache_size = 0x8000;
8519 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8520 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
8521 }
8522
8523 static void init_proc_POWER8(CPUPPCState *env)
8524 {
8525 /* Common Registers */
8526 init_proc_book3s_common(env);
8527 gen_spr_sdr1(env);
8528 gen_spr_book3s_207_dbg(env);
8529
8530 /* POWER8 Specific Registers */
8531 gen_spr_book3s_ids(env);
8532 gen_spr_amr(env);
8533 gen_spr_iamr(env);
8534 gen_spr_book3s_purr(env);
8535 gen_spr_power5p_common(env);
8536 gen_spr_power5p_lpar(env);
8537 gen_spr_power5p_ear(env);
8538 gen_spr_power6_common(env);
8539 gen_spr_power6_dbg(env);
8540 gen_spr_power8_tce_address_control(env);
8541 gen_spr_power8_ids(env);
8542 gen_spr_power8_ebb(env);
8543 gen_spr_power8_fscr(env);
8544 gen_spr_power8_pmu_sup(env);
8545 gen_spr_power8_pmu_user(env);
8546 gen_spr_power8_tm(env);
8547 gen_spr_power8_pspb(env);
8548 gen_spr_vtb(env);
8549 gen_spr_power8_ic(env);
8550 gen_spr_power8_book4(env);
8551 gen_spr_power8_rpr(env);
8552
8553 /* env variables */
8554 env->dcache_line_size = 128;
8555 env->icache_line_size = 128;
8556
8557 /* Allocate hardware IRQ controller */
8558 init_excp_POWER8(env);
8559 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8560 }
8561
8562 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8563 {
8564 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8565 return true;
8566 }
8567 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8568 return true;
8569 }
8570 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8571 return true;
8572 }
8573 return false;
8574 }
8575
8576 static bool cpu_has_work_POWER8(CPUState *cs)
8577 {
8578 PowerPCCPU *cpu = POWERPC_CPU(cs);
8579 CPUPPCState *env = &cpu->env;
8580
8581 if (cs->halted) {
8582 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8583 return false;
8584 }
8585 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8586 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
8587 return true;
8588 }
8589 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8590 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
8591 return true;
8592 }
8593 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8594 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8595 return true;
8596 }
8597 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8598 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8599 return true;
8600 }
8601 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8602 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
8603 return true;
8604 }
8605 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8606 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
8607 return true;
8608 }
8609 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8610 return true;
8611 }
8612 return false;
8613 } else {
8614 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8615 }
8616 }
8617
8618 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8619 {
8620 DeviceClass *dc = DEVICE_CLASS(oc);
8621 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8622 CPUClass *cc = CPU_CLASS(oc);
8623
8624 dc->fw_name = "PowerPC,POWER8";
8625 dc->desc = "POWER8";
8626 dc->props = powerpc_servercpu_properties;
8627 pcc->pvr_match = ppc_pvr_match_power8;
8628 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8629 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8630 pcc->init_proc = init_proc_POWER8;
8631 pcc->check_pow = check_pow_nocheck;
8632 cc->has_work = cpu_has_work_POWER8;
8633 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8634 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8635 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8636 PPC_FLOAT_FRSQRTES |
8637 PPC_FLOAT_STFIWX |
8638 PPC_FLOAT_EXT |
8639 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8640 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8641 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8642 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8643 PPC_SEGMENT_64B | PPC_SLBI |
8644 PPC_POPCNTB | PPC_POPCNTWD |
8645 PPC_CILDST;
8646 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8647 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8648 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8649 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8650 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8651 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8652 PPC2_TM | PPC2_PM_ISA206;
8653 pcc->msr_mask = (1ull << MSR_SF) |
8654 (1ull << MSR_SHV) |
8655 (1ull << MSR_TM) |
8656 (1ull << MSR_VR) |
8657 (1ull << MSR_VSX) |
8658 (1ull << MSR_EE) |
8659 (1ull << MSR_PR) |
8660 (1ull << MSR_FP) |
8661 (1ull << MSR_ME) |
8662 (1ull << MSR_FE0) |
8663 (1ull << MSR_SE) |
8664 (1ull << MSR_DE) |
8665 (1ull << MSR_FE1) |
8666 (1ull << MSR_IR) |
8667 (1ull << MSR_DR) |
8668 (1ull << MSR_PMM) |
8669 (1ull << MSR_RI) |
8670 (1ull << MSR_TS0) |
8671 (1ull << MSR_TS1) |
8672 (1ull << MSR_LE);
8673 pcc->mmu_model = POWERPC_MMU_2_07;
8674 #if defined(CONFIG_SOFTMMU)
8675 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8676 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8677 #endif
8678 pcc->excp_model = POWERPC_EXCP_POWER8;
8679 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8680 pcc->bfd_mach = bfd_mach_ppc64;
8681 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8682 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8683 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8684 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8685 pcc->l1_dcache_size = 0x8000;
8686 pcc->l1_icache_size = 0x8000;
8687 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8688 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
8689 LPCR_P8_PECE3 | LPCR_P8_PECE4;
8690 }
8691
8692 #ifdef CONFIG_SOFTMMU
8693 /*
8694 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8695 * Encoded as array of int_32s in the form:
8696 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8697 * x -> AP encoding
8698 * y -> radix mode supported page size (encoded as a shift)
8699 */
8700 static struct ppc_radix_page_info POWER9_radix_page_info = {
8701 .count = 4,
8702 .entries = {
8703 0x0000000c, /* 4K - enc: 0x0 */
8704 0xa0000010, /* 64K - enc: 0x5 */
8705 0x20000015, /* 2M - enc: 0x1 */
8706 0x4000001e /* 1G - enc: 0x2 */
8707 }
8708 };
8709 #endif /* CONFIG_SOFTMMU */
8710
8711 static void init_proc_POWER9(CPUPPCState *env)
8712 {
8713 /* Common Registers */
8714 init_proc_book3s_common(env);
8715 gen_spr_book3s_207_dbg(env);
8716
8717 /* POWER8 Specific Registers */
8718 gen_spr_book3s_ids(env);
8719 gen_spr_amr(env);
8720 gen_spr_iamr(env);
8721 gen_spr_book3s_purr(env);
8722 gen_spr_power5p_common(env);
8723 gen_spr_power5p_lpar(env);
8724 gen_spr_power5p_ear(env);
8725 gen_spr_power6_common(env);
8726 gen_spr_power6_dbg(env);
8727 gen_spr_power8_tce_address_control(env);
8728 gen_spr_power8_ids(env);
8729 gen_spr_power8_ebb(env);
8730 gen_spr_power8_fscr(env);
8731 gen_spr_power8_pmu_sup(env);
8732 gen_spr_power8_pmu_user(env);
8733 gen_spr_power8_tm(env);
8734 gen_spr_power8_pspb(env);
8735 gen_spr_vtb(env);
8736 gen_spr_power8_ic(env);
8737 gen_spr_power8_book4(env);
8738 gen_spr_power8_rpr(env);
8739 gen_spr_power9_mmu(env);
8740
8741 /* POWER9 Specific registers */
8742 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
8743 spr_read_generic, spr_write_generic,
8744 KVM_REG_PPC_TIDR, 0);
8745
8746 /* FIXME: Filter fields properly based on privilege level */
8747 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8748 spr_read_generic, spr_write_generic,
8749 KVM_REG_PPC_PSSCR, 0);
8750
8751 /* env variables */
8752 env->dcache_line_size = 128;
8753 env->icache_line_size = 128;
8754
8755 /* Allocate hardware IRQ controller */
8756 init_excp_POWER8(env);
8757 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8758 }
8759
8760 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
8761 {
8762 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8763 return true;
8764 }
8765 return false;
8766 }
8767
8768 static bool cpu_has_work_POWER9(CPUState *cs)
8769 {
8770 PowerPCCPU *cpu = POWERPC_CPU(cs);
8771 CPUPPCState *env = &cpu->env;
8772
8773 if (cs->halted) {
8774 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8775 return false;
8776 }
8777 /* External Exception */
8778 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8779 (env->spr[SPR_LPCR] & LPCR_EEE)) {
8780 return true;
8781 }
8782 /* Decrementer Exception */
8783 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8784 (env->spr[SPR_LPCR] & LPCR_DEE)) {
8785 return true;
8786 }
8787 /* Machine Check or Hypervisor Maintenance Exception */
8788 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8789 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8790 return true;
8791 }
8792 /* Privileged Doorbell Exception */
8793 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8794 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8795 return true;
8796 }
8797 /* Hypervisor Doorbell Exception */
8798 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8799 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8800 return true;
8801 }
8802 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8803 return true;
8804 }
8805 return false;
8806 } else {
8807 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8808 }
8809 }
8810
8811 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8812 {
8813 DeviceClass *dc = DEVICE_CLASS(oc);
8814 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8815 CPUClass *cc = CPU_CLASS(oc);
8816
8817 dc->fw_name = "PowerPC,POWER9";
8818 dc->desc = "POWER9";
8819 dc->props = powerpc_servercpu_properties;
8820 pcc->pvr_match = ppc_pvr_match_power9;
8821 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8822 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8823 PCR_COMPAT_2_05;
8824 pcc->init_proc = init_proc_POWER9;
8825 pcc->check_pow = check_pow_nocheck;
8826 cc->has_work = cpu_has_work_POWER9;
8827 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8828 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8829 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8830 PPC_FLOAT_FRSQRTES |
8831 PPC_FLOAT_STFIWX |
8832 PPC_FLOAT_EXT |
8833 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8834 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8835 PPC_MEM_TLBSYNC |
8836 PPC_64B | PPC_64BX | PPC_ALTIVEC |
8837 PPC_SEGMENT_64B | PPC_SLBI |
8838 PPC_POPCNTB | PPC_POPCNTWD |
8839 PPC_CILDST;
8840 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8841 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8842 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8843 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8844 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8845 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8846 PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300 | PPC2_PRCNTL;
8847 pcc->msr_mask = (1ull << MSR_SF) |
8848 (1ull << MSR_TM) |
8849 (1ull << MSR_VR) |
8850 (1ull << MSR_VSX) |
8851 (1ull << MSR_EE) |
8852 (1ull << MSR_PR) |
8853 (1ull << MSR_FP) |
8854 (1ull << MSR_ME) |
8855 (1ull << MSR_FE0) |
8856 (1ull << MSR_SE) |
8857 (1ull << MSR_DE) |
8858 (1ull << MSR_FE1) |
8859 (1ull << MSR_IR) |
8860 (1ull << MSR_DR) |
8861 (1ull << MSR_PMM) |
8862 (1ull << MSR_RI) |
8863 (1ull << MSR_LE);
8864 pcc->mmu_model = POWERPC_MMU_3_00;
8865 #if defined(CONFIG_SOFTMMU)
8866 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8867 /* segment page size remain the same */
8868 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8869 pcc->radix_page_info = &POWER9_radix_page_info;
8870 #endif
8871 pcc->excp_model = POWERPC_EXCP_POWER8;
8872 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8873 pcc->bfd_mach = bfd_mach_ppc64;
8874 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8875 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8876 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8877 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8878 pcc->l1_dcache_size = 0x8000;
8879 pcc->l1_icache_size = 0x8000;
8880 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8881 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8882 }
8883
8884 #if !defined(CONFIG_USER_ONLY)
8885 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8886 {
8887 CPUPPCState *env = &cpu->env;
8888
8889 cpu->vhyp = vhyp;
8890
8891 /*
8892 * With a virtual hypervisor mode we never allow the CPU to go
8893 * hypervisor mode itself
8894 */
8895 env->msr_mask &= ~MSR_HVB;
8896 }
8897
8898 #endif /* !defined(CONFIG_USER_ONLY) */
8899
8900 #endif /* defined(TARGET_PPC64) */
8901
8902 /*****************************************************************************/
8903 /* Generic CPU instantiation routine */
8904 static void init_ppc_proc(PowerPCCPU *cpu)
8905 {
8906 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8907 CPUPPCState *env = &cpu->env;
8908 #if !defined(CONFIG_USER_ONLY)
8909 int i;
8910
8911 env->irq_inputs = NULL;
8912 /* Set all exception vectors to an invalid address */
8913 for (i = 0; i < POWERPC_EXCP_NB; i++)
8914 env->excp_vectors[i] = (target_ulong)(-1ULL);
8915 env->ivor_mask = 0x00000000;
8916 env->ivpr_mask = 0x00000000;
8917 /* Default MMU definitions */
8918 env->nb_BATs = 0;
8919 env->nb_tlb = 0;
8920 env->nb_ways = 0;
8921 env->tlb_type = TLB_NONE;
8922 #endif
8923 /* Register SPR common to all PowerPC implementations */
8924 gen_spr_generic(env);
8925 spr_register(env, SPR_PVR, "PVR",
8926 /* Linux permits userspace to read PVR */
8927 #if defined(CONFIG_LINUX_USER)
8928 &spr_read_generic,
8929 #else
8930 SPR_NOACCESS,
8931 #endif
8932 SPR_NOACCESS,
8933 &spr_read_generic, SPR_NOACCESS,
8934 pcc->pvr);
8935 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8936 if (pcc->svr != POWERPC_SVR_NONE) {
8937 if (pcc->svr & POWERPC_SVR_E500) {
8938 spr_register(env, SPR_E500_SVR, "SVR",
8939 SPR_NOACCESS, SPR_NOACCESS,
8940 &spr_read_generic, SPR_NOACCESS,
8941 pcc->svr & ~POWERPC_SVR_E500);
8942 } else {
8943 spr_register(env, SPR_SVR, "SVR",
8944 SPR_NOACCESS, SPR_NOACCESS,
8945 &spr_read_generic, SPR_NOACCESS,
8946 pcc->svr);
8947 }
8948 }
8949 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8950 (*pcc->init_proc)(env);
8951
8952 /* MSR bits & flags consistency checks */
8953 if (env->msr_mask & (1 << 25)) {
8954 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8955 case POWERPC_FLAG_SPE:
8956 case POWERPC_FLAG_VRE:
8957 break;
8958 default:
8959 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8960 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8961 exit(1);
8962 }
8963 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8964 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8965 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8966 exit(1);
8967 }
8968 if (env->msr_mask & (1 << 17)) {
8969 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8970 case POWERPC_FLAG_TGPR:
8971 case POWERPC_FLAG_CE:
8972 break;
8973 default:
8974 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8975 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8976 exit(1);
8977 }
8978 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8979 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8980 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8981 exit(1);
8982 }
8983 if (env->msr_mask & (1 << 10)) {
8984 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8985 POWERPC_FLAG_UBLE)) {
8986 case POWERPC_FLAG_SE:
8987 case POWERPC_FLAG_DWE:
8988 case POWERPC_FLAG_UBLE:
8989 break;
8990 default:
8991 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8992 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8993 "POWERPC_FLAG_UBLE\n");
8994 exit(1);
8995 }
8996 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8997 POWERPC_FLAG_UBLE)) {
8998 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8999 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9000 "POWERPC_FLAG_UBLE\n");
9001 exit(1);
9002 }
9003 if (env->msr_mask & (1 << 9)) {
9004 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9005 case POWERPC_FLAG_BE:
9006 case POWERPC_FLAG_DE:
9007 break;
9008 default:
9009 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9010 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9011 exit(1);
9012 }
9013 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9014 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9015 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9016 exit(1);
9017 }
9018 if (env->msr_mask & (1 << 2)) {
9019 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9020 case POWERPC_FLAG_PX:
9021 case POWERPC_FLAG_PMM:
9022 break;
9023 default:
9024 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9025 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9026 exit(1);
9027 }
9028 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9029 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9030 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9031 exit(1);
9032 }
9033 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9034 fprintf(stderr, "PowerPC flags inconsistency\n"
9035 "Should define the time-base and decrementer clock source\n");
9036 exit(1);
9037 }
9038 /* Allocate TLBs buffer when needed */
9039 #if !defined(CONFIG_USER_ONLY)
9040 if (env->nb_tlb != 0) {
9041 int nb_tlb = env->nb_tlb;
9042 if (env->id_tlbs != 0)
9043 nb_tlb *= 2;
9044 switch (env->tlb_type) {
9045 case TLB_6XX:
9046 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9047 break;
9048 case TLB_EMB:
9049 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9050 break;
9051 case TLB_MAS:
9052 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9053 break;
9054 }
9055 /* Pre-compute some useful values */
9056 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9057 }
9058 if (env->irq_inputs == NULL) {
9059 warn_report("no internal IRQ controller registered."
9060 " Attempt QEMU to crash very soon !");
9061 }
9062 #endif
9063 if (env->check_pow == NULL) {
9064 warn_report("no power management check handler registered."
9065 " Attempt QEMU to crash very soon !");
9066 }
9067 }
9068
9069 #if defined(PPC_DUMP_CPU)
9070 static void dump_ppc_sprs(CPUPPCState *env)
9071 {
9072 ppc_spr_t *spr;
9073 #if !defined(CONFIG_USER_ONLY)
9074 uint32_t sr, sw;
9075 #endif
9076 uint32_t ur, uw;
9077 int i, j, n;
9078
9079 printf("Special purpose registers:\n");
9080 for (i = 0; i < 32; i++) {
9081 for (j = 0; j < 32; j++) {
9082 n = (i << 5) | j;
9083 spr = &env->spr_cb[n];
9084 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9085 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9086 #if !defined(CONFIG_USER_ONLY)
9087 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9088 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9089 if (sw || sr || uw || ur) {
9090 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9091 (i << 5) | j, (i << 5) | j, spr->name,
9092 sw ? 'w' : '-', sr ? 'r' : '-',
9093 uw ? 'w' : '-', ur ? 'r' : '-');
9094 }
9095 #else
9096 if (uw || ur) {
9097 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9098 (i << 5) | j, (i << 5) | j, spr->name,
9099 uw ? 'w' : '-', ur ? 'r' : '-');
9100 }
9101 #endif
9102 }
9103 }
9104 fflush(stdout);
9105 fflush(stderr);
9106 }
9107 #endif
9108
9109 /*****************************************************************************/
9110
9111 /* Opcode types */
9112 enum {
9113 PPC_DIRECT = 0, /* Opcode routine */
9114 PPC_INDIRECT = 1, /* Indirect opcode table */
9115 };
9116
9117 #define PPC_OPCODE_MASK 0x3
9118
9119 static inline int is_indirect_opcode(void *handler)
9120 {
9121 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
9122 }
9123
9124 static inline opc_handler_t **ind_table(void *handler)
9125 {
9126 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
9127 }
9128
9129 /* Instruction table creation */
9130 /* Opcodes tables creation */
9131 static void fill_new_table(opc_handler_t **table, int len)
9132 {
9133 int i;
9134
9135 for (i = 0; i < len; i++)
9136 table[i] = &invalid_handler;
9137 }
9138
9139 static int create_new_table(opc_handler_t **table, unsigned char idx)
9140 {
9141 opc_handler_t **tmp;
9142
9143 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
9144 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
9145 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9146
9147 return 0;
9148 }
9149
9150 static int insert_in_table(opc_handler_t **table, unsigned char idx,
9151 opc_handler_t *handler)
9152 {
9153 if (table[idx] != &invalid_handler)
9154 return -1;
9155 table[idx] = handler;
9156
9157 return 0;
9158 }
9159
9160 static int register_direct_insn(opc_handler_t **ppc_opcodes,
9161 unsigned char idx, opc_handler_t *handler)
9162 {
9163 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9164 printf("*** ERROR: opcode %02x already assigned in main "
9165 "opcode table\n", idx);
9166 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9167 printf(" Registered handler '%s' - new handler '%s'\n",
9168 ppc_opcodes[idx]->oname, handler->oname);
9169 #endif
9170 return -1;
9171 }
9172
9173 return 0;
9174 }
9175
9176 static int register_ind_in_table(opc_handler_t **table,
9177 unsigned char idx1, unsigned char idx2,
9178 opc_handler_t *handler)
9179 {
9180 if (table[idx1] == &invalid_handler) {
9181 if (create_new_table(table, idx1) < 0) {
9182 printf("*** ERROR: unable to create indirect table "
9183 "idx=%02x\n", idx1);
9184 return -1;
9185 }
9186 } else {
9187 if (!is_indirect_opcode(table[idx1])) {
9188 printf("*** ERROR: idx %02x already assigned to a direct "
9189 "opcode\n", idx1);
9190 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9191 printf(" Registered handler '%s' - new handler '%s'\n",
9192 ind_table(table[idx1])[idx2]->oname, handler->oname);
9193 #endif
9194 return -1;
9195 }
9196 }
9197 if (handler != NULL &&
9198 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9199 printf("*** ERROR: opcode %02x already assigned in "
9200 "opcode table %02x\n", idx2, idx1);
9201 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9202 printf(" Registered handler '%s' - new handler '%s'\n",
9203 ind_table(table[idx1])[idx2]->oname, handler->oname);
9204 #endif
9205 return -1;
9206 }
9207
9208 return 0;
9209 }
9210
9211 static int register_ind_insn(opc_handler_t **ppc_opcodes,
9212 unsigned char idx1, unsigned char idx2,
9213 opc_handler_t *handler)
9214 {
9215 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9216 }
9217
9218 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
9219 unsigned char idx1, unsigned char idx2,
9220 unsigned char idx3, opc_handler_t *handler)
9221 {
9222 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9223 printf("*** ERROR: unable to join indirect table idx "
9224 "[%02x-%02x]\n", idx1, idx2);
9225 return -1;
9226 }
9227 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9228 handler) < 0) {
9229 printf("*** ERROR: unable to insert opcode "
9230 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9231 return -1;
9232 }
9233
9234 return 0;
9235 }
9236
9237 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
9238 unsigned char idx1, unsigned char idx2,
9239 unsigned char idx3, unsigned char idx4,
9240 opc_handler_t *handler)
9241 {
9242 opc_handler_t **table;
9243
9244 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9245 printf("*** ERROR: unable to join indirect table idx "
9246 "[%02x-%02x]\n", idx1, idx2);
9247 return -1;
9248 }
9249 table = ind_table(ppc_opcodes[idx1]);
9250 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
9251 printf("*** ERROR: unable to join 2nd-level indirect table idx "
9252 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9253 return -1;
9254 }
9255 table = ind_table(table[idx2]);
9256 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
9257 printf("*** ERROR: unable to insert opcode "
9258 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
9259 return -1;
9260 }
9261 return 0;
9262 }
9263 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
9264 {
9265 if (insn->opc2 != 0xFF) {
9266 if (insn->opc3 != 0xFF) {
9267 if (insn->opc4 != 0xFF) {
9268 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9269 insn->opc3, insn->opc4,
9270 &insn->handler) < 0) {
9271 return -1;
9272 }
9273 } else {
9274 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9275 insn->opc3, &insn->handler) < 0)
9276 return -1;
9277 }
9278 } else {
9279 if (register_ind_insn(ppc_opcodes, insn->opc1,
9280 insn->opc2, &insn->handler) < 0)
9281 return -1;
9282 }
9283 } else {
9284 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9285 return -1;
9286 }
9287
9288 return 0;
9289 }
9290
9291 static int test_opcode_table(opc_handler_t **table, int len)
9292 {
9293 int i, count, tmp;
9294
9295 for (i = 0, count = 0; i < len; i++) {
9296 /* Consistency fixup */
9297 if (table[i] == NULL)
9298 table[i] = &invalid_handler;
9299 if (table[i] != &invalid_handler) {
9300 if (is_indirect_opcode(table[i])) {
9301 tmp = test_opcode_table(ind_table(table[i]),
9302 PPC_CPU_INDIRECT_OPCODES_LEN);
9303 if (tmp == 0) {
9304 free(table[i]);
9305 table[i] = &invalid_handler;
9306 } else {
9307 count++;
9308 }
9309 } else {
9310 count++;
9311 }
9312 }
9313 }
9314
9315 return count;
9316 }
9317
9318 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
9319 {
9320 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
9321 printf("*** WARNING: no opcode defined !\n");
9322 }
9323
9324 /*****************************************************************************/
9325 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9326 {
9327 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9328 CPUPPCState *env = &cpu->env;
9329 opcode_t *opc;
9330
9331 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
9332 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9333 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9334 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9335 if (register_insn(env->opcodes, opc) < 0) {
9336 error_setg(errp, "ERROR initializing PowerPC instruction "
9337 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9338 opc->opc3);
9339 return;
9340 }
9341 }
9342 }
9343 fix_opcode_tables(env->opcodes);
9344 fflush(stdout);
9345 fflush(stderr);
9346 }
9347
9348 #if defined(PPC_DUMP_CPU)
9349 static void dump_ppc_insns(CPUPPCState *env)
9350 {
9351 opc_handler_t **table, *handler;
9352 const char *p, *q;
9353 uint8_t opc1, opc2, opc3, opc4;
9354
9355 printf("Instructions set:\n");
9356 /* opc1 is 6 bits long */
9357 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
9358 table = env->opcodes;
9359 handler = table[opc1];
9360 if (is_indirect_opcode(handler)) {
9361 /* opc2 is 5 bits long */
9362 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
9363 table = env->opcodes;
9364 handler = env->opcodes[opc1];
9365 table = ind_table(handler);
9366 handler = table[opc2];
9367 if (is_indirect_opcode(handler)) {
9368 table = ind_table(handler);
9369 /* opc3 is 5 bits long */
9370 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9371 opc3++) {
9372 handler = table[opc3];
9373 if (is_indirect_opcode(handler)) {
9374 table = ind_table(handler);
9375 /* opc4 is 5 bits long */
9376 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9377 opc4++) {
9378 handler = table[opc4];
9379 if (handler->handler != &gen_invalid) {
9380 printf("INSN: %02x %02x %02x %02x -- "
9381 "(%02d %04d %02d) : %s\n",
9382 opc1, opc2, opc3, opc4,
9383 opc1, (opc3 << 5) | opc2, opc4,
9384 handler->oname);
9385 }
9386 }
9387 } else {
9388 if (handler->handler != &gen_invalid) {
9389 /* Special hack to properly dump SPE insns */
9390 p = strchr(handler->oname, '_');
9391 if (p == NULL) {
9392 printf("INSN: %02x %02x %02x (%02d %04d) : "
9393 "%s\n",
9394 opc1, opc2, opc3, opc1,
9395 (opc3 << 5) | opc2,
9396 handler->oname);
9397 } else {
9398 q = "speundef";
9399 if ((p - handler->oname) != strlen(q)
9400 || (memcmp(handler->oname, q, strlen(q))
9401 != 0)) {
9402 /* First instruction */
9403 printf("INSN: %02x %02x %02x"
9404 "(%02d %04d) : %.*s\n",
9405 opc1, opc2 << 1, opc3, opc1,
9406 (opc3 << 6) | (opc2 << 1),
9407 (int)(p - handler->oname),
9408 handler->oname);
9409 }
9410 if (strcmp(p + 1, q) != 0) {
9411 /* Second instruction */
9412 printf("INSN: %02x %02x %02x "
9413 "(%02d %04d) : %s\n", opc1,
9414 (opc2 << 1) | 1, opc3, opc1,
9415 (opc3 << 6) | (opc2 << 1) | 1,
9416 p + 1);
9417 }
9418 }
9419 }
9420 }
9421 }
9422 } else {
9423 if (handler->handler != &gen_invalid) {
9424 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9425 opc1, opc2, opc1, opc2, handler->oname);
9426 }
9427 }
9428 }
9429 } else {
9430 if (handler->handler != &gen_invalid) {
9431 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9432 opc1, opc1, handler->oname);
9433 }
9434 }
9435 }
9436 }
9437 #endif
9438
9439 static bool avr_need_swap(CPUPPCState *env)
9440 {
9441 #ifdef HOST_WORDS_BIGENDIAN
9442 return msr_le;
9443 #else
9444 return !msr_le;
9445 #endif
9446 }
9447
9448 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9449 {
9450 if (n < 32) {
9451 stfq_p(mem_buf, env->fpr[n]);
9452 ppc_maybe_bswap_register(env, mem_buf, 8);
9453 return 8;
9454 }
9455 if (n == 32) {
9456 stl_p(mem_buf, env->fpscr);
9457 ppc_maybe_bswap_register(env, mem_buf, 4);
9458 return 4;
9459 }
9460 return 0;
9461 }
9462
9463 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9464 {
9465 if (n < 32) {
9466 ppc_maybe_bswap_register(env, mem_buf, 8);
9467 env->fpr[n] = ldfq_p(mem_buf);
9468 return 8;
9469 }
9470 if (n == 32) {
9471 ppc_maybe_bswap_register(env, mem_buf, 4);
9472 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9473 return 4;
9474 }
9475 return 0;
9476 }
9477
9478 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9479 {
9480 if (n < 32) {
9481 if (!avr_need_swap(env)) {
9482 stq_p(mem_buf, env->avr[n].u64[0]);
9483 stq_p(mem_buf+8, env->avr[n].u64[1]);
9484 } else {
9485 stq_p(mem_buf, env->avr[n].u64[1]);
9486 stq_p(mem_buf+8, env->avr[n].u64[0]);
9487 }
9488 ppc_maybe_bswap_register(env, mem_buf, 8);
9489 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9490 return 16;
9491 }
9492 if (n == 32) {
9493 stl_p(mem_buf, env->vscr);
9494 ppc_maybe_bswap_register(env, mem_buf, 4);
9495 return 4;
9496 }
9497 if (n == 33) {
9498 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9499 ppc_maybe_bswap_register(env, mem_buf, 4);
9500 return 4;
9501 }
9502 return 0;
9503 }
9504
9505 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9506 {
9507 if (n < 32) {
9508 ppc_maybe_bswap_register(env, mem_buf, 8);
9509 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9510 if (!avr_need_swap(env)) {
9511 env->avr[n].u64[0] = ldq_p(mem_buf);
9512 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9513 } else {
9514 env->avr[n].u64[1] = ldq_p(mem_buf);
9515 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9516 }
9517 return 16;
9518 }
9519 if (n == 32) {
9520 ppc_maybe_bswap_register(env, mem_buf, 4);
9521 env->vscr = ldl_p(mem_buf);
9522 return 4;
9523 }
9524 if (n == 33) {
9525 ppc_maybe_bswap_register(env, mem_buf, 4);
9526 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9527 return 4;
9528 }
9529 return 0;
9530 }
9531
9532 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9533 {
9534 if (n < 32) {
9535 #if defined(TARGET_PPC64)
9536 stl_p(mem_buf, env->gpr[n] >> 32);
9537 ppc_maybe_bswap_register(env, mem_buf, 4);
9538 #else
9539 stl_p(mem_buf, env->gprh[n]);
9540 #endif
9541 return 4;
9542 }
9543 if (n == 32) {
9544 stq_p(mem_buf, env->spe_acc);
9545 ppc_maybe_bswap_register(env, mem_buf, 8);
9546 return 8;
9547 }
9548 if (n == 33) {
9549 stl_p(mem_buf, env->spe_fscr);
9550 ppc_maybe_bswap_register(env, mem_buf, 4);
9551 return 4;
9552 }
9553 return 0;
9554 }
9555
9556 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9557 {
9558 if (n < 32) {
9559 #if defined(TARGET_PPC64)
9560 target_ulong lo = (uint32_t)env->gpr[n];
9561 target_ulong hi;
9562
9563 ppc_maybe_bswap_register(env, mem_buf, 4);
9564
9565 hi = (target_ulong)ldl_p(mem_buf) << 32;
9566 env->gpr[n] = lo | hi;
9567 #else
9568 env->gprh[n] = ldl_p(mem_buf);
9569 #endif
9570 return 4;
9571 }
9572 if (n == 32) {
9573 ppc_maybe_bswap_register(env, mem_buf, 8);
9574 env->spe_acc = ldq_p(mem_buf);
9575 return 8;
9576 }
9577 if (n == 33) {
9578 ppc_maybe_bswap_register(env, mem_buf, 4);
9579 env->spe_fscr = ldl_p(mem_buf);
9580 return 4;
9581 }
9582 return 0;
9583 }
9584
9585 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9586 {
9587 if (n < 32) {
9588 stq_p(mem_buf, env->vsr[n]);
9589 ppc_maybe_bswap_register(env, mem_buf, 8);
9590 return 8;
9591 }
9592 return 0;
9593 }
9594
9595 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9596 {
9597 if (n < 32) {
9598 ppc_maybe_bswap_register(env, mem_buf, 8);
9599 env->vsr[n] = ldq_p(mem_buf);
9600 return 8;
9601 }
9602 return 0;
9603 }
9604
9605 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9606 {
9607 CPUPPCState *env = &cpu->env;
9608
9609 /* TCG doesn't (yet) emulate some groups of instructions that
9610 * are implemented on some otherwise supported CPUs (e.g. VSX
9611 * and decimal floating point instructions on POWER7). We
9612 * remove unsupported instruction groups from the cpu state's
9613 * instruction masks and hope the guest can cope. For at
9614 * least the pseries machine, the unavailability of these
9615 * instructions can be advertised to the guest via the device
9616 * tree. */
9617 if ((env->insns_flags & ~PPC_TCG_INSNS)
9618 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9619 warn_report("Disabling some instructions which are not "
9620 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
9621 env->insns_flags & ~PPC_TCG_INSNS,
9622 env->insns_flags2 & ~PPC_TCG_INSNS2);
9623 }
9624 env->insns_flags &= PPC_TCG_INSNS;
9625 env->insns_flags2 &= PPC_TCG_INSNS2;
9626 return 0;
9627 }
9628
9629 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9630 {
9631 #ifdef TARGET_PPCEMB
9632 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9633 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9634 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9635 #else
9636 return true;
9637 #endif
9638 }
9639
9640 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
9641 {
9642 CPUState *cs = CPU(dev);
9643 PowerPCCPU *cpu = POWERPC_CPU(dev);
9644 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9645 Error *local_err = NULL;
9646
9647 cpu_exec_realizefn(cs, &local_err);
9648 if (local_err != NULL) {
9649 error_propagate(errp, local_err);
9650 return;
9651 }
9652 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
9653 cpu->vcpu_id = cs->cpu_index;
9654 }
9655
9656 if (tcg_enabled()) {
9657 if (ppc_fixup_cpu(cpu) != 0) {
9658 error_setg(errp, "Unable to emulate selected CPU with TCG");
9659 goto unrealize;
9660 }
9661 }
9662
9663 assert(ppc_cpu_is_valid(pcc));
9664
9665 create_ppc_opcodes(cpu, &local_err);
9666 if (local_err != NULL) {
9667 error_propagate(errp, local_err);
9668 goto unrealize;
9669 }
9670 init_ppc_proc(cpu);
9671
9672 if (pcc->insns_flags & PPC_FLOAT) {
9673 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9674 33, "power-fpu.xml", 0);
9675 }
9676 if (pcc->insns_flags & PPC_ALTIVEC) {
9677 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9678 34, "power-altivec.xml", 0);
9679 }
9680 if (pcc->insns_flags & PPC_SPE) {
9681 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9682 34, "power-spe.xml", 0);
9683 }
9684 if (pcc->insns_flags2 & PPC2_VSX) {
9685 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9686 32, "power-vsx.xml", 0);
9687 }
9688
9689 qemu_init_vcpu(cs);
9690
9691 pcc->parent_realize(dev, errp);
9692
9693 #if defined(PPC_DUMP_CPU)
9694 {
9695 CPUPPCState *env = &cpu->env;
9696 const char *mmu_model, *excp_model, *bus_model;
9697 switch (env->mmu_model) {
9698 case POWERPC_MMU_32B:
9699 mmu_model = "PowerPC 32";
9700 break;
9701 case POWERPC_MMU_SOFT_6xx:
9702 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9703 break;
9704 case POWERPC_MMU_SOFT_74xx:
9705 mmu_model = "PowerPC 74xx with software driven TLBs";
9706 break;
9707 case POWERPC_MMU_SOFT_4xx:
9708 mmu_model = "PowerPC 4xx with software driven TLBs";
9709 break;
9710 case POWERPC_MMU_SOFT_4xx_Z:
9711 mmu_model = "PowerPC 4xx with software driven TLBs "
9712 "and zones protections";
9713 break;
9714 case POWERPC_MMU_REAL:
9715 mmu_model = "PowerPC real mode only";
9716 break;
9717 case POWERPC_MMU_MPC8xx:
9718 mmu_model = "PowerPC MPC8xx";
9719 break;
9720 case POWERPC_MMU_BOOKE:
9721 mmu_model = "PowerPC BookE";
9722 break;
9723 case POWERPC_MMU_BOOKE206:
9724 mmu_model = "PowerPC BookE 2.06";
9725 break;
9726 case POWERPC_MMU_601:
9727 mmu_model = "PowerPC 601";
9728 break;
9729 #if defined(TARGET_PPC64)
9730 case POWERPC_MMU_64B:
9731 mmu_model = "PowerPC 64";
9732 break;
9733 #endif
9734 default:
9735 mmu_model = "Unknown or invalid";
9736 break;
9737 }
9738 switch (env->excp_model) {
9739 case POWERPC_EXCP_STD:
9740 excp_model = "PowerPC";
9741 break;
9742 case POWERPC_EXCP_40x:
9743 excp_model = "PowerPC 40x";
9744 break;
9745 case POWERPC_EXCP_601:
9746 excp_model = "PowerPC 601";
9747 break;
9748 case POWERPC_EXCP_602:
9749 excp_model = "PowerPC 602";
9750 break;
9751 case POWERPC_EXCP_603:
9752 excp_model = "PowerPC 603";
9753 break;
9754 case POWERPC_EXCP_603E:
9755 excp_model = "PowerPC 603e";
9756 break;
9757 case POWERPC_EXCP_604:
9758 excp_model = "PowerPC 604";
9759 break;
9760 case POWERPC_EXCP_7x0:
9761 excp_model = "PowerPC 740/750";
9762 break;
9763 case POWERPC_EXCP_7x5:
9764 excp_model = "PowerPC 745/755";
9765 break;
9766 case POWERPC_EXCP_74xx:
9767 excp_model = "PowerPC 74xx";
9768 break;
9769 case POWERPC_EXCP_BOOKE:
9770 excp_model = "PowerPC BookE";
9771 break;
9772 #if defined(TARGET_PPC64)
9773 case POWERPC_EXCP_970:
9774 excp_model = "PowerPC 970";
9775 break;
9776 #endif
9777 default:
9778 excp_model = "Unknown or invalid";
9779 break;
9780 }
9781 switch (env->bus_model) {
9782 case PPC_FLAGS_INPUT_6xx:
9783 bus_model = "PowerPC 6xx";
9784 break;
9785 case PPC_FLAGS_INPUT_BookE:
9786 bus_model = "PowerPC BookE";
9787 break;
9788 case PPC_FLAGS_INPUT_405:
9789 bus_model = "PowerPC 405";
9790 break;
9791 case PPC_FLAGS_INPUT_401:
9792 bus_model = "PowerPC 401/403";
9793 break;
9794 case PPC_FLAGS_INPUT_RCPU:
9795 bus_model = "RCPU / MPC8xx";
9796 break;
9797 #if defined(TARGET_PPC64)
9798 case PPC_FLAGS_INPUT_970:
9799 bus_model = "PowerPC 970";
9800 break;
9801 #endif
9802 default:
9803 bus_model = "Unknown or invalid";
9804 break;
9805 }
9806 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9807 " MMU model : %s\n",
9808 object_class_get_name(OBJECT_CLASS(pcc)),
9809 pcc->pvr, pcc->msr_mask, mmu_model);
9810 #if !defined(CONFIG_USER_ONLY)
9811 if (env->tlb.tlb6) {
9812 printf(" %d %s TLB in %d ways\n",
9813 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9814 env->nb_ways);
9815 }
9816 #endif
9817 printf(" Exceptions model : %s\n"
9818 " Bus model : %s\n",
9819 excp_model, bus_model);
9820 printf(" MSR features :\n");
9821 if (env->flags & POWERPC_FLAG_SPE)
9822 printf(" signal processing engine enable"
9823 "\n");
9824 else if (env->flags & POWERPC_FLAG_VRE)
9825 printf(" vector processor enable\n");
9826 if (env->flags & POWERPC_FLAG_TGPR)
9827 printf(" temporary GPRs\n");
9828 else if (env->flags & POWERPC_FLAG_CE)
9829 printf(" critical input enable\n");
9830 if (env->flags & POWERPC_FLAG_SE)
9831 printf(" single-step trace mode\n");
9832 else if (env->flags & POWERPC_FLAG_DWE)
9833 printf(" debug wait enable\n");
9834 else if (env->flags & POWERPC_FLAG_UBLE)
9835 printf(" user BTB lock enable\n");
9836 if (env->flags & POWERPC_FLAG_BE)
9837 printf(" branch-step trace mode\n");
9838 else if (env->flags & POWERPC_FLAG_DE)
9839 printf(" debug interrupt enable\n");
9840 if (env->flags & POWERPC_FLAG_PX)
9841 printf(" inclusive protection\n");
9842 else if (env->flags & POWERPC_FLAG_PMM)
9843 printf(" performance monitor mark\n");
9844 if (env->flags == POWERPC_FLAG_NONE)
9845 printf(" none\n");
9846 printf(" Time-base/decrementer clock source: %s\n",
9847 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9848 dump_ppc_insns(env);
9849 dump_ppc_sprs(env);
9850 fflush(stdout);
9851 }
9852 #endif
9853 return;
9854
9855 unrealize:
9856 cpu_exec_unrealizefn(cs);
9857 }
9858
9859 static void ppc_cpu_unrealize(DeviceState *dev, Error **errp)
9860 {
9861 PowerPCCPU *cpu = POWERPC_CPU(dev);
9862 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9863 CPUPPCState *env = &cpu->env;
9864 Error *local_err = NULL;
9865 opc_handler_t **table, **table_2;
9866 int i, j, k;
9867
9868 pcc->parent_unrealize(dev, &local_err);
9869 if (local_err != NULL) {
9870 error_propagate(errp, local_err);
9871 return;
9872 }
9873
9874 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9875 if (env->opcodes[i] == &invalid_handler) {
9876 continue;
9877 }
9878 if (is_indirect_opcode(env->opcodes[i])) {
9879 table = ind_table(env->opcodes[i]);
9880 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
9881 if (table[j] == &invalid_handler) {
9882 continue;
9883 }
9884 if (is_indirect_opcode(table[j])) {
9885 table_2 = ind_table(table[j]);
9886 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
9887 if (table_2[k] != &invalid_handler &&
9888 is_indirect_opcode(table_2[k])) {
9889 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
9890 ~PPC_INDIRECT));
9891 }
9892 }
9893 g_free((opc_handler_t *)((uintptr_t)table[j] &
9894 ~PPC_INDIRECT));
9895 }
9896 }
9897 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
9898 ~PPC_INDIRECT));
9899 }
9900 }
9901 }
9902
9903 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9904 {
9905 ObjectClass *oc = (ObjectClass *)a;
9906 uint32_t pvr = *(uint32_t *)b;
9907 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9908
9909 /* -cpu host does a PVR lookup during construction */
9910 if (unlikely(strcmp(object_class_get_name(oc),
9911 TYPE_HOST_POWERPC_CPU) == 0)) {
9912 return -1;
9913 }
9914
9915 if (!ppc_cpu_is_valid(pcc)) {
9916 return -1;
9917 }
9918
9919 return pcc->pvr == pvr ? 0 : -1;
9920 }
9921
9922 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9923 {
9924 GSList *list, *item;
9925 PowerPCCPUClass *pcc = NULL;
9926
9927 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9928 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9929 if (item != NULL) {
9930 pcc = POWERPC_CPU_CLASS(item->data);
9931 }
9932 g_slist_free(list);
9933
9934 return pcc;
9935 }
9936
9937 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
9938 {
9939 ObjectClass *oc = (ObjectClass *)a;
9940 uint32_t pvr = *(uint32_t *)b;
9941 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9942
9943 /* -cpu host does a PVR lookup during construction */
9944 if (unlikely(strcmp(object_class_get_name(oc),
9945 TYPE_HOST_POWERPC_CPU) == 0)) {
9946 return -1;
9947 }
9948
9949 if (!ppc_cpu_is_valid(pcc)) {
9950 return -1;
9951 }
9952
9953 if (pcc->pvr_match(pcc, pvr)) {
9954 return 0;
9955 }
9956
9957 return -1;
9958 }
9959
9960 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
9961 {
9962 GSList *list, *item;
9963 PowerPCCPUClass *pcc = NULL;
9964
9965 list = object_class_get_list(TYPE_POWERPC_CPU, true);
9966 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
9967 if (item != NULL) {
9968 pcc = POWERPC_CPU_CLASS(item->data);
9969 }
9970 g_slist_free(list);
9971
9972 return pcc;
9973 }
9974
9975 static const char *ppc_cpu_lookup_alias(const char *alias)
9976 {
9977 int ai;
9978
9979 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
9980 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
9981 return ppc_cpu_aliases[ai].model;
9982 }
9983 }
9984
9985 return NULL;
9986 }
9987
9988 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9989 {
9990 char *cpu_model, *typename;
9991 ObjectClass *oc;
9992 const char *p;
9993 unsigned long pvr;
9994
9995 /* Lookup by PVR if cpu_model is valid 8 digit hex number
9996 * (excl: 0x prefix if present)
9997 */
9998 if (!qemu_strtoul(name, &p, 16, &pvr)) {
9999 int len = p - name;
10000 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
10001 if ((len == 8) && (*p == '\0')) {
10002 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
10003 }
10004 }
10005
10006 cpu_model = g_ascii_strdown(name, -1);
10007 p = ppc_cpu_lookup_alias(cpu_model);
10008 if (p) {
10009 g_free(cpu_model);
10010 cpu_model = g_strdup(p);
10011 }
10012
10013 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
10014 oc = object_class_by_name(typename);
10015 g_free(typename);
10016 g_free(cpu_model);
10017
10018 if (oc && ppc_cpu_is_valid(POWERPC_CPU_CLASS(oc))) {
10019 return oc;
10020 }
10021
10022 return NULL;
10023 }
10024
10025 static void ppc_cpu_parse_featurestr(const char *type, char *features,
10026 Error **errp)
10027 {
10028 Object *machine = qdev_get_machine();
10029 const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type));
10030
10031 if (!features) {
10032 return;
10033 }
10034
10035 if (object_property_find(machine, "max-cpu-compat", NULL)) {
10036 int i;
10037 char **inpieces;
10038 char *s = features;
10039 Error *local_err = NULL;
10040 char *compat_str = NULL;
10041
10042 /*
10043 * Backwards compatibility hack:
10044 *
10045 * CPUs had a "compat=" property which didn't make sense for
10046 * anything except pseries. It was replaced by "max-cpu-compat"
10047 * machine option. This supports old command lines like
10048 * -cpu POWER8,compat=power7
10049 * By stripping the compat option and applying it to the machine
10050 * before passing it on to the cpu level parser.
10051 */
10052 inpieces = g_strsplit(features, ",", 0);
10053 *s = '\0';
10054 for (i = 0; inpieces[i]; i++) {
10055 if (g_str_has_prefix(inpieces[i], "compat=")) {
10056 compat_str = inpieces[i];
10057 continue;
10058 }
10059 if ((i != 0) && (s != features)) {
10060 s = g_stpcpy(s, ",");
10061 }
10062 s = g_stpcpy(s, inpieces[i]);
10063 }
10064
10065 if (compat_str) {
10066 char *v = compat_str + strlen("compat=");
10067 object_property_set_str(machine, v, "max-cpu-compat", &local_err);
10068 }
10069 g_strfreev(inpieces);
10070 if (local_err) {
10071 error_propagate(errp, local_err);
10072 return;
10073 }
10074 }
10075
10076 /* do property processing with generic handler */
10077 pcc->parent_parse_features(type, features, errp);
10078 }
10079
10080 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
10081 {
10082 ObjectClass *oc = OBJECT_CLASS(pcc);
10083
10084 while (oc && !object_class_is_abstract(oc)) {
10085 oc = object_class_get_parent(oc);
10086 }
10087 assert(oc);
10088
10089 return POWERPC_CPU_CLASS(oc);
10090 }
10091
10092 /* Sort by PVR, ordering special case "host" last. */
10093 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10094 {
10095 ObjectClass *oc_a = (ObjectClass *)a;
10096 ObjectClass *oc_b = (ObjectClass *)b;
10097 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10098 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10099 const char *name_a = object_class_get_name(oc_a);
10100 const char *name_b = object_class_get_name(oc_b);
10101
10102 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10103 return 1;
10104 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10105 return -1;
10106 } else {
10107 /* Avoid an integer overflow during subtraction */
10108 if (pcc_a->pvr < pcc_b->pvr) {
10109 return -1;
10110 } else if (pcc_a->pvr > pcc_b->pvr) {
10111 return 1;
10112 } else {
10113 return 0;
10114 }
10115 }
10116 }
10117
10118 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10119 {
10120 ObjectClass *oc = data;
10121 CPUListState *s = user_data;
10122 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10123 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
10124 const char *typename = object_class_get_name(oc);
10125 char *name;
10126 int i;
10127
10128 if (!ppc_cpu_is_valid(pcc)) {
10129 return;
10130 }
10131 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
10132 return;
10133 }
10134
10135 name = g_strndup(typename,
10136 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10137 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
10138 name, pcc->pvr);
10139 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10140 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10141 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
10142
10143 if (alias_oc != oc) {
10144 continue;
10145 }
10146 /*
10147 * If running with KVM, we might update the family alias later, so
10148 * avoid printing the wrong alias here and use "preferred" instead
10149 */
10150 if (strcmp(alias->alias, family->desc) == 0) {
10151 (*s->cpu_fprintf)(s->file,
10152 "PowerPC %-16s (alias for preferred %s CPU)\n",
10153 alias->alias, family->desc);
10154 } else {
10155 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
10156 alias->alias, name);
10157 }
10158 }
10159 g_free(name);
10160 }
10161
10162 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10163 {
10164 CPUListState s = {
10165 .file = f,
10166 .cpu_fprintf = cpu_fprintf,
10167 };
10168 GSList *list;
10169
10170 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10171 list = g_slist_sort(list, ppc_cpu_list_compare);
10172 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10173 g_slist_free(list);
10174
10175 #ifdef CONFIG_KVM
10176 cpu_fprintf(f, "\n");
10177 cpu_fprintf(f, "PowerPC %-16s\n", "host");
10178 #endif
10179 }
10180
10181 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10182 {
10183 ObjectClass *oc = data;
10184 CpuDefinitionInfoList **first = user_data;
10185 const char *typename;
10186 CpuDefinitionInfoList *entry;
10187 CpuDefinitionInfo *info;
10188 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10189
10190 if (!ppc_cpu_is_valid(pcc)) {
10191 return;
10192 }
10193
10194 typename = object_class_get_name(oc);
10195 info = g_malloc0(sizeof(*info));
10196 info->name = g_strndup(typename,
10197 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10198
10199 entry = g_malloc0(sizeof(*entry));
10200 entry->value = info;
10201 entry->next = *first;
10202 *first = entry;
10203 }
10204
10205 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
10206 {
10207 CpuDefinitionInfoList *cpu_list = NULL;
10208 GSList *list;
10209 int i;
10210
10211 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10212 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10213 g_slist_free(list);
10214
10215 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10216 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10217 ObjectClass *oc;
10218 CpuDefinitionInfoList *entry;
10219 CpuDefinitionInfo *info;
10220
10221 oc = ppc_cpu_class_by_name(alias->model);
10222 if (oc == NULL) {
10223 continue;
10224 }
10225
10226 info = g_malloc0(sizeof(*info));
10227 info->name = g_strdup(alias->alias);
10228 info->q_typename = g_strdup(object_class_get_name(oc));
10229
10230 entry = g_malloc0(sizeof(*entry));
10231 entry->value = info;
10232 entry->next = cpu_list;
10233 cpu_list = entry;
10234 }
10235
10236 return cpu_list;
10237 }
10238
10239 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
10240 {
10241 PowerPCCPU *cpu = POWERPC_CPU(cs);
10242
10243 cpu->env.nip = value;
10244 }
10245
10246 static bool ppc_cpu_has_work(CPUState *cs)
10247 {
10248 PowerPCCPU *cpu = POWERPC_CPU(cs);
10249 CPUPPCState *env = &cpu->env;
10250
10251 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
10252 }
10253
10254 /* CPUClass::reset() */
10255 static void ppc_cpu_reset(CPUState *s)
10256 {
10257 PowerPCCPU *cpu = POWERPC_CPU(s);
10258 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10259 CPUPPCState *env = &cpu->env;
10260 target_ulong msr;
10261 int i;
10262
10263 pcc->parent_reset(s);
10264
10265 msr = (target_ulong)0;
10266 msr |= (target_ulong)MSR_HVB;
10267 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10268 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10269 msr |= (target_ulong)1 << MSR_EP;
10270 #if defined(DO_SINGLE_STEP) && 0
10271 /* Single step trace mode */
10272 msr |= (target_ulong)1 << MSR_SE;
10273 msr |= (target_ulong)1 << MSR_BE;
10274 #endif
10275 #if defined(CONFIG_USER_ONLY)
10276 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10277 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10278 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
10279 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10280 msr |= (target_ulong)1 << MSR_PR;
10281 #if defined(TARGET_PPC64)
10282 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
10283 #endif
10284 #if !defined(TARGET_WORDS_BIGENDIAN)
10285 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
10286 if (!((env->msr_mask >> MSR_LE) & 1)) {
10287 fprintf(stderr, "Selected CPU does not support little-endian.\n");
10288 exit(1);
10289 }
10290 #endif
10291 #endif
10292
10293 #if defined(TARGET_PPC64)
10294 if (env->mmu_model & POWERPC_MMU_64) {
10295 msr |= (1ULL << MSR_SF);
10296 }
10297 #endif
10298
10299 hreg_store_msr(env, msr, 1);
10300
10301 #if !defined(CONFIG_USER_ONLY)
10302 env->nip = env->hreset_vector | env->excp_prefix;
10303 if (env->mmu_model != POWERPC_MMU_REAL) {
10304 ppc_tlb_invalidate_all(env);
10305 }
10306 #endif
10307
10308 hreg_compute_hflags(env);
10309 env->reserve_addr = (target_ulong)-1ULL;
10310 /* Be sure no exception or interrupt is pending */
10311 env->pending_interrupts = 0;
10312 s->exception_index = POWERPC_EXCP_NONE;
10313 env->error_code = 0;
10314
10315 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
10316 env->vpa_addr = 0;
10317 env->slb_shadow_addr = 0;
10318 env->slb_shadow_size = 0;
10319 env->dtl_addr = 0;
10320 env->dtl_size = 0;
10321 #endif /* TARGET_PPC64 */
10322
10323 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
10324 ppc_spr_t *spr = &env->spr_cb[i];
10325
10326 if (!spr->name) {
10327 continue;
10328 }
10329 env->spr[i] = spr->default_value;
10330 }
10331 }
10332
10333 #ifndef CONFIG_USER_ONLY
10334 static bool ppc_cpu_is_big_endian(CPUState *cs)
10335 {
10336 PowerPCCPU *cpu = POWERPC_CPU(cs);
10337 CPUPPCState *env = &cpu->env;
10338
10339 cpu_synchronize_state(cs);
10340
10341 return !msr_le;
10342 }
10343 #endif
10344
10345 static void ppc_cpu_instance_init(Object *obj)
10346 {
10347 CPUState *cs = CPU(obj);
10348 PowerPCCPU *cpu = POWERPC_CPU(obj);
10349 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10350 CPUPPCState *env = &cpu->env;
10351
10352 cs->env_ptr = env;
10353 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
10354
10355 env->msr_mask = pcc->msr_mask;
10356 env->mmu_model = pcc->mmu_model;
10357 env->excp_model = pcc->excp_model;
10358 env->bus_model = pcc->bus_model;
10359 env->insns_flags = pcc->insns_flags;
10360 env->insns_flags2 = pcc->insns_flags2;
10361 env->flags = pcc->flags;
10362 env->bfd_mach = pcc->bfd_mach;
10363 env->check_pow = pcc->check_pow;
10364
10365 /* Mark HV mode as supported if the CPU has an MSR_HV bit
10366 * in the msr_mask. The mask can later be cleared by PAPR
10367 * mode but the hv mode support will remain, thus enforcing
10368 * that we cannot use priv. instructions in guest in PAPR
10369 * mode. For 970 we currently simply don't set HV in msr_mask
10370 * thus simulating an "Apple mode" 970. If we ever want to
10371 * support 970 HV mode, we'll have to add a processor attribute
10372 * of some sort.
10373 */
10374 #if !defined(CONFIG_USER_ONLY)
10375 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10376 #endif
10377
10378 ppc_hash64_init(cpu);
10379 }
10380
10381 static void ppc_cpu_instance_finalize(Object *obj)
10382 {
10383 PowerPCCPU *cpu = POWERPC_CPU(obj);
10384
10385 ppc_hash64_finalize(cpu);
10386 }
10387
10388 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10389 {
10390 return pcc->pvr == pvr;
10391 }
10392
10393 static gchar *ppc_gdb_arch_name(CPUState *cs)
10394 {
10395 #if defined(TARGET_PPC64)
10396 return g_strdup("powerpc:common64");
10397 #else
10398 return g_strdup("powerpc:common");
10399 #endif
10400 }
10401
10402 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
10403 {
10404 PowerPCCPU *cpu = POWERPC_CPU(cs);
10405 CPUPPCState *env = &cpu->env;
10406
10407 if ((env->hflags >> MSR_LE) & 1) {
10408 info->endian = BFD_ENDIAN_LITTLE;
10409 }
10410 info->mach = env->bfd_mach;
10411 if (!env->bfd_mach) {
10412 #ifdef TARGET_PPC64
10413 info->mach = bfd_mach_ppc64;
10414 #else
10415 info->mach = bfd_mach_ppc;
10416 #endif
10417 }
10418 info->disassembler_options = (char *)"any";
10419 info->print_insn = print_insn_ppc;
10420
10421 info->cap_arch = CS_ARCH_PPC;
10422 #ifdef TARGET_PPC64
10423 info->cap_mode = CS_MODE_64;
10424 #endif
10425 }
10426
10427 static Property ppc_cpu_properties[] = {
10428 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
10429 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
10430 false),
10431 DEFINE_PROP_BOOL("pre-2.13-migration", PowerPCCPU, pre_2_13_migration,
10432 false),
10433 DEFINE_PROP_END_OF_LIST(),
10434 };
10435
10436 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10437 {
10438 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10439 CPUClass *cc = CPU_CLASS(oc);
10440 DeviceClass *dc = DEVICE_CLASS(oc);
10441
10442 device_class_set_parent_realize(dc, ppc_cpu_realize,
10443 &pcc->parent_realize);
10444 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
10445 &pcc->parent_unrealize);
10446 pcc->pvr_match = ppc_pvr_match_default;
10447 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10448 dc->props = ppc_cpu_properties;
10449
10450 pcc->parent_reset = cc->reset;
10451 cc->reset = ppc_cpu_reset;
10452
10453 cc->class_by_name = ppc_cpu_class_by_name;
10454 pcc->parent_parse_features = cc->parse_features;
10455 cc->parse_features = ppc_cpu_parse_featurestr;
10456 cc->has_work = ppc_cpu_has_work;
10457 cc->do_interrupt = ppc_cpu_do_interrupt;
10458 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10459 cc->dump_state = ppc_cpu_dump_state;
10460 cc->dump_statistics = ppc_cpu_dump_statistics;
10461 cc->set_pc = ppc_cpu_set_pc;
10462 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10463 cc->gdb_write_register = ppc_cpu_gdb_write_register;
10464 #ifdef CONFIG_USER_ONLY
10465 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10466 #else
10467 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10468 cc->vmsd = &vmstate_ppc_cpu;
10469 #endif
10470 #if defined(CONFIG_SOFTMMU)
10471 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10472 cc->write_elf32_note = ppc32_cpu_write_elf32_note;
10473 #endif
10474
10475 cc->gdb_num_core_regs = 71;
10476
10477 #ifdef USE_APPLE_GDB
10478 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10479 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10480 cc->gdb_num_core_regs = 71 + 32;
10481 #endif
10482
10483 cc->gdb_arch_name = ppc_gdb_arch_name;
10484 #if defined(TARGET_PPC64)
10485 cc->gdb_core_xml_file = "power64-core.xml";
10486 #else
10487 cc->gdb_core_xml_file = "power-core.xml";
10488 #endif
10489 #ifndef CONFIG_USER_ONLY
10490 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10491 #endif
10492 #ifdef CONFIG_TCG
10493 cc->tcg_initialize = ppc_translate_init;
10494 #endif
10495 cc->disas_set_info = ppc_disas_set_info;
10496
10497 dc->fw_name = "PowerPC,UNKNOWN";
10498 }
10499
10500 static const TypeInfo ppc_cpu_type_info = {
10501 .name = TYPE_POWERPC_CPU,
10502 .parent = TYPE_CPU,
10503 .instance_size = sizeof(PowerPCCPU),
10504 .instance_init = ppc_cpu_instance_init,
10505 .instance_finalize = ppc_cpu_instance_finalize,
10506 .abstract = true,
10507 .class_size = sizeof(PowerPCCPUClass),
10508 .class_init = ppc_cpu_class_init,
10509 };
10510
10511 static const TypeInfo ppc_vhyp_type_info = {
10512 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
10513 .parent = TYPE_INTERFACE,
10514 .class_size = sizeof(PPCVirtualHypervisorClass),
10515 };
10516
10517 static void ppc_cpu_register_types(void)
10518 {
10519 type_register_static(&ppc_cpu_type_info);
10520 type_register_static(&ppc_vhyp_type_info);
10521 }
10522
10523 type_init(ppc_cpu_register_types)
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