target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "exec/exec-all.h"
  26 #include "qapi/error.h"
  27 #include "qemu/error-report.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30 #include "fpu/softfloat-helpers.h"
  31
  32 /* RISC-V CPU definitions */
  33
  34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  35
  36 const char * const riscv_int_regnames[] = {
  37   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  38   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  39   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  40   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  41   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  42 };
  43
  44 const char * const riscv_fpr_regnames[] = {
  45   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  46   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  47   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  48   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  49   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  50   "f30/ft10", "f31/ft11"
  51 };
  52
  53 const char * const riscv_excp_names[] = {
  54     "misaligned_fetch",
  55     "fault_fetch",
  56     "illegal_instruction",
  57     "breakpoint",
  58     "misaligned_load",
  59     "fault_load",
  60     "misaligned_store",
  61     "fault_store",
  62     "user_ecall",
  63     "supervisor_ecall",
  64     "hypervisor_ecall",
  65     "machine_ecall",
  66     "exec_page_fault",
  67     "load_page_fault",
  68     "reserved",
  69     "store_page_fault",
  70     "reserved",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "guest_exec_page_fault",
  75     "guest_load_page_fault",
  76     "reserved",
  77     "guest_store_page_fault",
  78 };
  79
  80 const char * const riscv_intr_names[] = {
  81     "u_software",
  82     "s_software",
  83     "vs_software",
  84     "m_software",
  85     "u_timer",
  86     "s_timer",
  87     "vs_timer",
  88     "m_timer",
  89     "u_external",
  90     "vs_external",
  91     "h_external",
  92     "m_external",
  93     "reserved",
  94     "reserved",
  95     "reserved",
  96     "reserved"
  97 };
  98
  99 static void set_misa(CPURISCVState *env, target_ulong misa)
 100 {
 101     env->misa_mask = env->misa = misa;
 102 }
 103
 104 static void set_priv_version(CPURISCVState *env, int priv_ver)
 105 {
 106     env->priv_ver = priv_ver;
 107 }
 108
 109 static void set_feature(CPURISCVState *env, int feature)
 110 {
 111     env->features |= (1ULL << feature);
 112 }
 113
 114 static void set_resetvec(CPURISCVState *env, int resetvec)
 115 {
 116 #ifndef CONFIG_USER_ONLY
 117     env->resetvec = resetvec;
 118 #endif
 119 }
 120
 121 static void riscv_any_cpu_init(Object *obj)
 122 {
 123     CPURISCVState *env = &RISCV_CPU(obj)->env;
 124     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 125     set_priv_version(env, PRIV_VERSION_1_11_0);
 126     set_resetvec(env, DEFAULT_RSTVEC);
 127 }
 128
 129 #if defined(TARGET_RISCV32)
 130
 131 static void riscv_base32_cpu_init(Object *obj)
 132 {
 133     CPURISCVState *env = &RISCV_CPU(obj)->env;
 134     /* We set this in the realise function */
 135     set_misa(env, 0);
 136 }
 137
 138 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
 139 {
 140     CPURISCVState *env = &RISCV_CPU(obj)->env;
 141     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 142     set_priv_version(env, PRIV_VERSION_1_10_0);
 143     set_resetvec(env, DEFAULT_RSTVEC);
 144     set_feature(env, RISCV_FEATURE_MMU);
 145     set_feature(env, RISCV_FEATURE_PMP);
 146 }
 147
 148 static void rv32imacu_nommu_cpu_init(Object *obj)
 149 {
 150     CPURISCVState *env = &RISCV_CPU(obj)->env;
 151     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 152     set_priv_version(env, PRIV_VERSION_1_10_0);
 153     set_resetvec(env, DEFAULT_RSTVEC);
 154     set_feature(env, RISCV_FEATURE_PMP);
 155 }
 156
 157 static void rv32imafcu_nommu_cpu_init(Object *obj)
 158 {
 159     CPURISCVState *env = &RISCV_CPU(obj)->env;
 160     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 161     set_priv_version(env, PRIV_VERSION_1_10_0);
 162     set_resetvec(env, DEFAULT_RSTVEC);
 163     set_feature(env, RISCV_FEATURE_PMP);
 164 }
 165
 166 #elif defined(TARGET_RISCV64)
 167
 168 static void riscv_base64_cpu_init(Object *obj)
 169 {
 170     CPURISCVState *env = &RISCV_CPU(obj)->env;
 171     /* We set this in the realise function */
 172     set_misa(env, 0);
 173 }
 174
 175 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
 176 {
 177     CPURISCVState *env = &RISCV_CPU(obj)->env;
 178     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 179     set_priv_version(env, PRIV_VERSION_1_10_0);
 180     set_resetvec(env, DEFAULT_RSTVEC);
 181     set_feature(env, RISCV_FEATURE_MMU);
 182     set_feature(env, RISCV_FEATURE_PMP);
 183 }
 184
 185 static void rv64imacu_nommu_cpu_init(Object *obj)
 186 {
 187     CPURISCVState *env = &RISCV_CPU(obj)->env;
 188     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 189     set_priv_version(env, PRIV_VERSION_1_10_0);
 190     set_resetvec(env, DEFAULT_RSTVEC);
 191     set_feature(env, RISCV_FEATURE_PMP);
 192 }
 193
 194 #endif
 195
 196 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 197 {
 198     ObjectClass *oc;
 199     char *typename;
 200     char **cpuname;
 201
 202     cpuname = g_strsplit(cpu_model, ",", 1);
 203     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 204     oc = object_class_by_name(typename);
 205     g_strfreev(cpuname);
 206     g_free(typename);
 207     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 208         object_class_is_abstract(oc)) {
 209         return NULL;
 210     }
 211     return oc;
 212 }
 213
 214 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 215 {
 216     RISCVCPU *cpu = RISCV_CPU(cs);
 217     CPURISCVState *env = &cpu->env;
 218     int i;
 219
 220 #if !defined(CONFIG_USER_ONLY)
 221     if (riscv_has_ext(env, RVH)) {
 222         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 223     }
 224 #endif
 225     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 226 #ifndef CONFIG_USER_ONLY
 227     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 228     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
 229 #ifdef TARGET_RISCV32
 230     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
 231 #endif
 232     if (riscv_has_ext(env, RVH)) {
 233         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 234         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
 235     }
 236     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 237     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 238     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 239     if (riscv_has_ext(env, RVH)) {
 240         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 241     }
 242     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 243     if (riscv_has_ext(env, RVH)) {
 244         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 245     }
 246     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 247     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 248     if (riscv_has_ext(env, RVH)) {
 249         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 250     }
 251     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 252     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 253     if (riscv_has_ext(env, RVH)) {
 254         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 255     }
 256     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 257     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 258     if (riscv_has_ext(env, RVH)) {
 259         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 260     }
 261     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 262     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 263     if (riscv_has_ext(env, RVH)) {
 264         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 265         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 266     }
 267 #endif
 268
 269     for (i = 0; i < 32; i++) {
 270         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 271                      riscv_int_regnames[i], env->gpr[i]);
 272         if ((i & 3) == 3) {
 273             qemu_fprintf(f, "\n");
 274         }
 275     }
 276     if (flags & CPU_DUMP_FPU) {
 277         for (i = 0; i < 32; i++) {
 278             qemu_fprintf(f, " %s %016" PRIx64,
 279                          riscv_fpr_regnames[i], env->fpr[i]);
 280             if ((i & 3) == 3) {
 281                 qemu_fprintf(f, "\n");
 282             }
 283         }
 284     }
 285 }
 286
 287 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 288 {
 289     RISCVCPU *cpu = RISCV_CPU(cs);
 290     CPURISCVState *env = &cpu->env;
 291     env->pc = value;
 292 }
 293
 294 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
 295 {
 296     RISCVCPU *cpu = RISCV_CPU(cs);
 297     CPURISCVState *env = &cpu->env;
 298     env->pc = tb->pc;
 299 }
 300
 301 static bool riscv_cpu_has_work(CPUState *cs)
 302 {
 303 #ifndef CONFIG_USER_ONLY
 304     RISCVCPU *cpu = RISCV_CPU(cs);
 305     CPURISCVState *env = &cpu->env;
 306     /*
 307      * Definition of the WFI instruction requires it to ignore the privilege
 308      * mode and delegation registers, but respect individual enables
 309      */
 310     return (env->mip & env->mie) != 0;
 311 #else
 312     return true;
 313 #endif
 314 }
 315
 316 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 317                           target_ulong *data)
 318 {
 319     env->pc = data[0];
 320 }
 321
 322 static void riscv_cpu_reset(DeviceState *dev)
 323 {
 324     CPUState *cs = CPU(dev);
 325     RISCVCPU *cpu = RISCV_CPU(cs);
 326     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 327     CPURISCVState *env = &cpu->env;
 328
 329     mcc->parent_reset(dev);
 330 #ifndef CONFIG_USER_ONLY
 331     env->priv = PRV_M;
 332     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 333     env->mcause = 0;
 334     env->pc = env->resetvec;
 335 #endif
 336     cs->exception_index = EXCP_NONE;
 337     env->load_res = -1;
 338     set_default_nan_mode(1, &env->fp_status);
 339 }
 340
 341 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 342 {
 343 #if defined(TARGET_RISCV32)
 344     info->print_insn = print_insn_riscv32;
 345 #elif defined(TARGET_RISCV64)
 346     info->print_insn = print_insn_riscv64;
 347 #endif
 348 }
 349
 350 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 351 {
 352     CPUState *cs = CPU(dev);
 353     RISCVCPU *cpu = RISCV_CPU(dev);
 354     CPURISCVState *env = &cpu->env;
 355     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 356     int priv_version = PRIV_VERSION_1_11_0;
 357     target_ulong target_misa = 0;
 358     Error *local_err = NULL;
 359
 360     cpu_exec_realizefn(cs, &local_err);
 361     if (local_err != NULL) {
 362         error_propagate(errp, local_err);
 363         return;
 364     }
 365
 366     if (cpu->cfg.priv_spec) {
 367         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 368             priv_version = PRIV_VERSION_1_11_0;
 369         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 370             priv_version = PRIV_VERSION_1_10_0;
 371         } else {
 372             error_setg(errp,
 373                        "Unsupported privilege spec version '%s'",
 374                        cpu->cfg.priv_spec);
 375             return;
 376         }
 377     }
 378
 379     set_priv_version(env, priv_version);
 380     set_resetvec(env, DEFAULT_RSTVEC);
 381
 382     if (cpu->cfg.mmu) {
 383         set_feature(env, RISCV_FEATURE_MMU);
 384     }
 385
 386     if (cpu->cfg.pmp) {
 387         set_feature(env, RISCV_FEATURE_PMP);
 388     }
 389
 390     /* If misa isn't set (rv32 and rv64 machines) set it here */
 391     if (!env->misa) {
 392         /* Do some ISA extension error checking */
 393         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 394             error_setg(errp,
 395                        "I and E extensions are incompatible");
 396                        return;
 397        }
 398
 399         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 400             error_setg(errp,
 401                        "Either I or E extension must be set");
 402                        return;
 403        }
 404
 405        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 406                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 407                                cpu->cfg.ext_d)) {
 408             warn_report("Setting G will also set IMAFD");
 409             cpu->cfg.ext_i = true;
 410             cpu->cfg.ext_m = true;
 411             cpu->cfg.ext_a = true;
 412             cpu->cfg.ext_f = true;
 413             cpu->cfg.ext_d = true;
 414         }
 415
 416         /* Set the ISA extensions, checks should have happened above */
 417         if (cpu->cfg.ext_i) {
 418             target_misa |= RVI;
 419         }
 420         if (cpu->cfg.ext_e) {
 421             target_misa |= RVE;
 422         }
 423         if (cpu->cfg.ext_m) {
 424             target_misa |= RVM;
 425         }
 426         if (cpu->cfg.ext_a) {
 427             target_misa |= RVA;
 428         }
 429         if (cpu->cfg.ext_f) {
 430             target_misa |= RVF;
 431         }
 432         if (cpu->cfg.ext_d) {
 433             target_misa |= RVD;
 434         }
 435         if (cpu->cfg.ext_c) {
 436             target_misa |= RVC;
 437         }
 438         if (cpu->cfg.ext_s) {
 439             target_misa |= RVS;
 440         }
 441         if (cpu->cfg.ext_u) {
 442             target_misa |= RVU;
 443         }
 444         if (cpu->cfg.ext_h) {
 445             target_misa |= RVH;
 446         }
 447
 448         set_misa(env, RVXLEN | target_misa);
 449     }
 450
 451     riscv_cpu_register_gdb_regs_for_features(cs);
 452
 453     qemu_init_vcpu(cs);
 454     cpu_reset(cs);
 455
 456     mcc->parent_realize(dev, errp);
 457 }
 458
 459 static void riscv_cpu_init(Object *obj)
 460 {
 461     RISCVCPU *cpu = RISCV_CPU(obj);
 462
 463     cpu_set_cpustate_pointers(cpu);
 464 }
 465
 466 static const VMStateDescription vmstate_riscv_cpu = {
 467     .name = "cpu",
 468     .unmigratable = 1,
 469 };
 470
 471 static Property riscv_cpu_properties[] = {
 472     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 473     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 474     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 475     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 476     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 477     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 478     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 479     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 480     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 481     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 482     /* This is experimental so mark with 'x-' */
 483     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 484     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 485     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 486     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 487     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 488     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 489     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 490     DEFINE_PROP_END_OF_LIST(),
 491 };
 492
 493 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 494 {
 495     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 496     CPUClass *cc = CPU_CLASS(c);
 497     DeviceClass *dc = DEVICE_CLASS(c);
 498
 499     device_class_set_parent_realize(dc, riscv_cpu_realize,
 500                                     &mcc->parent_realize);
 501
 502     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 503
 504     cc->class_by_name = riscv_cpu_class_by_name;
 505     cc->has_work = riscv_cpu_has_work;
 506     cc->do_interrupt = riscv_cpu_do_interrupt;
 507     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
 508     cc->dump_state = riscv_cpu_dump_state;
 509     cc->set_pc = riscv_cpu_set_pc;
 510     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
 511     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 512     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 513     cc->gdb_num_core_regs = 33;
 514 #if defined(TARGET_RISCV32)
 515     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 516 #elif defined(TARGET_RISCV64)
 517     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 518 #endif
 519     cc->gdb_stop_before_watchpoint = true;
 520     cc->disas_set_info = riscv_cpu_disas_set_info;
 521 #ifndef CONFIG_USER_ONLY
 522     cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
 523     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
 524     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 525 #endif
 526 #ifdef CONFIG_TCG
 527     cc->tcg_initialize = riscv_translate_init;
 528     cc->tlb_fill = riscv_cpu_tlb_fill;
 529 #endif
 530     /* For now, mark unmigratable: */
 531     cc->vmsd = &vmstate_riscv_cpu;
 532     device_class_set_props(dc, riscv_cpu_properties);
 533 }
 534
 535 char *riscv_isa_string(RISCVCPU *cpu)
 536 {
 537     int i;
 538     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 539     char *isa_str = g_new(char, maxlen);
 540     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 541     for (i = 0; i < sizeof(riscv_exts); i++) {
 542         if (cpu->env.misa & RV(riscv_exts[i])) {
 543             *p++ = qemu_tolower(riscv_exts[i]);
 544         }
 545     }
 546     *p = '\0';
 547     return isa_str;
 548 }
 549
 550 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 551 {
 552     ObjectClass *class_a = (ObjectClass *)a;
 553     ObjectClass *class_b = (ObjectClass *)b;
 554     const char *name_a, *name_b;
 555
 556     name_a = object_class_get_name(class_a);
 557     name_b = object_class_get_name(class_b);
 558     return strcmp(name_a, name_b);
 559 }
 560
 561 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 562 {
 563     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 564     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 565
 566     qemu_printf("%.*s\n", len, typename);
 567 }
 568
 569 void riscv_cpu_list(void)
 570 {
 571     GSList *list;
 572
 573     list = object_class_get_list(TYPE_RISCV_CPU, false);
 574     list = g_slist_sort(list, riscv_cpu_list_compare);
 575     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 576     g_slist_free(list);
 577 }
 578
 579 #define DEFINE_CPU(type_name, initfn)      \
 580     {                                      \
 581         .name = type_name,                 \
 582         .parent = TYPE_RISCV_CPU,          \
 583         .instance_init = initfn            \
 584     }
 585
 586 static const TypeInfo riscv_cpu_type_infos[] = {
 587     {
 588         .name = TYPE_RISCV_CPU,
 589         .parent = TYPE_CPU,
 590         .instance_size = sizeof(RISCVCPU),
 591         .instance_init = riscv_cpu_init,
 592         .abstract = true,
 593         .class_size = sizeof(RISCVCPUClass),
 594         .class_init = riscv_cpu_class_init,
 595     },
 596     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 597 #if defined(TARGET_RISCV32)
 598     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
 599     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
 600     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32imafcu_nommu_cpu_init),
 601     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
 602 #elif defined(TARGET_RISCV64)
 603     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
 604     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
 605     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
 606 #endif
 607 };
 608
 609 DEFINE_TYPES(riscv_cpu_type_infos)