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target/riscv: cpu: Add a config option for native debug
[mirror_qemu.git] / target / riscv / cpu.c
1 /*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
23 #include "qemu/log.h"
24 #include "cpu.h"
25 #include "internals.h"
26 #include "exec/exec-all.h"
27 #include "qapi/error.h"
28 #include "qemu/error-report.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "fpu/softfloat-helpers.h"
32 #include "sysemu/kvm.h"
33 #include "kvm_riscv.h"
34
35 /* RISC-V CPU definitions */
36
37 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
38
39 struct isa_ext_data {
40 const char *name;
41 bool enabled;
42 };
43
44 const char * const riscv_int_regnames[] = {
45 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
46 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
47 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
48 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
49 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
50 };
51
52 const char * const riscv_int_regnamesh[] = {
53 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
54 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
55 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
56 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
57 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
58 "x30h/t5h", "x31h/t6h"
59 };
60
61 const char * const riscv_fpr_regnames[] = {
62 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
63 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
64 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
65 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
66 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
67 "f30/ft10", "f31/ft11"
68 };
69
70 static const char * const riscv_excp_names[] = {
71 "misaligned_fetch",
72 "fault_fetch",
73 "illegal_instruction",
74 "breakpoint",
75 "misaligned_load",
76 "fault_load",
77 "misaligned_store",
78 "fault_store",
79 "user_ecall",
80 "supervisor_ecall",
81 "hypervisor_ecall",
82 "machine_ecall",
83 "exec_page_fault",
84 "load_page_fault",
85 "reserved",
86 "store_page_fault",
87 "reserved",
88 "reserved",
89 "reserved",
90 "reserved",
91 "guest_exec_page_fault",
92 "guest_load_page_fault",
93 "reserved",
94 "guest_store_page_fault",
95 };
96
97 static const char * const riscv_intr_names[] = {
98 "u_software",
99 "s_software",
100 "vs_software",
101 "m_software",
102 "u_timer",
103 "s_timer",
104 "vs_timer",
105 "m_timer",
106 "u_external",
107 "s_external",
108 "vs_external",
109 "m_external",
110 "reserved",
111 "reserved",
112 "reserved",
113 "reserved"
114 };
115
116 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
117 {
118 if (async) {
119 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
120 riscv_intr_names[cause] : "(unknown)";
121 } else {
122 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
123 riscv_excp_names[cause] : "(unknown)";
124 }
125 }
126
127 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
128 {
129 env->misa_mxl_max = env->misa_mxl = mxl;
130 env->misa_ext_mask = env->misa_ext = ext;
131 }
132
133 static void set_priv_version(CPURISCVState *env, int priv_ver)
134 {
135 env->priv_ver = priv_ver;
136 }
137
138 static void set_vext_version(CPURISCVState *env, int vext_ver)
139 {
140 env->vext_ver = vext_ver;
141 }
142
143 static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
144 {
145 #ifndef CONFIG_USER_ONLY
146 env->resetvec = resetvec;
147 #endif
148 }
149
150 static void riscv_any_cpu_init(Object *obj)
151 {
152 CPURISCVState *env = &RISCV_CPU(obj)->env;
153 #if defined(TARGET_RISCV32)
154 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
155 #elif defined(TARGET_RISCV64)
156 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
157 #endif
158 set_priv_version(env, PRIV_VERSION_1_12_0);
159 }
160
161 #if defined(TARGET_RISCV64)
162 static void rv64_base_cpu_init(Object *obj)
163 {
164 CPURISCVState *env = &RISCV_CPU(obj)->env;
165 /* We set this in the realise function */
166 set_misa(env, MXL_RV64, 0);
167 }
168
169 static void rv64_sifive_u_cpu_init(Object *obj)
170 {
171 CPURISCVState *env = &RISCV_CPU(obj)->env;
172 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
173 set_priv_version(env, PRIV_VERSION_1_10_0);
174 }
175
176 static void rv64_sifive_e_cpu_init(Object *obj)
177 {
178 CPURISCVState *env = &RISCV_CPU(obj)->env;
179 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
180 set_priv_version(env, PRIV_VERSION_1_10_0);
181 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
182 }
183
184 static void rv128_base_cpu_init(Object *obj)
185 {
186 if (qemu_tcg_mttcg_enabled()) {
187 /* Missing 128-bit aligned atomics */
188 error_report("128-bit RISC-V currently does not work with Multi "
189 "Threaded TCG. Please use: -accel tcg,thread=single");
190 exit(EXIT_FAILURE);
191 }
192 CPURISCVState *env = &RISCV_CPU(obj)->env;
193 /* We set this in the realise function */
194 set_misa(env, MXL_RV128, 0);
195 }
196 #else
197 static void rv32_base_cpu_init(Object *obj)
198 {
199 CPURISCVState *env = &RISCV_CPU(obj)->env;
200 /* We set this in the realise function */
201 set_misa(env, MXL_RV32, 0);
202 }
203
204 static void rv32_sifive_u_cpu_init(Object *obj)
205 {
206 CPURISCVState *env = &RISCV_CPU(obj)->env;
207 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
208 set_priv_version(env, PRIV_VERSION_1_10_0);
209 }
210
211 static void rv32_sifive_e_cpu_init(Object *obj)
212 {
213 CPURISCVState *env = &RISCV_CPU(obj)->env;
214 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
215 set_priv_version(env, PRIV_VERSION_1_10_0);
216 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
217 }
218
219 static void rv32_ibex_cpu_init(Object *obj)
220 {
221 CPURISCVState *env = &RISCV_CPU(obj)->env;
222 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
223 set_priv_version(env, PRIV_VERSION_1_10_0);
224 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
225 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
226 }
227
228 static void rv32_imafcu_nommu_cpu_init(Object *obj)
229 {
230 CPURISCVState *env = &RISCV_CPU(obj)->env;
231 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
232 set_priv_version(env, PRIV_VERSION_1_10_0);
233 set_resetvec(env, DEFAULT_RSTVEC);
234 qdev_prop_set_bit(DEVICE(obj), "mmu", false);
235 }
236 #endif
237
238 #if defined(CONFIG_KVM)
239 static void riscv_host_cpu_init(Object *obj)
240 {
241 CPURISCVState *env = &RISCV_CPU(obj)->env;
242 #if defined(TARGET_RISCV32)
243 set_misa(env, MXL_RV32, 0);
244 #elif defined(TARGET_RISCV64)
245 set_misa(env, MXL_RV64, 0);
246 #endif
247 }
248 #endif
249
250 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
251 {
252 ObjectClass *oc;
253 char *typename;
254 char **cpuname;
255
256 cpuname = g_strsplit(cpu_model, ",", 1);
257 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
258 oc = object_class_by_name(typename);
259 g_strfreev(cpuname);
260 g_free(typename);
261 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
262 object_class_is_abstract(oc)) {
263 return NULL;
264 }
265 return oc;
266 }
267
268 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
269 {
270 RISCVCPU *cpu = RISCV_CPU(cs);
271 CPURISCVState *env = &cpu->env;
272 int i;
273
274 #if !defined(CONFIG_USER_ONLY)
275 if (riscv_has_ext(env, RVH)) {
276 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
277 }
278 #endif
279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
280 #ifndef CONFIG_USER_ONLY
281 {
282 static const int dump_csrs[] = {
283 CSR_MHARTID,
284 CSR_MSTATUS,
285 CSR_MSTATUSH,
286 CSR_HSTATUS,
287 CSR_VSSTATUS,
288 CSR_MIP,
289 CSR_MIE,
290 CSR_MIDELEG,
291 CSR_HIDELEG,
292 CSR_MEDELEG,
293 CSR_HEDELEG,
294 CSR_MTVEC,
295 CSR_STVEC,
296 CSR_VSTVEC,
297 CSR_MEPC,
298 CSR_SEPC,
299 CSR_VSEPC,
300 CSR_MCAUSE,
301 CSR_SCAUSE,
302 CSR_VSCAUSE,
303 CSR_MTVAL,
304 CSR_STVAL,
305 CSR_HTVAL,
306 CSR_MTVAL2,
307 CSR_MSCRATCH,
308 CSR_SSCRATCH,
309 CSR_SATP,
310 CSR_MMTE,
311 CSR_UPMBASE,
312 CSR_UPMMASK,
313 CSR_SPMBASE,
314 CSR_SPMMASK,
315 CSR_MPMBASE,
316 CSR_MPMMASK,
317 };
318
319 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
320 int csrno = dump_csrs[i];
321 target_ulong val = 0;
322 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
323
324 /*
325 * Rely on the smode, hmode, etc, predicates within csr.c
326 * to do the filtering of the registers that are present.
327 */
328 if (res == RISCV_EXCP_NONE) {
329 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
330 csr_ops[csrno].name, val);
331 }
332 }
333 }
334 #endif
335
336 for (i = 0; i < 32; i++) {
337 qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
338 riscv_int_regnames[i], env->gpr[i]);
339 if ((i & 3) == 3) {
340 qemu_fprintf(f, "\n");
341 }
342 }
343 if (flags & CPU_DUMP_FPU) {
344 for (i = 0; i < 32; i++) {
345 qemu_fprintf(f, " %-8s %016" PRIx64,
346 riscv_fpr_regnames[i], env->fpr[i]);
347 if ((i & 3) == 3) {
348 qemu_fprintf(f, "\n");
349 }
350 }
351 }
352 }
353
354 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
355 {
356 RISCVCPU *cpu = RISCV_CPU(cs);
357 CPURISCVState *env = &cpu->env;
358
359 if (env->xl == MXL_RV32) {
360 env->pc = (int32_t)value;
361 } else {
362 env->pc = value;
363 }
364 }
365
366 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
367 const TranslationBlock *tb)
368 {
369 RISCVCPU *cpu = RISCV_CPU(cs);
370 CPURISCVState *env = &cpu->env;
371 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
372
373 if (xl == MXL_RV32) {
374 env->pc = (int32_t)tb->pc;
375 } else {
376 env->pc = tb->pc;
377 }
378 }
379
380 static bool riscv_cpu_has_work(CPUState *cs)
381 {
382 #ifndef CONFIG_USER_ONLY
383 RISCVCPU *cpu = RISCV_CPU(cs);
384 CPURISCVState *env = &cpu->env;
385 /*
386 * Definition of the WFI instruction requires it to ignore the privilege
387 * mode and delegation registers, but respect individual enables
388 */
389 return (env->mip & env->mie) != 0;
390 #else
391 return true;
392 #endif
393 }
394
395 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
396 target_ulong *data)
397 {
398 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
399 if (xl == MXL_RV32) {
400 env->pc = (int32_t)data[0];
401 } else {
402 env->pc = data[0];
403 }
404 }
405
406 static void riscv_cpu_reset(DeviceState *dev)
407 {
408 #ifndef CONFIG_USER_ONLY
409 uint8_t iprio;
410 int i, irq, rdzero;
411 #endif
412 CPUState *cs = CPU(dev);
413 RISCVCPU *cpu = RISCV_CPU(cs);
414 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
415 CPURISCVState *env = &cpu->env;
416
417 mcc->parent_reset(dev);
418 #ifndef CONFIG_USER_ONLY
419 env->misa_mxl = env->misa_mxl_max;
420 env->priv = PRV_M;
421 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
422 if (env->misa_mxl > MXL_RV32) {
423 /*
424 * The reset status of SXL/UXL is undefined, but mstatus is WARL
425 * and we must ensure that the value after init is valid for read.
426 */
427 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
428 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
429 if (riscv_has_ext(env, RVH)) {
430 env->vsstatus = set_field(env->vsstatus,
431 MSTATUS64_SXL, env->misa_mxl);
432 env->vsstatus = set_field(env->vsstatus,
433 MSTATUS64_UXL, env->misa_mxl);
434 env->mstatus_hs = set_field(env->mstatus_hs,
435 MSTATUS64_SXL, env->misa_mxl);
436 env->mstatus_hs = set_field(env->mstatus_hs,
437 MSTATUS64_UXL, env->misa_mxl);
438 }
439 }
440 env->mcause = 0;
441 env->miclaim = MIP_SGEIP;
442 env->pc = env->resetvec;
443 env->two_stage_lookup = false;
444
445 /* Initialized default priorities of local interrupts. */
446 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
447 iprio = riscv_cpu_default_priority(i);
448 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
449 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
450 env->hviprio[i] = 0;
451 }
452 i = 0;
453 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
454 if (!rdzero) {
455 env->hviprio[irq] = env->miprio[irq];
456 }
457 i++;
458 }
459 /* mmte is supposed to have pm.current hardwired to 1 */
460 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
461 #endif
462 env->xl = riscv_cpu_mxl(env);
463 riscv_cpu_update_mask(env);
464 cs->exception_index = RISCV_EXCP_NONE;
465 env->load_res = -1;
466 set_default_nan_mode(1, &env->fp_status);
467
468 #ifndef CONFIG_USER_ONLY
469 if (kvm_enabled()) {
470 kvm_riscv_reset_vcpu(cpu);
471 }
472 #endif
473 }
474
475 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
476 {
477 RISCVCPU *cpu = RISCV_CPU(s);
478
479 switch (riscv_cpu_mxl(&cpu->env)) {
480 case MXL_RV32:
481 info->print_insn = print_insn_riscv32;
482 break;
483 case MXL_RV64:
484 info->print_insn = print_insn_riscv64;
485 break;
486 case MXL_RV128:
487 info->print_insn = print_insn_riscv128;
488 break;
489 default:
490 g_assert_not_reached();
491 }
492 }
493
494 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
495 {
496 CPUState *cs = CPU(dev);
497 RISCVCPU *cpu = RISCV_CPU(dev);
498 CPURISCVState *env = &cpu->env;
499 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
500 CPUClass *cc = CPU_CLASS(mcc);
501 int priv_version = 0;
502 Error *local_err = NULL;
503
504 cpu_exec_realizefn(cs, &local_err);
505 if (local_err != NULL) {
506 error_propagate(errp, local_err);
507 return;
508 }
509
510 if (cpu->cfg.priv_spec) {
511 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
512 priv_version = PRIV_VERSION_1_12_0;
513 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
514 priv_version = PRIV_VERSION_1_11_0;
515 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
516 priv_version = PRIV_VERSION_1_10_0;
517 } else {
518 error_setg(errp,
519 "Unsupported privilege spec version '%s'",
520 cpu->cfg.priv_spec);
521 return;
522 }
523 }
524
525 if (priv_version) {
526 set_priv_version(env, priv_version);
527 } else if (!env->priv_ver) {
528 set_priv_version(env, PRIV_VERSION_1_12_0);
529 }
530
531 if (cpu->cfg.mmu) {
532 riscv_set_feature(env, RISCV_FEATURE_MMU);
533 }
534
535 if (cpu->cfg.pmp) {
536 riscv_set_feature(env, RISCV_FEATURE_PMP);
537
538 /*
539 * Enhanced PMP should only be available
540 * on harts with PMP support
541 */
542 if (cpu->cfg.epmp) {
543 riscv_set_feature(env, RISCV_FEATURE_EPMP);
544 }
545 }
546
547 if (cpu->cfg.aia) {
548 riscv_set_feature(env, RISCV_FEATURE_AIA);
549 }
550
551 if (cpu->cfg.debug) {
552 riscv_set_feature(env, RISCV_FEATURE_DEBUG);
553 }
554
555 set_resetvec(env, cpu->cfg.resetvec);
556
557 /* Validate that MISA_MXL is set properly. */
558 switch (env->misa_mxl_max) {
559 #ifdef TARGET_RISCV64
560 case MXL_RV64:
561 case MXL_RV128:
562 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
563 break;
564 #endif
565 case MXL_RV32:
566 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
567 break;
568 default:
569 g_assert_not_reached();
570 }
571 assert(env->misa_mxl_max == env->misa_mxl);
572
573 /* If only MISA_EXT is unset for misa, then set it from properties */
574 if (env->misa_ext == 0) {
575 uint32_t ext = 0;
576
577 /* Do some ISA extension error checking */
578 if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
579 error_setg(errp,
580 "I and E extensions are incompatible");
581 return;
582 }
583
584 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
585 error_setg(errp,
586 "Either I or E extension must be set");
587 return;
588 }
589
590 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
591 cpu->cfg.ext_a & cpu->cfg.ext_f &
592 cpu->cfg.ext_d)) {
593 warn_report("Setting G will also set IMAFD");
594 cpu->cfg.ext_i = true;
595 cpu->cfg.ext_m = true;
596 cpu->cfg.ext_a = true;
597 cpu->cfg.ext_f = true;
598 cpu->cfg.ext_d = true;
599 }
600
601 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
602 cpu->cfg.ext_zhinxmin) {
603 cpu->cfg.ext_zfinx = true;
604 }
605
606 /* Set the ISA extensions, checks should have happened above */
607 if (cpu->cfg.ext_i) {
608 ext |= RVI;
609 }
610 if (cpu->cfg.ext_e) {
611 ext |= RVE;
612 }
613 if (cpu->cfg.ext_m) {
614 ext |= RVM;
615 }
616 if (cpu->cfg.ext_a) {
617 ext |= RVA;
618 }
619 if (cpu->cfg.ext_f) {
620 ext |= RVF;
621 }
622 if (cpu->cfg.ext_d) {
623 ext |= RVD;
624 }
625 if (cpu->cfg.ext_c) {
626 ext |= RVC;
627 }
628 if (cpu->cfg.ext_s) {
629 ext |= RVS;
630 }
631 if (cpu->cfg.ext_u) {
632 ext |= RVU;
633 }
634 if (cpu->cfg.ext_h) {
635 ext |= RVH;
636 }
637 if (cpu->cfg.ext_v) {
638 int vext_version = VEXT_VERSION_1_00_0;
639 ext |= RVV;
640 if (!is_power_of_2(cpu->cfg.vlen)) {
641 error_setg(errp,
642 "Vector extension VLEN must be power of 2");
643 return;
644 }
645 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
646 error_setg(errp,
647 "Vector extension implementation only supports VLEN "
648 "in the range [128, %d]", RV_VLEN_MAX);
649 return;
650 }
651 if (!is_power_of_2(cpu->cfg.elen)) {
652 error_setg(errp,
653 "Vector extension ELEN must be power of 2");
654 return;
655 }
656 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
657 error_setg(errp,
658 "Vector extension implementation only supports ELEN "
659 "in the range [8, 64]");
660 return;
661 }
662 if (cpu->cfg.vext_spec) {
663 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
664 vext_version = VEXT_VERSION_1_00_0;
665 } else {
666 error_setg(errp,
667 "Unsupported vector spec version '%s'",
668 cpu->cfg.vext_spec);
669 return;
670 }
671 } else {
672 qemu_log("vector version is not specified, "
673 "use the default value v1.0\n");
674 }
675 set_vext_version(env, vext_version);
676 }
677 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
678 error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
679 return;
680 }
681 if (cpu->cfg.ext_j) {
682 ext |= RVJ;
683 }
684 if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh ||
685 cpu->cfg.ext_zfhmin)) {
686 error_setg(errp,
687 "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh',"
688 " 'Zfhmin'");
689 return;
690 }
691
692 set_misa(env, env->misa_mxl, ext);
693 }
694
695 riscv_cpu_register_gdb_regs_for_features(cs);
696
697 qemu_init_vcpu(cs);
698 cpu_reset(cs);
699
700 mcc->parent_realize(dev, errp);
701 }
702
703 #ifndef CONFIG_USER_ONLY
704 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
705 {
706 RISCVCPU *cpu = RISCV_CPU(opaque);
707 CPURISCVState *env = &cpu->env;
708
709 if (irq < IRQ_LOCAL_MAX) {
710 switch (irq) {
711 case IRQ_U_SOFT:
712 case IRQ_S_SOFT:
713 case IRQ_VS_SOFT:
714 case IRQ_M_SOFT:
715 case IRQ_U_TIMER:
716 case IRQ_S_TIMER:
717 case IRQ_VS_TIMER:
718 case IRQ_M_TIMER:
719 case IRQ_U_EXT:
720 case IRQ_VS_EXT:
721 case IRQ_M_EXT:
722 if (kvm_enabled()) {
723 kvm_riscv_set_irq(cpu, irq, level);
724 } else {
725 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
726 }
727 break;
728 case IRQ_S_EXT:
729 if (kvm_enabled()) {
730 kvm_riscv_set_irq(cpu, irq, level);
731 } else {
732 env->external_seip = level;
733 riscv_cpu_update_mip(cpu, 1 << irq,
734 BOOL_TO_MASK(level | env->software_seip));
735 }
736 break;
737 default:
738 g_assert_not_reached();
739 }
740 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
741 /* Require H-extension for handling guest local interrupts */
742 if (!riscv_has_ext(env, RVH)) {
743 g_assert_not_reached();
744 }
745
746 /* Compute bit position in HGEIP CSR */
747 irq = irq - IRQ_LOCAL_MAX + 1;
748 if (env->geilen < irq) {
749 g_assert_not_reached();
750 }
751
752 /* Update HGEIP CSR */
753 env->hgeip &= ~((target_ulong)1 << irq);
754 if (level) {
755 env->hgeip |= (target_ulong)1 << irq;
756 }
757
758 /* Update mip.SGEIP bit */
759 riscv_cpu_update_mip(cpu, MIP_SGEIP,
760 BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
761 } else {
762 g_assert_not_reached();
763 }
764 }
765 #endif /* CONFIG_USER_ONLY */
766
767 static void riscv_cpu_init(Object *obj)
768 {
769 RISCVCPU *cpu = RISCV_CPU(obj);
770
771 cpu_set_cpustate_pointers(cpu);
772
773 #ifndef CONFIG_USER_ONLY
774 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
775 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
776 #endif /* CONFIG_USER_ONLY */
777 }
778
779 static Property riscv_cpu_properties[] = {
780 /* Defaults for standard extensions */
781 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
782 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
783 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
784 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
785 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
786 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
787 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
788 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
789 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
790 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
791 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
792 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
793 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
794 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
795 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
796 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
797 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
798 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
799 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
800 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
801 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
802 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
803
804 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
805 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
806 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
807 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
808
809 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
810 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
811 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
812
813 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
814 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
815 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
816 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
817
818 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
819 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
820 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
821 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
822
823 /* Vendor-specific custom extensions */
824 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
825
826 /* These are experimental so mark with 'x-' */
827 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
828 /* ePMP 0.9.3 */
829 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
830 DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
831
832 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
833 DEFINE_PROP_END_OF_LIST(),
834 };
835
836 static gchar *riscv_gdb_arch_name(CPUState *cs)
837 {
838 RISCVCPU *cpu = RISCV_CPU(cs);
839 CPURISCVState *env = &cpu->env;
840
841 switch (riscv_cpu_mxl(env)) {
842 case MXL_RV32:
843 return g_strdup("riscv:rv32");
844 case MXL_RV64:
845 case MXL_RV128:
846 return g_strdup("riscv:rv64");
847 default:
848 g_assert_not_reached();
849 }
850 }
851
852 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
853 {
854 RISCVCPU *cpu = RISCV_CPU(cs);
855
856 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
857 return cpu->dyn_csr_xml;
858 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
859 return cpu->dyn_vreg_xml;
860 }
861
862 return NULL;
863 }
864
865 #ifndef CONFIG_USER_ONLY
866 #include "hw/core/sysemu-cpu-ops.h"
867
868 static const struct SysemuCPUOps riscv_sysemu_ops = {
869 .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
870 .write_elf64_note = riscv_cpu_write_elf64_note,
871 .write_elf32_note = riscv_cpu_write_elf32_note,
872 .legacy_vmsd = &vmstate_riscv_cpu,
873 };
874 #endif
875
876 #include "hw/core/tcg-cpu-ops.h"
877
878 static const struct TCGCPUOps riscv_tcg_ops = {
879 .initialize = riscv_translate_init,
880 .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
881
882 #ifndef CONFIG_USER_ONLY
883 .tlb_fill = riscv_cpu_tlb_fill,
884 .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
885 .do_interrupt = riscv_cpu_do_interrupt,
886 .do_transaction_failed = riscv_cpu_do_transaction_failed,
887 .do_unaligned_access = riscv_cpu_do_unaligned_access,
888 .debug_excp_handler = riscv_cpu_debug_excp_handler,
889 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
890 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
891 #endif /* !CONFIG_USER_ONLY */
892 };
893
894 static void riscv_cpu_class_init(ObjectClass *c, void *data)
895 {
896 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
897 CPUClass *cc = CPU_CLASS(c);
898 DeviceClass *dc = DEVICE_CLASS(c);
899
900 device_class_set_parent_realize(dc, riscv_cpu_realize,
901 &mcc->parent_realize);
902
903 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
904
905 cc->class_by_name = riscv_cpu_class_by_name;
906 cc->has_work = riscv_cpu_has_work;
907 cc->dump_state = riscv_cpu_dump_state;
908 cc->set_pc = riscv_cpu_set_pc;
909 cc->gdb_read_register = riscv_cpu_gdb_read_register;
910 cc->gdb_write_register = riscv_cpu_gdb_write_register;
911 cc->gdb_num_core_regs = 33;
912 cc->gdb_stop_before_watchpoint = true;
913 cc->disas_set_info = riscv_cpu_disas_set_info;
914 #ifndef CONFIG_USER_ONLY
915 cc->sysemu_ops = &riscv_sysemu_ops;
916 #endif
917 cc->gdb_arch_name = riscv_gdb_arch_name;
918 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
919 cc->tcg_ops = &riscv_tcg_ops;
920
921 device_class_set_props(dc, riscv_cpu_properties);
922 }
923
924 #define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
925
926 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
927 {
928 char *old = *isa_str;
929 char *new = *isa_str;
930 int i;
931
932 /**
933 * Here are the ordering rules of extension naming defined by RISC-V
934 * specification :
935 * 1. All extensions should be separated from other multi-letter extensions
936 * by an underscore.
937 * 2. The first letter following the 'Z' conventionally indicates the most
938 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
939 * If multiple 'Z' extensions are named, they should be ordered first
940 * by category, then alphabetically within a category.
941 * 3. Standard supervisor-level extensions (starts with 'S') should be
942 * listed after standard unprivileged extensions. If multiple
943 * supervisor-level extensions are listed, they should be ordered
944 * alphabetically.
945 * 4. Non-standard extensions (starts with 'X') must be listed after all
946 * standard extensions. They must be separated from other multi-letter
947 * extensions by an underscore.
948 */
949 struct isa_ext_data isa_edata_arr[] = {
950 ISA_EDATA_ENTRY(zfh, ext_zfh),
951 ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
952 ISA_EDATA_ENTRY(zfinx, ext_zfinx),
953 ISA_EDATA_ENTRY(zhinx, ext_zhinx),
954 ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
955 ISA_EDATA_ENTRY(zdinx, ext_zdinx),
956 ISA_EDATA_ENTRY(zba, ext_zba),
957 ISA_EDATA_ENTRY(zbb, ext_zbb),
958 ISA_EDATA_ENTRY(zbc, ext_zbc),
959 ISA_EDATA_ENTRY(zbs, ext_zbs),
960 ISA_EDATA_ENTRY(zve32f, ext_zve32f),
961 ISA_EDATA_ENTRY(zve64f, ext_zve64f),
962 ISA_EDATA_ENTRY(svinval, ext_svinval),
963 ISA_EDATA_ENTRY(svnapot, ext_svnapot),
964 ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
965 };
966
967 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
968 if (isa_edata_arr[i].enabled) {
969 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
970 g_free(old);
971 old = new;
972 }
973 }
974
975 *isa_str = new;
976 }
977
978 char *riscv_isa_string(RISCVCPU *cpu)
979 {
980 int i;
981 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
982 char *isa_str = g_new(char, maxlen);
983 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
984 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
985 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
986 *p++ = qemu_tolower(riscv_single_letter_exts[i]);
987 }
988 }
989 *p = '\0';
990 riscv_isa_string_ext(cpu, &isa_str, maxlen);
991 return isa_str;
992 }
993
994 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
995 {
996 ObjectClass *class_a = (ObjectClass *)a;
997 ObjectClass *class_b = (ObjectClass *)b;
998 const char *name_a, *name_b;
999
1000 name_a = object_class_get_name(class_a);
1001 name_b = object_class_get_name(class_b);
1002 return strcmp(name_a, name_b);
1003 }
1004
1005 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
1006 {
1007 const char *typename = object_class_get_name(OBJECT_CLASS(data));
1008 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
1009
1010 qemu_printf("%.*s\n", len, typename);
1011 }
1012
1013 void riscv_cpu_list(void)
1014 {
1015 GSList *list;
1016
1017 list = object_class_get_list(TYPE_RISCV_CPU, false);
1018 list = g_slist_sort(list, riscv_cpu_list_compare);
1019 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
1020 g_slist_free(list);
1021 }
1022
1023 #define DEFINE_CPU(type_name, initfn) \
1024 { \
1025 .name = type_name, \
1026 .parent = TYPE_RISCV_CPU, \
1027 .instance_init = initfn \
1028 }
1029
1030 static const TypeInfo riscv_cpu_type_infos[] = {
1031 {
1032 .name = TYPE_RISCV_CPU,
1033 .parent = TYPE_CPU,
1034 .instance_size = sizeof(RISCVCPU),
1035 .instance_align = __alignof__(RISCVCPU),
1036 .instance_init = riscv_cpu_init,
1037 .abstract = true,
1038 .class_size = sizeof(RISCVCPUClass),
1039 .class_init = riscv_cpu_class_init,
1040 },
1041 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
1042 #if defined(CONFIG_KVM)
1043 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
1044 #endif
1045 #if defined(TARGET_RISCV32)
1046 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
1047 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
1048 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
1049 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
1050 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
1051 #elif defined(TARGET_RISCV64)
1052 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
1053 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
1054 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
1055 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
1056 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
1057 #endif
1058 };
1059
1060 DEFINE_TYPES(riscv_cpu_type_infos)
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