target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "exec/exec-all.h"
  26 #include "qapi/error.h"
  27 #include "qemu/error-report.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30 #include "fpu/softfloat-helpers.h"
  31
  32 /* RISC-V CPU definitions */
  33
  34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  35
  36 const char * const riscv_int_regnames[] = {
  37   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  38   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  39   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  40   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  41   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  42 };
  43
  44 const char * const riscv_fpr_regnames[] = {
  45   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  46   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  47   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  48   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  49   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  50   "f30/ft10", "f31/ft11"
  51 };
  52
  53 const char * const riscv_excp_names[] = {
  54     "misaligned_fetch",
  55     "fault_fetch",
  56     "illegal_instruction",
  57     "breakpoint",
  58     "misaligned_load",
  59     "fault_load",
  60     "misaligned_store",
  61     "fault_store",
  62     "user_ecall",
  63     "supervisor_ecall",
  64     "hypervisor_ecall",
  65     "machine_ecall",
  66     "exec_page_fault",
  67     "load_page_fault",
  68     "reserved",
  69     "store_page_fault",
  70     "reserved",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "guest_exec_page_fault",
  75     "guest_load_page_fault",
  76     "reserved",
  77     "guest_store_page_fault",
  78 };
  79
  80 const char * const riscv_intr_names[] = {
  81     "u_software",
  82     "s_software",
  83     "vs_software",
  84     "m_software",
  85     "u_timer",
  86     "s_timer",
  87     "vs_timer",
  88     "m_timer",
  89     "u_external",
  90     "vs_external",
  91     "h_external",
  92     "m_external",
  93     "reserved",
  94     "reserved",
  95     "reserved",
  96     "reserved"
  97 };
  98
  99 static void set_misa(CPURISCVState *env, target_ulong misa)
 100 {
 101     env->misa_mask = env->misa = misa;
 102 }
 103
 104 static void set_priv_version(CPURISCVState *env, int priv_ver)
 105 {
 106     env->priv_ver = priv_ver;
 107 }
 108
 109 static void set_feature(CPURISCVState *env, int feature)
 110 {
 111     env->features |= (1ULL << feature);
 112 }
 113
 114 static void set_resetvec(CPURISCVState *env, int resetvec)
 115 {
 116 #ifndef CONFIG_USER_ONLY
 117     env->resetvec = resetvec;
 118 #endif
 119 }
 120
 121 static void riscv_any_cpu_init(Object *obj)
 122 {
 123     CPURISCVState *env = &RISCV_CPU(obj)->env;
 124     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 125     set_priv_version(env, PRIV_VERSION_1_11_0);
 126     set_resetvec(env, DEFAULT_RSTVEC);
 127 }
 128
 129 #if defined(TARGET_RISCV32)
 130
 131 static void riscv_base32_cpu_init(Object *obj)
 132 {
 133     CPURISCVState *env = &RISCV_CPU(obj)->env;
 134     /* We set this in the realise function */
 135     set_misa(env, 0);
 136 }
 137
 138 static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
 139 {
 140     CPURISCVState *env = &RISCV_CPU(obj)->env;
 141     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 142     set_priv_version(env, PRIV_VERSION_1_09_1);
 143     set_resetvec(env, DEFAULT_RSTVEC);
 144     set_feature(env, RISCV_FEATURE_MMU);
 145     set_feature(env, RISCV_FEATURE_PMP);
 146 }
 147
 148 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
 149 {
 150     CPURISCVState *env = &RISCV_CPU(obj)->env;
 151     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 152     set_priv_version(env, PRIV_VERSION_1_10_0);
 153     set_resetvec(env, DEFAULT_RSTVEC);
 154     set_feature(env, RISCV_FEATURE_MMU);
 155     set_feature(env, RISCV_FEATURE_PMP);
 156 }
 157
 158 static void rv32imacu_nommu_cpu_init(Object *obj)
 159 {
 160     CPURISCVState *env = &RISCV_CPU(obj)->env;
 161     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 162     set_priv_version(env, PRIV_VERSION_1_10_0);
 163     set_resetvec(env, DEFAULT_RSTVEC);
 164     set_feature(env, RISCV_FEATURE_PMP);
 165 }
 166
 167 #elif defined(TARGET_RISCV64)
 168
 169 static void riscv_base64_cpu_init(Object *obj)
 170 {
 171     CPURISCVState *env = &RISCV_CPU(obj)->env;
 172     /* We set this in the realise function */
 173     set_misa(env, 0);
 174 }
 175
 176 static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
 177 {
 178     CPURISCVState *env = &RISCV_CPU(obj)->env;
 179     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 180     set_priv_version(env, PRIV_VERSION_1_09_1);
 181     set_resetvec(env, DEFAULT_RSTVEC);
 182     set_feature(env, RISCV_FEATURE_MMU);
 183     set_feature(env, RISCV_FEATURE_PMP);
 184 }
 185
 186 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
 187 {
 188     CPURISCVState *env = &RISCV_CPU(obj)->env;
 189     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 190     set_priv_version(env, PRIV_VERSION_1_10_0);
 191     set_resetvec(env, DEFAULT_RSTVEC);
 192     set_feature(env, RISCV_FEATURE_MMU);
 193     set_feature(env, RISCV_FEATURE_PMP);
 194 }
 195
 196 static void rv64imacu_nommu_cpu_init(Object *obj)
 197 {
 198     CPURISCVState *env = &RISCV_CPU(obj)->env;
 199     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 200     set_priv_version(env, PRIV_VERSION_1_10_0);
 201     set_resetvec(env, DEFAULT_RSTVEC);
 202     set_feature(env, RISCV_FEATURE_PMP);
 203 }
 204
 205 #endif
 206
 207 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 208 {
 209     ObjectClass *oc;
 210     char *typename;
 211     char **cpuname;
 212
 213     cpuname = g_strsplit(cpu_model, ",", 1);
 214     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 215     oc = object_class_by_name(typename);
 216     g_strfreev(cpuname);
 217     g_free(typename);
 218     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 219         object_class_is_abstract(oc)) {
 220         return NULL;
 221     }
 222     return oc;
 223 }
 224
 225 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 226 {
 227     RISCVCPU *cpu = RISCV_CPU(cs);
 228     CPURISCVState *env = &cpu->env;
 229     int i;
 230
 231 #if !defined(CONFIG_USER_ONLY)
 232     if (riscv_has_ext(env, RVH)) {
 233         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 234     }
 235 #endif
 236     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 237 #ifndef CONFIG_USER_ONLY
 238     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 239     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
 240 #ifdef TARGET_RISCV32
 241     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
 242 #endif
 243     if (riscv_has_ext(env, RVH)) {
 244         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 245         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
 246     }
 247     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 248     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 249     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 250     if (riscv_has_ext(env, RVH)) {
 251         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 252     }
 253     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 254     if (riscv_has_ext(env, RVH)) {
 255         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 256     }
 257     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 258     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 259     if (riscv_has_ext(env, RVH)) {
 260         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 261     }
 262     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 263     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 264     if (riscv_has_ext(env, RVH)) {
 265         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 266     }
 267     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 268     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 269     if (riscv_has_ext(env, RVH)) {
 270         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 271     }
 272     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 273     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 274     if (riscv_has_ext(env, RVH)) {
 275         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 276         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 277     }
 278 #endif
 279
 280     for (i = 0; i < 32; i++) {
 281         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 282                      riscv_int_regnames[i], env->gpr[i]);
 283         if ((i & 3) == 3) {
 284             qemu_fprintf(f, "\n");
 285         }
 286     }
 287     if (flags & CPU_DUMP_FPU) {
 288         for (i = 0; i < 32; i++) {
 289             qemu_fprintf(f, " %s %016" PRIx64,
 290                          riscv_fpr_regnames[i], env->fpr[i]);
 291             if ((i & 3) == 3) {
 292                 qemu_fprintf(f, "\n");
 293             }
 294         }
 295     }
 296 }
 297
 298 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 299 {
 300     RISCVCPU *cpu = RISCV_CPU(cs);
 301     CPURISCVState *env = &cpu->env;
 302     env->pc = value;
 303 }
 304
 305 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
 306 {
 307     RISCVCPU *cpu = RISCV_CPU(cs);
 308     CPURISCVState *env = &cpu->env;
 309     env->pc = tb->pc;
 310 }
 311
 312 static bool riscv_cpu_has_work(CPUState *cs)
 313 {
 314 #ifndef CONFIG_USER_ONLY
 315     RISCVCPU *cpu = RISCV_CPU(cs);
 316     CPURISCVState *env = &cpu->env;
 317     /*
 318      * Definition of the WFI instruction requires it to ignore the privilege
 319      * mode and delegation registers, but respect individual enables
 320      */
 321     return (env->mip & env->mie) != 0;
 322 #else
 323     return true;
 324 #endif
 325 }
 326
 327 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 328                           target_ulong *data)
 329 {
 330     env->pc = data[0];
 331 }
 332
 333 static void riscv_cpu_reset(DeviceState *dev)
 334 {
 335     CPUState *cs = CPU(dev);
 336     RISCVCPU *cpu = RISCV_CPU(cs);
 337     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 338     CPURISCVState *env = &cpu->env;
 339
 340     mcc->parent_reset(dev);
 341 #ifndef CONFIG_USER_ONLY
 342     env->priv = PRV_M;
 343     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 344     env->mcause = 0;
 345     env->pc = env->resetvec;
 346 #endif
 347     cs->exception_index = EXCP_NONE;
 348     env->load_res = -1;
 349     set_default_nan_mode(1, &env->fp_status);
 350 }
 351
 352 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 353 {
 354 #if defined(TARGET_RISCV32)
 355     info->print_insn = print_insn_riscv32;
 356 #elif defined(TARGET_RISCV64)
 357     info->print_insn = print_insn_riscv64;
 358 #endif
 359 }
 360
 361 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 362 {
 363     CPUState *cs = CPU(dev);
 364     RISCVCPU *cpu = RISCV_CPU(dev);
 365     CPURISCVState *env = &cpu->env;
 366     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 367     int priv_version = PRIV_VERSION_1_11_0;
 368     target_ulong target_misa = 0;
 369     Error *local_err = NULL;
 370
 371     cpu_exec_realizefn(cs, &local_err);
 372     if (local_err != NULL) {
 373         error_propagate(errp, local_err);
 374         return;
 375     }
 376
 377     if (cpu->cfg.priv_spec) {
 378         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 379             priv_version = PRIV_VERSION_1_11_0;
 380         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 381             priv_version = PRIV_VERSION_1_10_0;
 382         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
 383             priv_version = PRIV_VERSION_1_09_1;
 384         } else {
 385             error_setg(errp,
 386                        "Unsupported privilege spec version '%s'",
 387                        cpu->cfg.priv_spec);
 388             return;
 389         }
 390     }
 391
 392     set_priv_version(env, priv_version);
 393     set_resetvec(env, DEFAULT_RSTVEC);
 394
 395     if (cpu->cfg.mmu) {
 396         set_feature(env, RISCV_FEATURE_MMU);
 397     }
 398
 399     if (cpu->cfg.pmp) {
 400         set_feature(env, RISCV_FEATURE_PMP);
 401     }
 402
 403     /* If misa isn't set (rv32 and rv64 machines) set it here */
 404     if (!env->misa) {
 405         /* Do some ISA extension error checking */
 406         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 407             error_setg(errp,
 408                        "I and E extensions are incompatible");
 409                        return;
 410        }
 411
 412         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 413             error_setg(errp,
 414                        "Either I or E extension must be set");
 415                        return;
 416        }
 417
 418        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 419                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 420                                cpu->cfg.ext_d)) {
 421             warn_report("Setting G will also set IMAFD");
 422             cpu->cfg.ext_i = true;
 423             cpu->cfg.ext_m = true;
 424             cpu->cfg.ext_a = true;
 425             cpu->cfg.ext_f = true;
 426             cpu->cfg.ext_d = true;
 427         }
 428
 429         /* Set the ISA extensions, checks should have happened above */
 430         if (cpu->cfg.ext_i) {
 431             target_misa |= RVI;
 432         }
 433         if (cpu->cfg.ext_e) {
 434             target_misa |= RVE;
 435         }
 436         if (cpu->cfg.ext_m) {
 437             target_misa |= RVM;
 438         }
 439         if (cpu->cfg.ext_a) {
 440             target_misa |= RVA;
 441         }
 442         if (cpu->cfg.ext_f) {
 443             target_misa |= RVF;
 444         }
 445         if (cpu->cfg.ext_d) {
 446             target_misa |= RVD;
 447         }
 448         if (cpu->cfg.ext_c) {
 449             target_misa |= RVC;
 450         }
 451         if (cpu->cfg.ext_s) {
 452             target_misa |= RVS;
 453         }
 454         if (cpu->cfg.ext_u) {
 455             target_misa |= RVU;
 456         }
 457         if (cpu->cfg.ext_h) {
 458             target_misa |= RVH;
 459         }
 460
 461         set_misa(env, RVXLEN | target_misa);
 462     }
 463
 464     riscv_cpu_register_gdb_regs_for_features(cs);
 465
 466     qemu_init_vcpu(cs);
 467     cpu_reset(cs);
 468
 469     mcc->parent_realize(dev, errp);
 470 }
 471
 472 static void riscv_cpu_init(Object *obj)
 473 {
 474     RISCVCPU *cpu = RISCV_CPU(obj);
 475
 476     cpu_set_cpustate_pointers(cpu);
 477 }
 478
 479 static const VMStateDescription vmstate_riscv_cpu = {
 480     .name = "cpu",
 481     .unmigratable = 1,
 482 };
 483
 484 static Property riscv_cpu_properties[] = {
 485     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 486     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 487     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 488     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 489     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 490     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 491     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 492     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 493     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 494     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 495     /* This is experimental so mark with 'x-' */
 496     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 497     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 498     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 499     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 500     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 501     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 502     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 503     DEFINE_PROP_END_OF_LIST(),
 504 };
 505
 506 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 507 {
 508     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 509     CPUClass *cc = CPU_CLASS(c);
 510     DeviceClass *dc = DEVICE_CLASS(c);
 511
 512     device_class_set_parent_realize(dc, riscv_cpu_realize,
 513                                     &mcc->parent_realize);
 514
 515     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 516
 517     cc->class_by_name = riscv_cpu_class_by_name;
 518     cc->has_work = riscv_cpu_has_work;
 519     cc->do_interrupt = riscv_cpu_do_interrupt;
 520     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
 521     cc->dump_state = riscv_cpu_dump_state;
 522     cc->set_pc = riscv_cpu_set_pc;
 523     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
 524     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 525     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 526     cc->gdb_num_core_regs = 33;
 527 #if defined(TARGET_RISCV32)
 528     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 529 #elif defined(TARGET_RISCV64)
 530     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 531 #endif
 532     cc->gdb_stop_before_watchpoint = true;
 533     cc->disas_set_info = riscv_cpu_disas_set_info;
 534 #ifndef CONFIG_USER_ONLY
 535     cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
 536     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
 537     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 538 #endif
 539 #ifdef CONFIG_TCG
 540     cc->tcg_initialize = riscv_translate_init;
 541     cc->tlb_fill = riscv_cpu_tlb_fill;
 542 #endif
 543     /* For now, mark unmigratable: */
 544     cc->vmsd = &vmstate_riscv_cpu;
 545     device_class_set_props(dc, riscv_cpu_properties);
 546 }
 547
 548 char *riscv_isa_string(RISCVCPU *cpu)
 549 {
 550     int i;
 551     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 552     char *isa_str = g_new(char, maxlen);
 553     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 554     for (i = 0; i < sizeof(riscv_exts); i++) {
 555         if (cpu->env.misa & RV(riscv_exts[i])) {
 556             *p++ = qemu_tolower(riscv_exts[i]);
 557         }
 558     }
 559     *p = '\0';
 560     return isa_str;
 561 }
 562
 563 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 564 {
 565     ObjectClass *class_a = (ObjectClass *)a;
 566     ObjectClass *class_b = (ObjectClass *)b;
 567     const char *name_a, *name_b;
 568
 569     name_a = object_class_get_name(class_a);
 570     name_b = object_class_get_name(class_b);
 571     return strcmp(name_a, name_b);
 572 }
 573
 574 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 575 {
 576     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 577     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 578
 579     qemu_printf("%.*s\n", len, typename);
 580 }
 581
 582 void riscv_cpu_list(void)
 583 {
 584     GSList *list;
 585
 586     list = object_class_get_list(TYPE_RISCV_CPU, false);
 587     list = g_slist_sort(list, riscv_cpu_list_compare);
 588     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 589     g_slist_free(list);
 590 }
 591
 592 #define DEFINE_CPU(type_name, initfn)      \
 593     {                                      \
 594         .name = type_name,                 \
 595         .parent = TYPE_RISCV_CPU,          \
 596         .instance_init = initfn            \
 597     }
 598
 599 static const TypeInfo riscv_cpu_type_infos[] = {
 600     {
 601         .name = TYPE_RISCV_CPU,
 602         .parent = TYPE_CPU,
 603         .instance_size = sizeof(RISCVCPU),
 604         .instance_init = riscv_cpu_init,
 605         .abstract = true,
 606         .class_size = sizeof(RISCVCPUClass),
 607         .class_init = riscv_cpu_class_init,
 608     },
 609     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 610 #if defined(TARGET_RISCV32)
 611     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
 612     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
 613     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
 614     /* Depreacted */
 615     DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
 616     DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
 617     DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
 618 #elif defined(TARGET_RISCV64)
 619     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
 620     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
 621     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
 622     /* Deprecated */
 623     DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
 624     DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
 625     DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
 626 #endif
 627 };
 628
 629 DEFINE_TYPES(riscv_cpu_type_infos)