target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "exec/exec-all.h"
  26 #include "qapi/error.h"
  27 #include "qemu/error-report.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30
  31 /* RISC-V CPU definitions */
  32
  33 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  34
  35 const char * const riscv_int_regnames[] = {
  36   "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",
  37   "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",
  38   "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",
  39   "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"
  40 };
  41
  42 const char * const riscv_fpr_regnames[] = {
  43   "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
  44   "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
  45   "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
  46   "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
  47 };
  48
  49 const char * const riscv_excp_names[] = {
  50     "misaligned_fetch",
  51     "fault_fetch",
  52     "illegal_instruction",
  53     "breakpoint",
  54     "misaligned_load",
  55     "fault_load",
  56     "misaligned_store",
  57     "fault_store",
  58     "user_ecall",
  59     "supervisor_ecall",
  60     "hypervisor_ecall",
  61     "machine_ecall",
  62     "exec_page_fault",
  63     "load_page_fault",
  64     "reserved",
  65     "store_page_fault"
  66 };
  67
  68 const char * const riscv_intr_names[] = {
  69     "u_software",
  70     "s_software",
  71     "h_software",
  72     "m_software",
  73     "u_timer",
  74     "s_timer",
  75     "h_timer",
  76     "m_timer",
  77     "u_external",
  78     "s_external",
  79     "h_external",
  80     "m_external",
  81     "reserved",
  82     "reserved",
  83     "reserved",
  84     "reserved"
  85 };
  86
  87 static void set_misa(CPURISCVState *env, target_ulong misa)
  88 {
  89     env->misa_mask = env->misa = misa;
  90 }
  91
  92 static void set_priv_version(CPURISCVState *env, int priv_ver)
  93 {
  94     env->priv_ver = priv_ver;
  95 }
  96
  97 static void set_feature(CPURISCVState *env, int feature)
  98 {
  99     env->features |= (1ULL << feature);
 100 }
 101
 102 static void set_resetvec(CPURISCVState *env, int resetvec)
 103 {
 104 #ifndef CONFIG_USER_ONLY
 105     env->resetvec = resetvec;
 106 #endif
 107 }
 108
 109 static void riscv_any_cpu_init(Object *obj)
 110 {
 111     CPURISCVState *env = &RISCV_CPU(obj)->env;
 112     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 113     set_priv_version(env, PRIV_VERSION_1_11_0);
 114     set_resetvec(env, DEFAULT_RSTVEC);
 115 }
 116
 117 #if defined(TARGET_RISCV32)
 118
 119 static void riscv_base32_cpu_init(Object *obj)
 120 {
 121     CPURISCVState *env = &RISCV_CPU(obj)->env;
 122     /* We set this in the realise function */
 123     set_misa(env, 0);
 124 }
 125
 126 static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
 127 {
 128     CPURISCVState *env = &RISCV_CPU(obj)->env;
 129     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 130     set_priv_version(env, PRIV_VERSION_1_09_1);
 131     set_resetvec(env, DEFAULT_RSTVEC);
 132     set_feature(env, RISCV_FEATURE_MMU);
 133     set_feature(env, RISCV_FEATURE_PMP);
 134 }
 135
 136 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
 137 {
 138     CPURISCVState *env = &RISCV_CPU(obj)->env;
 139     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 140     set_priv_version(env, PRIV_VERSION_1_10_0);
 141     set_resetvec(env, DEFAULT_RSTVEC);
 142     set_feature(env, RISCV_FEATURE_MMU);
 143     set_feature(env, RISCV_FEATURE_PMP);
 144 }
 145
 146 static void rv32imacu_nommu_cpu_init(Object *obj)
 147 {
 148     CPURISCVState *env = &RISCV_CPU(obj)->env;
 149     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 150     set_priv_version(env, PRIV_VERSION_1_10_0);
 151     set_resetvec(env, DEFAULT_RSTVEC);
 152     set_feature(env, RISCV_FEATURE_PMP);
 153 }
 154
 155 #elif defined(TARGET_RISCV64)
 156
 157 static void riscv_base64_cpu_init(Object *obj)
 158 {
 159     CPURISCVState *env = &RISCV_CPU(obj)->env;
 160     /* We set this in the realise function */
 161     set_misa(env, 0);
 162 }
 163
 164 static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
 165 {
 166     CPURISCVState *env = &RISCV_CPU(obj)->env;
 167     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 168     set_priv_version(env, PRIV_VERSION_1_09_1);
 169     set_resetvec(env, DEFAULT_RSTVEC);
 170     set_feature(env, RISCV_FEATURE_MMU);
 171     set_feature(env, RISCV_FEATURE_PMP);
 172 }
 173
 174 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
 175 {
 176     CPURISCVState *env = &RISCV_CPU(obj)->env;
 177     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 178     set_priv_version(env, PRIV_VERSION_1_10_0);
 179     set_resetvec(env, DEFAULT_RSTVEC);
 180     set_feature(env, RISCV_FEATURE_MMU);
 181     set_feature(env, RISCV_FEATURE_PMP);
 182 }
 183
 184 static void rv64imacu_nommu_cpu_init(Object *obj)
 185 {
 186     CPURISCVState *env = &RISCV_CPU(obj)->env;
 187     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 188     set_priv_version(env, PRIV_VERSION_1_10_0);
 189     set_resetvec(env, DEFAULT_RSTVEC);
 190     set_feature(env, RISCV_FEATURE_PMP);
 191 }
 192
 193 #endif
 194
 195 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 196 {
 197     ObjectClass *oc;
 198     char *typename;
 199     char **cpuname;
 200
 201     cpuname = g_strsplit(cpu_model, ",", 1);
 202     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 203     oc = object_class_by_name(typename);
 204     g_strfreev(cpuname);
 205     g_free(typename);
 206     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 207         object_class_is_abstract(oc)) {
 208         return NULL;
 209     }
 210     return oc;
 211 }
 212
 213 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 214 {
 215     RISCVCPU *cpu = RISCV_CPU(cs);
 216     CPURISCVState *env = &cpu->env;
 217     int i;
 218
 219     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 220 #ifndef CONFIG_USER_ONLY
 221     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 222     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
 223     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ",
 224                  (target_ulong)atomic_read(&env->mip));
 225     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 226     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 227     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 228     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 229     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 230     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 231 #endif
 232
 233     for (i = 0; i < 32; i++) {
 234         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 235                      riscv_int_regnames[i], env->gpr[i]);
 236         if ((i & 3) == 3) {
 237             qemu_fprintf(f, "\n");
 238         }
 239     }
 240     if (flags & CPU_DUMP_FPU) {
 241         for (i = 0; i < 32; i++) {
 242             qemu_fprintf(f, " %s %016" PRIx64,
 243                          riscv_fpr_regnames[i], env->fpr[i]);
 244             if ((i & 3) == 3) {
 245                 qemu_fprintf(f, "\n");
 246             }
 247         }
 248     }
 249 }
 250
 251 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 252 {
 253     RISCVCPU *cpu = RISCV_CPU(cs);
 254     CPURISCVState *env = &cpu->env;
 255     env->pc = value;
 256 }
 257
 258 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
 259 {
 260     RISCVCPU *cpu = RISCV_CPU(cs);
 261     CPURISCVState *env = &cpu->env;
 262     env->pc = tb->pc;
 263 }
 264
 265 static bool riscv_cpu_has_work(CPUState *cs)
 266 {
 267 #ifndef CONFIG_USER_ONLY
 268     RISCVCPU *cpu = RISCV_CPU(cs);
 269     CPURISCVState *env = &cpu->env;
 270     /*
 271      * Definition of the WFI instruction requires it to ignore the privilege
 272      * mode and delegation registers, but respect individual enables
 273      */
 274     return (atomic_read(&env->mip) & env->mie) != 0;
 275 #else
 276     return true;
 277 #endif
 278 }
 279
 280 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 281                           target_ulong *data)
 282 {
 283     env->pc = data[0];
 284 }
 285
 286 static void riscv_cpu_reset(CPUState *cs)
 287 {
 288     RISCVCPU *cpu = RISCV_CPU(cs);
 289     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 290     CPURISCVState *env = &cpu->env;
 291
 292     mcc->parent_reset(cs);
 293 #ifndef CONFIG_USER_ONLY
 294     env->priv = PRV_M;
 295     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 296     env->mcause = 0;
 297     env->pc = env->resetvec;
 298 #endif
 299     cs->exception_index = EXCP_NONE;
 300     set_default_nan_mode(1, &env->fp_status);
 301 }
 302
 303 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 304 {
 305 #if defined(TARGET_RISCV32)
 306     info->print_insn = print_insn_riscv32;
 307 #elif defined(TARGET_RISCV64)
 308     info->print_insn = print_insn_riscv64;
 309 #endif
 310 }
 311
 312 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 313 {
 314     CPUState *cs = CPU(dev);
 315     RISCVCPU *cpu = RISCV_CPU(dev);
 316     CPURISCVState *env = &cpu->env;
 317     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 318     int priv_version = PRIV_VERSION_1_11_0;
 319     target_ulong target_misa = 0;
 320     Error *local_err = NULL;
 321
 322     cpu_exec_realizefn(cs, &local_err);
 323     if (local_err != NULL) {
 324         error_propagate(errp, local_err);
 325         return;
 326     }
 327
 328     if (cpu->cfg.priv_spec) {
 329         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 330             priv_version = PRIV_VERSION_1_11_0;
 331         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 332             priv_version = PRIV_VERSION_1_10_0;
 333         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
 334             priv_version = PRIV_VERSION_1_09_1;
 335         } else {
 336             error_setg(errp,
 337                        "Unsupported privilege spec version '%s'",
 338                        cpu->cfg.priv_spec);
 339             return;
 340         }
 341     }
 342
 343     set_priv_version(env, priv_version);
 344     set_resetvec(env, DEFAULT_RSTVEC);
 345
 346     if (cpu->cfg.mmu) {
 347         set_feature(env, RISCV_FEATURE_MMU);
 348     }
 349
 350     if (cpu->cfg.pmp) {
 351         set_feature(env, RISCV_FEATURE_PMP);
 352     }
 353
 354     /* If misa isn't set (rv32 and rv64 machines) set it here */
 355     if (!env->misa) {
 356         /* Do some ISA extension error checking */
 357         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 358             error_setg(errp,
 359                        "I and E extensions are incompatible");
 360                        return;
 361        }
 362
 363         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 364             error_setg(errp,
 365                        "Either I or E extension must be set");
 366                        return;
 367        }
 368
 369        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 370                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 371                                cpu->cfg.ext_d)) {
 372             warn_report("Setting G will also set IMAFD");
 373             cpu->cfg.ext_i = true;
 374             cpu->cfg.ext_m = true;
 375             cpu->cfg.ext_a = true;
 376             cpu->cfg.ext_f = true;
 377             cpu->cfg.ext_d = true;
 378         }
 379
 380         /* Set the ISA extensions, checks should have happened above */
 381         if (cpu->cfg.ext_i) {
 382             target_misa |= RVI;
 383         }
 384         if (cpu->cfg.ext_e) {
 385             target_misa |= RVE;
 386         }
 387         if (cpu->cfg.ext_m) {
 388             target_misa |= RVM;
 389         }
 390         if (cpu->cfg.ext_a) {
 391             target_misa |= RVA;
 392         }
 393         if (cpu->cfg.ext_f) {
 394             target_misa |= RVF;
 395         }
 396         if (cpu->cfg.ext_d) {
 397             target_misa |= RVD;
 398         }
 399         if (cpu->cfg.ext_c) {
 400             target_misa |= RVC;
 401         }
 402         if (cpu->cfg.ext_s) {
 403             target_misa |= RVS;
 404         }
 405         if (cpu->cfg.ext_u) {
 406             target_misa |= RVU;
 407         }
 408
 409         set_misa(env, RVXLEN | target_misa);
 410     }
 411
 412     riscv_cpu_register_gdb_regs_for_features(cs);
 413
 414     qemu_init_vcpu(cs);
 415     cpu_reset(cs);
 416
 417     mcc->parent_realize(dev, errp);
 418 }
 419
 420 static void riscv_cpu_init(Object *obj)
 421 {
 422     RISCVCPU *cpu = RISCV_CPU(obj);
 423
 424     cpu_set_cpustate_pointers(cpu);
 425 }
 426
 427 static const VMStateDescription vmstate_riscv_cpu = {
 428     .name = "cpu",
 429     .unmigratable = 1,
 430 };
 431
 432 static Property riscv_cpu_properties[] = {
 433     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 434     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 435     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 436     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 437     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 438     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 439     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 440     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 441     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 442     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 443     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 444     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 445     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 446     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 447     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 448     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 449     DEFINE_PROP_END_OF_LIST(),
 450 };
 451
 452 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 453 {
 454     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 455     CPUClass *cc = CPU_CLASS(c);
 456     DeviceClass *dc = DEVICE_CLASS(c);
 457
 458     device_class_set_parent_realize(dc, riscv_cpu_realize,
 459                                     &mcc->parent_realize);
 460
 461     mcc->parent_reset = cc->reset;
 462     cc->reset = riscv_cpu_reset;
 463
 464     cc->class_by_name = riscv_cpu_class_by_name;
 465     cc->has_work = riscv_cpu_has_work;
 466     cc->do_interrupt = riscv_cpu_do_interrupt;
 467     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
 468     cc->dump_state = riscv_cpu_dump_state;
 469     cc->set_pc = riscv_cpu_set_pc;
 470     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
 471     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 472     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 473     cc->gdb_num_core_regs = 33;
 474 #if defined(TARGET_RISCV32)
 475     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 476 #elif defined(TARGET_RISCV64)
 477     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 478 #endif
 479     cc->gdb_stop_before_watchpoint = true;
 480     cc->disas_set_info = riscv_cpu_disas_set_info;
 481 #ifndef CONFIG_USER_ONLY
 482     cc->do_unassigned_access = riscv_cpu_unassigned_access;
 483     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
 484     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 485 #endif
 486 #ifdef CONFIG_TCG
 487     cc->tcg_initialize = riscv_translate_init;
 488     cc->tlb_fill = riscv_cpu_tlb_fill;
 489 #endif
 490     /* For now, mark unmigratable: */
 491     cc->vmsd = &vmstate_riscv_cpu;
 492     dc->props = riscv_cpu_properties;
 493 }
 494
 495 char *riscv_isa_string(RISCVCPU *cpu)
 496 {
 497     int i;
 498     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 499     char *isa_str = g_new(char, maxlen);
 500     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 501     for (i = 0; i < sizeof(riscv_exts); i++) {
 502         if (cpu->env.misa & RV(riscv_exts[i])) {
 503             *p++ = qemu_tolower(riscv_exts[i]);
 504         }
 505     }
 506     *p = '\0';
 507     return isa_str;
 508 }
 509
 510 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 511 {
 512     ObjectClass *class_a = (ObjectClass *)a;
 513     ObjectClass *class_b = (ObjectClass *)b;
 514     const char *name_a, *name_b;
 515
 516     name_a = object_class_get_name(class_a);
 517     name_b = object_class_get_name(class_b);
 518     return strcmp(name_a, name_b);
 519 }
 520
 521 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 522 {
 523     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 524     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 525
 526     qemu_printf("%.*s\n", len, typename);
 527 }
 528
 529 void riscv_cpu_list(void)
 530 {
 531     GSList *list;
 532
 533     list = object_class_get_list(TYPE_RISCV_CPU, false);
 534     list = g_slist_sort(list, riscv_cpu_list_compare);
 535     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 536     g_slist_free(list);
 537 }
 538
 539 #define DEFINE_CPU(type_name, initfn)      \
 540     {                                      \
 541         .name = type_name,                 \
 542         .parent = TYPE_RISCV_CPU,          \
 543         .instance_init = initfn            \
 544     }
 545
 546 static const TypeInfo riscv_cpu_type_infos[] = {
 547     {
 548         .name = TYPE_RISCV_CPU,
 549         .parent = TYPE_CPU,
 550         .instance_size = sizeof(RISCVCPU),
 551         .instance_init = riscv_cpu_init,
 552         .abstract = true,
 553         .class_size = sizeof(RISCVCPUClass),
 554         .class_init = riscv_cpu_class_init,
 555     },
 556     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 557 #if defined(TARGET_RISCV32)
 558     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
 559     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
 560     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
 561     /* Depreacted */
 562     DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
 563     DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
 564     DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
 565 #elif defined(TARGET_RISCV64)
 566     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
 567     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
 568     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
 569     /* Deprecated */
 570     DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
 571     DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
 572     DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
 573 #endif
 574 };
 575
 576 DEFINE_TYPES(riscv_cpu_type_infos)