4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
26 #include "internals.h"
27 #include "time_helper.h"
28 #include "exec/exec-all.h"
29 #include "qapi/error.h"
30 #include "qemu/error-report.h"
31 #include "hw/qdev-properties.h"
32 #include "migration/vmstate.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "sysemu/kvm.h"
35 #include "kvm_riscv.h"
37 /* RISC-V CPU definitions */
39 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
40 (QEMU_VERSION_MINOR << 8) | \
42 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
44 static const char riscv_single_letter_exts
[] = "IEMAFDQCPVH";
50 int ext_enable_offset
;
53 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
54 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
57 * Here are the ordering rules of extension naming defined by RISC-V
59 * 1. All extensions should be separated from other multi-letter extensions
61 * 2. The first letter following the 'Z' conventionally indicates the most
62 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
63 * If multiple 'Z' extensions are named, they should be ordered first
64 * by category, then alphabetically within a category.
65 * 3. Standard supervisor-level extensions (starts with 'S') should be
66 * listed after standard unprivileged extensions. If multiple
67 * supervisor-level extensions are listed, they should be ordered
69 * 4. Non-standard extensions (starts with 'X') must be listed after all
70 * standard extensions. They must be separated from other multi-letter
71 * extensions by an underscore.
73 static const struct isa_ext_data isa_edata_arr
[] = {
74 ISA_EXT_DATA_ENTRY(h
, false, PRIV_VERSION_1_12_0
, ext_h
),
75 ISA_EXT_DATA_ENTRY(v
, false, PRIV_VERSION_1_12_0
, ext_v
),
76 ISA_EXT_DATA_ENTRY(zicsr
, true, PRIV_VERSION_1_10_0
, ext_icsr
),
77 ISA_EXT_DATA_ENTRY(zifencei
, true, PRIV_VERSION_1_10_0
, ext_ifencei
),
78 ISA_EXT_DATA_ENTRY(zihintpause
, true, PRIV_VERSION_1_10_0
, ext_zihintpause
),
79 ISA_EXT_DATA_ENTRY(zfh
, true, PRIV_VERSION_1_12_0
, ext_zfh
),
80 ISA_EXT_DATA_ENTRY(zfhmin
, true, PRIV_VERSION_1_12_0
, ext_zfhmin
),
81 ISA_EXT_DATA_ENTRY(zfinx
, true, PRIV_VERSION_1_12_0
, ext_zfinx
),
82 ISA_EXT_DATA_ENTRY(zdinx
, true, PRIV_VERSION_1_12_0
, ext_zdinx
),
83 ISA_EXT_DATA_ENTRY(zba
, true, PRIV_VERSION_1_12_0
, ext_zba
),
84 ISA_EXT_DATA_ENTRY(zbb
, true, PRIV_VERSION_1_12_0
, ext_zbb
),
85 ISA_EXT_DATA_ENTRY(zbc
, true, PRIV_VERSION_1_12_0
, ext_zbc
),
86 ISA_EXT_DATA_ENTRY(zbkb
, true, PRIV_VERSION_1_12_0
, ext_zbkb
),
87 ISA_EXT_DATA_ENTRY(zbkc
, true, PRIV_VERSION_1_12_0
, ext_zbkc
),
88 ISA_EXT_DATA_ENTRY(zbkx
, true, PRIV_VERSION_1_12_0
, ext_zbkx
),
89 ISA_EXT_DATA_ENTRY(zbs
, true, PRIV_VERSION_1_12_0
, ext_zbs
),
90 ISA_EXT_DATA_ENTRY(zk
, true, PRIV_VERSION_1_12_0
, ext_zk
),
91 ISA_EXT_DATA_ENTRY(zkn
, true, PRIV_VERSION_1_12_0
, ext_zkn
),
92 ISA_EXT_DATA_ENTRY(zknd
, true, PRIV_VERSION_1_12_0
, ext_zknd
),
93 ISA_EXT_DATA_ENTRY(zkne
, true, PRIV_VERSION_1_12_0
, ext_zkne
),
94 ISA_EXT_DATA_ENTRY(zknh
, true, PRIV_VERSION_1_12_0
, ext_zknh
),
95 ISA_EXT_DATA_ENTRY(zkr
, true, PRIV_VERSION_1_12_0
, ext_zkr
),
96 ISA_EXT_DATA_ENTRY(zks
, true, PRIV_VERSION_1_12_0
, ext_zks
),
97 ISA_EXT_DATA_ENTRY(zksed
, true, PRIV_VERSION_1_12_0
, ext_zksed
),
98 ISA_EXT_DATA_ENTRY(zksh
, true, PRIV_VERSION_1_12_0
, ext_zksh
),
99 ISA_EXT_DATA_ENTRY(zkt
, true, PRIV_VERSION_1_12_0
, ext_zkt
),
100 ISA_EXT_DATA_ENTRY(zve32f
, true, PRIV_VERSION_1_12_0
, ext_zve32f
),
101 ISA_EXT_DATA_ENTRY(zve64f
, true, PRIV_VERSION_1_12_0
, ext_zve64f
),
102 ISA_EXT_DATA_ENTRY(zhinx
, true, PRIV_VERSION_1_12_0
, ext_zhinx
),
103 ISA_EXT_DATA_ENTRY(zhinxmin
, true, PRIV_VERSION_1_12_0
, ext_zhinxmin
),
104 ISA_EXT_DATA_ENTRY(smaia
, true, PRIV_VERSION_1_12_0
, ext_smaia
),
105 ISA_EXT_DATA_ENTRY(ssaia
, true, PRIV_VERSION_1_12_0
, ext_ssaia
),
106 ISA_EXT_DATA_ENTRY(sscofpmf
, true, PRIV_VERSION_1_12_0
, ext_sscofpmf
),
107 ISA_EXT_DATA_ENTRY(sstc
, true, PRIV_VERSION_1_12_0
, ext_sstc
),
108 ISA_EXT_DATA_ENTRY(svinval
, true, PRIV_VERSION_1_12_0
, ext_svinval
),
109 ISA_EXT_DATA_ENTRY(svnapot
, true, PRIV_VERSION_1_12_0
, ext_svnapot
),
110 ISA_EXT_DATA_ENTRY(svpbmt
, true, PRIV_VERSION_1_12_0
, ext_svpbmt
),
111 ISA_EXT_DATA_ENTRY(xventanacondops
, true, PRIV_VERSION_1_12_0
, ext_XVentanaCondOps
),
114 static bool isa_ext_is_enabled(RISCVCPU
*cpu
,
115 const struct isa_ext_data
*edata
)
117 bool *ext_enabled
= (void *)&cpu
->cfg
+ edata
->ext_enable_offset
;
122 static void isa_ext_update_enabled(RISCVCPU
*cpu
,
123 const struct isa_ext_data
*edata
, bool en
)
125 bool *ext_enabled
= (void *)&cpu
->cfg
+ edata
->ext_enable_offset
;
130 const char * const riscv_int_regnames
[] = {
131 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
132 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
133 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
134 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
135 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
138 const char * const riscv_int_regnamesh
[] = {
139 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
140 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
141 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
142 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
143 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
144 "x30h/t5h", "x31h/t6h"
147 const char * const riscv_fpr_regnames
[] = {
148 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
149 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
150 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
151 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
152 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
153 "f30/ft10", "f31/ft11"
156 static const char * const riscv_excp_names
[] = {
159 "illegal_instruction",
177 "guest_exec_page_fault",
178 "guest_load_page_fault",
180 "guest_store_page_fault",
183 static const char * const riscv_intr_names
[] = {
202 static void register_cpu_props(DeviceState
*dev
);
204 const char *riscv_cpu_get_trap_name(target_ulong cause
, bool async
)
207 return (cause
< ARRAY_SIZE(riscv_intr_names
)) ?
208 riscv_intr_names
[cause
] : "(unknown)";
210 return (cause
< ARRAY_SIZE(riscv_excp_names
)) ?
211 riscv_excp_names
[cause
] : "(unknown)";
215 static void set_misa(CPURISCVState
*env
, RISCVMXL mxl
, uint32_t ext
)
217 env
->misa_mxl_max
= env
->misa_mxl
= mxl
;
218 env
->misa_ext_mask
= env
->misa_ext
= ext
;
221 static void set_priv_version(CPURISCVState
*env
, int priv_ver
)
223 env
->priv_ver
= priv_ver
;
226 static void set_vext_version(CPURISCVState
*env
, int vext_ver
)
228 env
->vext_ver
= vext_ver
;
231 static void set_resetvec(CPURISCVState
*env
, target_ulong resetvec
)
233 #ifndef CONFIG_USER_ONLY
234 env
->resetvec
= resetvec
;
238 static void riscv_any_cpu_init(Object
*obj
)
240 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
241 #if defined(TARGET_RISCV32)
242 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
243 #elif defined(TARGET_RISCV64)
244 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
246 set_priv_version(env
, PRIV_VERSION_1_12_0
);
247 register_cpu_props(DEVICE(obj
));
250 #if defined(TARGET_RISCV64)
251 static void rv64_base_cpu_init(Object
*obj
)
253 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
254 /* We set this in the realise function */
255 set_misa(env
, MXL_RV64
, 0);
256 register_cpu_props(DEVICE(obj
));
257 /* Set latest version of privileged specification */
258 set_priv_version(env
, PRIV_VERSION_1_12_0
);
261 static void rv64_sifive_u_cpu_init(Object
*obj
)
263 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
264 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
265 set_priv_version(env
, PRIV_VERSION_1_10_0
);
268 static void rv64_sifive_e_cpu_init(Object
*obj
)
270 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
271 RISCVCPU
*cpu
= RISCV_CPU(obj
);
273 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVC
| RVU
);
274 set_priv_version(env
, PRIV_VERSION_1_10_0
);
275 cpu
->cfg
.mmu
= false;
278 static void rv128_base_cpu_init(Object
*obj
)
280 if (qemu_tcg_mttcg_enabled()) {
281 /* Missing 128-bit aligned atomics */
282 error_report("128-bit RISC-V currently does not work with Multi "
283 "Threaded TCG. Please use: -accel tcg,thread=single");
286 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
287 /* We set this in the realise function */
288 set_misa(env
, MXL_RV128
, 0);
289 register_cpu_props(DEVICE(obj
));
290 /* Set latest version of privileged specification */
291 set_priv_version(env
, PRIV_VERSION_1_12_0
);
294 static void rv32_base_cpu_init(Object
*obj
)
296 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
297 /* We set this in the realise function */
298 set_misa(env
, MXL_RV32
, 0);
299 register_cpu_props(DEVICE(obj
));
300 /* Set latest version of privileged specification */
301 set_priv_version(env
, PRIV_VERSION_1_12_0
);
304 static void rv32_sifive_u_cpu_init(Object
*obj
)
306 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
307 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
308 set_priv_version(env
, PRIV_VERSION_1_10_0
);
311 static void rv32_sifive_e_cpu_init(Object
*obj
)
313 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
314 RISCVCPU
*cpu
= RISCV_CPU(obj
);
316 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVC
| RVU
);
317 set_priv_version(env
, PRIV_VERSION_1_10_0
);
318 cpu
->cfg
.mmu
= false;
321 static void rv32_ibex_cpu_init(Object
*obj
)
323 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
324 RISCVCPU
*cpu
= RISCV_CPU(obj
);
326 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVC
| RVU
);
327 set_priv_version(env
, PRIV_VERSION_1_11_0
);
328 cpu
->cfg
.mmu
= false;
329 cpu
->cfg
.epmp
= true;
332 static void rv32_imafcu_nommu_cpu_init(Object
*obj
)
334 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
335 RISCVCPU
*cpu
= RISCV_CPU(obj
);
337 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVC
| RVU
);
338 set_priv_version(env
, PRIV_VERSION_1_10_0
);
339 set_resetvec(env
, DEFAULT_RSTVEC
);
340 cpu
->cfg
.mmu
= false;
344 #if defined(CONFIG_KVM)
345 static void riscv_host_cpu_init(Object
*obj
)
347 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
348 #if defined(TARGET_RISCV32)
349 set_misa(env
, MXL_RV32
, 0);
350 #elif defined(TARGET_RISCV64)
351 set_misa(env
, MXL_RV64
, 0);
353 register_cpu_props(DEVICE(obj
));
357 static ObjectClass
*riscv_cpu_class_by_name(const char *cpu_model
)
363 cpuname
= g_strsplit(cpu_model
, ",", 1);
364 typename
= g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname
[0]);
365 oc
= object_class_by_name(typename
);
368 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_RISCV_CPU
) ||
369 object_class_is_abstract(oc
)) {
375 static void riscv_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
377 RISCVCPU
*cpu
= RISCV_CPU(cs
);
378 CPURISCVState
*env
= &cpu
->env
;
381 #if !defined(CONFIG_USER_ONLY)
382 if (riscv_has_ext(env
, RVH
)) {
383 qemu_fprintf(f
, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env
));
386 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "pc ", env
->pc
);
387 #ifndef CONFIG_USER_ONLY
389 static const int dump_csrs
[] = {
426 for (int i
= 0; i
< ARRAY_SIZE(dump_csrs
); ++i
) {
427 int csrno
= dump_csrs
[i
];
428 target_ulong val
= 0;
429 RISCVException res
= riscv_csrrw_debug(env
, csrno
, &val
, 0, 0);
432 * Rely on the smode, hmode, etc, predicates within csr.c
433 * to do the filtering of the registers that are present.
435 if (res
== RISCV_EXCP_NONE
) {
436 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
"\n",
437 csr_ops
[csrno
].name
, val
);
443 for (i
= 0; i
< 32; i
++) {
444 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
,
445 riscv_int_regnames
[i
], env
->gpr
[i
]);
447 qemu_fprintf(f
, "\n");
450 if (flags
& CPU_DUMP_FPU
) {
451 for (i
= 0; i
< 32; i
++) {
452 qemu_fprintf(f
, " %-8s %016" PRIx64
,
453 riscv_fpr_regnames
[i
], env
->fpr
[i
]);
455 qemu_fprintf(f
, "\n");
461 static void riscv_cpu_set_pc(CPUState
*cs
, vaddr value
)
463 RISCVCPU
*cpu
= RISCV_CPU(cs
);
464 CPURISCVState
*env
= &cpu
->env
;
466 if (env
->xl
== MXL_RV32
) {
467 env
->pc
= (int32_t)value
;
473 static void riscv_cpu_synchronize_from_tb(CPUState
*cs
,
474 const TranslationBlock
*tb
)
476 RISCVCPU
*cpu
= RISCV_CPU(cs
);
477 CPURISCVState
*env
= &cpu
->env
;
478 RISCVMXL xl
= FIELD_EX32(tb
->flags
, TB_FLAGS
, XL
);
480 if (xl
== MXL_RV32
) {
481 env
->pc
= (int32_t)tb
->pc
;
487 static bool riscv_cpu_has_work(CPUState
*cs
)
489 #ifndef CONFIG_USER_ONLY
490 RISCVCPU
*cpu
= RISCV_CPU(cs
);
491 CPURISCVState
*env
= &cpu
->env
;
493 * Definition of the WFI instruction requires it to ignore the privilege
494 * mode and delegation registers, but respect individual enables
496 return riscv_cpu_all_pending(env
) != 0;
502 void restore_state_to_opc(CPURISCVState
*env
, TranslationBlock
*tb
,
505 RISCVMXL xl
= FIELD_EX32(tb
->flags
, TB_FLAGS
, XL
);
506 if (xl
== MXL_RV32
) {
507 env
->pc
= (int32_t)data
[0];
514 static void riscv_cpu_reset(DeviceState
*dev
)
516 #ifndef CONFIG_USER_ONLY
520 CPUState
*cs
= CPU(dev
);
521 RISCVCPU
*cpu
= RISCV_CPU(cs
);
522 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(cpu
);
523 CPURISCVState
*env
= &cpu
->env
;
525 mcc
->parent_reset(dev
);
526 #ifndef CONFIG_USER_ONLY
527 env
->misa_mxl
= env
->misa_mxl_max
;
529 env
->mstatus
&= ~(MSTATUS_MIE
| MSTATUS_MPRV
);
530 if (env
->misa_mxl
> MXL_RV32
) {
532 * The reset status of SXL/UXL is undefined, but mstatus is WARL
533 * and we must ensure that the value after init is valid for read.
535 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_SXL
, env
->misa_mxl
);
536 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_UXL
, env
->misa_mxl
);
537 if (riscv_has_ext(env
, RVH
)) {
538 env
->vsstatus
= set_field(env
->vsstatus
,
539 MSTATUS64_SXL
, env
->misa_mxl
);
540 env
->vsstatus
= set_field(env
->vsstatus
,
541 MSTATUS64_UXL
, env
->misa_mxl
);
542 env
->mstatus_hs
= set_field(env
->mstatus_hs
,
543 MSTATUS64_SXL
, env
->misa_mxl
);
544 env
->mstatus_hs
= set_field(env
->mstatus_hs
,
545 MSTATUS64_UXL
, env
->misa_mxl
);
549 env
->miclaim
= MIP_SGEIP
;
550 env
->pc
= env
->resetvec
;
552 env
->two_stage_lookup
= false;
554 /* Initialized default priorities of local interrupts. */
555 for (i
= 0; i
< ARRAY_SIZE(env
->miprio
); i
++) {
556 iprio
= riscv_cpu_default_priority(i
);
557 env
->miprio
[i
] = (i
== IRQ_M_EXT
) ? 0 : iprio
;
558 env
->siprio
[i
] = (i
== IRQ_S_EXT
) ? 0 : iprio
;
562 while (!riscv_cpu_hviprio_index2irq(i
, &irq
, &rdzero
)) {
564 env
->hviprio
[irq
] = env
->miprio
[irq
];
568 /* mmte is supposed to have pm.current hardwired to 1 */
569 env
->mmte
|= (PM_EXT_INITIAL
| MMTE_M_PM_CURRENT
);
571 env
->xl
= riscv_cpu_mxl(env
);
572 riscv_cpu_update_mask(env
);
573 cs
->exception_index
= RISCV_EXCP_NONE
;
575 set_default_nan_mode(1, &env
->fp_status
);
577 #ifndef CONFIG_USER_ONLY
578 if (riscv_feature(env
, RISCV_FEATURE_DEBUG
)) {
579 riscv_trigger_init(env
);
583 kvm_riscv_reset_vcpu(cpu
);
588 static void riscv_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
590 RISCVCPU
*cpu
= RISCV_CPU(s
);
592 switch (riscv_cpu_mxl(&cpu
->env
)) {
594 info
->print_insn
= print_insn_riscv32
;
597 info
->print_insn
= print_insn_riscv64
;
600 info
->print_insn
= print_insn_riscv128
;
603 g_assert_not_reached();
607 static void riscv_cpu_realize(DeviceState
*dev
, Error
**errp
)
609 CPUState
*cs
= CPU(dev
);
610 RISCVCPU
*cpu
= RISCV_CPU(dev
);
611 CPURISCVState
*env
= &cpu
->env
;
612 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(dev
);
613 CPUClass
*cc
= CPU_CLASS(mcc
);
614 int i
, priv_version
= -1;
615 Error
*local_err
= NULL
;
617 cpu_exec_realizefn(cs
, &local_err
);
618 if (local_err
!= NULL
) {
619 error_propagate(errp
, local_err
);
623 if (cpu
->cfg
.priv_spec
) {
624 if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.12.0")) {
625 priv_version
= PRIV_VERSION_1_12_0
;
626 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.11.0")) {
627 priv_version
= PRIV_VERSION_1_11_0
;
628 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.10.0")) {
629 priv_version
= PRIV_VERSION_1_10_0
;
632 "Unsupported privilege spec version '%s'",
638 if (priv_version
>= PRIV_VERSION_1_10_0
) {
639 set_priv_version(env
, priv_version
);
642 /* Force disable extensions if priv spec version does not match */
643 for (i
= 0; i
< ARRAY_SIZE(isa_edata_arr
); i
++) {
644 if (isa_ext_is_enabled(cpu
, &isa_edata_arr
[i
]) &&
645 (env
->priv_ver
< isa_edata_arr
[i
].min_version
)) {
646 isa_ext_update_enabled(cpu
, &isa_edata_arr
[i
], false);
647 #ifndef CONFIG_USER_ONLY
648 warn_report("disabling %s extension for hart 0x%lx because "
649 "privilege spec version does not match",
650 isa_edata_arr
[i
].name
, (unsigned long)env
->mhartid
);
652 warn_report("disabling %s extension because "
653 "privilege spec version does not match",
654 isa_edata_arr
[i
].name
);
660 riscv_set_feature(env
, RISCV_FEATURE_MMU
);
664 riscv_set_feature(env
, RISCV_FEATURE_PMP
);
667 * Enhanced PMP should only be available
668 * on harts with PMP support
671 riscv_set_feature(env
, RISCV_FEATURE_EPMP
);
675 if (cpu
->cfg
.debug
) {
676 riscv_set_feature(env
, RISCV_FEATURE_DEBUG
);
679 set_resetvec(env
, cpu
->cfg
.resetvec
);
681 #ifndef CONFIG_USER_ONLY
682 if (cpu
->cfg
.ext_sstc
) {
683 riscv_timer_init(cpu
);
685 #endif /* CONFIG_USER_ONLY */
687 /* Validate that MISA_MXL is set properly. */
688 switch (env
->misa_mxl_max
) {
689 #ifdef TARGET_RISCV64
692 cc
->gdb_core_xml_file
= "riscv-64bit-cpu.xml";
696 cc
->gdb_core_xml_file
= "riscv-32bit-cpu.xml";
699 g_assert_not_reached();
701 assert(env
->misa_mxl_max
== env
->misa_mxl
);
703 /* If only MISA_EXT is unset for misa, then set it from properties */
704 if (env
->misa_ext
== 0) {
707 /* Do some ISA extension error checking */
708 if (cpu
->cfg
.ext_g
&& !(cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_m
&&
709 cpu
->cfg
.ext_a
&& cpu
->cfg
.ext_f
&&
711 cpu
->cfg
.ext_icsr
&& cpu
->cfg
.ext_ifencei
)) {
712 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
713 cpu
->cfg
.ext_i
= true;
714 cpu
->cfg
.ext_m
= true;
715 cpu
->cfg
.ext_a
= true;
716 cpu
->cfg
.ext_f
= true;
717 cpu
->cfg
.ext_d
= true;
718 cpu
->cfg
.ext_icsr
= true;
719 cpu
->cfg
.ext_ifencei
= true;
722 if (cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_e
) {
724 "I and E extensions are incompatible");
728 if (!cpu
->cfg
.ext_i
&& !cpu
->cfg
.ext_e
) {
730 "Either I or E extension must be set");
734 if (cpu
->cfg
.ext_s
&& !cpu
->cfg
.ext_u
) {
736 "Setting S extension without U extension is illegal");
740 if (cpu
->cfg
.ext_h
&& !cpu
->cfg
.ext_i
) {
742 "H depends on an I base integer ISA with 32 x registers");
746 if (cpu
->cfg
.ext_h
&& !cpu
->cfg
.ext_s
) {
747 error_setg(errp
, "H extension implicitly requires S-mode");
751 if (cpu
->cfg
.ext_f
&& !cpu
->cfg
.ext_icsr
) {
752 error_setg(errp
, "F extension requires Zicsr");
756 if ((cpu
->cfg
.ext_zfh
|| cpu
->cfg
.ext_zfhmin
) && !cpu
->cfg
.ext_f
) {
757 error_setg(errp
, "Zfh/Zfhmin extensions require F extension");
761 if (cpu
->cfg
.ext_d
&& !cpu
->cfg
.ext_f
) {
762 error_setg(errp
, "D extension requires F extension");
766 if (cpu
->cfg
.ext_v
&& !cpu
->cfg
.ext_d
) {
767 error_setg(errp
, "V extension requires D extension");
771 if ((cpu
->cfg
.ext_zve32f
|| cpu
->cfg
.ext_zve64f
) && !cpu
->cfg
.ext_f
) {
772 error_setg(errp
, "Zve32f/Zve64f extensions require F extension");
776 /* Set the ISA extensions, checks should have happened above */
777 if (cpu
->cfg
.ext_zdinx
|| cpu
->cfg
.ext_zhinx
||
778 cpu
->cfg
.ext_zhinxmin
) {
779 cpu
->cfg
.ext_zfinx
= true;
782 if (cpu
->cfg
.ext_zfinx
) {
783 if (!cpu
->cfg
.ext_icsr
) {
784 error_setg(errp
, "Zfinx extension requires Zicsr");
787 if (cpu
->cfg
.ext_f
) {
789 "Zfinx cannot be supported together with F extension");
794 if (cpu
->cfg
.ext_zk
) {
795 cpu
->cfg
.ext_zkn
= true;
796 cpu
->cfg
.ext_zkr
= true;
797 cpu
->cfg
.ext_zkt
= true;
800 if (cpu
->cfg
.ext_zkn
) {
801 cpu
->cfg
.ext_zbkb
= true;
802 cpu
->cfg
.ext_zbkc
= true;
803 cpu
->cfg
.ext_zbkx
= true;
804 cpu
->cfg
.ext_zkne
= true;
805 cpu
->cfg
.ext_zknd
= true;
806 cpu
->cfg
.ext_zknh
= true;
809 if (cpu
->cfg
.ext_zks
) {
810 cpu
->cfg
.ext_zbkb
= true;
811 cpu
->cfg
.ext_zbkc
= true;
812 cpu
->cfg
.ext_zbkx
= true;
813 cpu
->cfg
.ext_zksed
= true;
814 cpu
->cfg
.ext_zksh
= true;
817 if (cpu
->cfg
.ext_i
) {
820 if (cpu
->cfg
.ext_e
) {
823 if (cpu
->cfg
.ext_m
) {
826 if (cpu
->cfg
.ext_a
) {
829 if (cpu
->cfg
.ext_f
) {
832 if (cpu
->cfg
.ext_d
) {
835 if (cpu
->cfg
.ext_c
) {
838 if (cpu
->cfg
.ext_s
) {
841 if (cpu
->cfg
.ext_u
) {
844 if (cpu
->cfg
.ext_h
) {
847 if (cpu
->cfg
.ext_v
) {
848 int vext_version
= VEXT_VERSION_1_00_0
;
850 if (!is_power_of_2(cpu
->cfg
.vlen
)) {
852 "Vector extension VLEN must be power of 2");
855 if (cpu
->cfg
.vlen
> RV_VLEN_MAX
|| cpu
->cfg
.vlen
< 128) {
857 "Vector extension implementation only supports VLEN "
858 "in the range [128, %d]", RV_VLEN_MAX
);
861 if (!is_power_of_2(cpu
->cfg
.elen
)) {
863 "Vector extension ELEN must be power of 2");
866 if (cpu
->cfg
.elen
> 64 || cpu
->cfg
.vlen
< 8) {
868 "Vector extension implementation only supports ELEN "
869 "in the range [8, 64]");
872 if (cpu
->cfg
.vext_spec
) {
873 if (!g_strcmp0(cpu
->cfg
.vext_spec
, "v1.0")) {
874 vext_version
= VEXT_VERSION_1_00_0
;
877 "Unsupported vector spec version '%s'",
882 qemu_log("vector version is not specified, "
883 "use the default value v1.0\n");
885 set_vext_version(env
, vext_version
);
887 if (cpu
->cfg
.ext_j
) {
891 set_misa(env
, env
->misa_mxl
, ext
);
894 #ifndef CONFIG_USER_ONLY
895 if (cpu
->cfg
.pmu_num
) {
896 if (!riscv_pmu_init(cpu
, cpu
->cfg
.pmu_num
) && cpu
->cfg
.ext_sscofpmf
) {
897 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
898 riscv_pmu_timer_cb
, cpu
);
903 riscv_cpu_register_gdb_regs_for_features(cs
);
908 mcc
->parent_realize(dev
, errp
);
911 #ifndef CONFIG_USER_ONLY
912 static void riscv_cpu_set_irq(void *opaque
, int irq
, int level
)
914 RISCVCPU
*cpu
= RISCV_CPU(opaque
);
915 CPURISCVState
*env
= &cpu
->env
;
917 if (irq
< IRQ_LOCAL_MAX
) {
931 kvm_riscv_set_irq(cpu
, irq
, level
);
933 riscv_cpu_update_mip(cpu
, 1 << irq
, BOOL_TO_MASK(level
));
938 kvm_riscv_set_irq(cpu
, irq
, level
);
940 env
->external_seip
= level
;
941 riscv_cpu_update_mip(cpu
, 1 << irq
,
942 BOOL_TO_MASK(level
| env
->software_seip
));
946 g_assert_not_reached();
948 } else if (irq
< (IRQ_LOCAL_MAX
+ IRQ_LOCAL_GUEST_MAX
)) {
949 /* Require H-extension for handling guest local interrupts */
950 if (!riscv_has_ext(env
, RVH
)) {
951 g_assert_not_reached();
954 /* Compute bit position in HGEIP CSR */
955 irq
= irq
- IRQ_LOCAL_MAX
+ 1;
956 if (env
->geilen
< irq
) {
957 g_assert_not_reached();
960 /* Update HGEIP CSR */
961 env
->hgeip
&= ~((target_ulong
)1 << irq
);
963 env
->hgeip
|= (target_ulong
)1 << irq
;
966 /* Update mip.SGEIP bit */
967 riscv_cpu_update_mip(cpu
, MIP_SGEIP
,
968 BOOL_TO_MASK(!!(env
->hgeie
& env
->hgeip
)));
970 g_assert_not_reached();
973 #endif /* CONFIG_USER_ONLY */
975 static void riscv_cpu_init(Object
*obj
)
977 RISCVCPU
*cpu
= RISCV_CPU(obj
);
979 cpu
->cfg
.ext_ifencei
= true;
980 cpu
->cfg
.ext_icsr
= true;
984 cpu_set_cpustate_pointers(cpu
);
986 #ifndef CONFIG_USER_ONLY
987 qdev_init_gpio_in(DEVICE(cpu
), riscv_cpu_set_irq
,
988 IRQ_LOCAL_MAX
+ IRQ_LOCAL_GUEST_MAX
);
989 #endif /* CONFIG_USER_ONLY */
992 static Property riscv_cpu_extensions
[] = {
993 /* Defaults for standard extensions */
994 DEFINE_PROP_BOOL("i", RISCVCPU
, cfg
.ext_i
, true),
995 DEFINE_PROP_BOOL("e", RISCVCPU
, cfg
.ext_e
, false),
996 DEFINE_PROP_BOOL("g", RISCVCPU
, cfg
.ext_g
, false),
997 DEFINE_PROP_BOOL("m", RISCVCPU
, cfg
.ext_m
, true),
998 DEFINE_PROP_BOOL("a", RISCVCPU
, cfg
.ext_a
, true),
999 DEFINE_PROP_BOOL("f", RISCVCPU
, cfg
.ext_f
, true),
1000 DEFINE_PROP_BOOL("d", RISCVCPU
, cfg
.ext_d
, true),
1001 DEFINE_PROP_BOOL("c", RISCVCPU
, cfg
.ext_c
, true),
1002 DEFINE_PROP_BOOL("s", RISCVCPU
, cfg
.ext_s
, true),
1003 DEFINE_PROP_BOOL("u", RISCVCPU
, cfg
.ext_u
, true),
1004 DEFINE_PROP_BOOL("v", RISCVCPU
, cfg
.ext_v
, false),
1005 DEFINE_PROP_BOOL("h", RISCVCPU
, cfg
.ext_h
, true),
1006 DEFINE_PROP_UINT8("pmu-num", RISCVCPU
, cfg
.pmu_num
, 16),
1007 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU
, cfg
.ext_sscofpmf
, false),
1008 DEFINE_PROP_BOOL("Zifencei", RISCVCPU
, cfg
.ext_ifencei
, true),
1009 DEFINE_PROP_BOOL("Zicsr", RISCVCPU
, cfg
.ext_icsr
, true),
1010 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU
, cfg
.ext_zihintpause
, true),
1011 DEFINE_PROP_BOOL("Zfh", RISCVCPU
, cfg
.ext_zfh
, false),
1012 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU
, cfg
.ext_zfhmin
, false),
1013 DEFINE_PROP_BOOL("Zve32f", RISCVCPU
, cfg
.ext_zve32f
, false),
1014 DEFINE_PROP_BOOL("Zve64f", RISCVCPU
, cfg
.ext_zve64f
, false),
1015 DEFINE_PROP_BOOL("mmu", RISCVCPU
, cfg
.mmu
, true),
1016 DEFINE_PROP_BOOL("pmp", RISCVCPU
, cfg
.pmp
, true),
1017 DEFINE_PROP_BOOL("sstc", RISCVCPU
, cfg
.ext_sstc
, true),
1019 DEFINE_PROP_STRING("priv_spec", RISCVCPU
, cfg
.priv_spec
),
1020 DEFINE_PROP_STRING("vext_spec", RISCVCPU
, cfg
.vext_spec
),
1021 DEFINE_PROP_UINT16("vlen", RISCVCPU
, cfg
.vlen
, 128),
1022 DEFINE_PROP_UINT16("elen", RISCVCPU
, cfg
.elen
, 64),
1024 DEFINE_PROP_BOOL("svinval", RISCVCPU
, cfg
.ext_svinval
, false),
1025 DEFINE_PROP_BOOL("svnapot", RISCVCPU
, cfg
.ext_svnapot
, false),
1026 DEFINE_PROP_BOOL("svpbmt", RISCVCPU
, cfg
.ext_svpbmt
, false),
1028 DEFINE_PROP_BOOL("zba", RISCVCPU
, cfg
.ext_zba
, true),
1029 DEFINE_PROP_BOOL("zbb", RISCVCPU
, cfg
.ext_zbb
, true),
1030 DEFINE_PROP_BOOL("zbc", RISCVCPU
, cfg
.ext_zbc
, true),
1031 DEFINE_PROP_BOOL("zbkb", RISCVCPU
, cfg
.ext_zbkb
, false),
1032 DEFINE_PROP_BOOL("zbkc", RISCVCPU
, cfg
.ext_zbkc
, false),
1033 DEFINE_PROP_BOOL("zbkx", RISCVCPU
, cfg
.ext_zbkx
, false),
1034 DEFINE_PROP_BOOL("zbs", RISCVCPU
, cfg
.ext_zbs
, true),
1035 DEFINE_PROP_BOOL("zk", RISCVCPU
, cfg
.ext_zk
, false),
1036 DEFINE_PROP_BOOL("zkn", RISCVCPU
, cfg
.ext_zkn
, false),
1037 DEFINE_PROP_BOOL("zknd", RISCVCPU
, cfg
.ext_zknd
, false),
1038 DEFINE_PROP_BOOL("zkne", RISCVCPU
, cfg
.ext_zkne
, false),
1039 DEFINE_PROP_BOOL("zknh", RISCVCPU
, cfg
.ext_zknh
, false),
1040 DEFINE_PROP_BOOL("zkr", RISCVCPU
, cfg
.ext_zkr
, false),
1041 DEFINE_PROP_BOOL("zks", RISCVCPU
, cfg
.ext_zks
, false),
1042 DEFINE_PROP_BOOL("zksed", RISCVCPU
, cfg
.ext_zksed
, false),
1043 DEFINE_PROP_BOOL("zksh", RISCVCPU
, cfg
.ext_zksh
, false),
1044 DEFINE_PROP_BOOL("zkt", RISCVCPU
, cfg
.ext_zkt
, false),
1046 DEFINE_PROP_BOOL("zdinx", RISCVCPU
, cfg
.ext_zdinx
, false),
1047 DEFINE_PROP_BOOL("zfinx", RISCVCPU
, cfg
.ext_zfinx
, false),
1048 DEFINE_PROP_BOOL("zhinx", RISCVCPU
, cfg
.ext_zhinx
, false),
1049 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU
, cfg
.ext_zhinxmin
, false),
1051 DEFINE_PROP_BOOL("zmmul", RISCVCPU
, cfg
.ext_zmmul
, false),
1053 /* Vendor-specific custom extensions */
1054 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU
, cfg
.ext_XVentanaCondOps
, false),
1056 /* These are experimental so mark with 'x-' */
1057 DEFINE_PROP_BOOL("x-j", RISCVCPU
, cfg
.ext_j
, false),
1059 DEFINE_PROP_BOOL("x-epmp", RISCVCPU
, cfg
.epmp
, false),
1060 DEFINE_PROP_BOOL("x-smaia", RISCVCPU
, cfg
.ext_smaia
, false),
1061 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU
, cfg
.ext_ssaia
, false),
1063 DEFINE_PROP_END_OF_LIST(),
1066 static void register_cpu_props(DeviceState
*dev
)
1070 for (prop
= riscv_cpu_extensions
; prop
&& prop
->name
; prop
++) {
1071 qdev_property_add_static(dev
, prop
);
1075 static Property riscv_cpu_properties
[] = {
1076 DEFINE_PROP_BOOL("debug", RISCVCPU
, cfg
.debug
, true),
1078 DEFINE_PROP_UINT32("mvendorid", RISCVCPU
, cfg
.mvendorid
, 0),
1079 DEFINE_PROP_UINT64("marchid", RISCVCPU
, cfg
.marchid
, RISCV_CPU_MARCHID
),
1080 DEFINE_PROP_UINT64("mimpid", RISCVCPU
, cfg
.mimpid
, RISCV_CPU_MIMPID
),
1082 DEFINE_PROP_UINT64("resetvec", RISCVCPU
, cfg
.resetvec
, DEFAULT_RSTVEC
),
1084 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU
, cfg
.short_isa_string
, false),
1086 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU
, cfg
.rvv_ta_all_1s
, false),
1087 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU
, cfg
.rvv_ma_all_1s
, false),
1088 DEFINE_PROP_END_OF_LIST(),
1091 static gchar
*riscv_gdb_arch_name(CPUState
*cs
)
1093 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1094 CPURISCVState
*env
= &cpu
->env
;
1096 switch (riscv_cpu_mxl(env
)) {
1098 return g_strdup("riscv:rv32");
1101 return g_strdup("riscv:rv64");
1103 g_assert_not_reached();
1107 static const char *riscv_gdb_get_dynamic_xml(CPUState
*cs
, const char *xmlname
)
1109 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1111 if (strcmp(xmlname
, "riscv-csr.xml") == 0) {
1112 return cpu
->dyn_csr_xml
;
1113 } else if (strcmp(xmlname
, "riscv-vector.xml") == 0) {
1114 return cpu
->dyn_vreg_xml
;
1120 #ifndef CONFIG_USER_ONLY
1121 #include "hw/core/sysemu-cpu-ops.h"
1123 static const struct SysemuCPUOps riscv_sysemu_ops
= {
1124 .get_phys_page_debug
= riscv_cpu_get_phys_page_debug
,
1125 .write_elf64_note
= riscv_cpu_write_elf64_note
,
1126 .write_elf32_note
= riscv_cpu_write_elf32_note
,
1127 .legacy_vmsd
= &vmstate_riscv_cpu
,
1131 #include "hw/core/tcg-cpu-ops.h"
1133 static const struct TCGCPUOps riscv_tcg_ops
= {
1134 .initialize
= riscv_translate_init
,
1135 .synchronize_from_tb
= riscv_cpu_synchronize_from_tb
,
1137 #ifndef CONFIG_USER_ONLY
1138 .tlb_fill
= riscv_cpu_tlb_fill
,
1139 .cpu_exec_interrupt
= riscv_cpu_exec_interrupt
,
1140 .do_interrupt
= riscv_cpu_do_interrupt
,
1141 .do_transaction_failed
= riscv_cpu_do_transaction_failed
,
1142 .do_unaligned_access
= riscv_cpu_do_unaligned_access
,
1143 .debug_excp_handler
= riscv_cpu_debug_excp_handler
,
1144 .debug_check_breakpoint
= riscv_cpu_debug_check_breakpoint
,
1145 .debug_check_watchpoint
= riscv_cpu_debug_check_watchpoint
,
1146 #endif /* !CONFIG_USER_ONLY */
1149 static void riscv_cpu_class_init(ObjectClass
*c
, void *data
)
1151 RISCVCPUClass
*mcc
= RISCV_CPU_CLASS(c
);
1152 CPUClass
*cc
= CPU_CLASS(c
);
1153 DeviceClass
*dc
= DEVICE_CLASS(c
);
1155 device_class_set_parent_realize(dc
, riscv_cpu_realize
,
1156 &mcc
->parent_realize
);
1158 device_class_set_parent_reset(dc
, riscv_cpu_reset
, &mcc
->parent_reset
);
1160 cc
->class_by_name
= riscv_cpu_class_by_name
;
1161 cc
->has_work
= riscv_cpu_has_work
;
1162 cc
->dump_state
= riscv_cpu_dump_state
;
1163 cc
->set_pc
= riscv_cpu_set_pc
;
1164 cc
->gdb_read_register
= riscv_cpu_gdb_read_register
;
1165 cc
->gdb_write_register
= riscv_cpu_gdb_write_register
;
1166 cc
->gdb_num_core_regs
= 33;
1167 cc
->gdb_stop_before_watchpoint
= true;
1168 cc
->disas_set_info
= riscv_cpu_disas_set_info
;
1169 #ifndef CONFIG_USER_ONLY
1170 cc
->sysemu_ops
= &riscv_sysemu_ops
;
1172 cc
->gdb_arch_name
= riscv_gdb_arch_name
;
1173 cc
->gdb_get_dynamic_xml
= riscv_gdb_get_dynamic_xml
;
1174 cc
->tcg_ops
= &riscv_tcg_ops
;
1176 device_class_set_props(dc
, riscv_cpu_properties
);
1179 static void riscv_isa_string_ext(RISCVCPU
*cpu
, char **isa_str
, int max_str_len
)
1181 char *old
= *isa_str
;
1182 char *new = *isa_str
;
1185 for (i
= 0; i
< ARRAY_SIZE(isa_edata_arr
); i
++) {
1186 if (isa_edata_arr
[i
].multi_letter
&&
1187 isa_ext_is_enabled(cpu
, &isa_edata_arr
[i
])) {
1188 new = g_strconcat(old
, "_", isa_edata_arr
[i
].name
, NULL
);
1197 char *riscv_isa_string(RISCVCPU
*cpu
)
1200 const size_t maxlen
= sizeof("rv128") + sizeof(riscv_single_letter_exts
);
1201 char *isa_str
= g_new(char, maxlen
);
1202 char *p
= isa_str
+ snprintf(isa_str
, maxlen
, "rv%d", TARGET_LONG_BITS
);
1203 for (i
= 0; i
< sizeof(riscv_single_letter_exts
) - 1; i
++) {
1204 if (cpu
->env
.misa_ext
& RV(riscv_single_letter_exts
[i
])) {
1205 *p
++ = qemu_tolower(riscv_single_letter_exts
[i
]);
1209 if (!cpu
->cfg
.short_isa_string
) {
1210 riscv_isa_string_ext(cpu
, &isa_str
, maxlen
);
1215 static gint
riscv_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1217 ObjectClass
*class_a
= (ObjectClass
*)a
;
1218 ObjectClass
*class_b
= (ObjectClass
*)b
;
1219 const char *name_a
, *name_b
;
1221 name_a
= object_class_get_name(class_a
);
1222 name_b
= object_class_get_name(class_b
);
1223 return strcmp(name_a
, name_b
);
1226 static void riscv_cpu_list_entry(gpointer data
, gpointer user_data
)
1228 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
1229 int len
= strlen(typename
) - strlen(RISCV_CPU_TYPE_SUFFIX
);
1231 qemu_printf("%.*s\n", len
, typename
);
1234 void riscv_cpu_list(void)
1238 list
= object_class_get_list(TYPE_RISCV_CPU
, false);
1239 list
= g_slist_sort(list
, riscv_cpu_list_compare
);
1240 g_slist_foreach(list
, riscv_cpu_list_entry
, NULL
);
1244 #define DEFINE_CPU(type_name, initfn) \
1246 .name = type_name, \
1247 .parent = TYPE_RISCV_CPU, \
1248 .instance_init = initfn \
1251 static const TypeInfo riscv_cpu_type_infos
[] = {
1253 .name
= TYPE_RISCV_CPU
,
1255 .instance_size
= sizeof(RISCVCPU
),
1256 .instance_align
= __alignof__(RISCVCPU
),
1257 .instance_init
= riscv_cpu_init
,
1259 .class_size
= sizeof(RISCVCPUClass
),
1260 .class_init
= riscv_cpu_class_init
,
1262 DEFINE_CPU(TYPE_RISCV_CPU_ANY
, riscv_any_cpu_init
),
1263 #if defined(CONFIG_KVM)
1264 DEFINE_CPU(TYPE_RISCV_CPU_HOST
, riscv_host_cpu_init
),
1266 #if defined(TARGET_RISCV32)
1267 DEFINE_CPU(TYPE_RISCV_CPU_BASE32
, rv32_base_cpu_init
),
1268 DEFINE_CPU(TYPE_RISCV_CPU_IBEX
, rv32_ibex_cpu_init
),
1269 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31
, rv32_sifive_e_cpu_init
),
1270 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34
, rv32_imafcu_nommu_cpu_init
),
1271 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34
, rv32_sifive_u_cpu_init
),
1272 #elif defined(TARGET_RISCV64)
1273 DEFINE_CPU(TYPE_RISCV_CPU_BASE64
, rv64_base_cpu_init
),
1274 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51
, rv64_sifive_e_cpu_init
),
1275 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54
, rv64_sifive_u_cpu_init
),
1276 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C
, rv64_sifive_u_cpu_init
),
1277 DEFINE_CPU(TYPE_RISCV_CPU_BASE128
, rv128_base_cpu_init
),
1281 DEFINE_TYPES(riscv_cpu_type_infos
)