4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
25 #include "internals.h"
26 #include "exec/exec-all.h"
27 #include "qapi/error.h"
28 #include "qemu/error-report.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "fpu/softfloat-helpers.h"
32 #include "sysemu/kvm.h"
33 #include "kvm_riscv.h"
35 /* RISC-V CPU definitions */
37 static const char riscv_single_letter_exts
[] = "IEMAFDQCPVH";
44 const char * const riscv_int_regnames
[] = {
45 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
46 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
47 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
48 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
49 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
52 const char * const riscv_int_regnamesh
[] = {
53 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
54 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
55 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
56 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
57 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
58 "x30h/t5h", "x31h/t6h"
61 const char * const riscv_fpr_regnames
[] = {
62 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
63 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
64 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
65 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
66 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
67 "f30/ft10", "f31/ft11"
70 static const char * const riscv_excp_names
[] = {
73 "illegal_instruction",
91 "guest_exec_page_fault",
92 "guest_load_page_fault",
94 "guest_store_page_fault",
97 static const char * const riscv_intr_names
[] = {
116 const char *riscv_cpu_get_trap_name(target_ulong cause
, bool async
)
119 return (cause
< ARRAY_SIZE(riscv_intr_names
)) ?
120 riscv_intr_names
[cause
] : "(unknown)";
122 return (cause
< ARRAY_SIZE(riscv_excp_names
)) ?
123 riscv_excp_names
[cause
] : "(unknown)";
127 static void set_misa(CPURISCVState
*env
, RISCVMXL mxl
, uint32_t ext
)
129 env
->misa_mxl_max
= env
->misa_mxl
= mxl
;
130 env
->misa_ext_mask
= env
->misa_ext
= ext
;
133 static void set_priv_version(CPURISCVState
*env
, int priv_ver
)
135 env
->priv_ver
= priv_ver
;
138 static void set_vext_version(CPURISCVState
*env
, int vext_ver
)
140 env
->vext_ver
= vext_ver
;
143 static void set_resetvec(CPURISCVState
*env
, target_ulong resetvec
)
145 #ifndef CONFIG_USER_ONLY
146 env
->resetvec
= resetvec
;
150 static void riscv_any_cpu_init(Object
*obj
)
152 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
153 #if defined(TARGET_RISCV32)
154 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
155 #elif defined(TARGET_RISCV64)
156 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
158 set_priv_version(env
, PRIV_VERSION_1_12_0
);
161 #if defined(TARGET_RISCV64)
162 static void rv64_base_cpu_init(Object
*obj
)
164 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
165 /* We set this in the realise function */
166 set_misa(env
, MXL_RV64
, 0);
169 static void rv64_sifive_u_cpu_init(Object
*obj
)
171 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
172 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
173 set_priv_version(env
, PRIV_VERSION_1_10_0
);
176 static void rv64_sifive_e_cpu_init(Object
*obj
)
178 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
179 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVC
| RVU
);
180 set_priv_version(env
, PRIV_VERSION_1_10_0
);
181 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
184 static void rv128_base_cpu_init(Object
*obj
)
186 if (qemu_tcg_mttcg_enabled()) {
187 /* Missing 128-bit aligned atomics */
188 error_report("128-bit RISC-V currently does not work with Multi "
189 "Threaded TCG. Please use: -accel tcg,thread=single");
192 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
193 /* We set this in the realise function */
194 set_misa(env
, MXL_RV128
, 0);
197 static void rv32_base_cpu_init(Object
*obj
)
199 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
200 /* We set this in the realise function */
201 set_misa(env
, MXL_RV32
, 0);
204 static void rv32_sifive_u_cpu_init(Object
*obj
)
206 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
207 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
208 set_priv_version(env
, PRIV_VERSION_1_10_0
);
211 static void rv32_sifive_e_cpu_init(Object
*obj
)
213 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
214 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVC
| RVU
);
215 set_priv_version(env
, PRIV_VERSION_1_10_0
);
216 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
219 static void rv32_ibex_cpu_init(Object
*obj
)
221 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
222 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVC
| RVU
);
223 set_priv_version(env
, PRIV_VERSION_1_10_0
);
224 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
225 qdev_prop_set_bit(DEVICE(obj
), "x-epmp", true);
228 static void rv32_imafcu_nommu_cpu_init(Object
*obj
)
230 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
231 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVC
| RVU
);
232 set_priv_version(env
, PRIV_VERSION_1_10_0
);
233 set_resetvec(env
, DEFAULT_RSTVEC
);
234 qdev_prop_set_bit(DEVICE(obj
), "mmu", false);
238 #if defined(CONFIG_KVM)
239 static void riscv_host_cpu_init(Object
*obj
)
241 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
242 #if defined(TARGET_RISCV32)
243 set_misa(env
, MXL_RV32
, 0);
244 #elif defined(TARGET_RISCV64)
245 set_misa(env
, MXL_RV64
, 0);
250 static ObjectClass
*riscv_cpu_class_by_name(const char *cpu_model
)
256 cpuname
= g_strsplit(cpu_model
, ",", 1);
257 typename
= g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname
[0]);
258 oc
= object_class_by_name(typename
);
261 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_RISCV_CPU
) ||
262 object_class_is_abstract(oc
)) {
268 static void riscv_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
270 RISCVCPU
*cpu
= RISCV_CPU(cs
);
271 CPURISCVState
*env
= &cpu
->env
;
274 #if !defined(CONFIG_USER_ONLY)
275 if (riscv_has_ext(env
, RVH
)) {
276 qemu_fprintf(f
, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env
));
279 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "pc ", env
->pc
);
280 #ifndef CONFIG_USER_ONLY
282 static const int dump_csrs
[] = {
319 for (int i
= 0; i
< ARRAY_SIZE(dump_csrs
); ++i
) {
320 int csrno
= dump_csrs
[i
];
321 target_ulong val
= 0;
322 RISCVException res
= riscv_csrrw_debug(env
, csrno
, &val
, 0, 0);
325 * Rely on the smode, hmode, etc, predicates within csr.c
326 * to do the filtering of the registers that are present.
328 if (res
== RISCV_EXCP_NONE
) {
329 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
"\n",
330 csr_ops
[csrno
].name
, val
);
336 for (i
= 0; i
< 32; i
++) {
337 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
,
338 riscv_int_regnames
[i
], env
->gpr
[i
]);
340 qemu_fprintf(f
, "\n");
343 if (flags
& CPU_DUMP_FPU
) {
344 for (i
= 0; i
< 32; i
++) {
345 qemu_fprintf(f
, " %-8s %016" PRIx64
,
346 riscv_fpr_regnames
[i
], env
->fpr
[i
]);
348 qemu_fprintf(f
, "\n");
354 static void riscv_cpu_set_pc(CPUState
*cs
, vaddr value
)
356 RISCVCPU
*cpu
= RISCV_CPU(cs
);
357 CPURISCVState
*env
= &cpu
->env
;
359 if (env
->xl
== MXL_RV32
) {
360 env
->pc
= (int32_t)value
;
366 static void riscv_cpu_synchronize_from_tb(CPUState
*cs
,
367 const TranslationBlock
*tb
)
369 RISCVCPU
*cpu
= RISCV_CPU(cs
);
370 CPURISCVState
*env
= &cpu
->env
;
371 RISCVMXL xl
= FIELD_EX32(tb
->flags
, TB_FLAGS
, XL
);
373 if (xl
== MXL_RV32
) {
374 env
->pc
= (int32_t)tb
->pc
;
380 static bool riscv_cpu_has_work(CPUState
*cs
)
382 #ifndef CONFIG_USER_ONLY
383 RISCVCPU
*cpu
= RISCV_CPU(cs
);
384 CPURISCVState
*env
= &cpu
->env
;
386 * Definition of the WFI instruction requires it to ignore the privilege
387 * mode and delegation registers, but respect individual enables
389 return (env
->mip
& env
->mie
) != 0;
395 void restore_state_to_opc(CPURISCVState
*env
, TranslationBlock
*tb
,
398 RISCVMXL xl
= FIELD_EX32(tb
->flags
, TB_FLAGS
, XL
);
399 if (xl
== MXL_RV32
) {
400 env
->pc
= (int32_t)data
[0];
406 static void riscv_cpu_reset(DeviceState
*dev
)
408 #ifndef CONFIG_USER_ONLY
412 CPUState
*cs
= CPU(dev
);
413 RISCVCPU
*cpu
= RISCV_CPU(cs
);
414 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(cpu
);
415 CPURISCVState
*env
= &cpu
->env
;
417 mcc
->parent_reset(dev
);
418 #ifndef CONFIG_USER_ONLY
419 env
->misa_mxl
= env
->misa_mxl_max
;
421 env
->mstatus
&= ~(MSTATUS_MIE
| MSTATUS_MPRV
);
422 if (env
->misa_mxl
> MXL_RV32
) {
424 * The reset status of SXL/UXL is undefined, but mstatus is WARL
425 * and we must ensure that the value after init is valid for read.
427 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_SXL
, env
->misa_mxl
);
428 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_UXL
, env
->misa_mxl
);
429 if (riscv_has_ext(env
, RVH
)) {
430 env
->vsstatus
= set_field(env
->vsstatus
,
431 MSTATUS64_SXL
, env
->misa_mxl
);
432 env
->vsstatus
= set_field(env
->vsstatus
,
433 MSTATUS64_UXL
, env
->misa_mxl
);
434 env
->mstatus_hs
= set_field(env
->mstatus_hs
,
435 MSTATUS64_SXL
, env
->misa_mxl
);
436 env
->mstatus_hs
= set_field(env
->mstatus_hs
,
437 MSTATUS64_UXL
, env
->misa_mxl
);
441 env
->miclaim
= MIP_SGEIP
;
442 env
->pc
= env
->resetvec
;
443 env
->two_stage_lookup
= false;
445 /* Initialized default priorities of local interrupts. */
446 for (i
= 0; i
< ARRAY_SIZE(env
->miprio
); i
++) {
447 iprio
= riscv_cpu_default_priority(i
);
448 env
->miprio
[i
] = (i
== IRQ_M_EXT
) ? 0 : iprio
;
449 env
->siprio
[i
] = (i
== IRQ_S_EXT
) ? 0 : iprio
;
453 while (!riscv_cpu_hviprio_index2irq(i
, &irq
, &rdzero
)) {
455 env
->hviprio
[irq
] = env
->miprio
[irq
];
459 /* mmte is supposed to have pm.current hardwired to 1 */
460 env
->mmte
|= (PM_EXT_INITIAL
| MMTE_M_PM_CURRENT
);
462 env
->xl
= riscv_cpu_mxl(env
);
463 riscv_cpu_update_mask(env
);
464 cs
->exception_index
= RISCV_EXCP_NONE
;
466 set_default_nan_mode(1, &env
->fp_status
);
468 #ifndef CONFIG_USER_ONLY
470 kvm_riscv_reset_vcpu(cpu
);
475 static void riscv_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
477 RISCVCPU
*cpu
= RISCV_CPU(s
);
479 switch (riscv_cpu_mxl(&cpu
->env
)) {
481 info
->print_insn
= print_insn_riscv32
;
484 info
->print_insn
= print_insn_riscv64
;
487 info
->print_insn
= print_insn_riscv128
;
490 g_assert_not_reached();
494 static void riscv_cpu_realize(DeviceState
*dev
, Error
**errp
)
496 CPUState
*cs
= CPU(dev
);
497 RISCVCPU
*cpu
= RISCV_CPU(dev
);
498 CPURISCVState
*env
= &cpu
->env
;
499 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(dev
);
500 CPUClass
*cc
= CPU_CLASS(mcc
);
501 int priv_version
= 0;
502 Error
*local_err
= NULL
;
504 cpu_exec_realizefn(cs
, &local_err
);
505 if (local_err
!= NULL
) {
506 error_propagate(errp
, local_err
);
510 if (cpu
->cfg
.priv_spec
) {
511 if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.12.0")) {
512 priv_version
= PRIV_VERSION_1_12_0
;
513 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.11.0")) {
514 priv_version
= PRIV_VERSION_1_11_0
;
515 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.10.0")) {
516 priv_version
= PRIV_VERSION_1_10_0
;
519 "Unsupported privilege spec version '%s'",
526 set_priv_version(env
, priv_version
);
527 } else if (!env
->priv_ver
) {
528 set_priv_version(env
, PRIV_VERSION_1_12_0
);
532 riscv_set_feature(env
, RISCV_FEATURE_MMU
);
536 riscv_set_feature(env
, RISCV_FEATURE_PMP
);
539 * Enhanced PMP should only be available
540 * on harts with PMP support
543 riscv_set_feature(env
, RISCV_FEATURE_EPMP
);
548 riscv_set_feature(env
, RISCV_FEATURE_AIA
);
551 set_resetvec(env
, cpu
->cfg
.resetvec
);
553 /* Validate that MISA_MXL is set properly. */
554 switch (env
->misa_mxl_max
) {
555 #ifdef TARGET_RISCV64
558 cc
->gdb_core_xml_file
= "riscv-64bit-cpu.xml";
562 cc
->gdb_core_xml_file
= "riscv-32bit-cpu.xml";
565 g_assert_not_reached();
567 assert(env
->misa_mxl_max
== env
->misa_mxl
);
569 /* If only MISA_EXT is unset for misa, then set it from properties */
570 if (env
->misa_ext
== 0) {
573 /* Do some ISA extension error checking */
574 if (cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_e
) {
576 "I and E extensions are incompatible");
580 if (!cpu
->cfg
.ext_i
&& !cpu
->cfg
.ext_e
) {
582 "Either I or E extension must be set");
586 if (cpu
->cfg
.ext_g
&& !(cpu
->cfg
.ext_i
& cpu
->cfg
.ext_m
&
587 cpu
->cfg
.ext_a
& cpu
->cfg
.ext_f
&
589 warn_report("Setting G will also set IMAFD");
590 cpu
->cfg
.ext_i
= true;
591 cpu
->cfg
.ext_m
= true;
592 cpu
->cfg
.ext_a
= true;
593 cpu
->cfg
.ext_f
= true;
594 cpu
->cfg
.ext_d
= true;
597 if (cpu
->cfg
.ext_zdinx
|| cpu
->cfg
.ext_zhinx
||
598 cpu
->cfg
.ext_zhinxmin
) {
599 cpu
->cfg
.ext_zfinx
= true;
602 /* Set the ISA extensions, checks should have happened above */
603 if (cpu
->cfg
.ext_i
) {
606 if (cpu
->cfg
.ext_e
) {
609 if (cpu
->cfg
.ext_m
) {
612 if (cpu
->cfg
.ext_a
) {
615 if (cpu
->cfg
.ext_f
) {
618 if (cpu
->cfg
.ext_d
) {
621 if (cpu
->cfg
.ext_c
) {
624 if (cpu
->cfg
.ext_s
) {
627 if (cpu
->cfg
.ext_u
) {
630 if (cpu
->cfg
.ext_h
) {
633 if (cpu
->cfg
.ext_v
) {
634 int vext_version
= VEXT_VERSION_1_00_0
;
636 if (!is_power_of_2(cpu
->cfg
.vlen
)) {
638 "Vector extension VLEN must be power of 2");
641 if (cpu
->cfg
.vlen
> RV_VLEN_MAX
|| cpu
->cfg
.vlen
< 128) {
643 "Vector extension implementation only supports VLEN "
644 "in the range [128, %d]", RV_VLEN_MAX
);
647 if (!is_power_of_2(cpu
->cfg
.elen
)) {
649 "Vector extension ELEN must be power of 2");
652 if (cpu
->cfg
.elen
> 64 || cpu
->cfg
.vlen
< 8) {
654 "Vector extension implementation only supports ELEN "
655 "in the range [8, 64]");
658 if (cpu
->cfg
.vext_spec
) {
659 if (!g_strcmp0(cpu
->cfg
.vext_spec
, "v1.0")) {
660 vext_version
= VEXT_VERSION_1_00_0
;
663 "Unsupported vector spec version '%s'",
668 qemu_log("vector version is not specified, "
669 "use the default value v1.0\n");
671 set_vext_version(env
, vext_version
);
673 if ((cpu
->cfg
.ext_zve32f
|| cpu
->cfg
.ext_zve64f
) && !cpu
->cfg
.ext_f
) {
674 error_setg(errp
, "Zve32f/Zve64f extension depends upon RVF.");
677 if (cpu
->cfg
.ext_j
) {
680 if (cpu
->cfg
.ext_zfinx
&& ((ext
& (RVF
| RVD
)) || cpu
->cfg
.ext_zfh
||
681 cpu
->cfg
.ext_zfhmin
)) {
683 "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh',"
688 set_misa(env
, env
->misa_mxl
, ext
);
691 riscv_cpu_register_gdb_regs_for_features(cs
);
696 mcc
->parent_realize(dev
, errp
);
699 #ifndef CONFIG_USER_ONLY
700 static void riscv_cpu_set_irq(void *opaque
, int irq
, int level
)
702 RISCVCPU
*cpu
= RISCV_CPU(opaque
);
703 CPURISCVState
*env
= &cpu
->env
;
705 if (irq
< IRQ_LOCAL_MAX
) {
719 kvm_riscv_set_irq(cpu
, irq
, level
);
721 riscv_cpu_update_mip(cpu
, 1 << irq
, BOOL_TO_MASK(level
));
726 kvm_riscv_set_irq(cpu
, irq
, level
);
728 env
->external_seip
= level
;
729 riscv_cpu_update_mip(cpu
, 1 << irq
,
730 BOOL_TO_MASK(level
| env
->software_seip
));
734 g_assert_not_reached();
736 } else if (irq
< (IRQ_LOCAL_MAX
+ IRQ_LOCAL_GUEST_MAX
)) {
737 /* Require H-extension for handling guest local interrupts */
738 if (!riscv_has_ext(env
, RVH
)) {
739 g_assert_not_reached();
742 /* Compute bit position in HGEIP CSR */
743 irq
= irq
- IRQ_LOCAL_MAX
+ 1;
744 if (env
->geilen
< irq
) {
745 g_assert_not_reached();
748 /* Update HGEIP CSR */
749 env
->hgeip
&= ~((target_ulong
)1 << irq
);
751 env
->hgeip
|= (target_ulong
)1 << irq
;
754 /* Update mip.SGEIP bit */
755 riscv_cpu_update_mip(cpu
, MIP_SGEIP
,
756 BOOL_TO_MASK(!!(env
->hgeie
& env
->hgeip
)));
758 g_assert_not_reached();
761 #endif /* CONFIG_USER_ONLY */
763 static void riscv_cpu_init(Object
*obj
)
765 RISCVCPU
*cpu
= RISCV_CPU(obj
);
767 cpu_set_cpustate_pointers(cpu
);
769 #ifndef CONFIG_USER_ONLY
770 qdev_init_gpio_in(DEVICE(cpu
), riscv_cpu_set_irq
,
771 IRQ_LOCAL_MAX
+ IRQ_LOCAL_GUEST_MAX
);
772 #endif /* CONFIG_USER_ONLY */
775 static Property riscv_cpu_properties
[] = {
776 /* Defaults for standard extensions */
777 DEFINE_PROP_BOOL("i", RISCVCPU
, cfg
.ext_i
, true),
778 DEFINE_PROP_BOOL("e", RISCVCPU
, cfg
.ext_e
, false),
779 DEFINE_PROP_BOOL("g", RISCVCPU
, cfg
.ext_g
, true),
780 DEFINE_PROP_BOOL("m", RISCVCPU
, cfg
.ext_m
, true),
781 DEFINE_PROP_BOOL("a", RISCVCPU
, cfg
.ext_a
, true),
782 DEFINE_PROP_BOOL("f", RISCVCPU
, cfg
.ext_f
, true),
783 DEFINE_PROP_BOOL("d", RISCVCPU
, cfg
.ext_d
, true),
784 DEFINE_PROP_BOOL("c", RISCVCPU
, cfg
.ext_c
, true),
785 DEFINE_PROP_BOOL("s", RISCVCPU
, cfg
.ext_s
, true),
786 DEFINE_PROP_BOOL("u", RISCVCPU
, cfg
.ext_u
, true),
787 DEFINE_PROP_BOOL("v", RISCVCPU
, cfg
.ext_v
, false),
788 DEFINE_PROP_BOOL("h", RISCVCPU
, cfg
.ext_h
, true),
789 DEFINE_PROP_BOOL("Counters", RISCVCPU
, cfg
.ext_counters
, true),
790 DEFINE_PROP_BOOL("Zifencei", RISCVCPU
, cfg
.ext_ifencei
, true),
791 DEFINE_PROP_BOOL("Zicsr", RISCVCPU
, cfg
.ext_icsr
, true),
792 DEFINE_PROP_BOOL("Zfh", RISCVCPU
, cfg
.ext_zfh
, false),
793 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU
, cfg
.ext_zfhmin
, false),
794 DEFINE_PROP_BOOL("Zve32f", RISCVCPU
, cfg
.ext_zve32f
, false),
795 DEFINE_PROP_BOOL("Zve64f", RISCVCPU
, cfg
.ext_zve64f
, false),
796 DEFINE_PROP_BOOL("mmu", RISCVCPU
, cfg
.mmu
, true),
797 DEFINE_PROP_BOOL("pmp", RISCVCPU
, cfg
.pmp
, true),
799 DEFINE_PROP_STRING("priv_spec", RISCVCPU
, cfg
.priv_spec
),
800 DEFINE_PROP_STRING("vext_spec", RISCVCPU
, cfg
.vext_spec
),
801 DEFINE_PROP_UINT16("vlen", RISCVCPU
, cfg
.vlen
, 128),
802 DEFINE_PROP_UINT16("elen", RISCVCPU
, cfg
.elen
, 64),
804 DEFINE_PROP_BOOL("svinval", RISCVCPU
, cfg
.ext_svinval
, false),
805 DEFINE_PROP_BOOL("svnapot", RISCVCPU
, cfg
.ext_svnapot
, false),
806 DEFINE_PROP_BOOL("svpbmt", RISCVCPU
, cfg
.ext_svpbmt
, false),
808 DEFINE_PROP_BOOL("zba", RISCVCPU
, cfg
.ext_zba
, true),
809 DEFINE_PROP_BOOL("zbb", RISCVCPU
, cfg
.ext_zbb
, true),
810 DEFINE_PROP_BOOL("zbc", RISCVCPU
, cfg
.ext_zbc
, true),
811 DEFINE_PROP_BOOL("zbs", RISCVCPU
, cfg
.ext_zbs
, true),
813 DEFINE_PROP_BOOL("zdinx", RISCVCPU
, cfg
.ext_zdinx
, false),
814 DEFINE_PROP_BOOL("zfinx", RISCVCPU
, cfg
.ext_zfinx
, false),
815 DEFINE_PROP_BOOL("zhinx", RISCVCPU
, cfg
.ext_zhinx
, false),
816 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU
, cfg
.ext_zhinxmin
, false),
818 /* Vendor-specific custom extensions */
819 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU
, cfg
.ext_XVentanaCondOps
, false),
821 /* These are experimental so mark with 'x-' */
822 DEFINE_PROP_BOOL("x-j", RISCVCPU
, cfg
.ext_j
, false),
824 DEFINE_PROP_BOOL("x-epmp", RISCVCPU
, cfg
.epmp
, false),
825 DEFINE_PROP_BOOL("x-aia", RISCVCPU
, cfg
.aia
, false),
827 DEFINE_PROP_UINT64("resetvec", RISCVCPU
, cfg
.resetvec
, DEFAULT_RSTVEC
),
828 DEFINE_PROP_END_OF_LIST(),
831 static gchar
*riscv_gdb_arch_name(CPUState
*cs
)
833 RISCVCPU
*cpu
= RISCV_CPU(cs
);
834 CPURISCVState
*env
= &cpu
->env
;
836 switch (riscv_cpu_mxl(env
)) {
838 return g_strdup("riscv:rv32");
841 return g_strdup("riscv:rv64");
843 g_assert_not_reached();
847 static const char *riscv_gdb_get_dynamic_xml(CPUState
*cs
, const char *xmlname
)
849 RISCVCPU
*cpu
= RISCV_CPU(cs
);
851 if (strcmp(xmlname
, "riscv-csr.xml") == 0) {
852 return cpu
->dyn_csr_xml
;
853 } else if (strcmp(xmlname
, "riscv-vector.xml") == 0) {
854 return cpu
->dyn_vreg_xml
;
860 #ifndef CONFIG_USER_ONLY
861 #include "hw/core/sysemu-cpu-ops.h"
863 static const struct SysemuCPUOps riscv_sysemu_ops
= {
864 .get_phys_page_debug
= riscv_cpu_get_phys_page_debug
,
865 .write_elf64_note
= riscv_cpu_write_elf64_note
,
866 .write_elf32_note
= riscv_cpu_write_elf32_note
,
867 .legacy_vmsd
= &vmstate_riscv_cpu
,
871 #include "hw/core/tcg-cpu-ops.h"
873 static const struct TCGCPUOps riscv_tcg_ops
= {
874 .initialize
= riscv_translate_init
,
875 .synchronize_from_tb
= riscv_cpu_synchronize_from_tb
,
877 #ifndef CONFIG_USER_ONLY
878 .tlb_fill
= riscv_cpu_tlb_fill
,
879 .cpu_exec_interrupt
= riscv_cpu_exec_interrupt
,
880 .do_interrupt
= riscv_cpu_do_interrupt
,
881 .do_transaction_failed
= riscv_cpu_do_transaction_failed
,
882 .do_unaligned_access
= riscv_cpu_do_unaligned_access
,
883 #endif /* !CONFIG_USER_ONLY */
886 static void riscv_cpu_class_init(ObjectClass
*c
, void *data
)
888 RISCVCPUClass
*mcc
= RISCV_CPU_CLASS(c
);
889 CPUClass
*cc
= CPU_CLASS(c
);
890 DeviceClass
*dc
= DEVICE_CLASS(c
);
892 device_class_set_parent_realize(dc
, riscv_cpu_realize
,
893 &mcc
->parent_realize
);
895 device_class_set_parent_reset(dc
, riscv_cpu_reset
, &mcc
->parent_reset
);
897 cc
->class_by_name
= riscv_cpu_class_by_name
;
898 cc
->has_work
= riscv_cpu_has_work
;
899 cc
->dump_state
= riscv_cpu_dump_state
;
900 cc
->set_pc
= riscv_cpu_set_pc
;
901 cc
->gdb_read_register
= riscv_cpu_gdb_read_register
;
902 cc
->gdb_write_register
= riscv_cpu_gdb_write_register
;
903 cc
->gdb_num_core_regs
= 33;
904 cc
->gdb_stop_before_watchpoint
= true;
905 cc
->disas_set_info
= riscv_cpu_disas_set_info
;
906 #ifndef CONFIG_USER_ONLY
907 cc
->sysemu_ops
= &riscv_sysemu_ops
;
909 cc
->gdb_arch_name
= riscv_gdb_arch_name
;
910 cc
->gdb_get_dynamic_xml
= riscv_gdb_get_dynamic_xml
;
911 cc
->tcg_ops
= &riscv_tcg_ops
;
913 device_class_set_props(dc
, riscv_cpu_properties
);
916 #define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
918 static void riscv_isa_string_ext(RISCVCPU
*cpu
, char **isa_str
, int max_str_len
)
920 char *old
= *isa_str
;
921 char *new = *isa_str
;
925 * Here are the ordering rules of extension naming defined by RISC-V
927 * 1. All extensions should be separated from other multi-letter extensions
929 * 2. The first letter following the 'Z' conventionally indicates the most
930 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
931 * If multiple 'Z' extensions are named, they should be ordered first
932 * by category, then alphabetically within a category.
933 * 3. Standard supervisor-level extensions (starts with 'S') should be
934 * listed after standard unprivileged extensions. If multiple
935 * supervisor-level extensions are listed, they should be ordered
937 * 4. Non-standard extensions (starts with 'X') must be listed after all
938 * standard extensions. They must be separated from other multi-letter
939 * extensions by an underscore.
941 struct isa_ext_data isa_edata_arr
[] = {
942 ISA_EDATA_ENTRY(zfh
, ext_zfh
),
943 ISA_EDATA_ENTRY(zfhmin
, ext_zfhmin
),
944 ISA_EDATA_ENTRY(zfinx
, ext_zfinx
),
945 ISA_EDATA_ENTRY(zhinx
, ext_zhinx
),
946 ISA_EDATA_ENTRY(zhinxmin
, ext_zhinxmin
),
947 ISA_EDATA_ENTRY(zdinx
, ext_zdinx
),
948 ISA_EDATA_ENTRY(zba
, ext_zba
),
949 ISA_EDATA_ENTRY(zbb
, ext_zbb
),
950 ISA_EDATA_ENTRY(zbc
, ext_zbc
),
951 ISA_EDATA_ENTRY(zbs
, ext_zbs
),
952 ISA_EDATA_ENTRY(zve32f
, ext_zve32f
),
953 ISA_EDATA_ENTRY(zve64f
, ext_zve64f
),
954 ISA_EDATA_ENTRY(svinval
, ext_svinval
),
955 ISA_EDATA_ENTRY(svnapot
, ext_svnapot
),
956 ISA_EDATA_ENTRY(svpbmt
, ext_svpbmt
),
959 for (i
= 0; i
< ARRAY_SIZE(isa_edata_arr
); i
++) {
960 if (isa_edata_arr
[i
].enabled
) {
961 new = g_strconcat(old
, "_", isa_edata_arr
[i
].name
, NULL
);
970 char *riscv_isa_string(RISCVCPU
*cpu
)
973 const size_t maxlen
= sizeof("rv128") + sizeof(riscv_single_letter_exts
);
974 char *isa_str
= g_new(char, maxlen
);
975 char *p
= isa_str
+ snprintf(isa_str
, maxlen
, "rv%d", TARGET_LONG_BITS
);
976 for (i
= 0; i
< sizeof(riscv_single_letter_exts
) - 1; i
++) {
977 if (cpu
->env
.misa_ext
& RV(riscv_single_letter_exts
[i
])) {
978 *p
++ = qemu_tolower(riscv_single_letter_exts
[i
]);
982 riscv_isa_string_ext(cpu
, &isa_str
, maxlen
);
986 static gint
riscv_cpu_list_compare(gconstpointer a
, gconstpointer b
)
988 ObjectClass
*class_a
= (ObjectClass
*)a
;
989 ObjectClass
*class_b
= (ObjectClass
*)b
;
990 const char *name_a
, *name_b
;
992 name_a
= object_class_get_name(class_a
);
993 name_b
= object_class_get_name(class_b
);
994 return strcmp(name_a
, name_b
);
997 static void riscv_cpu_list_entry(gpointer data
, gpointer user_data
)
999 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
1000 int len
= strlen(typename
) - strlen(RISCV_CPU_TYPE_SUFFIX
);
1002 qemu_printf("%.*s\n", len
, typename
);
1005 void riscv_cpu_list(void)
1009 list
= object_class_get_list(TYPE_RISCV_CPU
, false);
1010 list
= g_slist_sort(list
, riscv_cpu_list_compare
);
1011 g_slist_foreach(list
, riscv_cpu_list_entry
, NULL
);
1015 #define DEFINE_CPU(type_name, initfn) \
1017 .name = type_name, \
1018 .parent = TYPE_RISCV_CPU, \
1019 .instance_init = initfn \
1022 static const TypeInfo riscv_cpu_type_infos
[] = {
1024 .name
= TYPE_RISCV_CPU
,
1026 .instance_size
= sizeof(RISCVCPU
),
1027 .instance_align
= __alignof__(RISCVCPU
),
1028 .instance_init
= riscv_cpu_init
,
1030 .class_size
= sizeof(RISCVCPUClass
),
1031 .class_init
= riscv_cpu_class_init
,
1033 DEFINE_CPU(TYPE_RISCV_CPU_ANY
, riscv_any_cpu_init
),
1034 #if defined(CONFIG_KVM)
1035 DEFINE_CPU(TYPE_RISCV_CPU_HOST
, riscv_host_cpu_init
),
1037 #if defined(TARGET_RISCV32)
1038 DEFINE_CPU(TYPE_RISCV_CPU_BASE32
, rv32_base_cpu_init
),
1039 DEFINE_CPU(TYPE_RISCV_CPU_IBEX
, rv32_ibex_cpu_init
),
1040 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31
, rv32_sifive_e_cpu_init
),
1041 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34
, rv32_imafcu_nommu_cpu_init
),
1042 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34
, rv32_sifive_u_cpu_init
),
1043 #elif defined(TARGET_RISCV64)
1044 DEFINE_CPU(TYPE_RISCV_CPU_BASE64
, rv64_base_cpu_init
),
1045 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51
, rv64_sifive_e_cpu_init
),
1046 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54
, rv64_sifive_u_cpu_init
),
1047 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C
, rv64_sifive_u_cpu_init
),
1048 DEFINE_CPU(TYPE_RISCV_CPU_BASE128
, rv128_base_cpu_init
),
1052 DEFINE_TYPES(riscv_cpu_type_infos
)