4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
25 #include "exec/exec-all.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
30 #include "fpu/softfloat-helpers.h"
32 /* RISC-V CPU definitions */
34 static const char riscv_exts
[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
36 const char * const riscv_int_regnames
[] = {
37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
41 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
44 const char * const riscv_fpr_regnames
[] = {
45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
50 "f30/ft10", "f31/ft11"
53 const char * const riscv_excp_names
[] = {
56 "illegal_instruction",
74 "guest_exec_page_fault",
75 "guest_load_page_fault",
77 "guest_store_page_fault"
80 const char * const riscv_intr_names
[] = {
99 static void set_misa(CPURISCVState
*env
, target_ulong misa
)
101 env
->misa_mask
= env
->misa
= misa
;
104 static void set_priv_version(CPURISCVState
*env
, int priv_ver
)
106 env
->priv_ver
= priv_ver
;
109 static void set_feature(CPURISCVState
*env
, int feature
)
111 env
->features
|= (1ULL << feature
);
114 static void set_resetvec(CPURISCVState
*env
, int resetvec
)
116 #ifndef CONFIG_USER_ONLY
117 env
->resetvec
= resetvec
;
121 static void riscv_any_cpu_init(Object
*obj
)
123 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
124 set_misa(env
, RVXLEN
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
125 set_priv_version(env
, PRIV_VERSION_1_11_0
);
126 set_resetvec(env
, DEFAULT_RSTVEC
);
129 #if defined(TARGET_RISCV32)
131 static void riscv_base32_cpu_init(Object
*obj
)
133 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
134 /* We set this in the realise function */
138 static void rv32gcsu_priv1_09_1_cpu_init(Object
*obj
)
140 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
141 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
142 set_priv_version(env
, PRIV_VERSION_1_09_1
);
143 set_resetvec(env
, DEFAULT_RSTVEC
);
144 set_feature(env
, RISCV_FEATURE_MMU
);
145 set_feature(env
, RISCV_FEATURE_PMP
);
148 static void rv32gcsu_priv1_10_0_cpu_init(Object
*obj
)
150 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
151 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
152 set_priv_version(env
, PRIV_VERSION_1_10_0
);
153 set_resetvec(env
, DEFAULT_RSTVEC
);
154 set_feature(env
, RISCV_FEATURE_MMU
);
155 set_feature(env
, RISCV_FEATURE_PMP
);
158 static void rv32imacu_nommu_cpu_init(Object
*obj
)
160 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
161 set_misa(env
, RV32
| RVI
| RVM
| RVA
| RVC
| RVU
);
162 set_priv_version(env
, PRIV_VERSION_1_10_0
);
163 set_resetvec(env
, DEFAULT_RSTVEC
);
164 set_feature(env
, RISCV_FEATURE_PMP
);
167 #elif defined(TARGET_RISCV64)
169 static void riscv_base64_cpu_init(Object
*obj
)
171 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
172 /* We set this in the realise function */
176 static void rv64gcsu_priv1_09_1_cpu_init(Object
*obj
)
178 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
179 set_misa(env
, RV64
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
180 set_priv_version(env
, PRIV_VERSION_1_09_1
);
181 set_resetvec(env
, DEFAULT_RSTVEC
);
182 set_feature(env
, RISCV_FEATURE_MMU
);
183 set_feature(env
, RISCV_FEATURE_PMP
);
186 static void rv64gcsu_priv1_10_0_cpu_init(Object
*obj
)
188 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
189 set_misa(env
, RV64
| RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
190 set_priv_version(env
, PRIV_VERSION_1_10_0
);
191 set_resetvec(env
, DEFAULT_RSTVEC
);
192 set_feature(env
, RISCV_FEATURE_MMU
);
193 set_feature(env
, RISCV_FEATURE_PMP
);
196 static void rv64imacu_nommu_cpu_init(Object
*obj
)
198 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
199 set_misa(env
, RV64
| RVI
| RVM
| RVA
| RVC
| RVU
);
200 set_priv_version(env
, PRIV_VERSION_1_10_0
);
201 set_resetvec(env
, DEFAULT_RSTVEC
);
202 set_feature(env
, RISCV_FEATURE_PMP
);
207 static ObjectClass
*riscv_cpu_class_by_name(const char *cpu_model
)
213 cpuname
= g_strsplit(cpu_model
, ",", 1);
214 typename
= g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname
[0]);
215 oc
= object_class_by_name(typename
);
218 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_RISCV_CPU
) ||
219 object_class_is_abstract(oc
)) {
225 static void riscv_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
227 RISCVCPU
*cpu
= RISCV_CPU(cs
);
228 CPURISCVState
*env
= &cpu
->env
;
231 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "pc ", env
->pc
);
232 #ifndef CONFIG_USER_ONLY
233 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mhartid ", env
->mhartid
);
234 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mstatus ", env
->mstatus
);
235 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mip ", env
->mip
);
236 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mie ", env
->mie
);
237 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mideleg ", env
->mideleg
);
238 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "medeleg ", env
->medeleg
);
239 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mtvec ", env
->mtvec
);
240 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mepc ", env
->mepc
);
241 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "mcause ", env
->mcause
);
244 for (i
= 0; i
< 32; i
++) {
245 qemu_fprintf(f
, " %s " TARGET_FMT_lx
,
246 riscv_int_regnames
[i
], env
->gpr
[i
]);
248 qemu_fprintf(f
, "\n");
251 if (flags
& CPU_DUMP_FPU
) {
252 for (i
= 0; i
< 32; i
++) {
253 qemu_fprintf(f
, " %s %016" PRIx64
,
254 riscv_fpr_regnames
[i
], env
->fpr
[i
]);
256 qemu_fprintf(f
, "\n");
262 static void riscv_cpu_set_pc(CPUState
*cs
, vaddr value
)
264 RISCVCPU
*cpu
= RISCV_CPU(cs
);
265 CPURISCVState
*env
= &cpu
->env
;
269 static void riscv_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
271 RISCVCPU
*cpu
= RISCV_CPU(cs
);
272 CPURISCVState
*env
= &cpu
->env
;
276 static bool riscv_cpu_has_work(CPUState
*cs
)
278 #ifndef CONFIG_USER_ONLY
279 RISCVCPU
*cpu
= RISCV_CPU(cs
);
280 CPURISCVState
*env
= &cpu
->env
;
282 * Definition of the WFI instruction requires it to ignore the privilege
283 * mode and delegation registers, but respect individual enables
285 return (env
->mip
& env
->mie
) != 0;
291 void restore_state_to_opc(CPURISCVState
*env
, TranslationBlock
*tb
,
297 static void riscv_cpu_reset(CPUState
*cs
)
299 RISCVCPU
*cpu
= RISCV_CPU(cs
);
300 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(cpu
);
301 CPURISCVState
*env
= &cpu
->env
;
303 mcc
->parent_reset(cs
);
304 #ifndef CONFIG_USER_ONLY
306 env
->mstatus
&= ~(MSTATUS_MIE
| MSTATUS_MPRV
);
308 env
->pc
= env
->resetvec
;
310 cs
->exception_index
= EXCP_NONE
;
312 set_default_nan_mode(1, &env
->fp_status
);
315 static void riscv_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
317 #if defined(TARGET_RISCV32)
318 info
->print_insn
= print_insn_riscv32
;
319 #elif defined(TARGET_RISCV64)
320 info
->print_insn
= print_insn_riscv64
;
324 static void riscv_cpu_realize(DeviceState
*dev
, Error
**errp
)
326 CPUState
*cs
= CPU(dev
);
327 RISCVCPU
*cpu
= RISCV_CPU(dev
);
328 CPURISCVState
*env
= &cpu
->env
;
329 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(dev
);
330 int priv_version
= PRIV_VERSION_1_11_0
;
331 target_ulong target_misa
= 0;
332 Error
*local_err
= NULL
;
334 cpu_exec_realizefn(cs
, &local_err
);
335 if (local_err
!= NULL
) {
336 error_propagate(errp
, local_err
);
340 if (cpu
->cfg
.priv_spec
) {
341 if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.11.0")) {
342 priv_version
= PRIV_VERSION_1_11_0
;
343 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.10.0")) {
344 priv_version
= PRIV_VERSION_1_10_0
;
345 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.9.1")) {
346 priv_version
= PRIV_VERSION_1_09_1
;
349 "Unsupported privilege spec version '%s'",
355 set_priv_version(env
, priv_version
);
356 set_resetvec(env
, DEFAULT_RSTVEC
);
359 set_feature(env
, RISCV_FEATURE_MMU
);
363 set_feature(env
, RISCV_FEATURE_PMP
);
366 /* If misa isn't set (rv32 and rv64 machines) set it here */
368 /* Do some ISA extension error checking */
369 if (cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_e
) {
371 "I and E extensions are incompatible");
375 if (!cpu
->cfg
.ext_i
&& !cpu
->cfg
.ext_e
) {
377 "Either I or E extension must be set");
381 if (cpu
->cfg
.ext_g
&& !(cpu
->cfg
.ext_i
& cpu
->cfg
.ext_m
&
382 cpu
->cfg
.ext_a
& cpu
->cfg
.ext_f
&
384 warn_report("Setting G will also set IMAFD");
385 cpu
->cfg
.ext_i
= true;
386 cpu
->cfg
.ext_m
= true;
387 cpu
->cfg
.ext_a
= true;
388 cpu
->cfg
.ext_f
= true;
389 cpu
->cfg
.ext_d
= true;
392 /* Set the ISA extensions, checks should have happened above */
393 if (cpu
->cfg
.ext_i
) {
396 if (cpu
->cfg
.ext_e
) {
399 if (cpu
->cfg
.ext_m
) {
402 if (cpu
->cfg
.ext_a
) {
405 if (cpu
->cfg
.ext_f
) {
408 if (cpu
->cfg
.ext_d
) {
411 if (cpu
->cfg
.ext_c
) {
414 if (cpu
->cfg
.ext_s
) {
417 if (cpu
->cfg
.ext_u
) {
421 set_misa(env
, RVXLEN
| target_misa
);
424 riscv_cpu_register_gdb_regs_for_features(cs
);
429 mcc
->parent_realize(dev
, errp
);
432 static void riscv_cpu_init(Object
*obj
)
434 RISCVCPU
*cpu
= RISCV_CPU(obj
);
436 cpu_set_cpustate_pointers(cpu
);
439 static const VMStateDescription vmstate_riscv_cpu
= {
444 static Property riscv_cpu_properties
[] = {
445 DEFINE_PROP_BOOL("i", RISCVCPU
, cfg
.ext_i
, true),
446 DEFINE_PROP_BOOL("e", RISCVCPU
, cfg
.ext_e
, false),
447 DEFINE_PROP_BOOL("g", RISCVCPU
, cfg
.ext_g
, true),
448 DEFINE_PROP_BOOL("m", RISCVCPU
, cfg
.ext_m
, true),
449 DEFINE_PROP_BOOL("a", RISCVCPU
, cfg
.ext_a
, true),
450 DEFINE_PROP_BOOL("f", RISCVCPU
, cfg
.ext_f
, true),
451 DEFINE_PROP_BOOL("d", RISCVCPU
, cfg
.ext_d
, true),
452 DEFINE_PROP_BOOL("c", RISCVCPU
, cfg
.ext_c
, true),
453 DEFINE_PROP_BOOL("s", RISCVCPU
, cfg
.ext_s
, true),
454 DEFINE_PROP_BOOL("u", RISCVCPU
, cfg
.ext_u
, true),
455 DEFINE_PROP_BOOL("Counters", RISCVCPU
, cfg
.ext_counters
, true),
456 DEFINE_PROP_BOOL("Zifencei", RISCVCPU
, cfg
.ext_ifencei
, true),
457 DEFINE_PROP_BOOL("Zicsr", RISCVCPU
, cfg
.ext_icsr
, true),
458 DEFINE_PROP_STRING("priv_spec", RISCVCPU
, cfg
.priv_spec
),
459 DEFINE_PROP_BOOL("mmu", RISCVCPU
, cfg
.mmu
, true),
460 DEFINE_PROP_BOOL("pmp", RISCVCPU
, cfg
.pmp
, true),
461 DEFINE_PROP_END_OF_LIST(),
464 static void riscv_cpu_class_init(ObjectClass
*c
, void *data
)
466 RISCVCPUClass
*mcc
= RISCV_CPU_CLASS(c
);
467 CPUClass
*cc
= CPU_CLASS(c
);
468 DeviceClass
*dc
= DEVICE_CLASS(c
);
470 device_class_set_parent_realize(dc
, riscv_cpu_realize
,
471 &mcc
->parent_realize
);
473 cpu_class_set_parent_reset(cc
, riscv_cpu_reset
, &mcc
->parent_reset
);
475 cc
->class_by_name
= riscv_cpu_class_by_name
;
476 cc
->has_work
= riscv_cpu_has_work
;
477 cc
->do_interrupt
= riscv_cpu_do_interrupt
;
478 cc
->cpu_exec_interrupt
= riscv_cpu_exec_interrupt
;
479 cc
->dump_state
= riscv_cpu_dump_state
;
480 cc
->set_pc
= riscv_cpu_set_pc
;
481 cc
->synchronize_from_tb
= riscv_cpu_synchronize_from_tb
;
482 cc
->gdb_read_register
= riscv_cpu_gdb_read_register
;
483 cc
->gdb_write_register
= riscv_cpu_gdb_write_register
;
484 cc
->gdb_num_core_regs
= 33;
485 #if defined(TARGET_RISCV32)
486 cc
->gdb_core_xml_file
= "riscv-32bit-cpu.xml";
487 #elif defined(TARGET_RISCV64)
488 cc
->gdb_core_xml_file
= "riscv-64bit-cpu.xml";
490 cc
->gdb_stop_before_watchpoint
= true;
491 cc
->disas_set_info
= riscv_cpu_disas_set_info
;
492 #ifndef CONFIG_USER_ONLY
493 cc
->do_transaction_failed
= riscv_cpu_do_transaction_failed
;
494 cc
->do_unaligned_access
= riscv_cpu_do_unaligned_access
;
495 cc
->get_phys_page_debug
= riscv_cpu_get_phys_page_debug
;
498 cc
->tcg_initialize
= riscv_translate_init
;
499 cc
->tlb_fill
= riscv_cpu_tlb_fill
;
501 /* For now, mark unmigratable: */
502 cc
->vmsd
= &vmstate_riscv_cpu
;
503 device_class_set_props(dc
, riscv_cpu_properties
);
506 char *riscv_isa_string(RISCVCPU
*cpu
)
509 const size_t maxlen
= sizeof("rv128") + sizeof(riscv_exts
) + 1;
510 char *isa_str
= g_new(char, maxlen
);
511 char *p
= isa_str
+ snprintf(isa_str
, maxlen
, "rv%d", TARGET_LONG_BITS
);
512 for (i
= 0; i
< sizeof(riscv_exts
); i
++) {
513 if (cpu
->env
.misa
& RV(riscv_exts
[i
])) {
514 *p
++ = qemu_tolower(riscv_exts
[i
]);
521 static gint
riscv_cpu_list_compare(gconstpointer a
, gconstpointer b
)
523 ObjectClass
*class_a
= (ObjectClass
*)a
;
524 ObjectClass
*class_b
= (ObjectClass
*)b
;
525 const char *name_a
, *name_b
;
527 name_a
= object_class_get_name(class_a
);
528 name_b
= object_class_get_name(class_b
);
529 return strcmp(name_a
, name_b
);
532 static void riscv_cpu_list_entry(gpointer data
, gpointer user_data
)
534 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
535 int len
= strlen(typename
) - strlen(RISCV_CPU_TYPE_SUFFIX
);
537 qemu_printf("%.*s\n", len
, typename
);
540 void riscv_cpu_list(void)
544 list
= object_class_get_list(TYPE_RISCV_CPU
, false);
545 list
= g_slist_sort(list
, riscv_cpu_list_compare
);
546 g_slist_foreach(list
, riscv_cpu_list_entry
, NULL
);
550 #define DEFINE_CPU(type_name, initfn) \
553 .parent = TYPE_RISCV_CPU, \
554 .instance_init = initfn \
557 static const TypeInfo riscv_cpu_type_infos
[] = {
559 .name
= TYPE_RISCV_CPU
,
561 .instance_size
= sizeof(RISCVCPU
),
562 .instance_init
= riscv_cpu_init
,
564 .class_size
= sizeof(RISCVCPUClass
),
565 .class_init
= riscv_cpu_class_init
,
567 DEFINE_CPU(TYPE_RISCV_CPU_ANY
, riscv_any_cpu_init
),
568 #if defined(TARGET_RISCV32)
569 DEFINE_CPU(TYPE_RISCV_CPU_BASE32
, riscv_base32_cpu_init
),
570 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31
, rv32imacu_nommu_cpu_init
),
571 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34
, rv32gcsu_priv1_10_0_cpu_init
),
573 DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU
, rv32imacu_nommu_cpu_init
),
574 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1
, rv32gcsu_priv1_09_1_cpu_init
),
575 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0
, rv32gcsu_priv1_10_0_cpu_init
)
576 #elif defined(TARGET_RISCV64)
577 DEFINE_CPU(TYPE_RISCV_CPU_BASE64
, riscv_base64_cpu_init
),
578 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51
, rv64imacu_nommu_cpu_init
),
579 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54
, rv64gcsu_priv1_10_0_cpu_init
),
581 DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU
, rv64imacu_nommu_cpu_init
),
582 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1
, rv64gcsu_priv1_09_1_cpu_init
),
583 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0
, rv64gcsu_priv1_10_0_cpu_init
)
587 DEFINE_TYPES(riscv_cpu_type_infos
)