4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
23 /* QEMU addressing/paging config */
24 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
25 #if defined(TARGET_RISCV64)
26 #define TARGET_LONG_BITS 64
27 #define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
28 #define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
29 #elif defined(TARGET_RISCV32)
30 #define TARGET_LONG_BITS 32
31 #define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
35 #define TCG_GUEST_DEFAULT_MO 0
37 #define CPUArchState struct CPURISCVState
39 #include "qemu-common.h"
41 #include "exec/cpu-defs.h"
42 #include "fpu/softfloat.h"
44 #define TYPE_RISCV_CPU "riscv-cpu"
46 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
47 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
48 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
50 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
51 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
52 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
53 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
54 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
55 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
56 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
57 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
58 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
59 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
60 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
62 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
63 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
65 #if defined(TARGET_RISCV32)
67 #elif defined(TARGET_RISCV64)
71 #define RV(x) ((target_ulong)1 << (x - 'A'))
74 #define RVE RV('E') /* E and I are mutually exclusive */
83 /* S extension denotes that Supervisor mode exists, however it is possible
84 to have a core that support S mode but does not have an MMU and there
85 is currently no bit in misa to indicate whether an MMU exists or not
86 so a cpu features bitfield is required, likewise for optional PMP support */
93 #define USER_VERSION_2_02_0 0x00020200
94 #define PRIV_VERSION_1_09_1 0x00010901
95 #define PRIV_VERSION_1_10_0 0x00011000
97 #define TRANSLATE_FAIL 1
98 #define TRANSLATE_SUCCESS 0
99 #define NB_MMU_MODES 4
100 #define MMU_USER_IDX 3
102 #define MAX_RISCV_PMPS (16)
104 typedef struct CPURISCVState CPURISCVState
;
108 struct CPURISCVState
{
109 target_ulong gpr
[32];
110 uint64_t fpr
[32]; /* assume both F and D extensions */
112 target_ulong load_res
;
113 target_ulong load_val
;
117 target_ulong badaddr
;
119 target_ulong user_ver
;
120 target_ulong priv_ver
;
122 target_ulong misa_mask
;
126 #ifdef CONFIG_USER_ONLY
130 #ifndef CONFIG_USER_ONLY
132 target_ulong resetvec
;
134 target_ulong mhartid
;
135 target_ulong mstatus
;
138 * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
139 * by I/O threads. It should be read with atomic_read. It should be updated
140 * using riscv_cpu_update_mip with the iothread mutex held. The iothread
141 * mutex must be held because mip must be consistent with the CPU inturrept
142 * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
143 * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
144 * mip is 32-bits to allow atomic_read on 32-bit hosts.
150 target_ulong mideleg
;
152 target_ulong sptbr
; /* until: priv-1.9.1 */
153 target_ulong satp
; /* since: priv-1.10.0 */
154 target_ulong sbadaddr
;
155 target_ulong mbadaddr
;
156 target_ulong medeleg
;
165 target_ulong mtval
; /* since: priv-1.10.0 */
167 target_ulong scounteren
;
168 target_ulong mcounteren
;
170 target_ulong sscratch
;
171 target_ulong mscratch
;
173 /* temporary htif regs */
178 /* physical memory protection */
179 pmp_table_t pmp_state
;
181 /* True if in debugger mode. */
185 float_status fp_status
;
190 /* Fields from here on are preserved across CPU reset. */
191 QEMUTimer
*timer
; /* Internal timer */
194 #define RISCV_CPU_CLASS(klass) \
195 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
196 #define RISCV_CPU(obj) \
197 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
198 #define RISCV_CPU_GET_CLASS(obj) \
199 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
203 * @parent_realize: The parent class' realize handler.
204 * @parent_reset: The parent class' reset handler.
208 typedef struct RISCVCPUClass
{
210 CPUClass parent_class
;
212 DeviceRealize parent_realize
;
213 void (*parent_reset
)(CPUState
*cpu
);
218 * @env: #CPURISCVState
222 typedef struct RISCVCPU
{
228 /* Configuration Settings */
237 static inline RISCVCPU
*riscv_env_get_cpu(CPURISCVState
*env
)
239 return container_of(env
, RISCVCPU
, env
);
242 static inline int riscv_has_ext(CPURISCVState
*env
, target_ulong ext
)
244 return (env
->misa
& ext
) != 0;
247 static inline bool riscv_feature(CPURISCVState
*env
, int feature
)
249 return env
->features
& (1ULL << feature
);
252 #include "cpu_user.h"
253 #include "cpu_bits.h"
255 extern const char * const riscv_int_regnames
[];
256 extern const char * const riscv_fpr_regnames
[];
257 extern const char * const riscv_excp_names
[];
258 extern const char * const riscv_intr_names
[];
260 #define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e))
261 #define ENV_OFFSET offsetof(RISCVCPU, env)
263 void riscv_cpu_do_interrupt(CPUState
*cpu
);
264 int riscv_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
265 int riscv_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
266 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
);
267 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
);
268 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
269 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
270 MMUAccessType access_type
, int mmu_idx
,
272 bool riscv_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
273 MMUAccessType access_type
, int mmu_idx
,
274 bool probe
, uintptr_t retaddr
);
275 char *riscv_isa_string(RISCVCPU
*cpu
);
276 void riscv_cpu_list(void);
278 #define cpu_signal_handler riscv_cpu_signal_handler
279 #define cpu_list riscv_cpu_list
280 #define cpu_mmu_index riscv_cpu_mmu_index
282 #ifndef CONFIG_USER_ONLY
283 int riscv_cpu_claim_interrupts(RISCVCPU
*cpu
, uint32_t interrupts
);
284 uint32_t riscv_cpu_update_mip(RISCVCPU
*cpu
, uint32_t mask
, uint32_t value
);
285 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
287 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
);
289 void riscv_translate_init(void);
290 int riscv_cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
);
291 void QEMU_NORETURN
riscv_raise_exception(CPURISCVState
*env
,
292 uint32_t exception
, uintptr_t pc
);
294 target_ulong
riscv_cpu_get_fflags(CPURISCVState
*env
);
295 void riscv_cpu_set_fflags(CPURISCVState
*env
, target_ulong
);
297 #define TB_FLAGS_MMU_MASK 3
298 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
300 static inline void cpu_get_tb_cpu_state(CPURISCVState
*env
, target_ulong
*pc
,
301 target_ulong
*cs_base
, uint32_t *flags
)
305 #ifdef CONFIG_USER_ONLY
306 *flags
= TB_FLAGS_MSTATUS_FS
;
308 *flags
= cpu_mmu_index(env
, 0) | (env
->mstatus
& MSTATUS_FS
);
312 int riscv_csrrw(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
313 target_ulong new_value
, target_ulong write_mask
);
314 int riscv_csrrw_debug(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
315 target_ulong new_value
, target_ulong write_mask
);
317 static inline void riscv_csr_write(CPURISCVState
*env
, int csrno
,
320 riscv_csrrw(env
, csrno
, NULL
, val
, MAKE_64BIT_MASK(0, TARGET_LONG_BITS
));
323 static inline target_ulong
riscv_csr_read(CPURISCVState
*env
, int csrno
)
325 target_ulong val
= 0;
326 riscv_csrrw(env
, csrno
, &val
, 0, 0);
330 typedef int (*riscv_csr_predicate_fn
)(CPURISCVState
*env
, int csrno
);
331 typedef int (*riscv_csr_read_fn
)(CPURISCVState
*env
, int csrno
,
332 target_ulong
*ret_value
);
333 typedef int (*riscv_csr_write_fn
)(CPURISCVState
*env
, int csrno
,
334 target_ulong new_value
);
335 typedef int (*riscv_csr_op_fn
)(CPURISCVState
*env
, int csrno
,
336 target_ulong
*ret_value
, target_ulong new_value
, target_ulong write_mask
);
339 riscv_csr_predicate_fn predicate
;
340 riscv_csr_read_fn read
;
341 riscv_csr_write_fn write
;
343 } riscv_csr_operations
;
345 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
);
346 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
);
348 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
);
350 #include "exec/cpu-all.h"
352 #endif /* RISCV_CPU_H */