target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "hw/registerfields.h"
  25 #include "exec/cpu-defs.h"
  26 #include "fpu/softfloat-types.h"
  27 #include "qom/object.h"
  28 #include "cpu_bits.h"
  29
  30 #define TCG_GUEST_DEFAULT_MO 0
  31
  32 #define TYPE_RISCV_CPU "riscv-cpu"
  33
  34 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  35 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  36 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  37
  38 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  39 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  40 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  41 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
  42 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
  43 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  44 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
  45 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  46 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  47 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  48
  49 #if defined(TARGET_RISCV32)
  50 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
  51 #elif defined(TARGET_RISCV64)
  52 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  53 #endif
  54
  55 #define RV(x) ((target_ulong)1 << (x - 'A'))
  56
  57 #define RVI RV('I')
  58 #define RVE RV('E') /* E and I are mutually exclusive */
  59 #define RVM RV('M')
  60 #define RVA RV('A')
  61 #define RVF RV('F')
  62 #define RVD RV('D')
  63 #define RVV RV('V')
  64 #define RVC RV('C')
  65 #define RVS RV('S')
  66 #define RVU RV('U')
  67 #define RVH RV('H')
  68 #define RVJ RV('J')
  69
  70 /* S extension denotes that Supervisor mode exists, however it is possible
  71    to have a core that support S mode but does not have an MMU and there
  72    is currently no bit in misa to indicate whether an MMU exists or not
  73    so a cpu features bitfield is required, likewise for optional PMP support */
  74 enum {
  75     RISCV_FEATURE_MMU,
  76     RISCV_FEATURE_PMP,
  77     RISCV_FEATURE_EPMP,
  78     RISCV_FEATURE_MISA
  79 };
  80
  81 #define PRIV_VERSION_1_10_0 0x00011000
  82 #define PRIV_VERSION_1_11_0 0x00011100
  83
  84 #define VEXT_VERSION_1_00_0 0x00010000
  85
  86 enum {
  87     TRANSLATE_SUCCESS,
  88     TRANSLATE_FAIL,
  89     TRANSLATE_PMP_FAIL,
  90     TRANSLATE_G_STAGE_FAIL
  91 };
  92
  93 #define MMU_USER_IDX 3
  94
  95 #define MAX_RISCV_PMPS (16)
  96
  97 typedef struct CPURISCVState CPURISCVState;
  98
  99 #if !defined(CONFIG_USER_ONLY)
 100 #include "pmp.h"
 101 #endif
 102
 103 #define RV_VLEN_MAX 1024
 104
 105 FIELD(VTYPE, VLMUL, 0, 3)
 106 FIELD(VTYPE, VSEW, 3, 3)
 107 FIELD(VTYPE, VTA, 6, 1)
 108 FIELD(VTYPE, VMA, 7, 1)
 109 FIELD(VTYPE, VEDIV, 8, 2)
 110 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
 111 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 112
 113 struct CPURISCVState {
 114     target_ulong gpr[32];
 115     uint64_t fpr[32]; /* assume both F and D extensions */
 116
 117     /* vector coprocessor state. */
 118     uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
 119     target_ulong vxrm;
 120     target_ulong vxsat;
 121     target_ulong vl;
 122     target_ulong vstart;
 123     target_ulong vtype;
 124
 125     target_ulong pc;
 126     target_ulong load_res;
 127     target_ulong load_val;
 128
 129     target_ulong frm;
 130
 131     target_ulong badaddr;
 132     target_ulong guest_phys_fault_addr;
 133
 134     target_ulong priv_ver;
 135     target_ulong bext_ver;
 136     target_ulong vext_ver;
 137
 138     /* RISCVMXL, but uint32_t for vmstate migration */
 139     uint32_t misa_mxl;      /* current mxl */
 140     uint32_t misa_mxl_max;  /* max mxl for this cpu */
 141     uint32_t misa_ext;      /* current extensions */
 142     uint32_t misa_ext_mask; /* max ext for this cpu */
 143
 144     uint32_t features;
 145
 146 #ifdef CONFIG_USER_ONLY
 147     uint32_t elf_flags;
 148 #endif
 149
 150 #ifndef CONFIG_USER_ONLY
 151     target_ulong priv;
 152     /* This contains QEMU specific information about the virt state. */
 153     target_ulong virt;
 154     target_ulong resetvec;
 155
 156     target_ulong mhartid;
 157     /*
 158      * For RV32 this is 32-bit mstatus and 32-bit mstatush.
 159      * For RV64 this is a 64-bit mstatus.
 160      */
 161     uint64_t mstatus;
 162
 163     target_ulong mip;
 164
 165     uint32_t miclaim;
 166
 167     target_ulong mie;
 168     target_ulong mideleg;
 169
 170     target_ulong satp;   /* since: priv-1.10.0 */
 171     target_ulong stval;
 172     target_ulong medeleg;
 173
 174     target_ulong stvec;
 175     target_ulong sepc;
 176     target_ulong scause;
 177
 178     target_ulong mtvec;
 179     target_ulong mepc;
 180     target_ulong mcause;
 181     target_ulong mtval;  /* since: priv-1.10.0 */
 182
 183     /* Hypervisor CSRs */
 184     target_ulong hstatus;
 185     target_ulong hedeleg;
 186     target_ulong hideleg;
 187     target_ulong hcounteren;
 188     target_ulong htval;
 189     target_ulong htinst;
 190     target_ulong hgatp;
 191     uint64_t htimedelta;
 192
 193     /* Virtual CSRs */
 194     /*
 195      * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
 196      * For RV64 this is a 64-bit vsstatus.
 197      */
 198     uint64_t vsstatus;
 199     target_ulong vstvec;
 200     target_ulong vsscratch;
 201     target_ulong vsepc;
 202     target_ulong vscause;
 203     target_ulong vstval;
 204     target_ulong vsatp;
 205
 206     target_ulong mtval2;
 207     target_ulong mtinst;
 208
 209     /* HS Backup CSRs */
 210     target_ulong stvec_hs;
 211     target_ulong sscratch_hs;
 212     target_ulong sepc_hs;
 213     target_ulong scause_hs;
 214     target_ulong stval_hs;
 215     target_ulong satp_hs;
 216     uint64_t mstatus_hs;
 217
 218     /* Signals whether the current exception occurred with two-stage address
 219        translation active. */
 220     bool two_stage_lookup;
 221
 222     target_ulong scounteren;
 223     target_ulong mcounteren;
 224
 225     target_ulong sscratch;
 226     target_ulong mscratch;
 227
 228     /* temporary htif regs */
 229     uint64_t mfromhost;
 230     uint64_t mtohost;
 231     uint64_t timecmp;
 232
 233     /* physical memory protection */
 234     pmp_table_t pmp_state;
 235     target_ulong mseccfg;
 236
 237     /* machine specific rdtime callback */
 238     uint64_t (*rdtime_fn)(uint32_t);
 239     uint32_t rdtime_fn_arg;
 240
 241     /* True if in debugger mode.  */
 242     bool debugger;
 243
 244     /*
 245      * CSRs for PointerMasking extension
 246      */
 247     target_ulong mmte;
 248     target_ulong mpmmask;
 249     target_ulong mpmbase;
 250     target_ulong spmmask;
 251     target_ulong spmbase;
 252     target_ulong upmmask;
 253     target_ulong upmbase;
 254 #endif
 255
 256     float_status fp_status;
 257
 258     /* Fields from here on are preserved across CPU reset. */
 259     QEMUTimer *timer; /* Internal timer */
 260 };
 261
 262 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
 263                     RISCV_CPU)
 264
 265 /**
 266  * RISCVCPUClass:
 267  * @parent_realize: The parent class' realize handler.
 268  * @parent_reset: The parent class' reset handler.
 269  *
 270  * A RISCV CPU model.
 271  */
 272 struct RISCVCPUClass {
 273     /*< private >*/
 274     CPUClass parent_class;
 275     /*< public >*/
 276     DeviceRealize parent_realize;
 277     DeviceReset parent_reset;
 278 };
 279
 280 /**
 281  * RISCVCPU:
 282  * @env: #CPURISCVState
 283  *
 284  * A RISCV CPU.
 285  */
 286 struct RISCVCPU {
 287     /*< private >*/
 288     CPUState parent_obj;
 289     /*< public >*/
 290     CPUNegativeOffsetState neg;
 291     CPURISCVState env;
 292
 293     char *dyn_csr_xml;
 294
 295     /* Configuration Settings */
 296     struct {
 297         bool ext_i;
 298         bool ext_e;
 299         bool ext_g;
 300         bool ext_m;
 301         bool ext_a;
 302         bool ext_f;
 303         bool ext_d;
 304         bool ext_c;
 305         bool ext_s;
 306         bool ext_u;
 307         bool ext_h;
 308         bool ext_j;
 309         bool ext_v;
 310         bool ext_zba;
 311         bool ext_zbb;
 312         bool ext_zbc;
 313         bool ext_zbs;
 314         bool ext_counters;
 315         bool ext_ifencei;
 316         bool ext_icsr;
 317         bool ext_zfh;
 318         bool ext_zfhmin;
 319
 320         char *priv_spec;
 321         char *user_spec;
 322         char *bext_spec;
 323         char *vext_spec;
 324         uint16_t vlen;
 325         uint16_t elen;
 326         bool mmu;
 327         bool pmp;
 328         bool epmp;
 329         uint64_t resetvec;
 330     } cfg;
 331 };
 332
 333 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 334 {
 335     return (env->misa_ext & ext) != 0;
 336 }
 337
 338 static inline bool riscv_feature(CPURISCVState *env, int feature)
 339 {
 340     return env->features & (1ULL << feature);
 341 }
 342
 343 #include "cpu_user.h"
 344
 345 extern const char * const riscv_int_regnames[];
 346 extern const char * const riscv_fpr_regnames[];
 347
 348 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 349 void riscv_cpu_do_interrupt(CPUState *cpu);
 350 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 351                                int cpuid, void *opaque);
 352 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
 353                                int cpuid, void *opaque);
 354 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 355 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 356 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 357 bool riscv_cpu_vector_enabled(CPURISCVState *env);
 358 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 359 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 360 bool riscv_cpu_two_stage_lookup(int mmu_idx);
 361 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 362 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 363 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 364                                     MMUAccessType access_type, int mmu_idx,
 365                                     uintptr_t retaddr) QEMU_NORETURN;
 366 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 367                         MMUAccessType access_type, int mmu_idx,
 368                         bool probe, uintptr_t retaddr);
 369 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 370                                      vaddr addr, unsigned size,
 371                                      MMUAccessType access_type,
 372                                      int mmu_idx, MemTxAttrs attrs,
 373                                      MemTxResult response, uintptr_t retaddr);
 374 char *riscv_isa_string(RISCVCPU *cpu);
 375 void riscv_cpu_list(void);
 376
 377 #define cpu_list riscv_cpu_list
 378 #define cpu_mmu_index riscv_cpu_mmu_index
 379
 380 #ifndef CONFIG_USER_ONLY
 381 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 382 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 383 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 384 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 385 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 386 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
 387                              uint32_t arg);
 388 #endif
 389 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 390
 391 void riscv_translate_init(void);
 392 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 393                                          uint32_t exception, uintptr_t pc);
 394
 395 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 396 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 397
 398 #define TB_FLAGS_PRIV_MMU_MASK                3
 399 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 400 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 401 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
 402
 403 typedef CPURISCVState CPUArchState;
 404 typedef RISCVCPU ArchCPU;
 405 #include "exec/cpu-all.h"
 406
 407 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 408 FIELD(TB_FLAGS, LMUL, 3, 3)
 409 FIELD(TB_FLAGS, SEW, 6, 3)
 410 /* Skip MSTATUS_VS (0x600) bits */
 411 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
 412 FIELD(TB_FLAGS, VILL, 12, 1)
 413 /* Skip MSTATUS_FS (0x6000) bits */
 414 /* Is a Hypervisor instruction load/store allowed? */
 415 FIELD(TB_FLAGS, HLSX, 15, 1)
 416 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
 417 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
 418 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 419 FIELD(TB_FLAGS, XL, 20, 2)
 420 /* If PointerMasking should be applied */
 421 FIELD(TB_FLAGS, PM_ENABLED, 22, 1)
 422
 423 #ifdef TARGET_RISCV32
 424 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 425 #else
 426 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 427 {
 428     return env->misa_mxl;
 429 }
 430 #endif
 431
 432 /*
 433  * Encode LMUL to lmul as follows:
 434  *     LMUL    vlmul    lmul
 435  *      1       000       0
 436  *      2       001       1
 437  *      4       010       2
 438  *      8       011       3
 439  *      -       100       -
 440  *     1/8      101      -3
 441  *     1/4      110      -2
 442  *     1/2      111      -1
 443  *
 444  * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
 445  * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
 446  *      => VLMAX = vlen >> (1 + 3 - (-3))
 447  *               = 256 >> 7
 448  *               = 2
 449  */
 450 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 451 {
 452     uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
 453     int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
 454     return cpu->cfg.vlen >> (sew + 3 - lmul);
 455 }
 456
 457 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 458                           target_ulong *cs_base, uint32_t *pflags);
 459
 460 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
 461                            target_ulong *ret_value,
 462                            target_ulong new_value, target_ulong write_mask);
 463 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
 464                                  target_ulong *ret_value,
 465                                  target_ulong new_value,
 466                                  target_ulong write_mask);
 467
 468 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 469                                    target_ulong val)
 470 {
 471     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 472 }
 473
 474 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 475 {
 476     target_ulong val = 0;
 477     riscv_csrrw(env, csrno, &val, 0, 0);
 478     return val;
 479 }
 480
 481 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
 482                                                  int csrno);
 483 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 484                                             target_ulong *ret_value);
 485 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 486                                              target_ulong new_value);
 487 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 488                                           target_ulong *ret_value,
 489                                           target_ulong new_value,
 490                                           target_ulong write_mask);
 491
 492 typedef struct {
 493     const char *name;
 494     riscv_csr_predicate_fn predicate;
 495     riscv_csr_read_fn read;
 496     riscv_csr_write_fn write;
 497     riscv_csr_op_fn op;
 498 } riscv_csr_operations;
 499
 500 /* CSR function table constants */
 501 enum {
 502     CSR_TABLE_SIZE = 0x1000
 503 };
 504
 505 /* CSR function table */
 506 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 507
 508 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 509 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 510
 511 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 512
 513 #endif /* RISCV_CPU_H */