target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "hw/registerfields.h"
  25 #include "hw/qdev-properties.h"
  26 #include "exec/cpu-defs.h"
  27 #include "qemu/cpu-float.h"
  28 #include "qom/object.h"
  29 #include "qemu/int128.h"
  30 #include "cpu_bits.h"
  31 #include "cpu_cfg.h"
  32 #include "qapi/qapi-types-common.h"
  33 #include "cpu-qom.h"
  34
  35 typedef struct CPUArchState CPURISCVState;
  36
  37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  38
  39 #if defined(TARGET_RISCV32)
  40 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
  41 #elif defined(TARGET_RISCV64)
  42 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  43 #endif
  44
  45 #define TCG_GUEST_DEFAULT_MO 0
  46
  47 /*
  48  * RISC-V-specific extra insn start words:
  49  * 1: Original instruction opcode
  50  */
  51 #define TARGET_INSN_START_EXTRA_WORDS 1
  52
  53 #define RV(x) ((target_ulong)1 << (x - 'A'))
  54
  55 /*
  56  * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
  57  * when adding new MISA bits here.
  58  */
  59 #define RVI RV('I')
  60 #define RVE RV('E') /* E and I are mutually exclusive */
  61 #define RVM RV('M')
  62 #define RVA RV('A')
  63 #define RVF RV('F')
  64 #define RVD RV('D')
  65 #define RVV RV('V')
  66 #define RVC RV('C')
  67 #define RVS RV('S')
  68 #define RVU RV('U')
  69 #define RVH RV('H')
  70 #define RVJ RV('J')
  71 #define RVG RV('G')
  72
  73 extern const uint32_t misa_bits[];
  74 const char *riscv_get_misa_ext_name(uint32_t bit);
  75 const char *riscv_get_misa_ext_description(uint32_t bit);
  76
  77 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
  78
  79 typedef struct riscv_cpu_profile {
  80     struct riscv_cpu_profile *parent;
  81     const char *name;
  82     uint32_t misa_ext;
  83     bool enabled;
  84     bool user_set;
  85     int priv_spec;
  86     int satp_mode;
  87     const int32_t ext_offsets[];
  88 } RISCVCPUProfile;
  89
  90 #define RISCV_PROFILE_EXT_LIST_END -1
  91 #define RISCV_PROFILE_ATTR_UNUSED -1
  92
  93 extern RISCVCPUProfile *riscv_profiles[];
  94
  95 /* Privileged specification version */
  96 enum {
  97     PRIV_VERSION_1_10_0 = 0,
  98     PRIV_VERSION_1_11_0,
  99     PRIV_VERSION_1_12_0,
 100
 101     PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
 102 };
 103
 104 #define VEXT_VERSION_1_00_0 0x00010000
 105
 106 enum {
 107     TRANSLATE_SUCCESS,
 108     TRANSLATE_FAIL,
 109     TRANSLATE_PMP_FAIL,
 110     TRANSLATE_G_STAGE_FAIL
 111 };
 112
 113 /* Extension context status */
 114 typedef enum {
 115     EXT_STATUS_DISABLED = 0,
 116     EXT_STATUS_INITIAL,
 117     EXT_STATUS_CLEAN,
 118     EXT_STATUS_DIRTY,
 119 } RISCVExtStatus;
 120
 121 #define MMU_USER_IDX 3
 122
 123 #define MAX_RISCV_PMPS (16)
 124
 125 #if !defined(CONFIG_USER_ONLY)
 126 #include "pmp.h"
 127 #include "debug.h"
 128 #endif
 129
 130 #define RV_VLEN_MAX 1024
 131 #define RV_MAX_MHPMEVENTS 32
 132 #define RV_MAX_MHPMCOUNTERS 32
 133
 134 FIELD(VTYPE, VLMUL, 0, 3)
 135 FIELD(VTYPE, VSEW, 3, 3)
 136 FIELD(VTYPE, VTA, 6, 1)
 137 FIELD(VTYPE, VMA, 7, 1)
 138 FIELD(VTYPE, VEDIV, 8, 2)
 139 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
 140
 141 typedef struct PMUCTRState {
 142     /* Current value of a counter */
 143     target_ulong mhpmcounter_val;
 144     /* Current value of a counter in RV32 */
 145     target_ulong mhpmcounterh_val;
 146     /* Snapshot values of counter */
 147     target_ulong mhpmcounter_prev;
 148     /* Snapshort value of a counter in RV32 */
 149     target_ulong mhpmcounterh_prev;
 150     bool started;
 151     /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
 152     target_ulong irq_overflow_left;
 153 } PMUCTRState;
 154
 155 struct CPUArchState {
 156     target_ulong gpr[32];
 157     target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
 158
 159     /* vector coprocessor state. */
 160     uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
 161     target_ulong vxrm;
 162     target_ulong vxsat;
 163     target_ulong vl;
 164     target_ulong vstart;
 165     target_ulong vtype;
 166     bool vill;
 167
 168     target_ulong pc;
 169     target_ulong load_res;
 170     target_ulong load_val;
 171
 172     /* Floating-Point state */
 173     uint64_t fpr[32]; /* assume both F and D extensions */
 174     target_ulong frm;
 175     float_status fp_status;
 176
 177     target_ulong badaddr;
 178     target_ulong bins;
 179
 180     target_ulong guest_phys_fault_addr;
 181
 182     target_ulong priv_ver;
 183     target_ulong bext_ver;
 184     target_ulong vext_ver;
 185
 186     /* RISCVMXL, but uint32_t for vmstate migration */
 187     uint32_t misa_mxl;      /* current mxl */
 188     uint32_t misa_mxl_max;  /* max mxl for this cpu */
 189     uint32_t misa_ext;      /* current extensions */
 190     uint32_t misa_ext_mask; /* max ext for this cpu */
 191     uint32_t xl;            /* current xlen */
 192
 193     /* 128-bit helpers upper part return value */
 194     target_ulong retxh;
 195
 196     target_ulong jvt;
 197
 198 #ifdef CONFIG_USER_ONLY
 199     uint32_t elf_flags;
 200 #endif
 201
 202 #ifndef CONFIG_USER_ONLY
 203     target_ulong priv;
 204     /* This contains QEMU specific information about the virt state. */
 205     bool virt_enabled;
 206     target_ulong geilen;
 207     uint64_t resetvec;
 208
 209     target_ulong mhartid;
 210     /*
 211      * For RV32 this is 32-bit mstatus and 32-bit mstatush.
 212      * For RV64 this is a 64-bit mstatus.
 213      */
 214     uint64_t mstatus;
 215
 216     uint64_t mip;
 217     /*
 218      * MIP contains the software writable version of SEIP ORed with the
 219      * external interrupt value. The MIP register is always up-to-date.
 220      * To keep track of the current source, we also save booleans of the values
 221      * here.
 222      */
 223     bool external_seip;
 224     bool software_seip;
 225
 226     uint64_t miclaim;
 227
 228     uint64_t mie;
 229     uint64_t mideleg;
 230
 231     /*
 232      * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more
 233      * alias of mie[i] and needs to be maintained separately.
 234      */
 235     uint64_t sie;
 236
 237     /*
 238      * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more
 239      * alias of sie[i] (mie[i]) and needs to be maintained separately.
 240      */
 241     uint64_t vsie;
 242
 243     target_ulong satp;   /* since: priv-1.10.0 */
 244     target_ulong stval;
 245     target_ulong medeleg;
 246
 247     target_ulong stvec;
 248     target_ulong sepc;
 249     target_ulong scause;
 250
 251     target_ulong mtvec;
 252     target_ulong mepc;
 253     target_ulong mcause;
 254     target_ulong mtval;  /* since: priv-1.10.0 */
 255
 256     /* Machine and Supervisor interrupt priorities */
 257     uint8_t miprio[64];
 258     uint8_t siprio[64];
 259
 260     /* AIA CSRs */
 261     target_ulong miselect;
 262     target_ulong siselect;
 263     uint64_t mvien;
 264     uint64_t mvip;
 265
 266     /* Hypervisor CSRs */
 267     target_ulong hstatus;
 268     target_ulong hedeleg;
 269     uint64_t hideleg;
 270     target_ulong hcounteren;
 271     target_ulong htval;
 272     target_ulong htinst;
 273     target_ulong hgatp;
 274     target_ulong hgeie;
 275     target_ulong hgeip;
 276     uint64_t htimedelta;
 277     uint64_t hvien;
 278
 279     /*
 280      * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits
 281      * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately
 282      * maintain in hvip.
 283      */
 284     uint64_t hvip;
 285
 286     /* Hypervisor controlled virtual interrupt priorities */
 287     target_ulong hvictl;
 288     uint8_t hviprio[64];
 289
 290     /* Upper 64-bits of 128-bit CSRs */
 291     uint64_t mscratchh;
 292     uint64_t sscratchh;
 293
 294     /* Virtual CSRs */
 295     /*
 296      * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
 297      * For RV64 this is a 64-bit vsstatus.
 298      */
 299     uint64_t vsstatus;
 300     target_ulong vstvec;
 301     target_ulong vsscratch;
 302     target_ulong vsepc;
 303     target_ulong vscause;
 304     target_ulong vstval;
 305     target_ulong vsatp;
 306
 307     /* AIA VS-mode CSRs */
 308     target_ulong vsiselect;
 309
 310     target_ulong mtval2;
 311     target_ulong mtinst;
 312
 313     /* HS Backup CSRs */
 314     target_ulong stvec_hs;
 315     target_ulong sscratch_hs;
 316     target_ulong sepc_hs;
 317     target_ulong scause_hs;
 318     target_ulong stval_hs;
 319     target_ulong satp_hs;
 320     uint64_t mstatus_hs;
 321
 322     /*
 323      * Signals whether the current exception occurred with two-stage address
 324      * translation active.
 325      */
 326     bool two_stage_lookup;
 327     /*
 328      * Signals whether the current exception occurred while doing two-stage
 329      * address translation for the VS-stage page table walk.
 330      */
 331     bool two_stage_indirect_lookup;
 332
 333     target_ulong scounteren;
 334     target_ulong mcounteren;
 335
 336     target_ulong mcountinhibit;
 337
 338     /* PMU counter state */
 339     PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
 340
 341     /* PMU event selector configured values. First three are unused */
 342     target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
 343
 344     /* PMU event selector configured values for RV32 */
 345     target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
 346
 347     target_ulong sscratch;
 348     target_ulong mscratch;
 349
 350     /* Sstc CSRs */
 351     uint64_t stimecmp;
 352
 353     uint64_t vstimecmp;
 354
 355     /* physical memory protection */
 356     pmp_table_t pmp_state;
 357     target_ulong mseccfg;
 358
 359     /* trigger module */
 360     target_ulong trigger_cur;
 361     target_ulong tdata1[RV_MAX_TRIGGERS];
 362     target_ulong tdata2[RV_MAX_TRIGGERS];
 363     target_ulong tdata3[RV_MAX_TRIGGERS];
 364     struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
 365     struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
 366     QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
 367     int64_t last_icount;
 368     bool itrigger_enabled;
 369
 370     /* machine specific rdtime callback */
 371     uint64_t (*rdtime_fn)(void *);
 372     void *rdtime_fn_arg;
 373
 374     /* machine specific AIA ireg read-modify-write callback */
 375 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
 376     ((((__xlen) & 0xff) << 24) | \
 377      (((__vgein) & 0x3f) << 20) | \
 378      (((__virt) & 0x1) << 18) | \
 379      (((__priv) & 0x3) << 16) | \
 380      (__isel & 0xffff))
 381 #define AIA_IREG_ISEL(__ireg)                  ((__ireg) & 0xffff)
 382 #define AIA_IREG_PRIV(__ireg)                  (((__ireg) >> 16) & 0x3)
 383 #define AIA_IREG_VIRT(__ireg)                  (((__ireg) >> 18) & 0x1)
 384 #define AIA_IREG_VGEIN(__ireg)                 (((__ireg) >> 20) & 0x3f)
 385 #define AIA_IREG_XLEN(__ireg)                  (((__ireg) >> 24) & 0xff)
 386     int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
 387         target_ulong *val, target_ulong new_val, target_ulong write_mask);
 388     void *aia_ireg_rmw_fn_arg[4];
 389
 390     /* True if in debugger mode.  */
 391     bool debugger;
 392
 393     /*
 394      * CSRs for PointerMasking extension
 395      */
 396     target_ulong mmte;
 397     target_ulong mpmmask;
 398     target_ulong mpmbase;
 399     target_ulong spmmask;
 400     target_ulong spmbase;
 401     target_ulong upmmask;
 402     target_ulong upmbase;
 403
 404     /* CSRs for execution environment configuration */
 405     uint64_t menvcfg;
 406     uint64_t mstateen[SMSTATEEN_MAX_COUNT];
 407     uint64_t hstateen[SMSTATEEN_MAX_COUNT];
 408     uint64_t sstateen[SMSTATEEN_MAX_COUNT];
 409     target_ulong senvcfg;
 410     uint64_t henvcfg;
 411 #endif
 412     target_ulong cur_pmmask;
 413     target_ulong cur_pmbase;
 414
 415     /* Fields from here on are preserved across CPU reset. */
 416     QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
 417     QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
 418     bool vstime_irq;
 419
 420     hwaddr kernel_addr;
 421     hwaddr fdt_addr;
 422
 423 #ifdef CONFIG_KVM
 424     /* kvm timer */
 425     bool kvm_timer_dirty;
 426     uint64_t kvm_timer_time;
 427     uint64_t kvm_timer_compare;
 428     uint64_t kvm_timer_state;
 429     uint64_t kvm_timer_frequency;
 430 #endif /* CONFIG_KVM */
 431 };
 432
 433 /*
 434  * RISCVCPU:
 435  * @env: #CPURISCVState
 436  *
 437  * A RISCV CPU.
 438  */
 439 struct ArchCPU {
 440     CPUState parent_obj;
 441
 442     CPURISCVState env;
 443
 444     char *dyn_csr_xml;
 445     char *dyn_vreg_xml;
 446
 447     /* Configuration Settings */
 448     RISCVCPUConfig cfg;
 449
 450     QEMUTimer *pmu_timer;
 451     /* A bitmask of Available programmable counters */
 452     uint32_t pmu_avail_ctrs;
 453     /* Mapping of events to counters */
 454     GHashTable *pmu_event_ctr_map;
 455 };
 456
 457 /**
 458  * RISCVCPUClass:
 459  * @parent_realize: The parent class' realize handler.
 460  * @parent_phases: The parent class' reset phase handlers.
 461  *
 462  * A RISCV CPU model.
 463  */
 464 struct RISCVCPUClass {
 465     CPUClass parent_class;
 466
 467     DeviceRealize parent_realize;
 468     ResettablePhases parent_phases;
 469 };
 470
 471 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 472 {
 473     return (env->misa_ext & ext) != 0;
 474 }
 475
 476 #include "cpu_user.h"
 477
 478 extern const char * const riscv_int_regnames[];
 479 extern const char * const riscv_int_regnamesh[];
 480 extern const char * const riscv_fpr_regnames[];
 481
 482 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 483 void riscv_cpu_do_interrupt(CPUState *cpu);
 484 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 485                                int cpuid, DumpState *s);
 486 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
 487                                int cpuid, DumpState *s);
 488 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 489 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 490 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 491 uint8_t riscv_cpu_default_priority(int irq);
 492 uint64_t riscv_cpu_all_pending(CPURISCVState *env);
 493 int riscv_cpu_mirq_pending(CPURISCVState *env);
 494 int riscv_cpu_sirq_pending(CPURISCVState *env);
 495 int riscv_cpu_vsirq_pending(CPURISCVState *env);
 496 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 497 target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
 498 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
 499 bool riscv_cpu_vector_enabled(CPURISCVState *env);
 500 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 501 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 502 G_NORETURN void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 503                                                MMUAccessType access_type,
 504                                                int mmu_idx, uintptr_t retaddr);
 505 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 506                         MMUAccessType access_type, int mmu_idx,
 507                         bool probe, uintptr_t retaddr);
 508 char *riscv_isa_string(RISCVCPU *cpu);
 509
 510 #define cpu_mmu_index riscv_cpu_mmu_index
 511
 512 #ifndef CONFIG_USER_ONLY
 513 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 514                                      vaddr addr, unsigned size,
 515                                      MMUAccessType access_type,
 516                                      int mmu_idx, MemTxAttrs attrs,
 517                                      MemTxResult response, uintptr_t retaddr);
 518 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 519 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 520 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 521 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
 522 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
 523                               uint64_t value);
 524 void riscv_cpu_interrupt(CPURISCVState *env);
 525 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 526 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
 527                              void *arg);
 528 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
 529                                    int (*rmw_fn)(void *arg,
 530                                                  target_ulong reg,
 531                                                  target_ulong *val,
 532                                                  target_ulong new_val,
 533                                                  target_ulong write_mask),
 534                                    void *rmw_fn_arg);
 535
 536 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
 537 #endif
 538 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 539
 540 void riscv_translate_init(void);
 541 G_NORETURN void riscv_raise_exception(CPURISCVState *env,
 542                                       uint32_t exception, uintptr_t pc);
 543
 544 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 545 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 546
 547 #include "exec/cpu-all.h"
 548
 549 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 550 FIELD(TB_FLAGS, FS, 3, 2)
 551 /* Vector flags */
 552 FIELD(TB_FLAGS, VS, 5, 2)
 553 FIELD(TB_FLAGS, LMUL, 7, 3)
 554 FIELD(TB_FLAGS, SEW, 10, 3)
 555 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
 556 FIELD(TB_FLAGS, VILL, 14, 1)
 557 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
 558 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 559 FIELD(TB_FLAGS, XL, 16, 2)
 560 /* If PointerMasking should be applied */
 561 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
 562 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
 563 FIELD(TB_FLAGS, VTA, 20, 1)
 564 FIELD(TB_FLAGS, VMA, 21, 1)
 565 /* Native debug itrigger */
 566 FIELD(TB_FLAGS, ITRIGGER, 22, 1)
 567 /* Virtual mode enabled */
 568 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
 569 FIELD(TB_FLAGS, PRIV, 24, 2)
 570 FIELD(TB_FLAGS, AXL, 26, 2)
 571
 572 #ifdef TARGET_RISCV32
 573 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 574 #else
 575 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 576 {
 577     return env->misa_mxl;
 578 }
 579 #endif
 580 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 581
 582 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
 583 {
 584     return &env_archcpu(env)->cfg;
 585 }
 586
 587 #if !defined(CONFIG_USER_ONLY)
 588 static inline int cpu_address_mode(CPURISCVState *env)
 589 {
 590     int mode = env->priv;
 591
 592     if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
 593         mode = get_field(env->mstatus, MSTATUS_MPP);
 594     }
 595     return mode;
 596 }
 597
 598 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode)
 599 {
 600     RISCVMXL xl = env->misa_mxl;
 601     /*
 602      * When emulating a 32-bit-only cpu, use RV32.
 603      * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 604      * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 605      * back to RV64 for lower privs.
 606      */
 607     if (xl != MXL_RV32) {
 608         switch (mode) {
 609         case PRV_M:
 610             break;
 611         case PRV_U:
 612             xl = get_field(env->mstatus, MSTATUS64_UXL);
 613             break;
 614         default: /* PRV_S */
 615             xl = get_field(env->mstatus, MSTATUS64_SXL);
 616             break;
 617         }
 618     }
 619     return xl;
 620 }
 621 #endif
 622
 623 #if defined(TARGET_RISCV32)
 624 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 625 #else
 626 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 627 {
 628 #if !defined(CONFIG_USER_ONLY)
 629     return cpu_get_xl(env, env->priv);
 630 #else
 631     return env->misa_mxl;
 632 #endif
 633 }
 634 #endif
 635
 636 #if defined(TARGET_RISCV32)
 637 #define cpu_address_xl(env)  ((void)(env), MXL_RV32)
 638 #else
 639 static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
 640 {
 641 #ifdef CONFIG_USER_ONLY
 642     return env->xl;
 643 #else
 644     int mode = cpu_address_mode(env);
 645
 646     return cpu_get_xl(env, mode);
 647 #endif
 648 }
 649 #endif
 650
 651 static inline int riscv_cpu_xlen(CPURISCVState *env)
 652 {
 653     return 16 << env->xl;
 654 }
 655
 656 #ifdef TARGET_RISCV32
 657 #define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
 658 #else
 659 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 660 {
 661 #ifdef CONFIG_USER_ONLY
 662     return env->misa_mxl;
 663 #else
 664     return get_field(env->mstatus, MSTATUS64_SXL);
 665 #endif
 666 }
 667 #endif
 668
 669 /*
 670  * Encode LMUL to lmul as follows:
 671  *     LMUL    vlmul    lmul
 672  *      1       000       0
 673  *      2       001       1
 674  *      4       010       2
 675  *      8       011       3
 676  *      -       100       -
 677  *     1/8      101      -3
 678  *     1/4      110      -2
 679  *     1/2      111      -1
 680  *
 681  * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
 682  * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
 683  *      => VLMAX = vlen >> (1 + 3 - (-3))
 684  *               = 256 >> 7
 685  *               = 2
 686  */
 687 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 688 {
 689     uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
 690     int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
 691     return cpu->cfg.vlen >> (sew + 3 - lmul);
 692 }
 693
 694 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 695                           uint64_t *cs_base, uint32_t *pflags);
 696
 697 void riscv_cpu_update_mask(CPURISCVState *env);
 698 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 699
 700 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
 701                            target_ulong *ret_value,
 702                            target_ulong new_value, target_ulong write_mask);
 703 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
 704                                  target_ulong *ret_value,
 705                                  target_ulong new_value,
 706                                  target_ulong write_mask);
 707
 708 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 709                                    target_ulong val)
 710 {
 711     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 712 }
 713
 714 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 715 {
 716     target_ulong val = 0;
 717     riscv_csrrw(env, csrno, &val, 0, 0);
 718     return val;
 719 }
 720
 721 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
 722                                                  int csrno);
 723 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 724                                             target_ulong *ret_value);
 725 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 726                                              target_ulong new_value);
 727 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 728                                           target_ulong *ret_value,
 729                                           target_ulong new_value,
 730                                           target_ulong write_mask);
 731
 732 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
 733                                 Int128 *ret_value,
 734                                 Int128 new_value, Int128 write_mask);
 735
 736 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
 737                                                Int128 *ret_value);
 738 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
 739                                              Int128 new_value);
 740
 741 typedef struct {
 742     const char *name;
 743     riscv_csr_predicate_fn predicate;
 744     riscv_csr_read_fn read;
 745     riscv_csr_write_fn write;
 746     riscv_csr_op_fn op;
 747     riscv_csr_read128_fn read128;
 748     riscv_csr_write128_fn write128;
 749     /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
 750     uint32_t min_priv_ver;
 751 } riscv_csr_operations;
 752
 753 /* CSR function table constants */
 754 enum {
 755     CSR_TABLE_SIZE = 0x1000
 756 };
 757
 758 /*
 759  * The event id are encoded based on the encoding specified in the
 760  * SBI specification v0.3
 761  */
 762
 763 enum riscv_pmu_event_idx {
 764     RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
 765     RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
 766     RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
 767     RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
 768     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
 769 };
 770
 771 /* used by tcg/tcg-cpu.c*/
 772 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
 773 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
 774 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
 775
 776 typedef struct RISCVCPUMultiExtConfig {
 777     const char *name;
 778     uint32_t offset;
 779     bool enabled;
 780 } RISCVCPUMultiExtConfig;
 781
 782 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
 783 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
 784 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
 785 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[];
 786 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
 787 extern Property riscv_cpu_options[];
 788
 789 typedef struct isa_ext_data {
 790     const char *name;
 791     int min_version;
 792     int ext_enable_offset;
 793 } RISCVIsaExtData;
 794 extern const RISCVIsaExtData isa_edata_arr[];
 795 char *riscv_cpu_get_name(RISCVCPU *cpu);
 796
 797 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 798 void riscv_add_satp_mode_properties(Object *obj);
 799 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
 800
 801 /* CSR function table */
 802 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 803
 804 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
 805
 806 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 807 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 808
 809 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 810
 811 uint8_t satp_mode_max_from_map(uint32_t map);
 812 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 813
 814 #endif /* RISCV_CPU_H */