target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "exec/cpu-defs.h"
  25 #include "fpu/softfloat-types.h"
  26
  27 #define TCG_GUEST_DEFAULT_MO 0
  28
  29 #define TYPE_RISCV_CPU "riscv-cpu"
  30
  31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  34
  35 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  36 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  37 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  38 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  39 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
  40 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  41 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  42 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  43
  44 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  45 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  46
  47 #if defined(TARGET_RISCV32)
  48 #define RVXLEN RV32
  49 #elif defined(TARGET_RISCV64)
  50 #define RVXLEN RV64
  51 #endif
  52
  53 #define RV(x) ((target_ulong)1 << (x - 'A'))
  54
  55 #define RVI RV('I')
  56 #define RVE RV('E') /* E and I are mutually exclusive */
  57 #define RVM RV('M')
  58 #define RVA RV('A')
  59 #define RVF RV('F')
  60 #define RVD RV('D')
  61 #define RVC RV('C')
  62 #define RVS RV('S')
  63 #define RVU RV('U')
  64 #define RVH RV('H')
  65
  66 /* S extension denotes that Supervisor mode exists, however it is possible
  67    to have a core that support S mode but does not have an MMU and there
  68    is currently no bit in misa to indicate whether an MMU exists or not
  69    so a cpu features bitfield is required, likewise for optional PMP support */
  70 enum {
  71     RISCV_FEATURE_MMU,
  72     RISCV_FEATURE_PMP,
  73     RISCV_FEATURE_MISA
  74 };
  75
  76 #define PRIV_VERSION_1_10_0 0x00011000
  77 #define PRIV_VERSION_1_11_0 0x00011100
  78
  79 #define TRANSLATE_PMP_FAIL 2
  80 #define TRANSLATE_FAIL 1
  81 #define TRANSLATE_SUCCESS 0
  82 #define MMU_USER_IDX 3
  83
  84 #define MAX_RISCV_PMPS (16)
  85
  86 typedef struct CPURISCVState CPURISCVState;
  87
  88 #include "pmp.h"
  89
  90 struct CPURISCVState {
  91     target_ulong gpr[32];
  92     uint64_t fpr[32]; /* assume both F and D extensions */
  93     target_ulong pc;
  94     target_ulong load_res;
  95     target_ulong load_val;
  96
  97     target_ulong frm;
  98
  99     target_ulong badaddr;
 100     target_ulong guest_phys_fault_addr;
 101
 102     target_ulong priv_ver;
 103     target_ulong misa;
 104     target_ulong misa_mask;
 105
 106     uint32_t features;
 107
 108 #ifdef CONFIG_USER_ONLY
 109     uint32_t elf_flags;
 110 #endif
 111
 112 #ifndef CONFIG_USER_ONLY
 113     target_ulong priv;
 114     /* This contains QEMU specific information about the virt state. */
 115     target_ulong virt;
 116     target_ulong resetvec;
 117
 118     target_ulong mhartid;
 119     target_ulong mstatus;
 120
 121     target_ulong mip;
 122
 123 #ifdef TARGET_RISCV32
 124     target_ulong mstatush;
 125 #endif
 126
 127     uint32_t miclaim;
 128
 129     target_ulong mie;
 130     target_ulong mideleg;
 131
 132     target_ulong sptbr;  /* until: priv-1.9.1 */
 133     target_ulong satp;   /* since: priv-1.10.0 */
 134     target_ulong sbadaddr;
 135     target_ulong mbadaddr;
 136     target_ulong medeleg;
 137
 138     target_ulong stvec;
 139     target_ulong sepc;
 140     target_ulong scause;
 141
 142     target_ulong mtvec;
 143     target_ulong mepc;
 144     target_ulong mcause;
 145     target_ulong mtval;  /* since: priv-1.10.0 */
 146
 147     /* Hypervisor CSRs */
 148     target_ulong hstatus;
 149     target_ulong hedeleg;
 150     target_ulong hideleg;
 151     target_ulong hcounteren;
 152     target_ulong htval;
 153     target_ulong htinst;
 154     target_ulong hgatp;
 155     uint64_t htimedelta;
 156
 157     /* Virtual CSRs */
 158     target_ulong vsstatus;
 159     target_ulong vstvec;
 160     target_ulong vsscratch;
 161     target_ulong vsepc;
 162     target_ulong vscause;
 163     target_ulong vstval;
 164     target_ulong vsatp;
 165 #ifdef TARGET_RISCV32
 166     target_ulong vsstatush;
 167 #endif
 168
 169     target_ulong mtval2;
 170     target_ulong mtinst;
 171
 172     /* HS Backup CSRs */
 173     target_ulong stvec_hs;
 174     target_ulong sscratch_hs;
 175     target_ulong sepc_hs;
 176     target_ulong scause_hs;
 177     target_ulong stval_hs;
 178     target_ulong satp_hs;
 179     target_ulong mstatus_hs;
 180 #ifdef TARGET_RISCV32
 181     target_ulong mstatush_hs;
 182 #endif
 183
 184     target_ulong scounteren;
 185     target_ulong mcounteren;
 186
 187     target_ulong sscratch;
 188     target_ulong mscratch;
 189
 190     /* temporary htif regs */
 191     uint64_t mfromhost;
 192     uint64_t mtohost;
 193     uint64_t timecmp;
 194
 195     /* physical memory protection */
 196     pmp_table_t pmp_state;
 197
 198     /* machine specific rdtime callback */
 199     uint64_t (*rdtime_fn)(void);
 200
 201     /* True if in debugger mode.  */
 202     bool debugger;
 203 #endif
 204
 205     float_status fp_status;
 206
 207     /* Fields from here on are preserved across CPU reset. */
 208     QEMUTimer *timer; /* Internal timer */
 209 };
 210
 211 #define RISCV_CPU_CLASS(klass) \
 212     OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
 213 #define RISCV_CPU(obj) \
 214     OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
 215 #define RISCV_CPU_GET_CLASS(obj) \
 216     OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
 217
 218 /**
 219  * RISCVCPUClass:
 220  * @parent_realize: The parent class' realize handler.
 221  * @parent_reset: The parent class' reset handler.
 222  *
 223  * A RISCV CPU model.
 224  */
 225 typedef struct RISCVCPUClass {
 226     /*< private >*/
 227     CPUClass parent_class;
 228     /*< public >*/
 229     DeviceRealize parent_realize;
 230     DeviceReset parent_reset;
 231 } RISCVCPUClass;
 232
 233 /**
 234  * RISCVCPU:
 235  * @env: #CPURISCVState
 236  *
 237  * A RISCV CPU.
 238  */
 239 typedef struct RISCVCPU {
 240     /*< private >*/
 241     CPUState parent_obj;
 242     /*< public >*/
 243     CPUNegativeOffsetState neg;
 244     CPURISCVState env;
 245
 246     /* Configuration Settings */
 247     struct {
 248         bool ext_i;
 249         bool ext_e;
 250         bool ext_g;
 251         bool ext_m;
 252         bool ext_a;
 253         bool ext_f;
 254         bool ext_d;
 255         bool ext_c;
 256         bool ext_s;
 257         bool ext_u;
 258         bool ext_h;
 259         bool ext_counters;
 260         bool ext_ifencei;
 261         bool ext_icsr;
 262
 263         char *priv_spec;
 264         char *user_spec;
 265         bool mmu;
 266         bool pmp;
 267     } cfg;
 268 } RISCVCPU;
 269
 270 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 271 {
 272     return (env->misa & ext) != 0;
 273 }
 274
 275 static inline bool riscv_feature(CPURISCVState *env, int feature)
 276 {
 277     return env->features & (1ULL << feature);
 278 }
 279
 280 #include "cpu_user.h"
 281 #include "cpu_bits.h"
 282
 283 extern const char * const riscv_int_regnames[];
 284 extern const char * const riscv_fpr_regnames[];
 285 extern const char * const riscv_excp_names[];
 286 extern const char * const riscv_intr_names[];
 287
 288 void riscv_cpu_do_interrupt(CPUState *cpu);
 289 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 290 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 291 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 292 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 293 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 294 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 295 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
 296 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
 297 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 298 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 299 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 300                                     MMUAccessType access_type, int mmu_idx,
 301                                     uintptr_t retaddr);
 302 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 303                         MMUAccessType access_type, int mmu_idx,
 304                         bool probe, uintptr_t retaddr);
 305 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 306                                      vaddr addr, unsigned size,
 307                                      MMUAccessType access_type,
 308                                      int mmu_idx, MemTxAttrs attrs,
 309                                      MemTxResult response, uintptr_t retaddr);
 310 char *riscv_isa_string(RISCVCPU *cpu);
 311 void riscv_cpu_list(void);
 312
 313 #define cpu_signal_handler riscv_cpu_signal_handler
 314 #define cpu_list riscv_cpu_list
 315 #define cpu_mmu_index riscv_cpu_mmu_index
 316
 317 #ifndef CONFIG_USER_ONLY
 318 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 319 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 320 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 321 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 322 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
 323 #endif
 324 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 325
 326 void riscv_translate_init(void);
 327 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 328 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 329                                          uint32_t exception, uintptr_t pc);
 330
 331 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 332 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 333
 334 #define TB_FLAGS_MMU_MASK   3
 335 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 336
 337 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 338                                         target_ulong *cs_base, uint32_t *flags)
 339 {
 340     *pc = env->pc;
 341     *cs_base = 0;
 342 #ifdef CONFIG_USER_ONLY
 343     *flags = TB_FLAGS_MSTATUS_FS;
 344 #else
 345     *flags = cpu_mmu_index(env, 0);
 346     if (riscv_cpu_fp_enabled(env)) {
 347         *flags |= env->mstatus & MSTATUS_FS;
 348     }
 349 #endif
 350 }
 351
 352 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 353                 target_ulong new_value, target_ulong write_mask);
 354 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
 355                       target_ulong new_value, target_ulong write_mask);
 356
 357 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 358                                    target_ulong val)
 359 {
 360     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 361 }
 362
 363 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 364 {
 365     target_ulong val = 0;
 366     riscv_csrrw(env, csrno, &val, 0, 0);
 367     return val;
 368 }
 369
 370 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
 371 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 372     target_ulong *ret_value);
 373 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 374     target_ulong new_value);
 375 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 376     target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
 377
 378 typedef struct {
 379     riscv_csr_predicate_fn predicate;
 380     riscv_csr_read_fn read;
 381     riscv_csr_write_fn write;
 382     riscv_csr_op_fn op;
 383 } riscv_csr_operations;
 384
 385 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 386 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 387
 388 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 389
 390 typedef CPURISCVState CPUArchState;
 391 typedef RISCVCPU ArchCPU;
 392
 393 #include "exec/cpu-all.h"
 394
 395 #endif /* RISCV_CPU_H */