4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "hw/core/cpu.h"
24 #include "hw/registerfields.h"
25 #include "exec/cpu-defs.h"
26 #include "qemu/cpu-float.h"
27 #include "qom/object.h"
28 #include "qemu/int128.h"
31 #define TCG_GUEST_DEFAULT_MO 0
33 #define TYPE_RISCV_CPU "riscv-cpu"
35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
50 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
52 #if defined(TARGET_RISCV32)
53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
54 #elif defined(TARGET_RISCV64)
55 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
58 #define RV(x) ((target_ulong)1 << (x - 'A'))
61 #define RVE RV('E') /* E and I are mutually exclusive */
73 /* S extension denotes that Supervisor mode exists, however it is possible
74 to have a core that support S mode but does not have an MMU and there
75 is currently no bit in misa to indicate whether an MMU exists or not
76 so a cpu features bitfield is required, likewise for optional PMP support */
85 #define PRIV_VERSION_1_10_0 0x00011000
86 #define PRIV_VERSION_1_11_0 0x00011100
88 #define VEXT_VERSION_1_00_0 0x00010000
94 TRANSLATE_G_STAGE_FAIL
97 #define MMU_USER_IDX 3
99 #define MAX_RISCV_PMPS (16)
101 typedef struct CPUArchState CPURISCVState
;
103 #if !defined(CONFIG_USER_ONLY)
107 #define RV_VLEN_MAX 1024
109 FIELD(VTYPE
, VLMUL
, 0, 3)
110 FIELD(VTYPE
, VSEW
, 3, 3)
111 FIELD(VTYPE
, VTA
, 6, 1)
112 FIELD(VTYPE
, VMA
, 7, 1)
113 FIELD(VTYPE
, VEDIV
, 8, 2)
114 FIELD(VTYPE
, RESERVED
, 10, sizeof(target_ulong
) * 8 - 11)
116 struct CPUArchState
{
117 target_ulong gpr
[32];
118 target_ulong gprh
[32]; /* 64 top bits of the 128-bit registers */
119 uint64_t fpr
[32]; /* assume both F and D extensions */
121 /* vector coprocessor state. */
122 uint64_t vreg
[32 * RV_VLEN_MAX
/ 64] QEMU_ALIGNED(16);
131 target_ulong load_res
;
132 target_ulong load_val
;
136 target_ulong badaddr
;
139 target_ulong guest_phys_fault_addr
;
141 target_ulong priv_ver
;
142 target_ulong bext_ver
;
143 target_ulong vext_ver
;
145 /* RISCVMXL, but uint32_t for vmstate migration */
146 uint32_t misa_mxl
; /* current mxl */
147 uint32_t misa_mxl_max
; /* max mxl for this cpu */
148 uint32_t misa_ext
; /* current extensions */
149 uint32_t misa_ext_mask
; /* max ext for this cpu */
150 uint32_t xl
; /* current xlen */
152 /* 128-bit helpers upper part return value */
157 #ifdef CONFIG_USER_ONLY
161 #ifndef CONFIG_USER_ONLY
163 /* This contains QEMU specific information about the virt state. */
166 target_ulong resetvec
;
168 target_ulong mhartid
;
170 * For RV32 this is 32-bit mstatus and 32-bit mstatush.
171 * For RV64 this is a 64-bit mstatus.
182 target_ulong satp
; /* since: priv-1.10.0 */
184 target_ulong medeleg
;
193 target_ulong mtval
; /* since: priv-1.10.0 */
195 /* Machine and Supervisor interrupt priorities */
200 target_ulong miselect
;
201 target_ulong siselect
;
203 /* Hypervisor CSRs */
204 target_ulong hstatus
;
205 target_ulong hedeleg
;
207 target_ulong hcounteren
;
215 /* Hypervisor controlled virtual interrupt priorities */
219 /* Upper 64-bits of 128-bit CSRs */
225 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
226 * For RV64 this is a 64-bit vsstatus.
230 target_ulong vsscratch
;
232 target_ulong vscause
;
236 /* AIA VS-mode CSRs */
237 target_ulong vsiselect
;
243 target_ulong stvec_hs
;
244 target_ulong sscratch_hs
;
245 target_ulong sepc_hs
;
246 target_ulong scause_hs
;
247 target_ulong stval_hs
;
248 target_ulong satp_hs
;
251 /* Signals whether the current exception occurred with two-stage address
252 translation active. */
253 bool two_stage_lookup
;
255 target_ulong scounteren
;
256 target_ulong mcounteren
;
258 target_ulong sscratch
;
259 target_ulong mscratch
;
261 /* temporary htif regs */
266 /* physical memory protection */
267 pmp_table_t pmp_state
;
268 target_ulong mseccfg
;
270 /* machine specific rdtime callback */
271 uint64_t (*rdtime_fn
)(uint32_t);
272 uint32_t rdtime_fn_arg
;
274 /* machine specific AIA ireg read-modify-write callback */
275 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
276 ((((__xlen) & 0xff) << 24) | \
277 (((__vgein) & 0x3f) << 20) | \
278 (((__virt) & 0x1) << 18) | \
279 (((__priv) & 0x3) << 16) | \
281 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
282 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
283 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
284 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
285 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
286 int (*aia_ireg_rmw_fn
[4])(void *arg
, target_ulong reg
,
287 target_ulong
*val
, target_ulong new_val
, target_ulong write_mask
);
288 void *aia_ireg_rmw_fn_arg
[4];
290 /* True if in debugger mode. */
294 * CSRs for PointerMasking extension
297 target_ulong mpmmask
;
298 target_ulong mpmbase
;
299 target_ulong spmmask
;
300 target_ulong spmbase
;
301 target_ulong upmmask
;
302 target_ulong upmbase
;
304 target_ulong cur_pmmask
;
305 target_ulong cur_pmbase
;
307 float_status fp_status
;
309 /* Fields from here on are preserved across CPU reset. */
310 QEMUTimer
*timer
; /* Internal timer */
316 bool kvm_timer_dirty
;
317 uint64_t kvm_timer_time
;
318 uint64_t kvm_timer_compare
;
319 uint64_t kvm_timer_state
;
320 uint64_t kvm_timer_frequency
;
323 OBJECT_DECLARE_CPU_TYPE(RISCVCPU
, RISCVCPUClass
, RISCV_CPU
)
327 * @parent_realize: The parent class' realize handler.
328 * @parent_reset: The parent class' reset handler.
332 struct RISCVCPUClass
{
334 CPUClass parent_class
;
336 DeviceRealize parent_realize
;
337 DeviceReset parent_reset
;
340 struct RISCVCPUConfig
{
373 /* Vendor-specific custom extensions */
374 bool ext_XVentanaCondOps
;
389 typedef struct RISCVCPUConfig RISCVCPUConfig
;
393 * @env: #CPURISCVState
401 CPUNegativeOffsetState neg
;
407 /* Configuration Settings */
411 static inline int riscv_has_ext(CPURISCVState
*env
, target_ulong ext
)
413 return (env
->misa_ext
& ext
) != 0;
416 static inline bool riscv_feature(CPURISCVState
*env
, int feature
)
418 return env
->features
& (1ULL << feature
);
421 static inline void riscv_set_feature(CPURISCVState
*env
, int feature
)
423 env
->features
|= (1ULL << feature
);
426 #include "cpu_user.h"
428 extern const char * const riscv_int_regnames
[];
429 extern const char * const riscv_int_regnamesh
[];
430 extern const char * const riscv_fpr_regnames
[];
432 const char *riscv_cpu_get_trap_name(target_ulong cause
, bool async
);
433 void riscv_cpu_do_interrupt(CPUState
*cpu
);
434 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cs
,
435 int cpuid
, void *opaque
);
436 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cs
,
437 int cpuid
, void *opaque
);
438 int riscv_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
439 int riscv_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
440 int riscv_cpu_hviprio_index2irq(int index
, int *out_irq
, int *out_rdzero
);
441 uint8_t riscv_cpu_default_priority(int irq
);
442 int riscv_cpu_mirq_pending(CPURISCVState
*env
);
443 int riscv_cpu_sirq_pending(CPURISCVState
*env
);
444 int riscv_cpu_vsirq_pending(CPURISCVState
*env
);
445 bool riscv_cpu_fp_enabled(CPURISCVState
*env
);
446 target_ulong
riscv_cpu_get_geilen(CPURISCVState
*env
);
447 void riscv_cpu_set_geilen(CPURISCVState
*env
, target_ulong geilen
);
448 bool riscv_cpu_vector_enabled(CPURISCVState
*env
);
449 bool riscv_cpu_virt_enabled(CPURISCVState
*env
);
450 void riscv_cpu_set_virt_enabled(CPURISCVState
*env
, bool enable
);
451 bool riscv_cpu_two_stage_lookup(int mmu_idx
);
452 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
);
453 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
454 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
455 MMUAccessType access_type
, int mmu_idx
,
456 uintptr_t retaddr
) QEMU_NORETURN
;
457 bool riscv_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
458 MMUAccessType access_type
, int mmu_idx
,
459 bool probe
, uintptr_t retaddr
);
460 void riscv_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
461 vaddr addr
, unsigned size
,
462 MMUAccessType access_type
,
463 int mmu_idx
, MemTxAttrs attrs
,
464 MemTxResult response
, uintptr_t retaddr
);
465 char *riscv_isa_string(RISCVCPU
*cpu
);
466 void riscv_cpu_list(void);
468 #define cpu_list riscv_cpu_list
469 #define cpu_mmu_index riscv_cpu_mmu_index
471 #ifndef CONFIG_USER_ONLY
472 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
);
473 void riscv_cpu_swap_hypervisor_regs(CPURISCVState
*env
);
474 int riscv_cpu_claim_interrupts(RISCVCPU
*cpu
, uint64_t interrupts
);
475 uint64_t riscv_cpu_update_mip(RISCVCPU
*cpu
, uint64_t mask
, uint64_t value
);
476 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
477 void riscv_cpu_set_rdtime_fn(CPURISCVState
*env
, uint64_t (*fn
)(uint32_t),
479 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState
*env
, uint32_t priv
,
480 int (*rmw_fn
)(void *arg
,
483 target_ulong new_val
,
484 target_ulong write_mask
),
487 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
);
489 void riscv_translate_init(void);
490 void QEMU_NORETURN
riscv_raise_exception(CPURISCVState
*env
,
491 uint32_t exception
, uintptr_t pc
);
493 target_ulong
riscv_cpu_get_fflags(CPURISCVState
*env
);
494 void riscv_cpu_set_fflags(CPURISCVState
*env
, target_ulong
);
496 #define TB_FLAGS_PRIV_MMU_MASK 3
497 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
498 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
499 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
501 #include "exec/cpu-all.h"
503 FIELD(TB_FLAGS
, MEM_IDX
, 0, 3)
504 FIELD(TB_FLAGS
, LMUL
, 3, 3)
505 FIELD(TB_FLAGS
, SEW
, 6, 3)
506 /* Skip MSTATUS_VS (0x600) bits */
507 FIELD(TB_FLAGS
, VL_EQ_VLMAX
, 11, 1)
508 FIELD(TB_FLAGS
, VILL
, 12, 1)
509 /* Skip MSTATUS_FS (0x6000) bits */
510 /* Is a Hypervisor instruction load/store allowed? */
511 FIELD(TB_FLAGS
, HLSX
, 15, 1)
512 FIELD(TB_FLAGS
, MSTATUS_HS_FS
, 16, 2)
513 FIELD(TB_FLAGS
, MSTATUS_HS_VS
, 18, 2)
514 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
515 FIELD(TB_FLAGS
, XL
, 20, 2)
516 /* If PointerMasking should be applied */
517 FIELD(TB_FLAGS
, PM_MASK_ENABLED
, 22, 1)
518 FIELD(TB_FLAGS
, PM_BASE_ENABLED
, 23, 1)
520 #ifdef TARGET_RISCV32
521 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
523 static inline RISCVMXL
riscv_cpu_mxl(CPURISCVState
*env
)
525 return env
->misa_mxl
;
528 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
530 #if defined(TARGET_RISCV32)
531 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
533 static inline RISCVMXL
cpu_recompute_xl(CPURISCVState
*env
)
535 RISCVMXL xl
= env
->misa_mxl
;
536 #if !defined(CONFIG_USER_ONLY)
538 * When emulating a 32-bit-only cpu, use RV32.
539 * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
540 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
541 * back to RV64 for lower privs.
543 if (xl
!= MXL_RV32
) {
548 xl
= get_field(env
->mstatus
, MSTATUS64_UXL
);
550 default: /* PRV_S | PRV_H */
551 xl
= get_field(env
->mstatus
, MSTATUS64_SXL
);
560 static inline int riscv_cpu_xlen(CPURISCVState
*env
)
562 return 16 << env
->xl
;
565 #ifdef TARGET_RISCV32
566 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
568 static inline RISCVMXL
riscv_cpu_sxl(CPURISCVState
*env
)
570 #ifdef CONFIG_USER_ONLY
571 return env
->misa_mxl
;
573 return get_field(env
->mstatus
, MSTATUS64_SXL
);
579 * Encode LMUL to lmul as follows:
590 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
591 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
592 * => VLMAX = vlen >> (1 + 3 - (-3))
596 static inline uint32_t vext_get_vlmax(RISCVCPU
*cpu
, target_ulong vtype
)
598 uint8_t sew
= FIELD_EX64(vtype
, VTYPE
, VSEW
);
599 int8_t lmul
= sextract32(FIELD_EX64(vtype
, VTYPE
, VLMUL
), 0, 3);
600 return cpu
->cfg
.vlen
>> (sew
+ 3 - lmul
);
603 void cpu_get_tb_cpu_state(CPURISCVState
*env
, target_ulong
*pc
,
604 target_ulong
*cs_base
, uint32_t *pflags
);
606 void riscv_cpu_update_mask(CPURISCVState
*env
);
608 RISCVException
riscv_csrrw(CPURISCVState
*env
, int csrno
,
609 target_ulong
*ret_value
,
610 target_ulong new_value
, target_ulong write_mask
);
611 RISCVException
riscv_csrrw_debug(CPURISCVState
*env
, int csrno
,
612 target_ulong
*ret_value
,
613 target_ulong new_value
,
614 target_ulong write_mask
);
616 static inline void riscv_csr_write(CPURISCVState
*env
, int csrno
,
619 riscv_csrrw(env
, csrno
, NULL
, val
, MAKE_64BIT_MASK(0, TARGET_LONG_BITS
));
622 static inline target_ulong
riscv_csr_read(CPURISCVState
*env
, int csrno
)
624 target_ulong val
= 0;
625 riscv_csrrw(env
, csrno
, &val
, 0, 0);
629 typedef RISCVException (*riscv_csr_predicate_fn
)(CPURISCVState
*env
,
631 typedef RISCVException (*riscv_csr_read_fn
)(CPURISCVState
*env
, int csrno
,
632 target_ulong
*ret_value
);
633 typedef RISCVException (*riscv_csr_write_fn
)(CPURISCVState
*env
, int csrno
,
634 target_ulong new_value
);
635 typedef RISCVException (*riscv_csr_op_fn
)(CPURISCVState
*env
, int csrno
,
636 target_ulong
*ret_value
,
637 target_ulong new_value
,
638 target_ulong write_mask
);
640 RISCVException
riscv_csrrw_i128(CPURISCVState
*env
, int csrno
,
642 Int128 new_value
, Int128 write_mask
);
644 typedef RISCVException (*riscv_csr_read128_fn
)(CPURISCVState
*env
, int csrno
,
646 typedef RISCVException (*riscv_csr_write128_fn
)(CPURISCVState
*env
, int csrno
,
651 riscv_csr_predicate_fn predicate
;
652 riscv_csr_read_fn read
;
653 riscv_csr_write_fn write
;
655 riscv_csr_read128_fn read128
;
656 riscv_csr_write128_fn write128
;
657 } riscv_csr_operations
;
659 /* CSR function table constants */
661 CSR_TABLE_SIZE
= 0x1000
664 /* CSR function table */
665 extern riscv_csr_operations csr_ops
[CSR_TABLE_SIZE
];
667 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
);
668 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
);
670 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
);
672 #endif /* RISCV_CPU_H */