2 * RISC-V CPU helpers for qemu.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
28 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
)
30 #ifdef CONFIG_USER_ONLY
37 #ifndef CONFIG_USER_ONLY
38 static int riscv_cpu_local_irq_pending(CPURISCVState
*env
)
40 target_ulong mstatus_mie
= get_field(env
->mstatus
, MSTATUS_MIE
);
41 target_ulong mstatus_sie
= get_field(env
->mstatus
, MSTATUS_SIE
);
42 target_ulong pending
= env
->mip
& env
->mie
;
43 target_ulong mie
= env
->priv
< PRV_M
|| (env
->priv
== PRV_M
&& mstatus_mie
);
44 target_ulong sie
= env
->priv
< PRV_S
|| (env
->priv
== PRV_S
&& mstatus_sie
);
45 target_ulong irqs
= (pending
& ~env
->mideleg
& -mie
) |
46 (pending
& env
->mideleg
& -sie
);
49 return ctz64(irqs
); /* since non-zero */
51 return EXCP_NONE
; /* indicates no pending interrupt */
56 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
58 #if !defined(CONFIG_USER_ONLY)
59 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
60 RISCVCPU
*cpu
= RISCV_CPU(cs
);
61 CPURISCVState
*env
= &cpu
->env
;
62 int interruptno
= riscv_cpu_local_irq_pending(env
);
63 if (interruptno
>= 0) {
64 cs
->exception_index
= RISCV_EXCP_INT_FLAG
| interruptno
;
65 riscv_cpu_do_interrupt(cs
);
73 #if !defined(CONFIG_USER_ONLY)
75 /* Return true is floating point support is currently enabled */
76 bool riscv_cpu_fp_enabled(CPURISCVState
*env
)
78 if (env
->mstatus
& MSTATUS_FS
) {
85 bool riscv_cpu_virt_enabled(CPURISCVState
*env
)
87 if (!riscv_has_ext(env
, RVH
)) {
91 return get_field(env
->virt
, VIRT_ONOFF
);
94 void riscv_cpu_set_virt_enabled(CPURISCVState
*env
, bool enable
)
96 if (!riscv_has_ext(env
, RVH
)) {
100 env
->virt
= set_field(env
->virt
, VIRT_ONOFF
, enable
);
103 int riscv_cpu_claim_interrupts(RISCVCPU
*cpu
, uint32_t interrupts
)
105 CPURISCVState
*env
= &cpu
->env
;
106 if (env
->miclaim
& interrupts
) {
109 env
->miclaim
|= interrupts
;
114 uint32_t riscv_cpu_update_mip(RISCVCPU
*cpu
, uint32_t mask
, uint32_t value
)
116 CPURISCVState
*env
= &cpu
->env
;
117 CPUState
*cs
= CPU(cpu
);
118 uint32_t old
= env
->mip
;
121 if (!qemu_mutex_iothread_locked()) {
123 qemu_mutex_lock_iothread();
126 env
->mip
= (env
->mip
& ~mask
) | (value
& mask
);
129 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
131 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
135 qemu_mutex_unlock_iothread();
141 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
)
143 if (newpriv
> PRV_M
) {
144 g_assert_not_reached();
146 if (newpriv
== PRV_H
) {
149 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
153 * Clear the load reservation - otherwise a reservation placed in one
154 * context/process can be used by another, resulting in an SC succeeding
155 * incorrectly. Version 2.2 of the ISA specification explicitly requires
156 * this behaviour, while later revisions say that the kernel "should" use
157 * an SC instruction to force the yielding of a load reservation on a
158 * preemptive context switch. As a result, do both.
163 /* get_physical_address - get the physical address for this virtual address
165 * Do a page table walk to obtain the physical address corresponding to a
166 * virtual address. Returns 0 if the translation was successful
168 * Adapted from Spike's mmu_t::translate and mmu_t::walk
171 static int get_physical_address(CPURISCVState
*env
, hwaddr
*physical
,
172 int *prot
, target_ulong addr
,
173 int access_type
, int mmu_idx
)
175 /* NOTE: the env->pc value visible here will not be
176 * correct, but the value visible to the exception handler
177 * (riscv_cpu_do_interrupt) is correct */
179 MemTxAttrs attrs
= MEMTXATTRS_UNSPECIFIED
;
182 if (mode
== PRV_M
&& access_type
!= MMU_INST_FETCH
) {
183 if (get_field(env
->mstatus
, MSTATUS_MPRV
)) {
184 mode
= get_field(env
->mstatus
, MSTATUS_MPP
);
188 if (mode
== PRV_M
|| !riscv_feature(env
, RISCV_FEATURE_MMU
)) {
190 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
191 return TRANSLATE_SUCCESS
;
197 int levels
, ptidxbits
, ptesize
, vm
, sum
;
198 int mxr
= get_field(env
->mstatus
, MSTATUS_MXR
);
200 if (env
->priv_ver
>= PRIV_VERSION_1_10_0
) {
201 base
= (hwaddr
)get_field(env
->satp
, SATP_PPN
) << PGSHIFT
;
202 sum
= get_field(env
->mstatus
, MSTATUS_SUM
);
203 vm
= get_field(env
->satp
, SATP_MODE
);
206 levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
208 levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
210 levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
212 levels
= 5; ptidxbits
= 9; ptesize
= 8; break;
215 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
216 return TRANSLATE_SUCCESS
;
218 g_assert_not_reached();
221 base
= (hwaddr
)(env
->sptbr
) << PGSHIFT
;
222 sum
= !get_field(env
->mstatus
, MSTATUS_PUM
);
223 vm
= get_field(env
->mstatus
, MSTATUS_VM
);
226 levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
228 levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
230 levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
233 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
234 return TRANSLATE_SUCCESS
;
236 g_assert_not_reached();
240 CPUState
*cs
= env_cpu(env
);
241 int va_bits
= PGSHIFT
+ levels
* ptidxbits
;
242 target_ulong mask
= (1L << (TARGET_LONG_BITS
- (va_bits
- 1))) - 1;
243 target_ulong masked_msbs
= (addr
>> (va_bits
- 1)) & mask
;
244 if (masked_msbs
!= 0 && masked_msbs
!= mask
) {
245 return TRANSLATE_FAIL
;
248 int ptshift
= (levels
- 1) * ptidxbits
;
251 #if !TCG_OVERSIZED_GUEST
254 for (i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
255 target_ulong idx
= (addr
>> (PGSHIFT
+ ptshift
)) &
256 ((1 << ptidxbits
) - 1);
258 /* check that physical address of PTE is legal */
259 hwaddr pte_addr
= base
+ idx
* ptesize
;
261 if (riscv_feature(env
, RISCV_FEATURE_PMP
) &&
262 !pmp_hart_has_privs(env
, pte_addr
, sizeof(target_ulong
),
263 1 << MMU_DATA_LOAD
, PRV_S
)) {
264 return TRANSLATE_PMP_FAIL
;
267 #if defined(TARGET_RISCV32)
268 target_ulong pte
= address_space_ldl(cs
->as
, pte_addr
, attrs
, &res
);
269 #elif defined(TARGET_RISCV64)
270 target_ulong pte
= address_space_ldq(cs
->as
, pte_addr
, attrs
, &res
);
272 if (res
!= MEMTX_OK
) {
273 return TRANSLATE_FAIL
;
276 hwaddr ppn
= pte
>> PTE_PPN_SHIFT
;
278 if (!(pte
& PTE_V
)) {
280 return TRANSLATE_FAIL
;
281 } else if (!(pte
& (PTE_R
| PTE_W
| PTE_X
))) {
282 /* Inner PTE, continue walking */
283 base
= ppn
<< PGSHIFT
;
284 } else if ((pte
& (PTE_R
| PTE_W
| PTE_X
)) == PTE_W
) {
285 /* Reserved leaf PTE flags: PTE_W */
286 return TRANSLATE_FAIL
;
287 } else if ((pte
& (PTE_R
| PTE_W
| PTE_X
)) == (PTE_W
| PTE_X
)) {
288 /* Reserved leaf PTE flags: PTE_W + PTE_X */
289 return TRANSLATE_FAIL
;
290 } else if ((pte
& PTE_U
) && ((mode
!= PRV_U
) &&
291 (!sum
|| access_type
== MMU_INST_FETCH
))) {
292 /* User PTE flags when not U mode and mstatus.SUM is not set,
293 or the access type is an instruction fetch */
294 return TRANSLATE_FAIL
;
295 } else if (!(pte
& PTE_U
) && (mode
!= PRV_S
)) {
296 /* Supervisor PTE flags when not S mode */
297 return TRANSLATE_FAIL
;
298 } else if (ppn
& ((1ULL << ptshift
) - 1)) {
300 return TRANSLATE_FAIL
;
301 } else if (access_type
== MMU_DATA_LOAD
&& !((pte
& PTE_R
) ||
302 ((pte
& PTE_X
) && mxr
))) {
303 /* Read access check failed */
304 return TRANSLATE_FAIL
;
305 } else if (access_type
== MMU_DATA_STORE
&& !(pte
& PTE_W
)) {
306 /* Write access check failed */
307 return TRANSLATE_FAIL
;
308 } else if (access_type
== MMU_INST_FETCH
&& !(pte
& PTE_X
)) {
309 /* Fetch access check failed */
310 return TRANSLATE_FAIL
;
312 /* if necessary, set accessed and dirty bits. */
313 target_ulong updated_pte
= pte
| PTE_A
|
314 (access_type
== MMU_DATA_STORE
? PTE_D
: 0);
316 /* Page table updates need to be atomic with MTTCG enabled */
317 if (updated_pte
!= pte
) {
319 * - if accessed or dirty bits need updating, and the PTE is
320 * in RAM, then we do so atomically with a compare and swap.
321 * - if the PTE is in IO space or ROM, then it can't be updated
322 * and we return TRANSLATE_FAIL.
323 * - if the PTE changed by the time we went to update it, then
324 * it is no longer valid and we must re-walk the page table.
327 hwaddr l
= sizeof(target_ulong
), addr1
;
328 mr
= address_space_translate(cs
->as
, pte_addr
,
329 &addr1
, &l
, false, MEMTXATTRS_UNSPECIFIED
);
330 if (memory_region_is_ram(mr
)) {
331 target_ulong
*pte_pa
=
332 qemu_map_ram_ptr(mr
->ram_block
, addr1
);
333 #if TCG_OVERSIZED_GUEST
334 /* MTTCG is not enabled on oversized TCG guests so
335 * page table updates do not need to be atomic */
336 *pte_pa
= pte
= updated_pte
;
338 target_ulong old_pte
=
339 atomic_cmpxchg(pte_pa
, pte
, updated_pte
);
340 if (old_pte
!= pte
) {
347 /* misconfigured PTE in ROM (AD bits are not preset) or
348 * PTE is in IO space and can't be updated atomically */
349 return TRANSLATE_FAIL
;
353 /* for superpage mappings, make a fake leaf PTE for the TLB's
355 target_ulong vpn
= addr
>> PGSHIFT
;
356 *physical
= (ppn
| (vpn
& ((1L << ptshift
) - 1))) << PGSHIFT
;
358 /* set permissions on the TLB entry */
359 if ((pte
& PTE_R
) || ((pte
& PTE_X
) && mxr
)) {
365 /* add write permission on stores or if the page is already dirty,
366 so that we TLB miss on later writes to update the dirty bit */
368 (access_type
== MMU_DATA_STORE
|| (pte
& PTE_D
))) {
371 return TRANSLATE_SUCCESS
;
374 return TRANSLATE_FAIL
;
377 static void raise_mmu_exception(CPURISCVState
*env
, target_ulong address
,
378 MMUAccessType access_type
, bool pmp_violation
)
380 CPUState
*cs
= env_cpu(env
);
381 int page_fault_exceptions
=
382 (env
->priv_ver
>= PRIV_VERSION_1_10_0
) &&
383 get_field(env
->satp
, SATP_MODE
) != VM_1_10_MBARE
&&
385 switch (access_type
) {
387 cs
->exception_index
= page_fault_exceptions
?
388 RISCV_EXCP_INST_PAGE_FAULT
: RISCV_EXCP_INST_ACCESS_FAULT
;
391 cs
->exception_index
= page_fault_exceptions
?
392 RISCV_EXCP_LOAD_PAGE_FAULT
: RISCV_EXCP_LOAD_ACCESS_FAULT
;
395 cs
->exception_index
= page_fault_exceptions
?
396 RISCV_EXCP_STORE_PAGE_FAULT
: RISCV_EXCP_STORE_AMO_ACCESS_FAULT
;
399 g_assert_not_reached();
401 env
->badaddr
= address
;
404 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
406 RISCVCPU
*cpu
= RISCV_CPU(cs
);
409 int mmu_idx
= cpu_mmu_index(&cpu
->env
, false);
411 if (get_physical_address(&cpu
->env
, &phys_addr
, &prot
, addr
, 0, mmu_idx
)) {
417 void riscv_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
418 vaddr addr
, unsigned size
,
419 MMUAccessType access_type
,
420 int mmu_idx
, MemTxAttrs attrs
,
421 MemTxResult response
, uintptr_t retaddr
)
423 RISCVCPU
*cpu
= RISCV_CPU(cs
);
424 CPURISCVState
*env
= &cpu
->env
;
426 if (access_type
== MMU_DATA_STORE
) {
427 cs
->exception_index
= RISCV_EXCP_STORE_AMO_ACCESS_FAULT
;
429 cs
->exception_index
= RISCV_EXCP_LOAD_ACCESS_FAULT
;
433 riscv_raise_exception(&cpu
->env
, cs
->exception_index
, retaddr
);
436 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
437 MMUAccessType access_type
, int mmu_idx
,
440 RISCVCPU
*cpu
= RISCV_CPU(cs
);
441 CPURISCVState
*env
= &cpu
->env
;
442 switch (access_type
) {
444 cs
->exception_index
= RISCV_EXCP_INST_ADDR_MIS
;
447 cs
->exception_index
= RISCV_EXCP_LOAD_ADDR_MIS
;
450 cs
->exception_index
= RISCV_EXCP_STORE_AMO_ADDR_MIS
;
453 g_assert_not_reached();
456 riscv_raise_exception(env
, cs
->exception_index
, retaddr
);
460 bool riscv_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
461 MMUAccessType access_type
, int mmu_idx
,
462 bool probe
, uintptr_t retaddr
)
464 RISCVCPU
*cpu
= RISCV_CPU(cs
);
465 CPURISCVState
*env
= &cpu
->env
;
466 #ifndef CONFIG_USER_ONLY
469 bool pmp_violation
= false;
470 int ret
= TRANSLATE_FAIL
;
473 qemu_log_mask(CPU_LOG_MMU
, "%s ad %" VADDR_PRIx
" rw %d mmu_idx %d\n",
474 __func__
, address
, access_type
, mmu_idx
);
476 ret
= get_physical_address(env
, &pa
, &prot
, address
, access_type
, mmu_idx
);
478 if (mode
== PRV_M
&& access_type
!= MMU_INST_FETCH
) {
479 if (get_field(env
->mstatus
, MSTATUS_MPRV
)) {
480 mode
= get_field(env
->mstatus
, MSTATUS_MPP
);
484 qemu_log_mask(CPU_LOG_MMU
,
485 "%s address=%" VADDR_PRIx
" ret %d physical " TARGET_FMT_plx
486 " prot %d\n", __func__
, address
, ret
, pa
, prot
);
488 if (riscv_feature(env
, RISCV_FEATURE_PMP
) &&
489 (ret
== TRANSLATE_SUCCESS
) &&
490 !pmp_hart_has_privs(env
, pa
, size
, 1 << access_type
, mode
)) {
491 ret
= TRANSLATE_PMP_FAIL
;
493 if (ret
== TRANSLATE_PMP_FAIL
) {
494 pmp_violation
= true;
496 if (ret
== TRANSLATE_SUCCESS
) {
497 tlb_set_page(cs
, address
& TARGET_PAGE_MASK
, pa
& TARGET_PAGE_MASK
,
498 prot
, mmu_idx
, TARGET_PAGE_SIZE
);
503 raise_mmu_exception(env
, address
, access_type
, pmp_violation
);
504 riscv_raise_exception(env
, cs
->exception_index
, retaddr
);
507 switch (access_type
) {
509 cs
->exception_index
= RISCV_EXCP_INST_PAGE_FAULT
;
512 cs
->exception_index
= RISCV_EXCP_LOAD_PAGE_FAULT
;
515 cs
->exception_index
= RISCV_EXCP_STORE_PAGE_FAULT
;
518 g_assert_not_reached();
520 env
->badaddr
= address
;
521 cpu_loop_exit_restore(cs
, retaddr
);
528 * Adapted from Spike's processor_t::take_trap.
531 void riscv_cpu_do_interrupt(CPUState
*cs
)
533 #if !defined(CONFIG_USER_ONLY)
535 RISCVCPU
*cpu
= RISCV_CPU(cs
);
536 CPURISCVState
*env
= &cpu
->env
;
538 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
539 * so we mask off the MSB and separate into trap type and cause.
541 bool async
= !!(cs
->exception_index
& RISCV_EXCP_INT_FLAG
);
542 target_ulong cause
= cs
->exception_index
& RISCV_EXCP_INT_MASK
;
543 target_ulong deleg
= async
? env
->mideleg
: env
->medeleg
;
544 target_ulong tval
= 0;
546 static const int ecall_cause_map
[] = {
547 [PRV_U
] = RISCV_EXCP_U_ECALL
,
548 [PRV_S
] = RISCV_EXCP_S_ECALL
,
549 [PRV_H
] = RISCV_EXCP_VS_ECALL
,
550 [PRV_M
] = RISCV_EXCP_M_ECALL
554 /* set tval to badaddr for traps with address information */
556 case RISCV_EXCP_INST_GUEST_PAGE_FAULT
:
557 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
:
558 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
:
559 case RISCV_EXCP_INST_ADDR_MIS
:
560 case RISCV_EXCP_INST_ACCESS_FAULT
:
561 case RISCV_EXCP_LOAD_ADDR_MIS
:
562 case RISCV_EXCP_STORE_AMO_ADDR_MIS
:
563 case RISCV_EXCP_LOAD_ACCESS_FAULT
:
564 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT
:
565 case RISCV_EXCP_INST_PAGE_FAULT
:
566 case RISCV_EXCP_LOAD_PAGE_FAULT
:
567 case RISCV_EXCP_STORE_PAGE_FAULT
:
573 /* ecall is dispatched as one cause so translate based on mode */
574 if (cause
== RISCV_EXCP_U_ECALL
) {
575 assert(env
->priv
<= 3);
576 cause
= ecall_cause_map
[env
->priv
];
580 trace_riscv_trap(env
->mhartid
, async
, cause
, env
->pc
, tval
, cause
< 23 ?
581 (async
? riscv_intr_names
: riscv_excp_names
)[cause
] : "(unknown)");
583 if (env
->priv
<= PRV_S
&&
584 cause
< TARGET_LONG_BITS
&& ((deleg
>> cause
) & 1)) {
585 /* handle the trap in S-mode */
586 target_ulong s
= env
->mstatus
;
587 s
= set_field(s
, MSTATUS_SPIE
, env
->priv_ver
>= PRIV_VERSION_1_10_0
?
588 get_field(s
, MSTATUS_SIE
) : get_field(s
, MSTATUS_UIE
<< env
->priv
));
589 s
= set_field(s
, MSTATUS_SPP
, env
->priv
);
590 s
= set_field(s
, MSTATUS_SIE
, 0);
592 env
->scause
= cause
| ((target_ulong
)async
<< (TARGET_LONG_BITS
- 1));
594 env
->sbadaddr
= tval
;
595 env
->pc
= (env
->stvec
>> 2 << 2) +
596 ((async
&& (env
->stvec
& 3) == 1) ? cause
* 4 : 0);
597 riscv_cpu_set_mode(env
, PRV_S
);
599 /* handle the trap in M-mode */
600 target_ulong s
= env
->mstatus
;
601 s
= set_field(s
, MSTATUS_MPIE
, env
->priv_ver
>= PRIV_VERSION_1_10_0
?
602 get_field(s
, MSTATUS_MIE
) : get_field(s
, MSTATUS_UIE
<< env
->priv
));
603 s
= set_field(s
, MSTATUS_MPP
, env
->priv
);
604 s
= set_field(s
, MSTATUS_MIE
, 0);
606 env
->mcause
= cause
| ~(((target_ulong
)-1) >> async
);
608 env
->mbadaddr
= tval
;
609 env
->pc
= (env
->mtvec
>> 2 << 2) +
610 ((async
&& (env
->mtvec
& 3) == 1) ? cause
* 4 : 0);
611 riscv_cpu_set_mode(env
, PRV_M
);
614 /* NOTE: it is not necessary to yield load reservations here. It is only
615 * necessary for an SC from "another hart" to cause a load reservation
616 * to be yielded. Refer to the memory consistency model section of the
617 * RISC-V ISA Specification.
621 cs
->exception_index
= EXCP_NONE
; /* mark handled to qemu */