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target/riscv: Legalize MPP value in write_mstatus
[mirror_qemu.git] / target / riscv / cpu_helper.c
1 /*
2 * RISC-V CPU helpers for qemu.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/main-loop.h"
23 #include "cpu.h"
24 #include "pmu.h"
25 #include "exec/exec-all.h"
26 #include "instmap.h"
27 #include "tcg/tcg-op.h"
28 #include "trace.h"
29 #include "semihosting/common-semi.h"
30 #include "sysemu/cpu-timers.h"
31 #include "cpu_bits.h"
32 #include "debug.h"
33
34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
35 {
36 #ifdef CONFIG_USER_ONLY
37 return 0;
38 #else
39 return env->priv;
40 #endif
41 }
42
43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
44 target_ulong *cs_base, uint32_t *pflags)
45 {
46 CPUState *cs = env_cpu(env);
47 RISCVCPU *cpu = RISCV_CPU(cs);
48
49 uint32_t flags = 0;
50
51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
52 *cs_base = 0;
53
54 if (cpu->cfg.ext_zve32f) {
55 /*
56 * If env->vl equals to VLMAX, we can use generic vector operation
57 * expanders (GVEC) to accerlate the vector operations.
58 * However, as LMUL could be a fractional number. The maximum
59 * vector size can be operated might be less than 8 bytes,
60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
61 * only when maxsz >= 8 bytes.
62 */
63 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
65 uint32_t maxsz = vlmax << sew;
66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
67 (maxsz >= 8);
68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
71 FIELD_EX64(env->vtype, VTYPE, VLMUL));
72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
73 flags = FIELD_DP32(flags, TB_FLAGS, VTA,
74 FIELD_EX64(env->vtype, VTYPE, VTA));
75 flags = FIELD_DP32(flags, TB_FLAGS, VMA,
76 FIELD_EX64(env->vtype, VTYPE, VMA));
77 } else {
78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
79 }
80
81 #ifdef CONFIG_USER_ONLY
82 flags |= TB_FLAGS_MSTATUS_FS;
83 flags |= TB_FLAGS_MSTATUS_VS;
84 #else
85 flags |= cpu_mmu_index(env, 0);
86 if (riscv_cpu_fp_enabled(env)) {
87 flags |= env->mstatus & MSTATUS_FS;
88 }
89
90 if (riscv_cpu_vector_enabled(env)) {
91 flags |= env->mstatus & MSTATUS_VS;
92 }
93
94 if (riscv_has_ext(env, RVH)) {
95 if (env->priv == PRV_M ||
96 (env->priv == PRV_S && !env->virt_enabled) ||
97 (env->priv == PRV_U && !env->virt_enabled &&
98 get_field(env->hstatus, HSTATUS_HU))) {
99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
100 }
101
102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
103 get_field(env->mstatus_hs, MSTATUS_FS));
104
105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
106 get_field(env->mstatus_hs, MSTATUS_VS));
107 }
108 if (cpu->cfg.debug && !icount_enabled()) {
109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
110 }
111 #endif
112
113 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
114 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
115 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
116 }
117 if (env->cur_pmbase != 0) {
118 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
119 }
120
121 *pflags = flags;
122 }
123
124 void riscv_cpu_update_mask(CPURISCVState *env)
125 {
126 target_ulong mask = -1, base = 0;
127 /*
128 * TODO: Current RVJ spec does not specify
129 * how the extension interacts with XLEN.
130 */
131 #ifndef CONFIG_USER_ONLY
132 if (riscv_has_ext(env, RVJ)) {
133 switch (env->priv) {
134 case PRV_M:
135 if (env->mmte & M_PM_ENABLE) {
136 mask = env->mpmmask;
137 base = env->mpmbase;
138 }
139 break;
140 case PRV_S:
141 if (env->mmte & S_PM_ENABLE) {
142 mask = env->spmmask;
143 base = env->spmbase;
144 }
145 break;
146 case PRV_U:
147 if (env->mmte & U_PM_ENABLE) {
148 mask = env->upmmask;
149 base = env->upmbase;
150 }
151 break;
152 default:
153 g_assert_not_reached();
154 }
155 }
156 #endif
157 if (env->xl == MXL_RV32) {
158 env->cur_pmmask = mask & UINT32_MAX;
159 env->cur_pmbase = base & UINT32_MAX;
160 } else {
161 env->cur_pmmask = mask;
162 env->cur_pmbase = base;
163 }
164 }
165
166 #ifndef CONFIG_USER_ONLY
167
168 /*
169 * The HS-mode is allowed to configure priority only for the
170 * following VS-mode local interrupts:
171 *
172 * 0 (Reserved interrupt, reads as zero)
173 * 1 Supervisor software interrupt
174 * 4 (Reserved interrupt, reads as zero)
175 * 5 Supervisor timer interrupt
176 * 8 (Reserved interrupt, reads as zero)
177 * 13 (Reserved interrupt)
178 * 14 "
179 * 15 "
180 * 16 "
181 * 17 "
182 * 18 "
183 * 19 "
184 * 20 "
185 * 21 "
186 * 22 "
187 * 23 "
188 */
189
190 static const int hviprio_index2irq[] = {
191 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
192 static const int hviprio_index2rdzero[] = {
193 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
194
195 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
196 {
197 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
198 return -EINVAL;
199 }
200
201 if (out_irq) {
202 *out_irq = hviprio_index2irq[index];
203 }
204
205 if (out_rdzero) {
206 *out_rdzero = hviprio_index2rdzero[index];
207 }
208
209 return 0;
210 }
211
212 /*
213 * Default priorities of local interrupts are defined in the
214 * RISC-V Advanced Interrupt Architecture specification.
215 *
216 * ----------------------------------------------------------------
217 * Default |
218 * Priority | Major Interrupt Numbers
219 * ----------------------------------------------------------------
220 * Highest | 47, 23, 46, 45, 22, 44,
221 * | 43, 21, 42, 41, 20, 40
222 * |
223 * | 11 (0b), 3 (03), 7 (07)
224 * | 9 (09), 1 (01), 5 (05)
225 * | 12 (0c)
226 * | 10 (0a), 2 (02), 6 (06)
227 * |
228 * | 39, 19, 38, 37, 18, 36,
229 * Lowest | 35, 17, 34, 33, 16, 32
230 * ----------------------------------------------------------------
231 */
232 static const uint8_t default_iprio[64] = {
233 /* Custom interrupts 48 to 63 */
234 [63] = IPRIO_MMAXIPRIO,
235 [62] = IPRIO_MMAXIPRIO,
236 [61] = IPRIO_MMAXIPRIO,
237 [60] = IPRIO_MMAXIPRIO,
238 [59] = IPRIO_MMAXIPRIO,
239 [58] = IPRIO_MMAXIPRIO,
240 [57] = IPRIO_MMAXIPRIO,
241 [56] = IPRIO_MMAXIPRIO,
242 [55] = IPRIO_MMAXIPRIO,
243 [54] = IPRIO_MMAXIPRIO,
244 [53] = IPRIO_MMAXIPRIO,
245 [52] = IPRIO_MMAXIPRIO,
246 [51] = IPRIO_MMAXIPRIO,
247 [50] = IPRIO_MMAXIPRIO,
248 [49] = IPRIO_MMAXIPRIO,
249 [48] = IPRIO_MMAXIPRIO,
250
251 /* Custom interrupts 24 to 31 */
252 [31] = IPRIO_MMAXIPRIO,
253 [30] = IPRIO_MMAXIPRIO,
254 [29] = IPRIO_MMAXIPRIO,
255 [28] = IPRIO_MMAXIPRIO,
256 [27] = IPRIO_MMAXIPRIO,
257 [26] = IPRIO_MMAXIPRIO,
258 [25] = IPRIO_MMAXIPRIO,
259 [24] = IPRIO_MMAXIPRIO,
260
261 [47] = IPRIO_DEFAULT_UPPER,
262 [23] = IPRIO_DEFAULT_UPPER + 1,
263 [46] = IPRIO_DEFAULT_UPPER + 2,
264 [45] = IPRIO_DEFAULT_UPPER + 3,
265 [22] = IPRIO_DEFAULT_UPPER + 4,
266 [44] = IPRIO_DEFAULT_UPPER + 5,
267
268 [43] = IPRIO_DEFAULT_UPPER + 6,
269 [21] = IPRIO_DEFAULT_UPPER + 7,
270 [42] = IPRIO_DEFAULT_UPPER + 8,
271 [41] = IPRIO_DEFAULT_UPPER + 9,
272 [20] = IPRIO_DEFAULT_UPPER + 10,
273 [40] = IPRIO_DEFAULT_UPPER + 11,
274
275 [11] = IPRIO_DEFAULT_M,
276 [3] = IPRIO_DEFAULT_M + 1,
277 [7] = IPRIO_DEFAULT_M + 2,
278
279 [9] = IPRIO_DEFAULT_S,
280 [1] = IPRIO_DEFAULT_S + 1,
281 [5] = IPRIO_DEFAULT_S + 2,
282
283 [12] = IPRIO_DEFAULT_SGEXT,
284
285 [10] = IPRIO_DEFAULT_VS,
286 [2] = IPRIO_DEFAULT_VS + 1,
287 [6] = IPRIO_DEFAULT_VS + 2,
288
289 [39] = IPRIO_DEFAULT_LOWER,
290 [19] = IPRIO_DEFAULT_LOWER + 1,
291 [38] = IPRIO_DEFAULT_LOWER + 2,
292 [37] = IPRIO_DEFAULT_LOWER + 3,
293 [18] = IPRIO_DEFAULT_LOWER + 4,
294 [36] = IPRIO_DEFAULT_LOWER + 5,
295
296 [35] = IPRIO_DEFAULT_LOWER + 6,
297 [17] = IPRIO_DEFAULT_LOWER + 7,
298 [34] = IPRIO_DEFAULT_LOWER + 8,
299 [33] = IPRIO_DEFAULT_LOWER + 9,
300 [16] = IPRIO_DEFAULT_LOWER + 10,
301 [32] = IPRIO_DEFAULT_LOWER + 11,
302 };
303
304 uint8_t riscv_cpu_default_priority(int irq)
305 {
306 if (irq < 0 || irq > 63) {
307 return IPRIO_MMAXIPRIO;
308 }
309
310 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
311 };
312
313 static int riscv_cpu_pending_to_irq(CPURISCVState *env,
314 int extirq, unsigned int extirq_def_prio,
315 uint64_t pending, uint8_t *iprio)
316 {
317 int irq, best_irq = RISCV_EXCP_NONE;
318 unsigned int prio, best_prio = UINT_MAX;
319
320 if (!pending) {
321 return RISCV_EXCP_NONE;
322 }
323
324 irq = ctz64(pending);
325 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
326 riscv_cpu_cfg(env)->ext_ssaia)) {
327 return irq;
328 }
329
330 pending = pending >> irq;
331 while (pending) {
332 prio = iprio[irq];
333 if (!prio) {
334 if (irq == extirq) {
335 prio = extirq_def_prio;
336 } else {
337 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
338 1 : IPRIO_MMAXIPRIO;
339 }
340 }
341 if ((pending & 0x1) && (prio <= best_prio)) {
342 best_irq = irq;
343 best_prio = prio;
344 }
345 irq++;
346 pending = pending >> 1;
347 }
348
349 return best_irq;
350 }
351
352 uint64_t riscv_cpu_all_pending(CPURISCVState *env)
353 {
354 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
355 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
356 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
357
358 return (env->mip | vsgein | vstip) & env->mie;
359 }
360
361 int riscv_cpu_mirq_pending(CPURISCVState *env)
362 {
363 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
364 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
365
366 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
367 irqs, env->miprio);
368 }
369
370 int riscv_cpu_sirq_pending(CPURISCVState *env)
371 {
372 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
373 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
374
375 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
376 irqs, env->siprio);
377 }
378
379 int riscv_cpu_vsirq_pending(CPURISCVState *env)
380 {
381 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
382 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
383
384 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
385 irqs >> 1, env->hviprio);
386 }
387
388 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
389 {
390 int virq;
391 uint64_t irqs, pending, mie, hsie, vsie;
392
393 /* Determine interrupt enable state of all privilege modes */
394 if (env->virt_enabled) {
395 mie = 1;
396 hsie = 1;
397 vsie = (env->priv < PRV_S) ||
398 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
399 } else {
400 mie = (env->priv < PRV_M) ||
401 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
402 hsie = (env->priv < PRV_S) ||
403 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
404 vsie = 0;
405 }
406
407 /* Determine all pending interrupts */
408 pending = riscv_cpu_all_pending(env);
409
410 /* Check M-mode interrupts */
411 irqs = pending & ~env->mideleg & -mie;
412 if (irqs) {
413 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
414 irqs, env->miprio);
415 }
416
417 /* Check HS-mode interrupts */
418 irqs = pending & env->mideleg & ~env->hideleg & -hsie;
419 if (irqs) {
420 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
421 irqs, env->siprio);
422 }
423
424 /* Check VS-mode interrupts */
425 irqs = pending & env->mideleg & env->hideleg & -vsie;
426 if (irqs) {
427 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
428 irqs >> 1, env->hviprio);
429 return (virq <= 0) ? virq : virq + 1;
430 }
431
432 /* Indicate no pending interrupt */
433 return RISCV_EXCP_NONE;
434 }
435
436 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
437 {
438 if (interrupt_request & CPU_INTERRUPT_HARD) {
439 RISCVCPU *cpu = RISCV_CPU(cs);
440 CPURISCVState *env = &cpu->env;
441 int interruptno = riscv_cpu_local_irq_pending(env);
442 if (interruptno >= 0) {
443 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
444 riscv_cpu_do_interrupt(cs);
445 return true;
446 }
447 }
448 return false;
449 }
450
451 /* Return true is floating point support is currently enabled */
452 bool riscv_cpu_fp_enabled(CPURISCVState *env)
453 {
454 if (env->mstatus & MSTATUS_FS) {
455 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
456 return false;
457 }
458 return true;
459 }
460
461 return false;
462 }
463
464 /* Return true is vector support is currently enabled */
465 bool riscv_cpu_vector_enabled(CPURISCVState *env)
466 {
467 if (env->mstatus & MSTATUS_VS) {
468 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
469 return false;
470 }
471 return true;
472 }
473
474 return false;
475 }
476
477 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
478 {
479 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
480 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
481 MSTATUS64_UXL | MSTATUS_VS;
482
483 if (riscv_has_ext(env, RVF)) {
484 mstatus_mask |= MSTATUS_FS;
485 }
486 bool current_virt = env->virt_enabled;
487
488 g_assert(riscv_has_ext(env, RVH));
489
490 if (current_virt) {
491 /* Current V=1 and we are about to change to V=0 */
492 env->vsstatus = env->mstatus & mstatus_mask;
493 env->mstatus &= ~mstatus_mask;
494 env->mstatus |= env->mstatus_hs;
495
496 env->vstvec = env->stvec;
497 env->stvec = env->stvec_hs;
498
499 env->vsscratch = env->sscratch;
500 env->sscratch = env->sscratch_hs;
501
502 env->vsepc = env->sepc;
503 env->sepc = env->sepc_hs;
504
505 env->vscause = env->scause;
506 env->scause = env->scause_hs;
507
508 env->vstval = env->stval;
509 env->stval = env->stval_hs;
510
511 env->vsatp = env->satp;
512 env->satp = env->satp_hs;
513 } else {
514 /* Current V=0 and we are about to change to V=1 */
515 env->mstatus_hs = env->mstatus & mstatus_mask;
516 env->mstatus &= ~mstatus_mask;
517 env->mstatus |= env->vsstatus;
518
519 env->stvec_hs = env->stvec;
520 env->stvec = env->vstvec;
521
522 env->sscratch_hs = env->sscratch;
523 env->sscratch = env->vsscratch;
524
525 env->sepc_hs = env->sepc;
526 env->sepc = env->vsepc;
527
528 env->scause_hs = env->scause;
529 env->scause = env->vscause;
530
531 env->stval_hs = env->stval;
532 env->stval = env->vstval;
533
534 env->satp_hs = env->satp;
535 env->satp = env->vsatp;
536 }
537 }
538
539 target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
540 {
541 if (!riscv_has_ext(env, RVH)) {
542 return 0;
543 }
544
545 return env->geilen;
546 }
547
548 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
549 {
550 if (!riscv_has_ext(env, RVH)) {
551 return;
552 }
553
554 if (geilen > (TARGET_LONG_BITS - 1)) {
555 return;
556 }
557
558 env->geilen = geilen;
559 }
560
561 /* This function can only be called to set virt when RVH is enabled */
562 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
563 {
564 /* Flush the TLB on all virt mode changes. */
565 if (env->virt_enabled != enable) {
566 tlb_flush(env_cpu(env));
567 }
568
569 env->virt_enabled = enable;
570
571 if (enable) {
572 /*
573 * The guest external interrupts from an interrupt controller are
574 * delivered only when the Guest/VM is running (i.e. V=1). This means
575 * any guest external interrupt which is triggered while the Guest/VM
576 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
577 * with sluggish response to serial console input and other I/O events.
578 *
579 * To solve this, we check and inject interrupt after setting V=1.
580 */
581 riscv_cpu_update_mip(env, 0, 0);
582 }
583 }
584
585 bool riscv_cpu_two_stage_lookup(int mmu_idx)
586 {
587 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
588 }
589
590 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
591 {
592 CPURISCVState *env = &cpu->env;
593 if (env->miclaim & interrupts) {
594 return -1;
595 } else {
596 env->miclaim |= interrupts;
597 return 0;
598 }
599 }
600
601 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
602 uint64_t value)
603 {
604 CPUState *cs = env_cpu(env);
605 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
606
607 if (env->virt_enabled) {
608 gein = get_field(env->hstatus, HSTATUS_VGEIN);
609 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
610 }
611
612 vstip = env->vstime_irq ? MIP_VSTIP : 0;
613
614 QEMU_IOTHREAD_LOCK_GUARD();
615
616 env->mip = (env->mip & ~mask) | (value & mask);
617
618 if (env->mip | vsgein | vstip) {
619 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
620 } else {
621 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
622 }
623
624 return old;
625 }
626
627 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
628 void *arg)
629 {
630 env->rdtime_fn = fn;
631 env->rdtime_fn_arg = arg;
632 }
633
634 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
635 int (*rmw_fn)(void *arg,
636 target_ulong reg,
637 target_ulong *val,
638 target_ulong new_val,
639 target_ulong write_mask),
640 void *rmw_fn_arg)
641 {
642 if (priv <= PRV_M) {
643 env->aia_ireg_rmw_fn[priv] = rmw_fn;
644 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
645 }
646 }
647
648 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
649 {
650 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
651
652 if (icount_enabled() && newpriv != env->priv) {
653 riscv_itrigger_update_priv(env);
654 }
655 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
656 env->priv = newpriv;
657 env->xl = cpu_recompute_xl(env);
658 riscv_cpu_update_mask(env);
659
660 /*
661 * Clear the load reservation - otherwise a reservation placed in one
662 * context/process can be used by another, resulting in an SC succeeding
663 * incorrectly. Version 2.2 of the ISA specification explicitly requires
664 * this behaviour, while later revisions say that the kernel "should" use
665 * an SC instruction to force the yielding of a load reservation on a
666 * preemptive context switch. As a result, do both.
667 */
668 env->load_res = -1;
669 }
670
671 /*
672 * get_physical_address_pmp - check PMP permission for this physical address
673 *
674 * Match the PMP region and check permission for this physical address and it's
675 * TLB page. Returns 0 if the permission checking was successful
676 *
677 * @env: CPURISCVState
678 * @prot: The returned protection attributes
679 * @tlb_size: TLB page size containing addr. It could be modified after PMP
680 * permission checking. NULL if not set TLB page for addr.
681 * @addr: The physical address to be checked permission
682 * @access_type: The type of MMU access
683 * @mode: Indicates current privilege level.
684 */
685 static int get_physical_address_pmp(CPURISCVState *env, int *prot,
686 target_ulong *tlb_size, hwaddr addr,
687 int size, MMUAccessType access_type,
688 int mode)
689 {
690 pmp_priv_t pmp_priv;
691 int pmp_index = -1;
692
693 if (!riscv_cpu_cfg(env)->pmp) {
694 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
695 return TRANSLATE_SUCCESS;
696 }
697
698 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
699 &pmp_priv, mode);
700 if (pmp_index < 0) {
701 *prot = 0;
702 return TRANSLATE_PMP_FAIL;
703 }
704
705 *prot = pmp_priv_to_page_prot(pmp_priv);
706 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
707 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
708 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
709
710 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
711 }
712
713 return TRANSLATE_SUCCESS;
714 }
715
716 /*
717 * get_physical_address - get the physical address for this virtual address
718 *
719 * Do a page table walk to obtain the physical address corresponding to a
720 * virtual address. Returns 0 if the translation was successful
721 *
722 * Adapted from Spike's mmu_t::translate and mmu_t::walk
723 *
724 * @env: CPURISCVState
725 * @physical: This will be set to the calculated physical address
726 * @prot: The returned protection attributes
727 * @addr: The virtual address or guest physical address to be translated
728 * @fault_pte_addr: If not NULL, this will be set to fault pte address
729 * when a error occurs on pte address translation.
730 * This will already be shifted to match htval.
731 * @access_type: The type of MMU access
732 * @mmu_idx: Indicates current privilege level
733 * @first_stage: Are we in first stage translation?
734 * Second stage is used for hypervisor guest translation
735 * @two_stage: Are we going to perform two stage translation
736 * @is_debug: Is this access from a debugger or the monitor?
737 */
738 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
739 int *prot, vaddr addr,
740 target_ulong *fault_pte_addr,
741 int access_type, int mmu_idx,
742 bool first_stage, bool two_stage,
743 bool is_debug)
744 {
745 /*
746 * NOTE: the env->pc value visible here will not be
747 * correct, but the value visible to the exception handler
748 * (riscv_cpu_do_interrupt) is correct
749 */
750 MemTxResult res;
751 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
752 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
753 bool use_background = false;
754 hwaddr ppn;
755 int napot_bits = 0;
756 target_ulong napot_mask;
757
758 /*
759 * Check if we should use the background registers for the two
760 * stage translation. We don't need to check if we actually need
761 * two stage translation as that happened before this function
762 * was called. Background registers will be used if the guest has
763 * forced a two stage translation to be on (in HS or M mode).
764 */
765 if (!env->virt_enabled && two_stage) {
766 use_background = true;
767 }
768
769 /*
770 * MPRV does not affect the virtual-machine load/store
771 * instructions, HLV, HLVX, and HSV.
772 */
773 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
774 mode = get_field(env->hstatus, HSTATUS_SPVP);
775 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
776 if (get_field(env->mstatus, MSTATUS_MPRV)) {
777 mode = get_field(env->mstatus, MSTATUS_MPP);
778 }
779 }
780
781 if (first_stage == false) {
782 /*
783 * We are in stage 2 translation, this is similar to stage 1.
784 * Stage 2 is always taken as U-mode
785 */
786 mode = PRV_U;
787 }
788
789 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
790 *physical = addr;
791 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
792 return TRANSLATE_SUCCESS;
793 }
794
795 *prot = 0;
796
797 hwaddr base;
798 int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
799
800 if (first_stage == true) {
801 mxr = get_field(env->mstatus, MSTATUS_MXR);
802 } else {
803 mxr = get_field(env->vsstatus, MSTATUS_MXR);
804 }
805
806 if (first_stage == true) {
807 if (use_background) {
808 if (riscv_cpu_mxl(env) == MXL_RV32) {
809 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
810 vm = get_field(env->vsatp, SATP32_MODE);
811 } else {
812 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
813 vm = get_field(env->vsatp, SATP64_MODE);
814 }
815 } else {
816 if (riscv_cpu_mxl(env) == MXL_RV32) {
817 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
818 vm = get_field(env->satp, SATP32_MODE);
819 } else {
820 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
821 vm = get_field(env->satp, SATP64_MODE);
822 }
823 }
824 widened = 0;
825 } else {
826 if (riscv_cpu_mxl(env) == MXL_RV32) {
827 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
828 vm = get_field(env->hgatp, SATP32_MODE);
829 } else {
830 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
831 vm = get_field(env->hgatp, SATP64_MODE);
832 }
833 widened = 2;
834 }
835 /* status.SUM will be ignored if execute on background */
836 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
837 switch (vm) {
838 case VM_1_10_SV32:
839 levels = 2; ptidxbits = 10; ptesize = 4; break;
840 case VM_1_10_SV39:
841 levels = 3; ptidxbits = 9; ptesize = 8; break;
842 case VM_1_10_SV48:
843 levels = 4; ptidxbits = 9; ptesize = 8; break;
844 case VM_1_10_SV57:
845 levels = 5; ptidxbits = 9; ptesize = 8; break;
846 case VM_1_10_MBARE:
847 *physical = addr;
848 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
849 return TRANSLATE_SUCCESS;
850 default:
851 g_assert_not_reached();
852 }
853
854 CPUState *cs = env_cpu(env);
855 int va_bits = PGSHIFT + levels * ptidxbits + widened;
856 target_ulong mask, masked_msbs;
857
858 if (TARGET_LONG_BITS > (va_bits - 1)) {
859 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
860 } else {
861 mask = 0;
862 }
863 masked_msbs = (addr >> (va_bits - 1)) & mask;
864
865 if (masked_msbs != 0 && masked_msbs != mask) {
866 return TRANSLATE_FAIL;
867 }
868
869 int ptshift = (levels - 1) * ptidxbits;
870 int i;
871
872 #if !TCG_OVERSIZED_GUEST
873 restart:
874 #endif
875 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
876 target_ulong idx;
877 if (i == 0) {
878 idx = (addr >> (PGSHIFT + ptshift)) &
879 ((1 << (ptidxbits + widened)) - 1);
880 } else {
881 idx = (addr >> (PGSHIFT + ptshift)) &
882 ((1 << ptidxbits) - 1);
883 }
884
885 /* check that physical address of PTE is legal */
886 hwaddr pte_addr;
887
888 if (two_stage && first_stage) {
889 int vbase_prot;
890 hwaddr vbase;
891
892 /* Do the second stage translation on the base PTE address. */
893 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
894 base, NULL, MMU_DATA_LOAD,
895 mmu_idx, false, true,
896 is_debug);
897
898 if (vbase_ret != TRANSLATE_SUCCESS) {
899 if (fault_pte_addr) {
900 *fault_pte_addr = (base + idx * ptesize) >> 2;
901 }
902 return TRANSLATE_G_STAGE_FAIL;
903 }
904
905 pte_addr = vbase + idx * ptesize;
906 } else {
907 pte_addr = base + idx * ptesize;
908 }
909
910 int pmp_prot;
911 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
912 sizeof(target_ulong),
913 MMU_DATA_LOAD, PRV_S);
914 if (pmp_ret != TRANSLATE_SUCCESS) {
915 return TRANSLATE_PMP_FAIL;
916 }
917
918 target_ulong pte;
919 if (riscv_cpu_mxl(env) == MXL_RV32) {
920 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
921 } else {
922 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
923 }
924
925 if (res != MEMTX_OK) {
926 return TRANSLATE_FAIL;
927 }
928
929 bool pbmte = env->menvcfg & MENVCFG_PBMTE;
930 bool hade = env->menvcfg & MENVCFG_HADE;
931
932 if (first_stage && two_stage && env->virt_enabled) {
933 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
934 hade = hade && (env->henvcfg & HENVCFG_HADE);
935 }
936
937 if (riscv_cpu_sxl(env) == MXL_RV32) {
938 ppn = pte >> PTE_PPN_SHIFT;
939 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
940 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
941 } else {
942 ppn = pte >> PTE_PPN_SHIFT;
943 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
944 return TRANSLATE_FAIL;
945 }
946 }
947
948 if (!(pte & PTE_V)) {
949 /* Invalid PTE */
950 return TRANSLATE_FAIL;
951 } else if (!pbmte && (pte & PTE_PBMT)) {
952 return TRANSLATE_FAIL;
953 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
954 /* Inner PTE, continue walking */
955 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
956 return TRANSLATE_FAIL;
957 }
958 base = ppn << PGSHIFT;
959 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
960 /* Reserved leaf PTE flags: PTE_W */
961 return TRANSLATE_FAIL;
962 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
963 /* Reserved leaf PTE flags: PTE_W + PTE_X */
964 return TRANSLATE_FAIL;
965 } else if ((pte & PTE_U) && ((mode != PRV_U) &&
966 (!sum || access_type == MMU_INST_FETCH))) {
967 /* User PTE flags when not U mode and mstatus.SUM is not set,
968 or the access type is an instruction fetch */
969 return TRANSLATE_FAIL;
970 } else if (!(pte & PTE_U) && (mode != PRV_S)) {
971 /* Supervisor PTE flags when not S mode */
972 return TRANSLATE_FAIL;
973 } else if (ppn & ((1ULL << ptshift) - 1)) {
974 /* Misaligned PPN */
975 return TRANSLATE_FAIL;
976 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
977 ((pte & PTE_X) && mxr))) {
978 /* Read access check failed */
979 return TRANSLATE_FAIL;
980 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
981 /* Write access check failed */
982 return TRANSLATE_FAIL;
983 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
984 /* Fetch access check failed */
985 return TRANSLATE_FAIL;
986 } else {
987 /* if necessary, set accessed and dirty bits. */
988 target_ulong updated_pte = pte | PTE_A |
989 (access_type == MMU_DATA_STORE ? PTE_D : 0);
990
991 /* Page table updates need to be atomic with MTTCG enabled */
992 if (updated_pte != pte) {
993 if (!hade) {
994 return TRANSLATE_FAIL;
995 }
996
997 /*
998 * - if accessed or dirty bits need updating, and the PTE is
999 * in RAM, then we do so atomically with a compare and swap.
1000 * - if the PTE is in IO space or ROM, then it can't be updated
1001 * and we return TRANSLATE_FAIL.
1002 * - if the PTE changed by the time we went to update it, then
1003 * it is no longer valid and we must re-walk the page table.
1004 */
1005 MemoryRegion *mr;
1006 hwaddr l = sizeof(target_ulong), addr1;
1007 mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
1008 false, MEMTXATTRS_UNSPECIFIED);
1009 if (memory_region_is_ram(mr)) {
1010 target_ulong *pte_pa =
1011 qemu_map_ram_ptr(mr->ram_block, addr1);
1012 #if TCG_OVERSIZED_GUEST
1013 /*
1014 * MTTCG is not enabled on oversized TCG guests so
1015 * page table updates do not need to be atomic
1016 */
1017 *pte_pa = pte = updated_pte;
1018 #else
1019 target_ulong old_pte =
1020 qatomic_cmpxchg(pte_pa, pte, updated_pte);
1021 if (old_pte != pte) {
1022 goto restart;
1023 } else {
1024 pte = updated_pte;
1025 }
1026 #endif
1027 } else {
1028 /*
1029 * misconfigured PTE in ROM (AD bits are not preset) or
1030 * PTE is in IO space and can't be updated atomically
1031 */
1032 return TRANSLATE_FAIL;
1033 }
1034 }
1035
1036 /*
1037 * for superpage mappings, make a fake leaf PTE for the TLB's
1038 * benefit.
1039 */
1040 target_ulong vpn = addr >> PGSHIFT;
1041
1042 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
1043 napot_bits = ctzl(ppn) + 1;
1044 if ((i != (levels - 1)) || (napot_bits != 4)) {
1045 return TRANSLATE_FAIL;
1046 }
1047 }
1048
1049 napot_mask = (1 << napot_bits) - 1;
1050 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
1051 (vpn & (((target_ulong)1 << ptshift) - 1))
1052 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
1053
1054 /* set permissions on the TLB entry */
1055 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
1056 *prot |= PAGE_READ;
1057 }
1058 if (pte & PTE_X) {
1059 *prot |= PAGE_EXEC;
1060 }
1061 /*
1062 * add write permission on stores or if the page is already dirty,
1063 * so that we TLB miss on later writes to update the dirty bit
1064 */
1065 if ((pte & PTE_W) &&
1066 (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
1067 *prot |= PAGE_WRITE;
1068 }
1069 return TRANSLATE_SUCCESS;
1070 }
1071 }
1072 return TRANSLATE_FAIL;
1073 }
1074
1075 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
1076 MMUAccessType access_type, bool pmp_violation,
1077 bool first_stage, bool two_stage,
1078 bool two_stage_indirect)
1079 {
1080 CPUState *cs = env_cpu(env);
1081 int page_fault_exceptions, vm;
1082 uint64_t stap_mode;
1083
1084 if (riscv_cpu_mxl(env) == MXL_RV32) {
1085 stap_mode = SATP32_MODE;
1086 } else {
1087 stap_mode = SATP64_MODE;
1088 }
1089
1090 if (first_stage) {
1091 vm = get_field(env->satp, stap_mode);
1092 } else {
1093 vm = get_field(env->hgatp, stap_mode);
1094 }
1095
1096 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
1097
1098 switch (access_type) {
1099 case MMU_INST_FETCH:
1100 if (env->virt_enabled && !first_stage) {
1101 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1102 } else {
1103 cs->exception_index = page_fault_exceptions ?
1104 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
1105 }
1106 break;
1107 case MMU_DATA_LOAD:
1108 if (two_stage && !first_stage) {
1109 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1110 } else {
1111 cs->exception_index = page_fault_exceptions ?
1112 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
1113 }
1114 break;
1115 case MMU_DATA_STORE:
1116 if (two_stage && !first_stage) {
1117 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1118 } else {
1119 cs->exception_index = page_fault_exceptions ?
1120 RISCV_EXCP_STORE_PAGE_FAULT :
1121 RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1122 }
1123 break;
1124 default:
1125 g_assert_not_reached();
1126 }
1127 env->badaddr = address;
1128 env->two_stage_lookup = two_stage;
1129 env->two_stage_indirect_lookup = two_stage_indirect;
1130 }
1131
1132 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
1133 {
1134 RISCVCPU *cpu = RISCV_CPU(cs);
1135 CPURISCVState *env = &cpu->env;
1136 hwaddr phys_addr;
1137 int prot;
1138 int mmu_idx = cpu_mmu_index(&cpu->env, false);
1139
1140 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
1141 true, env->virt_enabled, true)) {
1142 return -1;
1143 }
1144
1145 if (env->virt_enabled) {
1146 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
1147 0, mmu_idx, false, true, true)) {
1148 return -1;
1149 }
1150 }
1151
1152 return phys_addr & TARGET_PAGE_MASK;
1153 }
1154
1155 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1156 vaddr addr, unsigned size,
1157 MMUAccessType access_type,
1158 int mmu_idx, MemTxAttrs attrs,
1159 MemTxResult response, uintptr_t retaddr)
1160 {
1161 RISCVCPU *cpu = RISCV_CPU(cs);
1162 CPURISCVState *env = &cpu->env;
1163
1164 if (access_type == MMU_DATA_STORE) {
1165 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1166 } else if (access_type == MMU_DATA_LOAD) {
1167 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
1168 } else {
1169 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
1170 }
1171
1172 env->badaddr = addr;
1173 env->two_stage_lookup = env->virt_enabled ||
1174 riscv_cpu_two_stage_lookup(mmu_idx);
1175 env->two_stage_indirect_lookup = false;
1176 cpu_loop_exit_restore(cs, retaddr);
1177 }
1178
1179 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1180 MMUAccessType access_type, int mmu_idx,
1181 uintptr_t retaddr)
1182 {
1183 RISCVCPU *cpu = RISCV_CPU(cs);
1184 CPURISCVState *env = &cpu->env;
1185 switch (access_type) {
1186 case MMU_INST_FETCH:
1187 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1188 break;
1189 case MMU_DATA_LOAD:
1190 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1191 break;
1192 case MMU_DATA_STORE:
1193 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1194 break;
1195 default:
1196 g_assert_not_reached();
1197 }
1198 env->badaddr = addr;
1199 env->two_stage_lookup = env->virt_enabled ||
1200 riscv_cpu_two_stage_lookup(mmu_idx);
1201 env->two_stage_indirect_lookup = false;
1202 cpu_loop_exit_restore(cs, retaddr);
1203 }
1204
1205
1206 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
1207 {
1208 enum riscv_pmu_event_idx pmu_event_type;
1209
1210 switch (access_type) {
1211 case MMU_INST_FETCH:
1212 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
1213 break;
1214 case MMU_DATA_LOAD:
1215 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
1216 break;
1217 case MMU_DATA_STORE:
1218 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
1219 break;
1220 default:
1221 return;
1222 }
1223
1224 riscv_pmu_incr_ctr(cpu, pmu_event_type);
1225 }
1226
1227 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1228 MMUAccessType access_type, int mmu_idx,
1229 bool probe, uintptr_t retaddr)
1230 {
1231 RISCVCPU *cpu = RISCV_CPU(cs);
1232 CPURISCVState *env = &cpu->env;
1233 vaddr im_address;
1234 hwaddr pa = 0;
1235 int prot, prot2, prot_pmp;
1236 bool pmp_violation = false;
1237 bool first_stage_error = true;
1238 bool two_stage_lookup = false;
1239 bool two_stage_indirect_error = false;
1240 int ret = TRANSLATE_FAIL;
1241 int mode = mmu_idx;
1242 /* default TLB page size */
1243 target_ulong tlb_size = TARGET_PAGE_SIZE;
1244
1245 env->guest_phys_fault_addr = 0;
1246
1247 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
1248 __func__, address, access_type, mmu_idx);
1249
1250 /*
1251 * MPRV does not affect the virtual-machine load/store
1252 * instructions, HLV, HLVX, and HSV.
1253 */
1254 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
1255 mode = get_field(env->hstatus, HSTATUS_SPVP);
1256 } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
1257 get_field(env->mstatus, MSTATUS_MPRV)) {
1258 mode = get_field(env->mstatus, MSTATUS_MPP);
1259 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
1260 two_stage_lookup = true;
1261 }
1262 }
1263
1264 pmu_tlb_fill_incr_ctr(cpu, access_type);
1265 if (env->virt_enabled ||
1266 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
1267 access_type != MMU_INST_FETCH)) {
1268 /* Two stage lookup */
1269 ret = get_physical_address(env, &pa, &prot, address,
1270 &env->guest_phys_fault_addr, access_type,
1271 mmu_idx, true, true, false);
1272
1273 /*
1274 * A G-stage exception may be triggered during two state lookup.
1275 * And the env->guest_phys_fault_addr has already been set in
1276 * get_physical_address().
1277 */
1278 if (ret == TRANSLATE_G_STAGE_FAIL) {
1279 first_stage_error = false;
1280 two_stage_indirect_error = true;
1281 access_type = MMU_DATA_LOAD;
1282 }
1283
1284 qemu_log_mask(CPU_LOG_MMU,
1285 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
1286 HWADDR_FMT_plx " prot %d\n",
1287 __func__, address, ret, pa, prot);
1288
1289 if (ret == TRANSLATE_SUCCESS) {
1290 /* Second stage lookup */
1291 im_address = pa;
1292
1293 ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
1294 access_type, mmu_idx, false, true,
1295 false);
1296
1297 qemu_log_mask(CPU_LOG_MMU,
1298 "%s 2nd-stage address=%" VADDR_PRIx
1299 " ret %d physical "
1300 HWADDR_FMT_plx " prot %d\n",
1301 __func__, im_address, ret, pa, prot2);
1302
1303 prot &= prot2;
1304
1305 if (ret == TRANSLATE_SUCCESS) {
1306 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1307 size, access_type, mode);
1308
1309 qemu_log_mask(CPU_LOG_MMU,
1310 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1311 " %d tlb_size " TARGET_FMT_lu "\n",
1312 __func__, pa, ret, prot_pmp, tlb_size);
1313
1314 prot &= prot_pmp;
1315 }
1316
1317 if (ret != TRANSLATE_SUCCESS) {
1318 /*
1319 * Guest physical address translation failed, this is a HS
1320 * level exception
1321 */
1322 first_stage_error = false;
1323 env->guest_phys_fault_addr = (im_address |
1324 (address &
1325 (TARGET_PAGE_SIZE - 1))) >> 2;
1326 }
1327 }
1328 } else {
1329 /* Single stage lookup */
1330 ret = get_physical_address(env, &pa, &prot, address, NULL,
1331 access_type, mmu_idx, true, false, false);
1332
1333 qemu_log_mask(CPU_LOG_MMU,
1334 "%s address=%" VADDR_PRIx " ret %d physical "
1335 HWADDR_FMT_plx " prot %d\n",
1336 __func__, address, ret, pa, prot);
1337
1338 if (ret == TRANSLATE_SUCCESS) {
1339 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1340 size, access_type, mode);
1341
1342 qemu_log_mask(CPU_LOG_MMU,
1343 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1344 " %d tlb_size " TARGET_FMT_lu "\n",
1345 __func__, pa, ret, prot_pmp, tlb_size);
1346
1347 prot &= prot_pmp;
1348 }
1349 }
1350
1351 if (ret == TRANSLATE_PMP_FAIL) {
1352 pmp_violation = true;
1353 }
1354
1355 if (ret == TRANSLATE_SUCCESS) {
1356 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1357 prot, mmu_idx, tlb_size);
1358 return true;
1359 } else if (probe) {
1360 return false;
1361 } else {
1362 raise_mmu_exception(env, address, access_type, pmp_violation,
1363 first_stage_error,
1364 env->virt_enabled ||
1365 riscv_cpu_two_stage_lookup(mmu_idx),
1366 two_stage_indirect_error);
1367 cpu_loop_exit_restore(cs, retaddr);
1368 }
1369
1370 return true;
1371 }
1372
1373 static target_ulong riscv_transformed_insn(CPURISCVState *env,
1374 target_ulong insn,
1375 target_ulong taddr)
1376 {
1377 target_ulong xinsn = 0;
1378 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0;
1379
1380 /*
1381 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1382 * be uncompressed. The Quadrant 1 of RVC instruction space need
1383 * not be transformed because these instructions won't generate
1384 * any load/store trap.
1385 */
1386
1387 if ((insn & 0x3) != 0x3) {
1388 /* Transform 16bit instruction into 32bit instruction */
1389 switch (GET_C_OP(insn)) {
1390 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
1391 switch (GET_C_FUNC(insn)) {
1392 case OPC_RISC_C_FUNC_FLD_LQ:
1393 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */
1394 xinsn = OPC_RISC_FLD;
1395 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1396 access_rs1 = GET_C_RS1S(insn);
1397 access_imm = GET_C_LD_IMM(insn);
1398 access_size = 8;
1399 }
1400 break;
1401 case OPC_RISC_C_FUNC_LW: /* C.LW */
1402 xinsn = OPC_RISC_LW;
1403 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1404 access_rs1 = GET_C_RS1S(insn);
1405 access_imm = GET_C_LW_IMM(insn);
1406 access_size = 4;
1407 break;
1408 case OPC_RISC_C_FUNC_FLW_LD:
1409 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */
1410 xinsn = OPC_RISC_FLW;
1411 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1412 access_rs1 = GET_C_RS1S(insn);
1413 access_imm = GET_C_LW_IMM(insn);
1414 access_size = 4;
1415 } else { /* C.LD (RV64/RV128) */
1416 xinsn = OPC_RISC_LD;
1417 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1418 access_rs1 = GET_C_RS1S(insn);
1419 access_imm = GET_C_LD_IMM(insn);
1420 access_size = 8;
1421 }
1422 break;
1423 case OPC_RISC_C_FUNC_FSD_SQ:
1424 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */
1425 xinsn = OPC_RISC_FSD;
1426 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1427 access_rs1 = GET_C_RS1S(insn);
1428 access_imm = GET_C_SD_IMM(insn);
1429 access_size = 8;
1430 }
1431 break;
1432 case OPC_RISC_C_FUNC_SW: /* C.SW */
1433 xinsn = OPC_RISC_SW;
1434 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1435 access_rs1 = GET_C_RS1S(insn);
1436 access_imm = GET_C_SW_IMM(insn);
1437 access_size = 4;
1438 break;
1439 case OPC_RISC_C_FUNC_FSW_SD:
1440 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */
1441 xinsn = OPC_RISC_FSW;
1442 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1443 access_rs1 = GET_C_RS1S(insn);
1444 access_imm = GET_C_SW_IMM(insn);
1445 access_size = 4;
1446 } else { /* C.SD (RV64/RV128) */
1447 xinsn = OPC_RISC_SD;
1448 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1449 access_rs1 = GET_C_RS1S(insn);
1450 access_imm = GET_C_SD_IMM(insn);
1451 access_size = 8;
1452 }
1453 break;
1454 default:
1455 break;
1456 }
1457 break;
1458 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
1459 switch (GET_C_FUNC(insn)) {
1460 case OPC_RISC_C_FUNC_FLDSP_LQSP:
1461 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */
1462 xinsn = OPC_RISC_FLD;
1463 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1464 access_rs1 = 2;
1465 access_imm = GET_C_LDSP_IMM(insn);
1466 access_size = 8;
1467 }
1468 break;
1469 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
1470 xinsn = OPC_RISC_LW;
1471 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1472 access_rs1 = 2;
1473 access_imm = GET_C_LWSP_IMM(insn);
1474 access_size = 4;
1475 break;
1476 case OPC_RISC_C_FUNC_FLWSP_LDSP:
1477 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */
1478 xinsn = OPC_RISC_FLW;
1479 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1480 access_rs1 = 2;
1481 access_imm = GET_C_LWSP_IMM(insn);
1482 access_size = 4;
1483 } else { /* C.LDSP (RV64/RV128) */
1484 xinsn = OPC_RISC_LD;
1485 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1486 access_rs1 = 2;
1487 access_imm = GET_C_LDSP_IMM(insn);
1488 access_size = 8;
1489 }
1490 break;
1491 case OPC_RISC_C_FUNC_FSDSP_SQSP:
1492 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */
1493 xinsn = OPC_RISC_FSD;
1494 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1495 access_rs1 = 2;
1496 access_imm = GET_C_SDSP_IMM(insn);
1497 access_size = 8;
1498 }
1499 break;
1500 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
1501 xinsn = OPC_RISC_SW;
1502 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1503 access_rs1 = 2;
1504 access_imm = GET_C_SWSP_IMM(insn);
1505 access_size = 4;
1506 break;
1507 case 7:
1508 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */
1509 xinsn = OPC_RISC_FSW;
1510 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1511 access_rs1 = 2;
1512 access_imm = GET_C_SWSP_IMM(insn);
1513 access_size = 4;
1514 } else { /* C.SDSP (RV64/RV128) */
1515 xinsn = OPC_RISC_SD;
1516 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1517 access_rs1 = 2;
1518 access_imm = GET_C_SDSP_IMM(insn);
1519 access_size = 8;
1520 }
1521 break;
1522 default:
1523 break;
1524 }
1525 break;
1526 default:
1527 break;
1528 }
1529
1530 /*
1531 * Clear Bit1 of transformed instruction to indicate that
1532 * original insruction was a 16bit instruction
1533 */
1534 xinsn &= ~((target_ulong)0x2);
1535 } else {
1536 /* Transform 32bit (or wider) instructions */
1537 switch (MASK_OP_MAJOR(insn)) {
1538 case OPC_RISC_ATOMIC:
1539 xinsn = insn;
1540 access_rs1 = GET_RS1(insn);
1541 access_size = 1 << GET_FUNCT3(insn);
1542 break;
1543 case OPC_RISC_LOAD:
1544 case OPC_RISC_FP_LOAD:
1545 xinsn = SET_I_IMM(insn, 0);
1546 access_rs1 = GET_RS1(insn);
1547 access_imm = GET_IMM(insn);
1548 access_size = 1 << GET_FUNCT3(insn);
1549 break;
1550 case OPC_RISC_STORE:
1551 case OPC_RISC_FP_STORE:
1552 xinsn = SET_S_IMM(insn, 0);
1553 access_rs1 = GET_RS1(insn);
1554 access_imm = GET_STORE_IMM(insn);
1555 access_size = 1 << GET_FUNCT3(insn);
1556 break;
1557 case OPC_RISC_SYSTEM:
1558 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) {
1559 xinsn = insn;
1560 access_rs1 = GET_RS1(insn);
1561 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3);
1562 access_size = 1 << access_size;
1563 }
1564 break;
1565 default:
1566 break;
1567 }
1568 }
1569
1570 if (access_size) {
1571 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1572 (access_size - 1));
1573 }
1574
1575 return xinsn;
1576 }
1577 #endif /* !CONFIG_USER_ONLY */
1578
1579 /*
1580 * Handle Traps
1581 *
1582 * Adapted from Spike's processor_t::take_trap.
1583 *
1584 */
1585 void riscv_cpu_do_interrupt(CPUState *cs)
1586 {
1587 #if !defined(CONFIG_USER_ONLY)
1588
1589 RISCVCPU *cpu = RISCV_CPU(cs);
1590 CPURISCVState *env = &cpu->env;
1591 bool write_gva = false;
1592 uint64_t s;
1593
1594 /*
1595 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1596 * so we mask off the MSB and separate into trap type and cause.
1597 */
1598 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1599 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
1600 uint64_t deleg = async ? env->mideleg : env->medeleg;
1601 target_ulong tval = 0;
1602 target_ulong tinst = 0;
1603 target_ulong htval = 0;
1604 target_ulong mtval2 = 0;
1605
1606 if (cause == RISCV_EXCP_SEMIHOST) {
1607 do_common_semihosting(cs);
1608 env->pc += 4;
1609 return;
1610 }
1611
1612 if (!async) {
1613 /* set tval to badaddr for traps with address information */
1614 switch (cause) {
1615 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
1616 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
1617 case RISCV_EXCP_LOAD_ADDR_MIS:
1618 case RISCV_EXCP_STORE_AMO_ADDR_MIS:
1619 case RISCV_EXCP_LOAD_ACCESS_FAULT:
1620 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
1621 case RISCV_EXCP_LOAD_PAGE_FAULT:
1622 case RISCV_EXCP_STORE_PAGE_FAULT:
1623 write_gva = env->two_stage_lookup;
1624 tval = env->badaddr;
1625 if (env->two_stage_indirect_lookup) {
1626 /*
1627 * special pseudoinstruction for G-stage fault taken while
1628 * doing VS-stage page table walk.
1629 */
1630 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1631 } else {
1632 /*
1633 * The "Addr. Offset" field in transformed instruction is
1634 * non-zero only for misaligned access.
1635 */
1636 tinst = riscv_transformed_insn(env, env->bins, tval);
1637 }
1638 break;
1639 case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
1640 case RISCV_EXCP_INST_ADDR_MIS:
1641 case RISCV_EXCP_INST_ACCESS_FAULT:
1642 case RISCV_EXCP_INST_PAGE_FAULT:
1643 write_gva = env->two_stage_lookup;
1644 tval = env->badaddr;
1645 if (env->two_stage_indirect_lookup) {
1646 /*
1647 * special pseudoinstruction for G-stage fault taken while
1648 * doing VS-stage page table walk.
1649 */
1650 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1651 }
1652 break;
1653 case RISCV_EXCP_ILLEGAL_INST:
1654 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
1655 tval = env->bins;
1656 break;
1657 case RISCV_EXCP_BREAKPOINT:
1658 if (cs->watchpoint_hit) {
1659 tval = cs->watchpoint_hit->hitaddr;
1660 cs->watchpoint_hit = NULL;
1661 }
1662 break;
1663 default:
1664 break;
1665 }
1666 /* ecall is dispatched as one cause so translate based on mode */
1667 if (cause == RISCV_EXCP_U_ECALL) {
1668 assert(env->priv <= 3);
1669
1670 if (env->priv == PRV_M) {
1671 cause = RISCV_EXCP_M_ECALL;
1672 } else if (env->priv == PRV_S && env->virt_enabled) {
1673 cause = RISCV_EXCP_VS_ECALL;
1674 } else if (env->priv == PRV_S && !env->virt_enabled) {
1675 cause = RISCV_EXCP_S_ECALL;
1676 } else if (env->priv == PRV_U) {
1677 cause = RISCV_EXCP_U_ECALL;
1678 }
1679 }
1680 }
1681
1682 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
1683 riscv_cpu_get_trap_name(cause, async));
1684
1685 qemu_log_mask(CPU_LOG_INT,
1686 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
1687 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
1688 __func__, env->mhartid, async, cause, env->pc, tval,
1689 riscv_cpu_get_trap_name(cause, async));
1690
1691 if (env->priv <= PRV_S &&
1692 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
1693 /* handle the trap in S-mode */
1694 if (riscv_has_ext(env, RVH)) {
1695 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1696
1697 if (env->virt_enabled && ((hdeleg >> cause) & 1)) {
1698 /* Trap to VS mode */
1699 /*
1700 * See if we need to adjust cause. Yes if its VS mode interrupt
1701 * no if hypervisor has delegated one of hs mode's interrupt
1702 */
1703 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
1704 cause == IRQ_VS_EXT) {
1705 cause = cause - 1;
1706 }
1707 write_gva = false;
1708 } else if (env->virt_enabled) {
1709 /* Trap into HS mode, from virt */
1710 riscv_cpu_swap_hypervisor_regs(env);
1711 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
1712 env->priv);
1713 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
1714
1715 htval = env->guest_phys_fault_addr;
1716
1717 riscv_cpu_set_virt_enabled(env, 0);
1718 } else {
1719 /* Trap into HS mode */
1720 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
1721 htval = env->guest_phys_fault_addr;
1722 }
1723 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
1724 }
1725
1726 s = env->mstatus;
1727 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
1728 s = set_field(s, MSTATUS_SPP, env->priv);
1729 s = set_field(s, MSTATUS_SIE, 0);
1730 env->mstatus = s;
1731 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
1732 env->sepc = env->pc;
1733 env->stval = tval;
1734 env->htval = htval;
1735 env->htinst = tinst;
1736 env->pc = (env->stvec >> 2 << 2) +
1737 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
1738 riscv_cpu_set_mode(env, PRV_S);
1739 } else {
1740 /* handle the trap in M-mode */
1741 if (riscv_has_ext(env, RVH)) {
1742 if (env->virt_enabled) {
1743 riscv_cpu_swap_hypervisor_regs(env);
1744 }
1745 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
1746 env->virt_enabled);
1747 if (env->virt_enabled && tval) {
1748 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1749 }
1750
1751 mtval2 = env->guest_phys_fault_addr;
1752
1753 /* Trapping to M mode, virt is disabled */
1754 riscv_cpu_set_virt_enabled(env, 0);
1755 }
1756
1757 s = env->mstatus;
1758 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
1759 s = set_field(s, MSTATUS_MPP, env->priv);
1760 s = set_field(s, MSTATUS_MIE, 0);
1761 env->mstatus = s;
1762 env->mcause = cause | ~(((target_ulong)-1) >> async);
1763 env->mepc = env->pc;
1764 env->mtval = tval;
1765 env->mtval2 = mtval2;
1766 env->mtinst = tinst;
1767 env->pc = (env->mtvec >> 2 << 2) +
1768 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
1769 riscv_cpu_set_mode(env, PRV_M);
1770 }
1771
1772 /*
1773 * NOTE: it is not necessary to yield load reservations here. It is only
1774 * necessary for an SC from "another hart" to cause a load reservation
1775 * to be yielded. Refer to the memory consistency model section of the
1776 * RISC-V ISA Specification.
1777 */
1778
1779 env->two_stage_lookup = false;
1780 env->two_stage_indirect_lookup = false;
1781 #endif
1782 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
1783 }
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