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target/riscv: Introduce mmuidx_priv
[mirror_qemu.git] / target / riscv / cpu_helper.c
1 /*
2 * RISC-V CPU helpers for qemu.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/main-loop.h"
23 #include "cpu.h"
24 #include "internals.h"
25 #include "pmu.h"
26 #include "exec/exec-all.h"
27 #include "instmap.h"
28 #include "tcg/tcg-op.h"
29 #include "trace.h"
30 #include "semihosting/common-semi.h"
31 #include "sysemu/cpu-timers.h"
32 #include "cpu_bits.h"
33 #include "debug.h"
34
35 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
36 {
37 #ifdef CONFIG_USER_ONLY
38 return 0;
39 #else
40 if (ifetch) {
41 return env->priv;
42 }
43
44 /* All priv -> mmu_idx mapping are here */
45 int mode = env->priv;
46 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
47 mode = get_field(env->mstatus, MSTATUS_MPP);
48 }
49 if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) {
50 return MMUIdx_S_SUM;
51 }
52 return mode;
53 #endif
54 }
55
56 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
57 target_ulong *cs_base, uint32_t *pflags)
58 {
59 CPUState *cs = env_cpu(env);
60 RISCVCPU *cpu = RISCV_CPU(cs);
61 RISCVExtStatus fs, vs;
62 uint32_t flags = 0;
63
64 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
65 *cs_base = 0;
66
67 if (cpu->cfg.ext_zve32f) {
68 /*
69 * If env->vl equals to VLMAX, we can use generic vector operation
70 * expanders (GVEC) to accerlate the vector operations.
71 * However, as LMUL could be a fractional number. The maximum
72 * vector size can be operated might be less than 8 bytes,
73 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
74 * only when maxsz >= 8 bytes.
75 */
76 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype);
77 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
78 uint32_t maxsz = vlmax << sew;
79 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
80 (maxsz >= 8);
81 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
82 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
83 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
84 FIELD_EX64(env->vtype, VTYPE, VLMUL));
85 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
86 flags = FIELD_DP32(flags, TB_FLAGS, VTA,
87 FIELD_EX64(env->vtype, VTYPE, VTA));
88 flags = FIELD_DP32(flags, TB_FLAGS, VMA,
89 FIELD_EX64(env->vtype, VTYPE, VMA));
90 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
91 } else {
92 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
93 }
94
95 #ifdef CONFIG_USER_ONLY
96 fs = EXT_STATUS_DIRTY;
97 vs = EXT_STATUS_DIRTY;
98 #else
99 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
100
101 flags |= cpu_mmu_index(env, 0);
102 fs = get_field(env->mstatus, MSTATUS_FS);
103 vs = get_field(env->mstatus, MSTATUS_VS);
104
105 if (env->virt_enabled) {
106 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
107 /*
108 * Merge DISABLED and !DIRTY states using MIN.
109 * We will set both fields when dirtying.
110 */
111 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
112 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
113 }
114
115 if (cpu->cfg.debug && !icount_enabled()) {
116 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
117 }
118 #endif
119
120 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
121 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
122 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
123 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
124 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
125 }
126 if (env->cur_pmbase != 0) {
127 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
128 }
129
130 *pflags = flags;
131 }
132
133 void riscv_cpu_update_mask(CPURISCVState *env)
134 {
135 target_ulong mask = -1, base = 0;
136 /*
137 * TODO: Current RVJ spec does not specify
138 * how the extension interacts with XLEN.
139 */
140 #ifndef CONFIG_USER_ONLY
141 if (riscv_has_ext(env, RVJ)) {
142 switch (env->priv) {
143 case PRV_M:
144 if (env->mmte & M_PM_ENABLE) {
145 mask = env->mpmmask;
146 base = env->mpmbase;
147 }
148 break;
149 case PRV_S:
150 if (env->mmte & S_PM_ENABLE) {
151 mask = env->spmmask;
152 base = env->spmbase;
153 }
154 break;
155 case PRV_U:
156 if (env->mmte & U_PM_ENABLE) {
157 mask = env->upmmask;
158 base = env->upmbase;
159 }
160 break;
161 default:
162 g_assert_not_reached();
163 }
164 }
165 #endif
166 if (env->xl == MXL_RV32) {
167 env->cur_pmmask = mask & UINT32_MAX;
168 env->cur_pmbase = base & UINT32_MAX;
169 } else {
170 env->cur_pmmask = mask;
171 env->cur_pmbase = base;
172 }
173 }
174
175 #ifndef CONFIG_USER_ONLY
176
177 /*
178 * The HS-mode is allowed to configure priority only for the
179 * following VS-mode local interrupts:
180 *
181 * 0 (Reserved interrupt, reads as zero)
182 * 1 Supervisor software interrupt
183 * 4 (Reserved interrupt, reads as zero)
184 * 5 Supervisor timer interrupt
185 * 8 (Reserved interrupt, reads as zero)
186 * 13 (Reserved interrupt)
187 * 14 "
188 * 15 "
189 * 16 "
190 * 17 "
191 * 18 "
192 * 19 "
193 * 20 "
194 * 21 "
195 * 22 "
196 * 23 "
197 */
198
199 static const int hviprio_index2irq[] = {
200 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
201 static const int hviprio_index2rdzero[] = {
202 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
203
204 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero)
205 {
206 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) {
207 return -EINVAL;
208 }
209
210 if (out_irq) {
211 *out_irq = hviprio_index2irq[index];
212 }
213
214 if (out_rdzero) {
215 *out_rdzero = hviprio_index2rdzero[index];
216 }
217
218 return 0;
219 }
220
221 /*
222 * Default priorities of local interrupts are defined in the
223 * RISC-V Advanced Interrupt Architecture specification.
224 *
225 * ----------------------------------------------------------------
226 * Default |
227 * Priority | Major Interrupt Numbers
228 * ----------------------------------------------------------------
229 * Highest | 47, 23, 46, 45, 22, 44,
230 * | 43, 21, 42, 41, 20, 40
231 * |
232 * | 11 (0b), 3 (03), 7 (07)
233 * | 9 (09), 1 (01), 5 (05)
234 * | 12 (0c)
235 * | 10 (0a), 2 (02), 6 (06)
236 * |
237 * | 39, 19, 38, 37, 18, 36,
238 * Lowest | 35, 17, 34, 33, 16, 32
239 * ----------------------------------------------------------------
240 */
241 static const uint8_t default_iprio[64] = {
242 /* Custom interrupts 48 to 63 */
243 [63] = IPRIO_MMAXIPRIO,
244 [62] = IPRIO_MMAXIPRIO,
245 [61] = IPRIO_MMAXIPRIO,
246 [60] = IPRIO_MMAXIPRIO,
247 [59] = IPRIO_MMAXIPRIO,
248 [58] = IPRIO_MMAXIPRIO,
249 [57] = IPRIO_MMAXIPRIO,
250 [56] = IPRIO_MMAXIPRIO,
251 [55] = IPRIO_MMAXIPRIO,
252 [54] = IPRIO_MMAXIPRIO,
253 [53] = IPRIO_MMAXIPRIO,
254 [52] = IPRIO_MMAXIPRIO,
255 [51] = IPRIO_MMAXIPRIO,
256 [50] = IPRIO_MMAXIPRIO,
257 [49] = IPRIO_MMAXIPRIO,
258 [48] = IPRIO_MMAXIPRIO,
259
260 /* Custom interrupts 24 to 31 */
261 [31] = IPRIO_MMAXIPRIO,
262 [30] = IPRIO_MMAXIPRIO,
263 [29] = IPRIO_MMAXIPRIO,
264 [28] = IPRIO_MMAXIPRIO,
265 [27] = IPRIO_MMAXIPRIO,
266 [26] = IPRIO_MMAXIPRIO,
267 [25] = IPRIO_MMAXIPRIO,
268 [24] = IPRIO_MMAXIPRIO,
269
270 [47] = IPRIO_DEFAULT_UPPER,
271 [23] = IPRIO_DEFAULT_UPPER + 1,
272 [46] = IPRIO_DEFAULT_UPPER + 2,
273 [45] = IPRIO_DEFAULT_UPPER + 3,
274 [22] = IPRIO_DEFAULT_UPPER + 4,
275 [44] = IPRIO_DEFAULT_UPPER + 5,
276
277 [43] = IPRIO_DEFAULT_UPPER + 6,
278 [21] = IPRIO_DEFAULT_UPPER + 7,
279 [42] = IPRIO_DEFAULT_UPPER + 8,
280 [41] = IPRIO_DEFAULT_UPPER + 9,
281 [20] = IPRIO_DEFAULT_UPPER + 10,
282 [40] = IPRIO_DEFAULT_UPPER + 11,
283
284 [11] = IPRIO_DEFAULT_M,
285 [3] = IPRIO_DEFAULT_M + 1,
286 [7] = IPRIO_DEFAULT_M + 2,
287
288 [9] = IPRIO_DEFAULT_S,
289 [1] = IPRIO_DEFAULT_S + 1,
290 [5] = IPRIO_DEFAULT_S + 2,
291
292 [12] = IPRIO_DEFAULT_SGEXT,
293
294 [10] = IPRIO_DEFAULT_VS,
295 [2] = IPRIO_DEFAULT_VS + 1,
296 [6] = IPRIO_DEFAULT_VS + 2,
297
298 [39] = IPRIO_DEFAULT_LOWER,
299 [19] = IPRIO_DEFAULT_LOWER + 1,
300 [38] = IPRIO_DEFAULT_LOWER + 2,
301 [37] = IPRIO_DEFAULT_LOWER + 3,
302 [18] = IPRIO_DEFAULT_LOWER + 4,
303 [36] = IPRIO_DEFAULT_LOWER + 5,
304
305 [35] = IPRIO_DEFAULT_LOWER + 6,
306 [17] = IPRIO_DEFAULT_LOWER + 7,
307 [34] = IPRIO_DEFAULT_LOWER + 8,
308 [33] = IPRIO_DEFAULT_LOWER + 9,
309 [16] = IPRIO_DEFAULT_LOWER + 10,
310 [32] = IPRIO_DEFAULT_LOWER + 11,
311 };
312
313 uint8_t riscv_cpu_default_priority(int irq)
314 {
315 if (irq < 0 || irq > 63) {
316 return IPRIO_MMAXIPRIO;
317 }
318
319 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
320 };
321
322 static int riscv_cpu_pending_to_irq(CPURISCVState *env,
323 int extirq, unsigned int extirq_def_prio,
324 uint64_t pending, uint8_t *iprio)
325 {
326 int irq, best_irq = RISCV_EXCP_NONE;
327 unsigned int prio, best_prio = UINT_MAX;
328
329 if (!pending) {
330 return RISCV_EXCP_NONE;
331 }
332
333 irq = ctz64(pending);
334 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
335 riscv_cpu_cfg(env)->ext_ssaia)) {
336 return irq;
337 }
338
339 pending = pending >> irq;
340 while (pending) {
341 prio = iprio[irq];
342 if (!prio) {
343 if (irq == extirq) {
344 prio = extirq_def_prio;
345 } else {
346 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ?
347 1 : IPRIO_MMAXIPRIO;
348 }
349 }
350 if ((pending & 0x1) && (prio <= best_prio)) {
351 best_irq = irq;
352 best_prio = prio;
353 }
354 irq++;
355 pending = pending >> 1;
356 }
357
358 return best_irq;
359 }
360
361 uint64_t riscv_cpu_all_pending(CPURISCVState *env)
362 {
363 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
364 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
365 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0;
366
367 return (env->mip | vsgein | vstip) & env->mie;
368 }
369
370 int riscv_cpu_mirq_pending(CPURISCVState *env)
371 {
372 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
373 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
374
375 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
376 irqs, env->miprio);
377 }
378
379 int riscv_cpu_sirq_pending(CPURISCVState *env)
380 {
381 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
382 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
383
384 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
385 irqs, env->siprio);
386 }
387
388 int riscv_cpu_vsirq_pending(CPURISCVState *env)
389 {
390 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
391 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
392
393 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
394 irqs >> 1, env->hviprio);
395 }
396
397 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
398 {
399 int virq;
400 uint64_t irqs, pending, mie, hsie, vsie;
401
402 /* Determine interrupt enable state of all privilege modes */
403 if (env->virt_enabled) {
404 mie = 1;
405 hsie = 1;
406 vsie = (env->priv < PRV_S) ||
407 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
408 } else {
409 mie = (env->priv < PRV_M) ||
410 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE));
411 hsie = (env->priv < PRV_S) ||
412 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE));
413 vsie = 0;
414 }
415
416 /* Determine all pending interrupts */
417 pending = riscv_cpu_all_pending(env);
418
419 /* Check M-mode interrupts */
420 irqs = pending & ~env->mideleg & -mie;
421 if (irqs) {
422 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M,
423 irqs, env->miprio);
424 }
425
426 /* Check HS-mode interrupts */
427 irqs = pending & env->mideleg & ~env->hideleg & -hsie;
428 if (irqs) {
429 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
430 irqs, env->siprio);
431 }
432
433 /* Check VS-mode interrupts */
434 irqs = pending & env->mideleg & env->hideleg & -vsie;
435 if (irqs) {
436 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
437 irqs >> 1, env->hviprio);
438 return (virq <= 0) ? virq : virq + 1;
439 }
440
441 /* Indicate no pending interrupt */
442 return RISCV_EXCP_NONE;
443 }
444
445 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
446 {
447 if (interrupt_request & CPU_INTERRUPT_HARD) {
448 RISCVCPU *cpu = RISCV_CPU(cs);
449 CPURISCVState *env = &cpu->env;
450 int interruptno = riscv_cpu_local_irq_pending(env);
451 if (interruptno >= 0) {
452 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
453 riscv_cpu_do_interrupt(cs);
454 return true;
455 }
456 }
457 return false;
458 }
459
460 /* Return true is floating point support is currently enabled */
461 bool riscv_cpu_fp_enabled(CPURISCVState *env)
462 {
463 if (env->mstatus & MSTATUS_FS) {
464 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
465 return false;
466 }
467 return true;
468 }
469
470 return false;
471 }
472
473 /* Return true is vector support is currently enabled */
474 bool riscv_cpu_vector_enabled(CPURISCVState *env)
475 {
476 if (env->mstatus & MSTATUS_VS) {
477 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
478 return false;
479 }
480 return true;
481 }
482
483 return false;
484 }
485
486 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
487 {
488 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
489 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
490 MSTATUS64_UXL | MSTATUS_VS;
491
492 if (riscv_has_ext(env, RVF)) {
493 mstatus_mask |= MSTATUS_FS;
494 }
495 bool current_virt = env->virt_enabled;
496
497 g_assert(riscv_has_ext(env, RVH));
498
499 if (current_virt) {
500 /* Current V=1 and we are about to change to V=0 */
501 env->vsstatus = env->mstatus & mstatus_mask;
502 env->mstatus &= ~mstatus_mask;
503 env->mstatus |= env->mstatus_hs;
504
505 env->vstvec = env->stvec;
506 env->stvec = env->stvec_hs;
507
508 env->vsscratch = env->sscratch;
509 env->sscratch = env->sscratch_hs;
510
511 env->vsepc = env->sepc;
512 env->sepc = env->sepc_hs;
513
514 env->vscause = env->scause;
515 env->scause = env->scause_hs;
516
517 env->vstval = env->stval;
518 env->stval = env->stval_hs;
519
520 env->vsatp = env->satp;
521 env->satp = env->satp_hs;
522 } else {
523 /* Current V=0 and we are about to change to V=1 */
524 env->mstatus_hs = env->mstatus & mstatus_mask;
525 env->mstatus &= ~mstatus_mask;
526 env->mstatus |= env->vsstatus;
527
528 env->stvec_hs = env->stvec;
529 env->stvec = env->vstvec;
530
531 env->sscratch_hs = env->sscratch;
532 env->sscratch = env->vsscratch;
533
534 env->sepc_hs = env->sepc;
535 env->sepc = env->vsepc;
536
537 env->scause_hs = env->scause;
538 env->scause = env->vscause;
539
540 env->stval_hs = env->stval;
541 env->stval = env->vstval;
542
543 env->satp_hs = env->satp;
544 env->satp = env->vsatp;
545 }
546 }
547
548 target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
549 {
550 if (!riscv_has_ext(env, RVH)) {
551 return 0;
552 }
553
554 return env->geilen;
555 }
556
557 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
558 {
559 if (!riscv_has_ext(env, RVH)) {
560 return;
561 }
562
563 if (geilen > (TARGET_LONG_BITS - 1)) {
564 return;
565 }
566
567 env->geilen = geilen;
568 }
569
570 /* This function can only be called to set virt when RVH is enabled */
571 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
572 {
573 /* Flush the TLB on all virt mode changes. */
574 if (env->virt_enabled != enable) {
575 tlb_flush(env_cpu(env));
576 }
577
578 env->virt_enabled = enable;
579
580 if (enable) {
581 /*
582 * The guest external interrupts from an interrupt controller are
583 * delivered only when the Guest/VM is running (i.e. V=1). This means
584 * any guest external interrupt which is triggered while the Guest/VM
585 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
586 * with sluggish response to serial console input and other I/O events.
587 *
588 * To solve this, we check and inject interrupt after setting V=1.
589 */
590 riscv_cpu_update_mip(env, 0, 0);
591 }
592 }
593
594 bool riscv_cpu_two_stage_lookup(int mmu_idx)
595 {
596 return mmu_idx & MMU_2STAGE_BIT;
597 }
598
599 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
600 {
601 CPURISCVState *env = &cpu->env;
602 if (env->miclaim & interrupts) {
603 return -1;
604 } else {
605 env->miclaim |= interrupts;
606 return 0;
607 }
608 }
609
610 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
611 uint64_t value)
612 {
613 CPUState *cs = env_cpu(env);
614 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
615
616 if (env->virt_enabled) {
617 gein = get_field(env->hstatus, HSTATUS_VGEIN);
618 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
619 }
620
621 vstip = env->vstime_irq ? MIP_VSTIP : 0;
622
623 QEMU_IOTHREAD_LOCK_GUARD();
624
625 env->mip = (env->mip & ~mask) | (value & mask);
626
627 if (env->mip | vsgein | vstip) {
628 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
629 } else {
630 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
631 }
632
633 return old;
634 }
635
636 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
637 void *arg)
638 {
639 env->rdtime_fn = fn;
640 env->rdtime_fn_arg = arg;
641 }
642
643 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
644 int (*rmw_fn)(void *arg,
645 target_ulong reg,
646 target_ulong *val,
647 target_ulong new_val,
648 target_ulong write_mask),
649 void *rmw_fn_arg)
650 {
651 if (priv <= PRV_M) {
652 env->aia_ireg_rmw_fn[priv] = rmw_fn;
653 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
654 }
655 }
656
657 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
658 {
659 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
660
661 if (icount_enabled() && newpriv != env->priv) {
662 riscv_itrigger_update_priv(env);
663 }
664 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
665 env->priv = newpriv;
666 env->xl = cpu_recompute_xl(env);
667 riscv_cpu_update_mask(env);
668
669 /*
670 * Clear the load reservation - otherwise a reservation placed in one
671 * context/process can be used by another, resulting in an SC succeeding
672 * incorrectly. Version 2.2 of the ISA specification explicitly requires
673 * this behaviour, while later revisions say that the kernel "should" use
674 * an SC instruction to force the yielding of a load reservation on a
675 * preemptive context switch. As a result, do both.
676 */
677 env->load_res = -1;
678 }
679
680 /*
681 * get_physical_address_pmp - check PMP permission for this physical address
682 *
683 * Match the PMP region and check permission for this physical address and it's
684 * TLB page. Returns 0 if the permission checking was successful
685 *
686 * @env: CPURISCVState
687 * @prot: The returned protection attributes
688 * @tlb_size: TLB page size containing addr. It could be modified after PMP
689 * permission checking. NULL if not set TLB page for addr.
690 * @addr: The physical address to be checked permission
691 * @access_type: The type of MMU access
692 * @mode: Indicates current privilege level.
693 */
694 static int get_physical_address_pmp(CPURISCVState *env, int *prot,
695 target_ulong *tlb_size, hwaddr addr,
696 int size, MMUAccessType access_type,
697 int mode)
698 {
699 pmp_priv_t pmp_priv;
700 int pmp_index = -1;
701
702 if (!riscv_cpu_cfg(env)->pmp) {
703 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
704 return TRANSLATE_SUCCESS;
705 }
706
707 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
708 &pmp_priv, mode);
709 if (pmp_index < 0) {
710 *prot = 0;
711 return TRANSLATE_PMP_FAIL;
712 }
713
714 *prot = pmp_priv_to_page_prot(pmp_priv);
715 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
716 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
717 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
718
719 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
720 }
721
722 return TRANSLATE_SUCCESS;
723 }
724
725 /*
726 * get_physical_address - get the physical address for this virtual address
727 *
728 * Do a page table walk to obtain the physical address corresponding to a
729 * virtual address. Returns 0 if the translation was successful
730 *
731 * Adapted from Spike's mmu_t::translate and mmu_t::walk
732 *
733 * @env: CPURISCVState
734 * @physical: This will be set to the calculated physical address
735 * @prot: The returned protection attributes
736 * @addr: The virtual address or guest physical address to be translated
737 * @fault_pte_addr: If not NULL, this will be set to fault pte address
738 * when a error occurs on pte address translation.
739 * This will already be shifted to match htval.
740 * @access_type: The type of MMU access
741 * @mmu_idx: Indicates current privilege level
742 * @first_stage: Are we in first stage translation?
743 * Second stage is used for hypervisor guest translation
744 * @two_stage: Are we going to perform two stage translation
745 * @is_debug: Is this access from a debugger or the monitor?
746 */
747 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
748 int *prot, vaddr addr,
749 target_ulong *fault_pte_addr,
750 int access_type, int mmu_idx,
751 bool first_stage, bool two_stage,
752 bool is_debug)
753 {
754 /*
755 * NOTE: the env->pc value visible here will not be
756 * correct, but the value visible to the exception handler
757 * (riscv_cpu_do_interrupt) is correct
758 */
759 MemTxResult res;
760 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
761 int mode = mmuidx_priv(mmu_idx);
762 bool use_background = false;
763 hwaddr ppn;
764 int napot_bits = 0;
765 target_ulong napot_mask;
766
767 /*
768 * Check if we should use the background registers for the two
769 * stage translation. We don't need to check if we actually need
770 * two stage translation as that happened before this function
771 * was called. Background registers will be used if the guest has
772 * forced a two stage translation to be on (in HS or M mode).
773 */
774 if (!env->virt_enabled && two_stage) {
775 use_background = true;
776 }
777
778 /*
779 * MPRV does not affect the virtual-machine load/store
780 * instructions, HLV, HLVX, and HSV.
781 */
782 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
783 mode = get_field(env->hstatus, HSTATUS_SPVP);
784 }
785
786 if (first_stage == false) {
787 /*
788 * We are in stage 2 translation, this is similar to stage 1.
789 * Stage 2 is always taken as U-mode
790 */
791 mode = PRV_U;
792 }
793
794 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
795 *physical = addr;
796 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
797 return TRANSLATE_SUCCESS;
798 }
799
800 *prot = 0;
801
802 hwaddr base;
803 int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
804
805 if (first_stage == true) {
806 mxr = get_field(env->mstatus, MSTATUS_MXR);
807 } else {
808 mxr = get_field(env->vsstatus, MSTATUS_MXR);
809 }
810
811 if (first_stage == true) {
812 if (use_background) {
813 if (riscv_cpu_mxl(env) == MXL_RV32) {
814 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
815 vm = get_field(env->vsatp, SATP32_MODE);
816 } else {
817 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
818 vm = get_field(env->vsatp, SATP64_MODE);
819 }
820 } else {
821 if (riscv_cpu_mxl(env) == MXL_RV32) {
822 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
823 vm = get_field(env->satp, SATP32_MODE);
824 } else {
825 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
826 vm = get_field(env->satp, SATP64_MODE);
827 }
828 }
829 widened = 0;
830 } else {
831 if (riscv_cpu_mxl(env) == MXL_RV32) {
832 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
833 vm = get_field(env->hgatp, SATP32_MODE);
834 } else {
835 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
836 vm = get_field(env->hgatp, SATP64_MODE);
837 }
838 widened = 2;
839 }
840 /* status.SUM will be ignored if execute on background */
841 sum = mmuidx_sum(mmu_idx) || use_background || is_debug;
842 switch (vm) {
843 case VM_1_10_SV32:
844 levels = 2; ptidxbits = 10; ptesize = 4; break;
845 case VM_1_10_SV39:
846 levels = 3; ptidxbits = 9; ptesize = 8; break;
847 case VM_1_10_SV48:
848 levels = 4; ptidxbits = 9; ptesize = 8; break;
849 case VM_1_10_SV57:
850 levels = 5; ptidxbits = 9; ptesize = 8; break;
851 case VM_1_10_MBARE:
852 *physical = addr;
853 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
854 return TRANSLATE_SUCCESS;
855 default:
856 g_assert_not_reached();
857 }
858
859 CPUState *cs = env_cpu(env);
860 int va_bits = PGSHIFT + levels * ptidxbits + widened;
861 target_ulong mask, masked_msbs;
862
863 if (TARGET_LONG_BITS > (va_bits - 1)) {
864 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
865 } else {
866 mask = 0;
867 }
868 masked_msbs = (addr >> (va_bits - 1)) & mask;
869
870 if (masked_msbs != 0 && masked_msbs != mask) {
871 return TRANSLATE_FAIL;
872 }
873
874 int ptshift = (levels - 1) * ptidxbits;
875 int i;
876
877 #if !TCG_OVERSIZED_GUEST
878 restart:
879 #endif
880 for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
881 target_ulong idx;
882 if (i == 0) {
883 idx = (addr >> (PGSHIFT + ptshift)) &
884 ((1 << (ptidxbits + widened)) - 1);
885 } else {
886 idx = (addr >> (PGSHIFT + ptshift)) &
887 ((1 << ptidxbits) - 1);
888 }
889
890 /* check that physical address of PTE is legal */
891 hwaddr pte_addr;
892
893 if (two_stage && first_stage) {
894 int vbase_prot;
895 hwaddr vbase;
896
897 /* Do the second stage translation on the base PTE address. */
898 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
899 base, NULL, MMU_DATA_LOAD,
900 mmu_idx, false, true,
901 is_debug);
902
903 if (vbase_ret != TRANSLATE_SUCCESS) {
904 if (fault_pte_addr) {
905 *fault_pte_addr = (base + idx * ptesize) >> 2;
906 }
907 return TRANSLATE_G_STAGE_FAIL;
908 }
909
910 pte_addr = vbase + idx * ptesize;
911 } else {
912 pte_addr = base + idx * ptesize;
913 }
914
915 int pmp_prot;
916 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
917 sizeof(target_ulong),
918 MMU_DATA_LOAD, PRV_S);
919 if (pmp_ret != TRANSLATE_SUCCESS) {
920 return TRANSLATE_PMP_FAIL;
921 }
922
923 target_ulong pte;
924 if (riscv_cpu_mxl(env) == MXL_RV32) {
925 pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
926 } else {
927 pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
928 }
929
930 if (res != MEMTX_OK) {
931 return TRANSLATE_FAIL;
932 }
933
934 bool pbmte = env->menvcfg & MENVCFG_PBMTE;
935 bool hade = env->menvcfg & MENVCFG_HADE;
936
937 if (first_stage && two_stage && env->virt_enabled) {
938 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
939 hade = hade && (env->henvcfg & HENVCFG_HADE);
940 }
941
942 if (riscv_cpu_sxl(env) == MXL_RV32) {
943 ppn = pte >> PTE_PPN_SHIFT;
944 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
945 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
946 } else {
947 ppn = pte >> PTE_PPN_SHIFT;
948 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
949 return TRANSLATE_FAIL;
950 }
951 }
952
953 if (!(pte & PTE_V)) {
954 /* Invalid PTE */
955 return TRANSLATE_FAIL;
956 } else if (!pbmte && (pte & PTE_PBMT)) {
957 return TRANSLATE_FAIL;
958 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
959 /* Inner PTE, continue walking */
960 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
961 return TRANSLATE_FAIL;
962 }
963 base = ppn << PGSHIFT;
964 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
965 /* Reserved leaf PTE flags: PTE_W */
966 return TRANSLATE_FAIL;
967 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
968 /* Reserved leaf PTE flags: PTE_W + PTE_X */
969 return TRANSLATE_FAIL;
970 } else if ((pte & PTE_U) && ((mode != PRV_U) &&
971 (!sum || access_type == MMU_INST_FETCH))) {
972 /* User PTE flags when not U mode and mstatus.SUM is not set,
973 or the access type is an instruction fetch */
974 return TRANSLATE_FAIL;
975 } else if (!(pte & PTE_U) && (mode != PRV_S)) {
976 /* Supervisor PTE flags when not S mode */
977 return TRANSLATE_FAIL;
978 } else if (ppn & ((1ULL << ptshift) - 1)) {
979 /* Misaligned PPN */
980 return TRANSLATE_FAIL;
981 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
982 ((pte & PTE_X) && mxr))) {
983 /* Read access check failed */
984 return TRANSLATE_FAIL;
985 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
986 /* Write access check failed */
987 return TRANSLATE_FAIL;
988 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
989 /* Fetch access check failed */
990 return TRANSLATE_FAIL;
991 } else {
992 /* if necessary, set accessed and dirty bits. */
993 target_ulong updated_pte = pte | PTE_A |
994 (access_type == MMU_DATA_STORE ? PTE_D : 0);
995
996 /* Page table updates need to be atomic with MTTCG enabled */
997 if (updated_pte != pte) {
998 if (!hade) {
999 return TRANSLATE_FAIL;
1000 }
1001
1002 /*
1003 * - if accessed or dirty bits need updating, and the PTE is
1004 * in RAM, then we do so atomically with a compare and swap.
1005 * - if the PTE is in IO space or ROM, then it can't be updated
1006 * and we return TRANSLATE_FAIL.
1007 * - if the PTE changed by the time we went to update it, then
1008 * it is no longer valid and we must re-walk the page table.
1009 */
1010 MemoryRegion *mr;
1011 hwaddr l = sizeof(target_ulong), addr1;
1012 mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
1013 false, MEMTXATTRS_UNSPECIFIED);
1014 if (memory_region_is_ram(mr)) {
1015 target_ulong *pte_pa =
1016 qemu_map_ram_ptr(mr->ram_block, addr1);
1017 #if TCG_OVERSIZED_GUEST
1018 /*
1019 * MTTCG is not enabled on oversized TCG guests so
1020 * page table updates do not need to be atomic
1021 */
1022 *pte_pa = pte = updated_pte;
1023 #else
1024 target_ulong old_pte =
1025 qatomic_cmpxchg(pte_pa, pte, updated_pte);
1026 if (old_pte != pte) {
1027 goto restart;
1028 } else {
1029 pte = updated_pte;
1030 }
1031 #endif
1032 } else {
1033 /*
1034 * misconfigured PTE in ROM (AD bits are not preset) or
1035 * PTE is in IO space and can't be updated atomically
1036 */
1037 return TRANSLATE_FAIL;
1038 }
1039 }
1040
1041 /*
1042 * for superpage mappings, make a fake leaf PTE for the TLB's
1043 * benefit.
1044 */
1045 target_ulong vpn = addr >> PGSHIFT;
1046
1047 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
1048 napot_bits = ctzl(ppn) + 1;
1049 if ((i != (levels - 1)) || (napot_bits != 4)) {
1050 return TRANSLATE_FAIL;
1051 }
1052 }
1053
1054 napot_mask = (1 << napot_bits) - 1;
1055 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
1056 (vpn & (((target_ulong)1 << ptshift) - 1))
1057 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
1058
1059 /* set permissions on the TLB entry */
1060 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
1061 *prot |= PAGE_READ;
1062 }
1063 if (pte & PTE_X) {
1064 *prot |= PAGE_EXEC;
1065 }
1066 /*
1067 * add write permission on stores or if the page is already dirty,
1068 * so that we TLB miss on later writes to update the dirty bit
1069 */
1070 if ((pte & PTE_W) &&
1071 (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
1072 *prot |= PAGE_WRITE;
1073 }
1074 return TRANSLATE_SUCCESS;
1075 }
1076 }
1077 return TRANSLATE_FAIL;
1078 }
1079
1080 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
1081 MMUAccessType access_type, bool pmp_violation,
1082 bool first_stage, bool two_stage,
1083 bool two_stage_indirect)
1084 {
1085 CPUState *cs = env_cpu(env);
1086 int page_fault_exceptions, vm;
1087 uint64_t stap_mode;
1088
1089 if (riscv_cpu_mxl(env) == MXL_RV32) {
1090 stap_mode = SATP32_MODE;
1091 } else {
1092 stap_mode = SATP64_MODE;
1093 }
1094
1095 if (first_stage) {
1096 vm = get_field(env->satp, stap_mode);
1097 } else {
1098 vm = get_field(env->hgatp, stap_mode);
1099 }
1100
1101 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
1102
1103 switch (access_type) {
1104 case MMU_INST_FETCH:
1105 if (env->virt_enabled && !first_stage) {
1106 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
1107 } else {
1108 cs->exception_index = page_fault_exceptions ?
1109 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
1110 }
1111 break;
1112 case MMU_DATA_LOAD:
1113 if (two_stage && !first_stage) {
1114 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
1115 } else {
1116 cs->exception_index = page_fault_exceptions ?
1117 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
1118 }
1119 break;
1120 case MMU_DATA_STORE:
1121 if (two_stage && !first_stage) {
1122 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
1123 } else {
1124 cs->exception_index = page_fault_exceptions ?
1125 RISCV_EXCP_STORE_PAGE_FAULT :
1126 RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1127 }
1128 break;
1129 default:
1130 g_assert_not_reached();
1131 }
1132 env->badaddr = address;
1133 env->two_stage_lookup = two_stage;
1134 env->two_stage_indirect_lookup = two_stage_indirect;
1135 }
1136
1137 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
1138 {
1139 RISCVCPU *cpu = RISCV_CPU(cs);
1140 CPURISCVState *env = &cpu->env;
1141 hwaddr phys_addr;
1142 int prot;
1143 int mmu_idx = cpu_mmu_index(&cpu->env, false);
1144
1145 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
1146 true, env->virt_enabled, true)) {
1147 return -1;
1148 }
1149
1150 if (env->virt_enabled) {
1151 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
1152 0, mmu_idx, false, true, true)) {
1153 return -1;
1154 }
1155 }
1156
1157 return phys_addr & TARGET_PAGE_MASK;
1158 }
1159
1160 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1161 vaddr addr, unsigned size,
1162 MMUAccessType access_type,
1163 int mmu_idx, MemTxAttrs attrs,
1164 MemTxResult response, uintptr_t retaddr)
1165 {
1166 RISCVCPU *cpu = RISCV_CPU(cs);
1167 CPURISCVState *env = &cpu->env;
1168
1169 if (access_type == MMU_DATA_STORE) {
1170 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
1171 } else if (access_type == MMU_DATA_LOAD) {
1172 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
1173 } else {
1174 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
1175 }
1176
1177 env->badaddr = addr;
1178 env->two_stage_lookup = env->virt_enabled ||
1179 riscv_cpu_two_stage_lookup(mmu_idx);
1180 env->two_stage_indirect_lookup = false;
1181 cpu_loop_exit_restore(cs, retaddr);
1182 }
1183
1184 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1185 MMUAccessType access_type, int mmu_idx,
1186 uintptr_t retaddr)
1187 {
1188 RISCVCPU *cpu = RISCV_CPU(cs);
1189 CPURISCVState *env = &cpu->env;
1190 switch (access_type) {
1191 case MMU_INST_FETCH:
1192 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
1193 break;
1194 case MMU_DATA_LOAD:
1195 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
1196 break;
1197 case MMU_DATA_STORE:
1198 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
1199 break;
1200 default:
1201 g_assert_not_reached();
1202 }
1203 env->badaddr = addr;
1204 env->two_stage_lookup = env->virt_enabled ||
1205 riscv_cpu_two_stage_lookup(mmu_idx);
1206 env->two_stage_indirect_lookup = false;
1207 cpu_loop_exit_restore(cs, retaddr);
1208 }
1209
1210
1211 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
1212 {
1213 enum riscv_pmu_event_idx pmu_event_type;
1214
1215 switch (access_type) {
1216 case MMU_INST_FETCH:
1217 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
1218 break;
1219 case MMU_DATA_LOAD:
1220 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
1221 break;
1222 case MMU_DATA_STORE:
1223 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
1224 break;
1225 default:
1226 return;
1227 }
1228
1229 riscv_pmu_incr_ctr(cpu, pmu_event_type);
1230 }
1231
1232 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1233 MMUAccessType access_type, int mmu_idx,
1234 bool probe, uintptr_t retaddr)
1235 {
1236 RISCVCPU *cpu = RISCV_CPU(cs);
1237 CPURISCVState *env = &cpu->env;
1238 vaddr im_address;
1239 hwaddr pa = 0;
1240 int prot, prot2, prot_pmp;
1241 bool pmp_violation = false;
1242 bool first_stage_error = true;
1243 bool two_stage_lookup = false;
1244 bool two_stage_indirect_error = false;
1245 int ret = TRANSLATE_FAIL;
1246 int mode = mmu_idx;
1247 /* default TLB page size */
1248 target_ulong tlb_size = TARGET_PAGE_SIZE;
1249
1250 env->guest_phys_fault_addr = 0;
1251
1252 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
1253 __func__, address, access_type, mmu_idx);
1254
1255 /*
1256 * MPRV does not affect the virtual-machine load/store
1257 * instructions, HLV, HLVX, and HSV.
1258 */
1259 if (riscv_cpu_two_stage_lookup(mmu_idx)) {
1260 mode = get_field(env->hstatus, HSTATUS_SPVP);
1261 } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
1262 get_field(env->mstatus, MSTATUS_MPRV)) {
1263 mode = get_field(env->mstatus, MSTATUS_MPP);
1264 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
1265 two_stage_lookup = true;
1266 }
1267 }
1268
1269 pmu_tlb_fill_incr_ctr(cpu, access_type);
1270 if (env->virt_enabled ||
1271 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
1272 access_type != MMU_INST_FETCH)) {
1273 /* Two stage lookup */
1274 ret = get_physical_address(env, &pa, &prot, address,
1275 &env->guest_phys_fault_addr, access_type,
1276 mmu_idx, true, true, false);
1277
1278 /*
1279 * A G-stage exception may be triggered during two state lookup.
1280 * And the env->guest_phys_fault_addr has already been set in
1281 * get_physical_address().
1282 */
1283 if (ret == TRANSLATE_G_STAGE_FAIL) {
1284 first_stage_error = false;
1285 two_stage_indirect_error = true;
1286 access_type = MMU_DATA_LOAD;
1287 }
1288
1289 qemu_log_mask(CPU_LOG_MMU,
1290 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
1291 HWADDR_FMT_plx " prot %d\n",
1292 __func__, address, ret, pa, prot);
1293
1294 if (ret == TRANSLATE_SUCCESS) {
1295 /* Second stage lookup */
1296 im_address = pa;
1297
1298 ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
1299 access_type, mmu_idx, false, true,
1300 false);
1301
1302 qemu_log_mask(CPU_LOG_MMU,
1303 "%s 2nd-stage address=%" VADDR_PRIx
1304 " ret %d physical "
1305 HWADDR_FMT_plx " prot %d\n",
1306 __func__, im_address, ret, pa, prot2);
1307
1308 prot &= prot2;
1309
1310 if (ret == TRANSLATE_SUCCESS) {
1311 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1312 size, access_type, mode);
1313
1314 qemu_log_mask(CPU_LOG_MMU,
1315 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1316 " %d tlb_size " TARGET_FMT_lu "\n",
1317 __func__, pa, ret, prot_pmp, tlb_size);
1318
1319 prot &= prot_pmp;
1320 }
1321
1322 if (ret != TRANSLATE_SUCCESS) {
1323 /*
1324 * Guest physical address translation failed, this is a HS
1325 * level exception
1326 */
1327 first_stage_error = false;
1328 env->guest_phys_fault_addr = (im_address |
1329 (address &
1330 (TARGET_PAGE_SIZE - 1))) >> 2;
1331 }
1332 }
1333 } else {
1334 /* Single stage lookup */
1335 ret = get_physical_address(env, &pa, &prot, address, NULL,
1336 access_type, mmu_idx, true, false, false);
1337
1338 qemu_log_mask(CPU_LOG_MMU,
1339 "%s address=%" VADDR_PRIx " ret %d physical "
1340 HWADDR_FMT_plx " prot %d\n",
1341 __func__, address, ret, pa, prot);
1342
1343 if (ret == TRANSLATE_SUCCESS) {
1344 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
1345 size, access_type, mode);
1346
1347 qemu_log_mask(CPU_LOG_MMU,
1348 "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
1349 " %d tlb_size " TARGET_FMT_lu "\n",
1350 __func__, pa, ret, prot_pmp, tlb_size);
1351
1352 prot &= prot_pmp;
1353 }
1354 }
1355
1356 if (ret == TRANSLATE_PMP_FAIL) {
1357 pmp_violation = true;
1358 }
1359
1360 if (ret == TRANSLATE_SUCCESS) {
1361 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
1362 prot, mmu_idx, tlb_size);
1363 return true;
1364 } else if (probe) {
1365 return false;
1366 } else {
1367 raise_mmu_exception(env, address, access_type, pmp_violation,
1368 first_stage_error,
1369 env->virt_enabled ||
1370 riscv_cpu_two_stage_lookup(mmu_idx),
1371 two_stage_indirect_error);
1372 cpu_loop_exit_restore(cs, retaddr);
1373 }
1374
1375 return true;
1376 }
1377
1378 static target_ulong riscv_transformed_insn(CPURISCVState *env,
1379 target_ulong insn,
1380 target_ulong taddr)
1381 {
1382 target_ulong xinsn = 0;
1383 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0;
1384
1385 /*
1386 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1387 * be uncompressed. The Quadrant 1 of RVC instruction space need
1388 * not be transformed because these instructions won't generate
1389 * any load/store trap.
1390 */
1391
1392 if ((insn & 0x3) != 0x3) {
1393 /* Transform 16bit instruction into 32bit instruction */
1394 switch (GET_C_OP(insn)) {
1395 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
1396 switch (GET_C_FUNC(insn)) {
1397 case OPC_RISC_C_FUNC_FLD_LQ:
1398 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */
1399 xinsn = OPC_RISC_FLD;
1400 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1401 access_rs1 = GET_C_RS1S(insn);
1402 access_imm = GET_C_LD_IMM(insn);
1403 access_size = 8;
1404 }
1405 break;
1406 case OPC_RISC_C_FUNC_LW: /* C.LW */
1407 xinsn = OPC_RISC_LW;
1408 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1409 access_rs1 = GET_C_RS1S(insn);
1410 access_imm = GET_C_LW_IMM(insn);
1411 access_size = 4;
1412 break;
1413 case OPC_RISC_C_FUNC_FLW_LD:
1414 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */
1415 xinsn = OPC_RISC_FLW;
1416 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1417 access_rs1 = GET_C_RS1S(insn);
1418 access_imm = GET_C_LW_IMM(insn);
1419 access_size = 4;
1420 } else { /* C.LD (RV64/RV128) */
1421 xinsn = OPC_RISC_LD;
1422 xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
1423 access_rs1 = GET_C_RS1S(insn);
1424 access_imm = GET_C_LD_IMM(insn);
1425 access_size = 8;
1426 }
1427 break;
1428 case OPC_RISC_C_FUNC_FSD_SQ:
1429 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */
1430 xinsn = OPC_RISC_FSD;
1431 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1432 access_rs1 = GET_C_RS1S(insn);
1433 access_imm = GET_C_SD_IMM(insn);
1434 access_size = 8;
1435 }
1436 break;
1437 case OPC_RISC_C_FUNC_SW: /* C.SW */
1438 xinsn = OPC_RISC_SW;
1439 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1440 access_rs1 = GET_C_RS1S(insn);
1441 access_imm = GET_C_SW_IMM(insn);
1442 access_size = 4;
1443 break;
1444 case OPC_RISC_C_FUNC_FSW_SD:
1445 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */
1446 xinsn = OPC_RISC_FSW;
1447 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1448 access_rs1 = GET_C_RS1S(insn);
1449 access_imm = GET_C_SW_IMM(insn);
1450 access_size = 4;
1451 } else { /* C.SD (RV64/RV128) */
1452 xinsn = OPC_RISC_SD;
1453 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
1454 access_rs1 = GET_C_RS1S(insn);
1455 access_imm = GET_C_SD_IMM(insn);
1456 access_size = 8;
1457 }
1458 break;
1459 default:
1460 break;
1461 }
1462 break;
1463 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
1464 switch (GET_C_FUNC(insn)) {
1465 case OPC_RISC_C_FUNC_FLDSP_LQSP:
1466 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */
1467 xinsn = OPC_RISC_FLD;
1468 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1469 access_rs1 = 2;
1470 access_imm = GET_C_LDSP_IMM(insn);
1471 access_size = 8;
1472 }
1473 break;
1474 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
1475 xinsn = OPC_RISC_LW;
1476 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1477 access_rs1 = 2;
1478 access_imm = GET_C_LWSP_IMM(insn);
1479 access_size = 4;
1480 break;
1481 case OPC_RISC_C_FUNC_FLWSP_LDSP:
1482 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */
1483 xinsn = OPC_RISC_FLW;
1484 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1485 access_rs1 = 2;
1486 access_imm = GET_C_LWSP_IMM(insn);
1487 access_size = 4;
1488 } else { /* C.LDSP (RV64/RV128) */
1489 xinsn = OPC_RISC_LD;
1490 xinsn = SET_RD(xinsn, GET_C_RD(insn));
1491 access_rs1 = 2;
1492 access_imm = GET_C_LDSP_IMM(insn);
1493 access_size = 8;
1494 }
1495 break;
1496 case OPC_RISC_C_FUNC_FSDSP_SQSP:
1497 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */
1498 xinsn = OPC_RISC_FSD;
1499 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1500 access_rs1 = 2;
1501 access_imm = GET_C_SDSP_IMM(insn);
1502 access_size = 8;
1503 }
1504 break;
1505 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
1506 xinsn = OPC_RISC_SW;
1507 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1508 access_rs1 = 2;
1509 access_imm = GET_C_SWSP_IMM(insn);
1510 access_size = 4;
1511 break;
1512 case 7:
1513 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */
1514 xinsn = OPC_RISC_FSW;
1515 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1516 access_rs1 = 2;
1517 access_imm = GET_C_SWSP_IMM(insn);
1518 access_size = 4;
1519 } else { /* C.SDSP (RV64/RV128) */
1520 xinsn = OPC_RISC_SD;
1521 xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
1522 access_rs1 = 2;
1523 access_imm = GET_C_SDSP_IMM(insn);
1524 access_size = 8;
1525 }
1526 break;
1527 default:
1528 break;
1529 }
1530 break;
1531 default:
1532 break;
1533 }
1534
1535 /*
1536 * Clear Bit1 of transformed instruction to indicate that
1537 * original insruction was a 16bit instruction
1538 */
1539 xinsn &= ~((target_ulong)0x2);
1540 } else {
1541 /* Transform 32bit (or wider) instructions */
1542 switch (MASK_OP_MAJOR(insn)) {
1543 case OPC_RISC_ATOMIC:
1544 xinsn = insn;
1545 access_rs1 = GET_RS1(insn);
1546 access_size = 1 << GET_FUNCT3(insn);
1547 break;
1548 case OPC_RISC_LOAD:
1549 case OPC_RISC_FP_LOAD:
1550 xinsn = SET_I_IMM(insn, 0);
1551 access_rs1 = GET_RS1(insn);
1552 access_imm = GET_IMM(insn);
1553 access_size = 1 << GET_FUNCT3(insn);
1554 break;
1555 case OPC_RISC_STORE:
1556 case OPC_RISC_FP_STORE:
1557 xinsn = SET_S_IMM(insn, 0);
1558 access_rs1 = GET_RS1(insn);
1559 access_imm = GET_STORE_IMM(insn);
1560 access_size = 1 << GET_FUNCT3(insn);
1561 break;
1562 case OPC_RISC_SYSTEM:
1563 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) {
1564 xinsn = insn;
1565 access_rs1 = GET_RS1(insn);
1566 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3);
1567 access_size = 1 << access_size;
1568 }
1569 break;
1570 default:
1571 break;
1572 }
1573 }
1574
1575 if (access_size) {
1576 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) &
1577 (access_size - 1));
1578 }
1579
1580 return xinsn;
1581 }
1582 #endif /* !CONFIG_USER_ONLY */
1583
1584 /*
1585 * Handle Traps
1586 *
1587 * Adapted from Spike's processor_t::take_trap.
1588 *
1589 */
1590 void riscv_cpu_do_interrupt(CPUState *cs)
1591 {
1592 #if !defined(CONFIG_USER_ONLY)
1593
1594 RISCVCPU *cpu = RISCV_CPU(cs);
1595 CPURISCVState *env = &cpu->env;
1596 bool write_gva = false;
1597 uint64_t s;
1598
1599 /*
1600 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1601 * so we mask off the MSB and separate into trap type and cause.
1602 */
1603 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
1604 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
1605 uint64_t deleg = async ? env->mideleg : env->medeleg;
1606 target_ulong tval = 0;
1607 target_ulong tinst = 0;
1608 target_ulong htval = 0;
1609 target_ulong mtval2 = 0;
1610
1611 if (cause == RISCV_EXCP_SEMIHOST) {
1612 do_common_semihosting(cs);
1613 env->pc += 4;
1614 return;
1615 }
1616
1617 if (!async) {
1618 /* set tval to badaddr for traps with address information */
1619 switch (cause) {
1620 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
1621 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
1622 case RISCV_EXCP_LOAD_ADDR_MIS:
1623 case RISCV_EXCP_STORE_AMO_ADDR_MIS:
1624 case RISCV_EXCP_LOAD_ACCESS_FAULT:
1625 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
1626 case RISCV_EXCP_LOAD_PAGE_FAULT:
1627 case RISCV_EXCP_STORE_PAGE_FAULT:
1628 write_gva = env->two_stage_lookup;
1629 tval = env->badaddr;
1630 if (env->two_stage_indirect_lookup) {
1631 /*
1632 * special pseudoinstruction for G-stage fault taken while
1633 * doing VS-stage page table walk.
1634 */
1635 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1636 } else {
1637 /*
1638 * The "Addr. Offset" field in transformed instruction is
1639 * non-zero only for misaligned access.
1640 */
1641 tinst = riscv_transformed_insn(env, env->bins, tval);
1642 }
1643 break;
1644 case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
1645 case RISCV_EXCP_INST_ADDR_MIS:
1646 case RISCV_EXCP_INST_ACCESS_FAULT:
1647 case RISCV_EXCP_INST_PAGE_FAULT:
1648 write_gva = env->two_stage_lookup;
1649 tval = env->badaddr;
1650 if (env->two_stage_indirect_lookup) {
1651 /*
1652 * special pseudoinstruction for G-stage fault taken while
1653 * doing VS-stage page table walk.
1654 */
1655 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000;
1656 }
1657 break;
1658 case RISCV_EXCP_ILLEGAL_INST:
1659 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
1660 tval = env->bins;
1661 break;
1662 case RISCV_EXCP_BREAKPOINT:
1663 if (cs->watchpoint_hit) {
1664 tval = cs->watchpoint_hit->hitaddr;
1665 cs->watchpoint_hit = NULL;
1666 }
1667 break;
1668 default:
1669 break;
1670 }
1671 /* ecall is dispatched as one cause so translate based on mode */
1672 if (cause == RISCV_EXCP_U_ECALL) {
1673 assert(env->priv <= 3);
1674
1675 if (env->priv == PRV_M) {
1676 cause = RISCV_EXCP_M_ECALL;
1677 } else if (env->priv == PRV_S && env->virt_enabled) {
1678 cause = RISCV_EXCP_VS_ECALL;
1679 } else if (env->priv == PRV_S && !env->virt_enabled) {
1680 cause = RISCV_EXCP_S_ECALL;
1681 } else if (env->priv == PRV_U) {
1682 cause = RISCV_EXCP_U_ECALL;
1683 }
1684 }
1685 }
1686
1687 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
1688 riscv_cpu_get_trap_name(cause, async));
1689
1690 qemu_log_mask(CPU_LOG_INT,
1691 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
1692 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
1693 __func__, env->mhartid, async, cause, env->pc, tval,
1694 riscv_cpu_get_trap_name(cause, async));
1695
1696 if (env->priv <= PRV_S &&
1697 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
1698 /* handle the trap in S-mode */
1699 if (riscv_has_ext(env, RVH)) {
1700 uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
1701
1702 if (env->virt_enabled && ((hdeleg >> cause) & 1)) {
1703 /* Trap to VS mode */
1704 /*
1705 * See if we need to adjust cause. Yes if its VS mode interrupt
1706 * no if hypervisor has delegated one of hs mode's interrupt
1707 */
1708 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
1709 cause == IRQ_VS_EXT) {
1710 cause = cause - 1;
1711 }
1712 write_gva = false;
1713 } else if (env->virt_enabled) {
1714 /* Trap into HS mode, from virt */
1715 riscv_cpu_swap_hypervisor_regs(env);
1716 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
1717 env->priv);
1718 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true);
1719
1720 htval = env->guest_phys_fault_addr;
1721
1722 riscv_cpu_set_virt_enabled(env, 0);
1723 } else {
1724 /* Trap into HS mode */
1725 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
1726 htval = env->guest_phys_fault_addr;
1727 }
1728 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva);
1729 }
1730
1731 s = env->mstatus;
1732 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
1733 s = set_field(s, MSTATUS_SPP, env->priv);
1734 s = set_field(s, MSTATUS_SIE, 0);
1735 env->mstatus = s;
1736 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
1737 env->sepc = env->pc;
1738 env->stval = tval;
1739 env->htval = htval;
1740 env->htinst = tinst;
1741 env->pc = (env->stvec >> 2 << 2) +
1742 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
1743 riscv_cpu_set_mode(env, PRV_S);
1744 } else {
1745 /* handle the trap in M-mode */
1746 if (riscv_has_ext(env, RVH)) {
1747 if (env->virt_enabled) {
1748 riscv_cpu_swap_hypervisor_regs(env);
1749 }
1750 env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
1751 env->virt_enabled);
1752 if (env->virt_enabled && tval) {
1753 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
1754 }
1755
1756 mtval2 = env->guest_phys_fault_addr;
1757
1758 /* Trapping to M mode, virt is disabled */
1759 riscv_cpu_set_virt_enabled(env, 0);
1760 }
1761
1762 s = env->mstatus;
1763 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
1764 s = set_field(s, MSTATUS_MPP, env->priv);
1765 s = set_field(s, MSTATUS_MIE, 0);
1766 env->mstatus = s;
1767 env->mcause = cause | ~(((target_ulong)-1) >> async);
1768 env->mepc = env->pc;
1769 env->mtval = tval;
1770 env->mtval2 = mtval2;
1771 env->mtinst = tinst;
1772 env->pc = (env->mtvec >> 2 << 2) +
1773 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
1774 riscv_cpu_set_mode(env, PRV_M);
1775 }
1776
1777 /*
1778 * NOTE: it is not necessary to yield load reservations here. It is only
1779 * necessary for an SC from "another hart" to cause a load reservation
1780 * to be yielded. Refer to the memory consistency model section of the
1781 * RISC-V ISA Specification.
1782 */
1783
1784 env->two_stage_lookup = false;
1785 env->two_stage_indirect_lookup = false;
1786 #endif
1787 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
1788 }
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