2 * RISC-V CPU helpers for qemu.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/main-loop.h"
24 #include "internals.h"
26 #include "exec/exec-all.h"
28 #include "tcg/tcg-op.h"
30 #include "semihosting/common-semi.h"
31 #include "sysemu/cpu-timers.h"
34 #include "tcg/oversized-guest.h"
36 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
)
38 #ifdef CONFIG_USER_ONLY
41 bool virt
= env
->virt_enabled
;
44 /* All priv -> mmu_idx mapping are here */
46 uint64_t status
= env
->mstatus
;
48 if (mode
== PRV_M
&& get_field(status
, MSTATUS_MPRV
)) {
49 mode
= get_field(env
->mstatus
, MSTATUS_MPP
);
50 virt
= get_field(env
->mstatus
, MSTATUS_MPV
);
52 status
= env
->vsstatus
;
55 if (mode
== PRV_S
&& get_field(status
, MSTATUS_SUM
)) {
60 return mode
| (virt
? MMU_2STAGE_BIT
: 0);
64 void cpu_get_tb_cpu_state(CPURISCVState
*env
, target_ulong
*pc
,
65 target_ulong
*cs_base
, uint32_t *pflags
)
67 CPUState
*cs
= env_cpu(env
);
68 RISCVCPU
*cpu
= RISCV_CPU(cs
);
69 RISCVExtStatus fs
, vs
;
72 *pc
= env
->xl
== MXL_RV32
? env
->pc
& UINT32_MAX
: env
->pc
;
75 if (cpu
->cfg
.ext_zve32f
) {
77 * If env->vl equals to VLMAX, we can use generic vector operation
78 * expanders (GVEC) to accerlate the vector operations.
79 * However, as LMUL could be a fractional number. The maximum
80 * vector size can be operated might be less than 8 bytes,
81 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
82 * only when maxsz >= 8 bytes.
84 uint32_t vlmax
= vext_get_vlmax(cpu
, env
->vtype
);
85 uint32_t sew
= FIELD_EX64(env
->vtype
, VTYPE
, VSEW
);
86 uint32_t maxsz
= vlmax
<< sew
;
87 bool vl_eq_vlmax
= (env
->vstart
== 0) && (vlmax
== env
->vl
) &&
89 flags
= FIELD_DP32(flags
, TB_FLAGS
, VILL
, env
->vill
);
90 flags
= FIELD_DP32(flags
, TB_FLAGS
, SEW
, sew
);
91 flags
= FIELD_DP32(flags
, TB_FLAGS
, LMUL
,
92 FIELD_EX64(env
->vtype
, VTYPE
, VLMUL
));
93 flags
= FIELD_DP32(flags
, TB_FLAGS
, VL_EQ_VLMAX
, vl_eq_vlmax
);
94 flags
= FIELD_DP32(flags
, TB_FLAGS
, VTA
,
95 FIELD_EX64(env
->vtype
, VTYPE
, VTA
));
96 flags
= FIELD_DP32(flags
, TB_FLAGS
, VMA
,
97 FIELD_EX64(env
->vtype
, VTYPE
, VMA
));
98 flags
= FIELD_DP32(flags
, TB_FLAGS
, VSTART_EQ_ZERO
, env
->vstart
== 0);
100 flags
= FIELD_DP32(flags
, TB_FLAGS
, VILL
, 1);
103 #ifdef CONFIG_USER_ONLY
104 fs
= EXT_STATUS_DIRTY
;
105 vs
= EXT_STATUS_DIRTY
;
107 flags
= FIELD_DP32(flags
, TB_FLAGS
, PRIV
, env
->priv
);
109 flags
|= cpu_mmu_index(env
, 0);
110 fs
= get_field(env
->mstatus
, MSTATUS_FS
);
111 vs
= get_field(env
->mstatus
, MSTATUS_VS
);
113 if (env
->virt_enabled
) {
114 flags
= FIELD_DP32(flags
, TB_FLAGS
, VIRT_ENABLED
, 1);
116 * Merge DISABLED and !DIRTY states using MIN.
117 * We will set both fields when dirtying.
119 fs
= MIN(fs
, get_field(env
->mstatus_hs
, MSTATUS_FS
));
120 vs
= MIN(vs
, get_field(env
->mstatus_hs
, MSTATUS_VS
));
123 if (cpu
->cfg
.debug
&& !icount_enabled()) {
124 flags
= FIELD_DP32(flags
, TB_FLAGS
, ITRIGGER
, env
->itrigger_enabled
);
128 flags
= FIELD_DP32(flags
, TB_FLAGS
, FS
, fs
);
129 flags
= FIELD_DP32(flags
, TB_FLAGS
, VS
, vs
);
130 flags
= FIELD_DP32(flags
, TB_FLAGS
, XL
, env
->xl
);
131 if (env
->cur_pmmask
< (env
->xl
== MXL_RV32
? UINT32_MAX
: UINT64_MAX
)) {
132 flags
= FIELD_DP32(flags
, TB_FLAGS
, PM_MASK_ENABLED
, 1);
134 if (env
->cur_pmbase
!= 0) {
135 flags
= FIELD_DP32(flags
, TB_FLAGS
, PM_BASE_ENABLED
, 1);
141 void riscv_cpu_update_mask(CPURISCVState
*env
)
143 target_ulong mask
= -1, base
= 0;
145 * TODO: Current RVJ spec does not specify
146 * how the extension interacts with XLEN.
148 #ifndef CONFIG_USER_ONLY
149 if (riscv_has_ext(env
, RVJ
)) {
152 if (env
->mmte
& M_PM_ENABLE
) {
158 if (env
->mmte
& S_PM_ENABLE
) {
164 if (env
->mmte
& U_PM_ENABLE
) {
170 g_assert_not_reached();
174 if (env
->xl
== MXL_RV32
) {
175 env
->cur_pmmask
= mask
& UINT32_MAX
;
176 env
->cur_pmbase
= base
& UINT32_MAX
;
178 env
->cur_pmmask
= mask
;
179 env
->cur_pmbase
= base
;
183 #ifndef CONFIG_USER_ONLY
186 * The HS-mode is allowed to configure priority only for the
187 * following VS-mode local interrupts:
189 * 0 (Reserved interrupt, reads as zero)
190 * 1 Supervisor software interrupt
191 * 4 (Reserved interrupt, reads as zero)
192 * 5 Supervisor timer interrupt
193 * 8 (Reserved interrupt, reads as zero)
194 * 13 (Reserved interrupt)
207 static const int hviprio_index2irq
[] = {
208 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
209 static const int hviprio_index2rdzero
[] = {
210 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
212 int riscv_cpu_hviprio_index2irq(int index
, int *out_irq
, int *out_rdzero
)
214 if (index
< 0 || ARRAY_SIZE(hviprio_index2irq
) <= index
) {
219 *out_irq
= hviprio_index2irq
[index
];
223 *out_rdzero
= hviprio_index2rdzero
[index
];
230 * Default priorities of local interrupts are defined in the
231 * RISC-V Advanced Interrupt Architecture specification.
233 * ----------------------------------------------------------------
235 * Priority | Major Interrupt Numbers
236 * ----------------------------------------------------------------
237 * Highest | 47, 23, 46, 45, 22, 44,
238 * | 43, 21, 42, 41, 20, 40
240 * | 11 (0b), 3 (03), 7 (07)
241 * | 9 (09), 1 (01), 5 (05)
243 * | 10 (0a), 2 (02), 6 (06)
245 * | 39, 19, 38, 37, 18, 36,
246 * Lowest | 35, 17, 34, 33, 16, 32
247 * ----------------------------------------------------------------
249 static const uint8_t default_iprio
[64] = {
250 /* Custom interrupts 48 to 63 */
251 [63] = IPRIO_MMAXIPRIO
,
252 [62] = IPRIO_MMAXIPRIO
,
253 [61] = IPRIO_MMAXIPRIO
,
254 [60] = IPRIO_MMAXIPRIO
,
255 [59] = IPRIO_MMAXIPRIO
,
256 [58] = IPRIO_MMAXIPRIO
,
257 [57] = IPRIO_MMAXIPRIO
,
258 [56] = IPRIO_MMAXIPRIO
,
259 [55] = IPRIO_MMAXIPRIO
,
260 [54] = IPRIO_MMAXIPRIO
,
261 [53] = IPRIO_MMAXIPRIO
,
262 [52] = IPRIO_MMAXIPRIO
,
263 [51] = IPRIO_MMAXIPRIO
,
264 [50] = IPRIO_MMAXIPRIO
,
265 [49] = IPRIO_MMAXIPRIO
,
266 [48] = IPRIO_MMAXIPRIO
,
268 /* Custom interrupts 24 to 31 */
269 [31] = IPRIO_MMAXIPRIO
,
270 [30] = IPRIO_MMAXIPRIO
,
271 [29] = IPRIO_MMAXIPRIO
,
272 [28] = IPRIO_MMAXIPRIO
,
273 [27] = IPRIO_MMAXIPRIO
,
274 [26] = IPRIO_MMAXIPRIO
,
275 [25] = IPRIO_MMAXIPRIO
,
276 [24] = IPRIO_MMAXIPRIO
,
278 [47] = IPRIO_DEFAULT_UPPER
,
279 [23] = IPRIO_DEFAULT_UPPER
+ 1,
280 [46] = IPRIO_DEFAULT_UPPER
+ 2,
281 [45] = IPRIO_DEFAULT_UPPER
+ 3,
282 [22] = IPRIO_DEFAULT_UPPER
+ 4,
283 [44] = IPRIO_DEFAULT_UPPER
+ 5,
285 [43] = IPRIO_DEFAULT_UPPER
+ 6,
286 [21] = IPRIO_DEFAULT_UPPER
+ 7,
287 [42] = IPRIO_DEFAULT_UPPER
+ 8,
288 [41] = IPRIO_DEFAULT_UPPER
+ 9,
289 [20] = IPRIO_DEFAULT_UPPER
+ 10,
290 [40] = IPRIO_DEFAULT_UPPER
+ 11,
292 [11] = IPRIO_DEFAULT_M
,
293 [3] = IPRIO_DEFAULT_M
+ 1,
294 [7] = IPRIO_DEFAULT_M
+ 2,
296 [9] = IPRIO_DEFAULT_S
,
297 [1] = IPRIO_DEFAULT_S
+ 1,
298 [5] = IPRIO_DEFAULT_S
+ 2,
300 [12] = IPRIO_DEFAULT_SGEXT
,
302 [10] = IPRIO_DEFAULT_VS
,
303 [2] = IPRIO_DEFAULT_VS
+ 1,
304 [6] = IPRIO_DEFAULT_VS
+ 2,
306 [39] = IPRIO_DEFAULT_LOWER
,
307 [19] = IPRIO_DEFAULT_LOWER
+ 1,
308 [38] = IPRIO_DEFAULT_LOWER
+ 2,
309 [37] = IPRIO_DEFAULT_LOWER
+ 3,
310 [18] = IPRIO_DEFAULT_LOWER
+ 4,
311 [36] = IPRIO_DEFAULT_LOWER
+ 5,
313 [35] = IPRIO_DEFAULT_LOWER
+ 6,
314 [17] = IPRIO_DEFAULT_LOWER
+ 7,
315 [34] = IPRIO_DEFAULT_LOWER
+ 8,
316 [33] = IPRIO_DEFAULT_LOWER
+ 9,
317 [16] = IPRIO_DEFAULT_LOWER
+ 10,
318 [32] = IPRIO_DEFAULT_LOWER
+ 11,
321 uint8_t riscv_cpu_default_priority(int irq
)
323 if (irq
< 0 || irq
> 63) {
324 return IPRIO_MMAXIPRIO
;
327 return default_iprio
[irq
] ? default_iprio
[irq
] : IPRIO_MMAXIPRIO
;
330 static int riscv_cpu_pending_to_irq(CPURISCVState
*env
,
331 int extirq
, unsigned int extirq_def_prio
,
332 uint64_t pending
, uint8_t *iprio
)
334 int irq
, best_irq
= RISCV_EXCP_NONE
;
335 unsigned int prio
, best_prio
= UINT_MAX
;
338 return RISCV_EXCP_NONE
;
341 irq
= ctz64(pending
);
342 if (!((extirq
== IRQ_M_EXT
) ? riscv_cpu_cfg(env
)->ext_smaia
:
343 riscv_cpu_cfg(env
)->ext_ssaia
)) {
347 pending
= pending
>> irq
;
352 prio
= extirq_def_prio
;
354 prio
= (riscv_cpu_default_priority(irq
) < extirq_def_prio
) ?
358 if ((pending
& 0x1) && (prio
<= best_prio
)) {
363 pending
= pending
>> 1;
369 uint64_t riscv_cpu_all_pending(CPURISCVState
*env
)
371 uint32_t gein
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
372 uint64_t vsgein
= (env
->hgeip
& (1ULL << gein
)) ? MIP_VSEIP
: 0;
373 uint64_t vstip
= (env
->vstime_irq
) ? MIP_VSTIP
: 0;
375 return (env
->mip
| vsgein
| vstip
) & env
->mie
;
378 int riscv_cpu_mirq_pending(CPURISCVState
*env
)
380 uint64_t irqs
= riscv_cpu_all_pending(env
) & ~env
->mideleg
&
381 ~(MIP_SGEIP
| MIP_VSSIP
| MIP_VSTIP
| MIP_VSEIP
);
383 return riscv_cpu_pending_to_irq(env
, IRQ_M_EXT
, IPRIO_DEFAULT_M
,
387 int riscv_cpu_sirq_pending(CPURISCVState
*env
)
389 uint64_t irqs
= riscv_cpu_all_pending(env
) & env
->mideleg
&
390 ~(MIP_VSSIP
| MIP_VSTIP
| MIP_VSEIP
);
392 return riscv_cpu_pending_to_irq(env
, IRQ_S_EXT
, IPRIO_DEFAULT_S
,
396 int riscv_cpu_vsirq_pending(CPURISCVState
*env
)
398 uint64_t irqs
= riscv_cpu_all_pending(env
) & env
->mideleg
&
399 (MIP_VSSIP
| MIP_VSTIP
| MIP_VSEIP
);
401 return riscv_cpu_pending_to_irq(env
, IRQ_S_EXT
, IPRIO_DEFAULT_S
,
402 irqs
>> 1, env
->hviprio
);
405 static int riscv_cpu_local_irq_pending(CPURISCVState
*env
)
408 uint64_t irqs
, pending
, mie
, hsie
, vsie
;
410 /* Determine interrupt enable state of all privilege modes */
411 if (env
->virt_enabled
) {
414 vsie
= (env
->priv
< PRV_S
) ||
415 (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_SIE
));
417 mie
= (env
->priv
< PRV_M
) ||
418 (env
->priv
== PRV_M
&& get_field(env
->mstatus
, MSTATUS_MIE
));
419 hsie
= (env
->priv
< PRV_S
) ||
420 (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_SIE
));
424 /* Determine all pending interrupts */
425 pending
= riscv_cpu_all_pending(env
);
427 /* Check M-mode interrupts */
428 irqs
= pending
& ~env
->mideleg
& -mie
;
430 return riscv_cpu_pending_to_irq(env
, IRQ_M_EXT
, IPRIO_DEFAULT_M
,
434 /* Check HS-mode interrupts */
435 irqs
= pending
& env
->mideleg
& ~env
->hideleg
& -hsie
;
437 return riscv_cpu_pending_to_irq(env
, IRQ_S_EXT
, IPRIO_DEFAULT_S
,
441 /* Check VS-mode interrupts */
442 irqs
= pending
& env
->mideleg
& env
->hideleg
& -vsie
;
444 virq
= riscv_cpu_pending_to_irq(env
, IRQ_S_EXT
, IPRIO_DEFAULT_S
,
445 irqs
>> 1, env
->hviprio
);
446 return (virq
<= 0) ? virq
: virq
+ 1;
449 /* Indicate no pending interrupt */
450 return RISCV_EXCP_NONE
;
453 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
455 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
456 RISCVCPU
*cpu
= RISCV_CPU(cs
);
457 CPURISCVState
*env
= &cpu
->env
;
458 int interruptno
= riscv_cpu_local_irq_pending(env
);
459 if (interruptno
>= 0) {
460 cs
->exception_index
= RISCV_EXCP_INT_FLAG
| interruptno
;
461 riscv_cpu_do_interrupt(cs
);
468 /* Return true is floating point support is currently enabled */
469 bool riscv_cpu_fp_enabled(CPURISCVState
*env
)
471 if (env
->mstatus
& MSTATUS_FS
) {
472 if (env
->virt_enabled
&& !(env
->mstatus_hs
& MSTATUS_FS
)) {
481 /* Return true is vector support is currently enabled */
482 bool riscv_cpu_vector_enabled(CPURISCVState
*env
)
484 if (env
->mstatus
& MSTATUS_VS
) {
485 if (env
->virt_enabled
&& !(env
->mstatus_hs
& MSTATUS_VS
)) {
494 void riscv_cpu_swap_hypervisor_regs(CPURISCVState
*env
)
496 uint64_t mstatus_mask
= MSTATUS_MXR
| MSTATUS_SUM
|
497 MSTATUS_SPP
| MSTATUS_SPIE
| MSTATUS_SIE
|
498 MSTATUS64_UXL
| MSTATUS_VS
;
500 if (riscv_has_ext(env
, RVF
)) {
501 mstatus_mask
|= MSTATUS_FS
;
503 bool current_virt
= env
->virt_enabled
;
505 g_assert(riscv_has_ext(env
, RVH
));
508 /* Current V=1 and we are about to change to V=0 */
509 env
->vsstatus
= env
->mstatus
& mstatus_mask
;
510 env
->mstatus
&= ~mstatus_mask
;
511 env
->mstatus
|= env
->mstatus_hs
;
513 env
->vstvec
= env
->stvec
;
514 env
->stvec
= env
->stvec_hs
;
516 env
->vsscratch
= env
->sscratch
;
517 env
->sscratch
= env
->sscratch_hs
;
519 env
->vsepc
= env
->sepc
;
520 env
->sepc
= env
->sepc_hs
;
522 env
->vscause
= env
->scause
;
523 env
->scause
= env
->scause_hs
;
525 env
->vstval
= env
->stval
;
526 env
->stval
= env
->stval_hs
;
528 env
->vsatp
= env
->satp
;
529 env
->satp
= env
->satp_hs
;
531 /* Current V=0 and we are about to change to V=1 */
532 env
->mstatus_hs
= env
->mstatus
& mstatus_mask
;
533 env
->mstatus
&= ~mstatus_mask
;
534 env
->mstatus
|= env
->vsstatus
;
536 env
->stvec_hs
= env
->stvec
;
537 env
->stvec
= env
->vstvec
;
539 env
->sscratch_hs
= env
->sscratch
;
540 env
->sscratch
= env
->vsscratch
;
542 env
->sepc_hs
= env
->sepc
;
543 env
->sepc
= env
->vsepc
;
545 env
->scause_hs
= env
->scause
;
546 env
->scause
= env
->vscause
;
548 env
->stval_hs
= env
->stval
;
549 env
->stval
= env
->vstval
;
551 env
->satp_hs
= env
->satp
;
552 env
->satp
= env
->vsatp
;
556 target_ulong
riscv_cpu_get_geilen(CPURISCVState
*env
)
558 if (!riscv_has_ext(env
, RVH
)) {
565 void riscv_cpu_set_geilen(CPURISCVState
*env
, target_ulong geilen
)
567 if (!riscv_has_ext(env
, RVH
)) {
571 if (geilen
> (TARGET_LONG_BITS
- 1)) {
575 env
->geilen
= geilen
;
578 /* This function can only be called to set virt when RVH is enabled */
579 void riscv_cpu_set_virt_enabled(CPURISCVState
*env
, bool enable
)
581 /* Flush the TLB on all virt mode changes. */
582 if (env
->virt_enabled
!= enable
) {
583 tlb_flush(env_cpu(env
));
586 env
->virt_enabled
= enable
;
590 * The guest external interrupts from an interrupt controller are
591 * delivered only when the Guest/VM is running (i.e. V=1). This means
592 * any guest external interrupt which is triggered while the Guest/VM
593 * is not running (i.e. V=0) will be missed on QEMU resulting in guest
594 * with sluggish response to serial console input and other I/O events.
596 * To solve this, we check and inject interrupt after setting V=1.
598 riscv_cpu_update_mip(env
, 0, 0);
602 int riscv_cpu_claim_interrupts(RISCVCPU
*cpu
, uint64_t interrupts
)
604 CPURISCVState
*env
= &cpu
->env
;
605 if (env
->miclaim
& interrupts
) {
608 env
->miclaim
|= interrupts
;
613 uint64_t riscv_cpu_update_mip(CPURISCVState
*env
, uint64_t mask
,
616 CPUState
*cs
= env_cpu(env
);
617 uint64_t gein
, vsgein
= 0, vstip
= 0, old
= env
->mip
;
619 if (env
->virt_enabled
) {
620 gein
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
621 vsgein
= (env
->hgeip
& (1ULL << gein
)) ? MIP_VSEIP
: 0;
624 vstip
= env
->vstime_irq
? MIP_VSTIP
: 0;
626 QEMU_IOTHREAD_LOCK_GUARD();
628 env
->mip
= (env
->mip
& ~mask
) | (value
& mask
);
630 if (env
->mip
| vsgein
| vstip
) {
631 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
633 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
639 void riscv_cpu_set_rdtime_fn(CPURISCVState
*env
, uint64_t (*fn
)(void *),
643 env
->rdtime_fn_arg
= arg
;
646 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState
*env
, uint32_t priv
,
647 int (*rmw_fn
)(void *arg
,
650 target_ulong new_val
,
651 target_ulong write_mask
),
655 env
->aia_ireg_rmw_fn
[priv
] = rmw_fn
;
656 env
->aia_ireg_rmw_fn_arg
[priv
] = rmw_fn_arg
;
660 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
)
662 g_assert(newpriv
<= PRV_M
&& newpriv
!= PRV_RESERVED
);
664 if (icount_enabled() && newpriv
!= env
->priv
) {
665 riscv_itrigger_update_priv(env
);
667 /* tlb_flush is unnecessary as mode is contained in mmu_idx */
669 env
->xl
= cpu_recompute_xl(env
);
670 riscv_cpu_update_mask(env
);
673 * Clear the load reservation - otherwise a reservation placed in one
674 * context/process can be used by another, resulting in an SC succeeding
675 * incorrectly. Version 2.2 of the ISA specification explicitly requires
676 * this behaviour, while later revisions say that the kernel "should" use
677 * an SC instruction to force the yielding of a load reservation on a
678 * preemptive context switch. As a result, do both.
684 * get_physical_address_pmp - check PMP permission for this physical address
686 * Match the PMP region and check permission for this physical address and it's
687 * TLB page. Returns 0 if the permission checking was successful
689 * @env: CPURISCVState
690 * @prot: The returned protection attributes
691 * @tlb_size: TLB page size containing addr. It could be modified after PMP
692 * permission checking. NULL if not set TLB page for addr.
693 * @addr: The physical address to be checked permission
694 * @access_type: The type of MMU access
695 * @mode: Indicates current privilege level.
697 static int get_physical_address_pmp(CPURISCVState
*env
, int *prot
,
698 target_ulong
*tlb_size
, hwaddr addr
,
699 int size
, MMUAccessType access_type
,
705 if (!riscv_cpu_cfg(env
)->pmp
) {
706 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
707 return TRANSLATE_SUCCESS
;
710 pmp_index
= pmp_hart_has_privs(env
, addr
, size
, 1 << access_type
,
714 return TRANSLATE_PMP_FAIL
;
717 *prot
= pmp_priv_to_page_prot(pmp_priv
);
718 if ((tlb_size
!= NULL
) && pmp_index
!= MAX_RISCV_PMPS
) {
719 target_ulong tlb_sa
= addr
& ~(TARGET_PAGE_SIZE
- 1);
720 target_ulong tlb_ea
= tlb_sa
+ TARGET_PAGE_SIZE
- 1;
722 *tlb_size
= pmp_get_tlb_size(env
, pmp_index
, tlb_sa
, tlb_ea
);
725 return TRANSLATE_SUCCESS
;
729 * get_physical_address - get the physical address for this virtual address
731 * Do a page table walk to obtain the physical address corresponding to a
732 * virtual address. Returns 0 if the translation was successful
734 * Adapted from Spike's mmu_t::translate and mmu_t::walk
736 * @env: CPURISCVState
737 * @physical: This will be set to the calculated physical address
738 * @prot: The returned protection attributes
739 * @addr: The virtual address or guest physical address to be translated
740 * @fault_pte_addr: If not NULL, this will be set to fault pte address
741 * when a error occurs on pte address translation.
742 * This will already be shifted to match htval.
743 * @access_type: The type of MMU access
744 * @mmu_idx: Indicates current privilege level
745 * @first_stage: Are we in first stage translation?
746 * Second stage is used for hypervisor guest translation
747 * @two_stage: Are we going to perform two stage translation
748 * @is_debug: Is this access from a debugger or the monitor?
750 static int get_physical_address(CPURISCVState
*env
, hwaddr
*physical
,
751 int *ret_prot
, vaddr addr
,
752 target_ulong
*fault_pte_addr
,
753 int access_type
, int mmu_idx
,
754 bool first_stage
, bool two_stage
,
758 * NOTE: the env->pc value visible here will not be
759 * correct, but the value visible to the exception handler
760 * (riscv_cpu_do_interrupt) is correct
763 MemTxAttrs attrs
= MEMTXATTRS_UNSPECIFIED
;
764 int mode
= mmuidx_priv(mmu_idx
);
765 bool use_background
= false;
768 target_ulong napot_mask
;
771 * Check if we should use the background registers for the two
772 * stage translation. We don't need to check if we actually need
773 * two stage translation as that happened before this function
774 * was called. Background registers will be used if the guest has
775 * forced a two stage translation to be on (in HS or M mode).
777 if (!env
->virt_enabled
&& two_stage
) {
778 use_background
= true;
781 if (mode
== PRV_M
|| !riscv_cpu_cfg(env
)->mmu
) {
783 *ret_prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
784 return TRANSLATE_SUCCESS
;
790 int levels
, ptidxbits
, ptesize
, vm
, widened
;
792 if (first_stage
== true) {
793 if (use_background
) {
794 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
795 base
= (hwaddr
)get_field(env
->vsatp
, SATP32_PPN
) << PGSHIFT
;
796 vm
= get_field(env
->vsatp
, SATP32_MODE
);
798 base
= (hwaddr
)get_field(env
->vsatp
, SATP64_PPN
) << PGSHIFT
;
799 vm
= get_field(env
->vsatp
, SATP64_MODE
);
802 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
803 base
= (hwaddr
)get_field(env
->satp
, SATP32_PPN
) << PGSHIFT
;
804 vm
= get_field(env
->satp
, SATP32_MODE
);
806 base
= (hwaddr
)get_field(env
->satp
, SATP64_PPN
) << PGSHIFT
;
807 vm
= get_field(env
->satp
, SATP64_MODE
);
812 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
813 base
= (hwaddr
)get_field(env
->hgatp
, SATP32_PPN
) << PGSHIFT
;
814 vm
= get_field(env
->hgatp
, SATP32_MODE
);
816 base
= (hwaddr
)get_field(env
->hgatp
, SATP64_PPN
) << PGSHIFT
;
817 vm
= get_field(env
->hgatp
, SATP64_MODE
);
824 levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
826 levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
828 levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
830 levels
= 5; ptidxbits
= 9; ptesize
= 8; break;
833 *ret_prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
834 return TRANSLATE_SUCCESS
;
836 g_assert_not_reached();
839 CPUState
*cs
= env_cpu(env
);
840 int va_bits
= PGSHIFT
+ levels
* ptidxbits
+ widened
;
842 if (first_stage
== true) {
843 target_ulong mask
, masked_msbs
;
845 if (TARGET_LONG_BITS
> (va_bits
- 1)) {
846 mask
= (1L << (TARGET_LONG_BITS
- (va_bits
- 1))) - 1;
850 masked_msbs
= (addr
>> (va_bits
- 1)) & mask
;
852 if (masked_msbs
!= 0 && masked_msbs
!= mask
) {
853 return TRANSLATE_FAIL
;
856 if (vm
!= VM_1_10_SV32
&& addr
>> va_bits
!= 0) {
857 return TRANSLATE_FAIL
;
861 bool pbmte
= env
->menvcfg
& MENVCFG_PBMTE
;
862 bool hade
= env
->menvcfg
& MENVCFG_HADE
;
864 if (first_stage
&& two_stage
&& env
->virt_enabled
) {
865 pbmte
= pbmte
&& (env
->henvcfg
& HENVCFG_PBMTE
);
866 hade
= hade
&& (env
->henvcfg
& HENVCFG_HADE
);
869 int ptshift
= (levels
- 1) * ptidxbits
;
874 #if !TCG_OVERSIZED_GUEST
877 for (i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
880 idx
= (addr
>> (PGSHIFT
+ ptshift
)) &
881 ((1 << (ptidxbits
+ widened
)) - 1);
883 idx
= (addr
>> (PGSHIFT
+ ptshift
)) &
884 ((1 << ptidxbits
) - 1);
887 /* check that physical address of PTE is legal */
889 if (two_stage
&& first_stage
) {
893 /* Do the second stage translation on the base PTE address. */
894 int vbase_ret
= get_physical_address(env
, &vbase
, &vbase_prot
,
895 base
, NULL
, MMU_DATA_LOAD
,
896 MMUIdx_U
, false, true,
899 if (vbase_ret
!= TRANSLATE_SUCCESS
) {
900 if (fault_pte_addr
) {
901 *fault_pte_addr
= (base
+ idx
* ptesize
) >> 2;
903 return TRANSLATE_G_STAGE_FAIL
;
906 pte_addr
= vbase
+ idx
* ptesize
;
908 pte_addr
= base
+ idx
* ptesize
;
912 int pmp_ret
= get_physical_address_pmp(env
, &pmp_prot
, NULL
, pte_addr
,
913 sizeof(target_ulong
),
914 MMU_DATA_LOAD
, PRV_S
);
915 if (pmp_ret
!= TRANSLATE_SUCCESS
) {
916 return TRANSLATE_PMP_FAIL
;
919 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
920 pte
= address_space_ldl(cs
->as
, pte_addr
, attrs
, &res
);
922 pte
= address_space_ldq(cs
->as
, pte_addr
, attrs
, &res
);
925 if (res
!= MEMTX_OK
) {
926 return TRANSLATE_FAIL
;
929 if (riscv_cpu_sxl(env
) == MXL_RV32
) {
930 ppn
= pte
>> PTE_PPN_SHIFT
;
932 if (pte
& PTE_RESERVED
) {
933 return TRANSLATE_FAIL
;
936 if (!pbmte
&& (pte
& PTE_PBMT
)) {
937 return TRANSLATE_FAIL
;
940 if (!riscv_cpu_cfg(env
)->ext_svnapot
&& (pte
& PTE_N
)) {
941 return TRANSLATE_FAIL
;
944 ppn
= (pte
& (target_ulong
)PTE_PPN_MASK
) >> PTE_PPN_SHIFT
;
947 if (!(pte
& PTE_V
)) {
949 return TRANSLATE_FAIL
;
951 if (pte
& (PTE_R
| PTE_W
| PTE_X
)) {
955 /* Inner PTE, continue walking */
956 if (pte
& (PTE_D
| PTE_A
| PTE_U
| PTE_ATTR
)) {
957 return TRANSLATE_FAIL
;
959 base
= ppn
<< PGSHIFT
;
962 /* No leaf pte at any translation level. */
963 return TRANSLATE_FAIL
;
966 if (ppn
& ((1ULL << ptshift
) - 1)) {
968 return TRANSLATE_FAIL
;
970 if (!pbmte
&& (pte
& PTE_PBMT
)) {
971 /* Reserved without Svpbmt. */
972 return TRANSLATE_FAIL
;
975 /* Check for reserved combinations of RWX flags. */
976 switch (pte
& (PTE_R
| PTE_W
| PTE_X
)) {
979 return TRANSLATE_FAIL
;
992 if (first_stage
== true) {
993 mxr
= get_field(env
->mstatus
, MSTATUS_MXR
);
995 mxr
= get_field(env
->vsstatus
, MSTATUS_MXR
);
1004 if (mode
!= PRV_U
) {
1005 if (!mmuidx_sum(mmu_idx
)) {
1006 return TRANSLATE_FAIL
;
1008 /* SUM allows only read+write, not execute. */
1009 prot
&= PAGE_READ
| PAGE_WRITE
;
1011 } else if (mode
!= PRV_S
) {
1012 /* Supervisor PTE flags when not S mode */
1013 return TRANSLATE_FAIL
;
1016 if (!((prot
>> access_type
) & 1)) {
1017 /* Access check failed */
1018 return TRANSLATE_FAIL
;
1021 /* If necessary, set accessed and dirty bits. */
1022 target_ulong updated_pte
= pte
| PTE_A
|
1023 (access_type
== MMU_DATA_STORE
? PTE_D
: 0);
1025 /* Page table updates need to be atomic with MTTCG enabled */
1026 if (updated_pte
!= pte
&& !is_debug
) {
1028 return TRANSLATE_FAIL
;
1032 * - if accessed or dirty bits need updating, and the PTE is
1033 * in RAM, then we do so atomically with a compare and swap.
1034 * - if the PTE is in IO space or ROM, then it can't be updated
1035 * and we return TRANSLATE_FAIL.
1036 * - if the PTE changed by the time we went to update it, then
1037 * it is no longer valid and we must re-walk the page table.
1040 hwaddr l
= sizeof(target_ulong
), addr1
;
1041 mr
= address_space_translate(cs
->as
, pte_addr
, &addr1
, &l
,
1042 false, MEMTXATTRS_UNSPECIFIED
);
1043 if (memory_region_is_ram(mr
)) {
1044 target_ulong
*pte_pa
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
1045 #if TCG_OVERSIZED_GUEST
1047 * MTTCG is not enabled on oversized TCG guests so
1048 * page table updates do not need to be atomic
1050 *pte_pa
= pte
= updated_pte
;
1052 target_ulong old_pte
= qatomic_cmpxchg(pte_pa
, pte
, updated_pte
);
1053 if (old_pte
!= pte
) {
1060 * Misconfigured PTE in ROM (AD bits are not preset) or
1061 * PTE is in IO space and can't be updated atomically.
1063 return TRANSLATE_FAIL
;
1067 /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */
1068 target_ulong vpn
= addr
>> PGSHIFT
;
1070 if (riscv_cpu_cfg(env
)->ext_svnapot
&& (pte
& PTE_N
)) {
1071 napot_bits
= ctzl(ppn
) + 1;
1072 if ((i
!= (levels
- 1)) || (napot_bits
!= 4)) {
1073 return TRANSLATE_FAIL
;
1077 napot_mask
= (1 << napot_bits
) - 1;
1078 *physical
= (((ppn
& ~napot_mask
) | (vpn
& napot_mask
) |
1079 (vpn
& (((target_ulong
)1 << ptshift
) - 1))
1080 ) << PGSHIFT
) | (addr
& ~TARGET_PAGE_MASK
);
1083 * Remove write permission unless this is a store, or the page is
1084 * already dirty, so that we TLB miss on later writes to update
1087 if (access_type
!= MMU_DATA_STORE
&& !(pte
& PTE_D
)) {
1088 prot
&= ~PAGE_WRITE
;
1092 return TRANSLATE_SUCCESS
;
1095 static void raise_mmu_exception(CPURISCVState
*env
, target_ulong address
,
1096 MMUAccessType access_type
, bool pmp_violation
,
1097 bool first_stage
, bool two_stage
,
1098 bool two_stage_indirect
)
1100 CPUState
*cs
= env_cpu(env
);
1101 int page_fault_exceptions
, vm
;
1104 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1105 stap_mode
= SATP32_MODE
;
1107 stap_mode
= SATP64_MODE
;
1111 vm
= get_field(env
->satp
, stap_mode
);
1113 vm
= get_field(env
->hgatp
, stap_mode
);
1116 page_fault_exceptions
= vm
!= VM_1_10_MBARE
&& !pmp_violation
;
1118 switch (access_type
) {
1119 case MMU_INST_FETCH
:
1120 if (env
->virt_enabled
&& !first_stage
) {
1121 cs
->exception_index
= RISCV_EXCP_INST_GUEST_PAGE_FAULT
;
1123 cs
->exception_index
= page_fault_exceptions
?
1124 RISCV_EXCP_INST_PAGE_FAULT
: RISCV_EXCP_INST_ACCESS_FAULT
;
1128 if (two_stage
&& !first_stage
) {
1129 cs
->exception_index
= RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
;
1131 cs
->exception_index
= page_fault_exceptions
?
1132 RISCV_EXCP_LOAD_PAGE_FAULT
: RISCV_EXCP_LOAD_ACCESS_FAULT
;
1135 case MMU_DATA_STORE
:
1136 if (two_stage
&& !first_stage
) {
1137 cs
->exception_index
= RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
;
1139 cs
->exception_index
= page_fault_exceptions
?
1140 RISCV_EXCP_STORE_PAGE_FAULT
:
1141 RISCV_EXCP_STORE_AMO_ACCESS_FAULT
;
1145 g_assert_not_reached();
1147 env
->badaddr
= address
;
1148 env
->two_stage_lookup
= two_stage
;
1149 env
->two_stage_indirect_lookup
= two_stage_indirect
;
1152 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
1154 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1155 CPURISCVState
*env
= &cpu
->env
;
1158 int mmu_idx
= cpu_mmu_index(&cpu
->env
, false);
1160 if (get_physical_address(env
, &phys_addr
, &prot
, addr
, NULL
, 0, mmu_idx
,
1161 true, env
->virt_enabled
, true)) {
1165 if (env
->virt_enabled
) {
1166 if (get_physical_address(env
, &phys_addr
, &prot
, phys_addr
, NULL
,
1167 0, mmu_idx
, false, true, true)) {
1172 return phys_addr
& TARGET_PAGE_MASK
;
1175 void riscv_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
1176 vaddr addr
, unsigned size
,
1177 MMUAccessType access_type
,
1178 int mmu_idx
, MemTxAttrs attrs
,
1179 MemTxResult response
, uintptr_t retaddr
)
1181 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1182 CPURISCVState
*env
= &cpu
->env
;
1184 if (access_type
== MMU_DATA_STORE
) {
1185 cs
->exception_index
= RISCV_EXCP_STORE_AMO_ACCESS_FAULT
;
1186 } else if (access_type
== MMU_DATA_LOAD
) {
1187 cs
->exception_index
= RISCV_EXCP_LOAD_ACCESS_FAULT
;
1189 cs
->exception_index
= RISCV_EXCP_INST_ACCESS_FAULT
;
1192 env
->badaddr
= addr
;
1193 env
->two_stage_lookup
= mmuidx_2stage(mmu_idx
);
1194 env
->two_stage_indirect_lookup
= false;
1195 cpu_loop_exit_restore(cs
, retaddr
);
1198 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
1199 MMUAccessType access_type
, int mmu_idx
,
1202 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1203 CPURISCVState
*env
= &cpu
->env
;
1204 switch (access_type
) {
1205 case MMU_INST_FETCH
:
1206 cs
->exception_index
= RISCV_EXCP_INST_ADDR_MIS
;
1209 cs
->exception_index
= RISCV_EXCP_LOAD_ADDR_MIS
;
1211 case MMU_DATA_STORE
:
1212 cs
->exception_index
= RISCV_EXCP_STORE_AMO_ADDR_MIS
;
1215 g_assert_not_reached();
1217 env
->badaddr
= addr
;
1218 env
->two_stage_lookup
= mmuidx_2stage(mmu_idx
);
1219 env
->two_stage_indirect_lookup
= false;
1220 cpu_loop_exit_restore(cs
, retaddr
);
1224 static void pmu_tlb_fill_incr_ctr(RISCVCPU
*cpu
, MMUAccessType access_type
)
1226 enum riscv_pmu_event_idx pmu_event_type
;
1228 switch (access_type
) {
1229 case MMU_INST_FETCH
:
1230 pmu_event_type
= RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS
;
1233 pmu_event_type
= RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS
;
1235 case MMU_DATA_STORE
:
1236 pmu_event_type
= RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS
;
1242 riscv_pmu_incr_ctr(cpu
, pmu_event_type
);
1245 bool riscv_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
1246 MMUAccessType access_type
, int mmu_idx
,
1247 bool probe
, uintptr_t retaddr
)
1249 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1250 CPURISCVState
*env
= &cpu
->env
;
1253 int prot
, prot2
, prot_pmp
;
1254 bool pmp_violation
= false;
1255 bool first_stage_error
= true;
1256 bool two_stage_lookup
= mmuidx_2stage(mmu_idx
);
1257 bool two_stage_indirect_error
= false;
1258 int ret
= TRANSLATE_FAIL
;
1260 /* default TLB page size */
1261 target_ulong tlb_size
= TARGET_PAGE_SIZE
;
1263 env
->guest_phys_fault_addr
= 0;
1265 qemu_log_mask(CPU_LOG_MMU
, "%s ad %" VADDR_PRIx
" rw %d mmu_idx %d\n",
1266 __func__
, address
, access_type
, mmu_idx
);
1268 pmu_tlb_fill_incr_ctr(cpu
, access_type
);
1269 if (two_stage_lookup
) {
1270 /* Two stage lookup */
1271 ret
= get_physical_address(env
, &pa
, &prot
, address
,
1272 &env
->guest_phys_fault_addr
, access_type
,
1273 mmu_idx
, true, true, false);
1276 * A G-stage exception may be triggered during two state lookup.
1277 * And the env->guest_phys_fault_addr has already been set in
1278 * get_physical_address().
1280 if (ret
== TRANSLATE_G_STAGE_FAIL
) {
1281 first_stage_error
= false;
1282 two_stage_indirect_error
= true;
1283 access_type
= MMU_DATA_LOAD
;
1286 qemu_log_mask(CPU_LOG_MMU
,
1287 "%s 1st-stage address=%" VADDR_PRIx
" ret %d physical "
1288 HWADDR_FMT_plx
" prot %d\n",
1289 __func__
, address
, ret
, pa
, prot
);
1291 if (ret
== TRANSLATE_SUCCESS
) {
1292 /* Second stage lookup */
1295 ret
= get_physical_address(env
, &pa
, &prot2
, im_address
, NULL
,
1296 access_type
, MMUIdx_U
, false, true,
1299 qemu_log_mask(CPU_LOG_MMU
,
1300 "%s 2nd-stage address=%" VADDR_PRIx
1302 HWADDR_FMT_plx
" prot %d\n",
1303 __func__
, im_address
, ret
, pa
, prot2
);
1307 if (ret
== TRANSLATE_SUCCESS
) {
1308 ret
= get_physical_address_pmp(env
, &prot_pmp
, &tlb_size
, pa
,
1309 size
, access_type
, mode
);
1311 qemu_log_mask(CPU_LOG_MMU
,
1312 "%s PMP address=" HWADDR_FMT_plx
" ret %d prot"
1313 " %d tlb_size " TARGET_FMT_lu
"\n",
1314 __func__
, pa
, ret
, prot_pmp
, tlb_size
);
1319 if (ret
!= TRANSLATE_SUCCESS
) {
1321 * Guest physical address translation failed, this is a HS
1324 first_stage_error
= false;
1325 env
->guest_phys_fault_addr
= (im_address
|
1327 (TARGET_PAGE_SIZE
- 1))) >> 2;
1331 /* Single stage lookup */
1332 ret
= get_physical_address(env
, &pa
, &prot
, address
, NULL
,
1333 access_type
, mmu_idx
, true, false, false);
1335 qemu_log_mask(CPU_LOG_MMU
,
1336 "%s address=%" VADDR_PRIx
" ret %d physical "
1337 HWADDR_FMT_plx
" prot %d\n",
1338 __func__
, address
, ret
, pa
, prot
);
1340 if (ret
== TRANSLATE_SUCCESS
) {
1341 ret
= get_physical_address_pmp(env
, &prot_pmp
, &tlb_size
, pa
,
1342 size
, access_type
, mode
);
1344 qemu_log_mask(CPU_LOG_MMU
,
1345 "%s PMP address=" HWADDR_FMT_plx
" ret %d prot"
1346 " %d tlb_size " TARGET_FMT_lu
"\n",
1347 __func__
, pa
, ret
, prot_pmp
, tlb_size
);
1353 if (ret
== TRANSLATE_PMP_FAIL
) {
1354 pmp_violation
= true;
1357 if (ret
== TRANSLATE_SUCCESS
) {
1358 tlb_set_page(cs
, address
& ~(tlb_size
- 1), pa
& ~(tlb_size
- 1),
1359 prot
, mmu_idx
, tlb_size
);
1364 raise_mmu_exception(env
, address
, access_type
, pmp_violation
,
1365 first_stage_error
, two_stage_lookup
,
1366 two_stage_indirect_error
);
1367 cpu_loop_exit_restore(cs
, retaddr
);
1373 static target_ulong
riscv_transformed_insn(CPURISCVState
*env
,
1377 target_ulong xinsn
= 0;
1378 target_ulong access_rs1
= 0, access_imm
= 0, access_size
= 0;
1381 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to
1382 * be uncompressed. The Quadrant 1 of RVC instruction space need
1383 * not be transformed because these instructions won't generate
1384 * any load/store trap.
1387 if ((insn
& 0x3) != 0x3) {
1388 /* Transform 16bit instruction into 32bit instruction */
1389 switch (GET_C_OP(insn
)) {
1390 case OPC_RISC_C_OP_QUAD0
: /* Quadrant 0 */
1391 switch (GET_C_FUNC(insn
)) {
1392 case OPC_RISC_C_FUNC_FLD_LQ
:
1393 if (riscv_cpu_xlen(env
) != 128) { /* C.FLD (RV32/64) */
1394 xinsn
= OPC_RISC_FLD
;
1395 xinsn
= SET_RD(xinsn
, GET_C_RS2S(insn
));
1396 access_rs1
= GET_C_RS1S(insn
);
1397 access_imm
= GET_C_LD_IMM(insn
);
1401 case OPC_RISC_C_FUNC_LW
: /* C.LW */
1402 xinsn
= OPC_RISC_LW
;
1403 xinsn
= SET_RD(xinsn
, GET_C_RS2S(insn
));
1404 access_rs1
= GET_C_RS1S(insn
);
1405 access_imm
= GET_C_LW_IMM(insn
);
1408 case OPC_RISC_C_FUNC_FLW_LD
:
1409 if (riscv_cpu_xlen(env
) == 32) { /* C.FLW (RV32) */
1410 xinsn
= OPC_RISC_FLW
;
1411 xinsn
= SET_RD(xinsn
, GET_C_RS2S(insn
));
1412 access_rs1
= GET_C_RS1S(insn
);
1413 access_imm
= GET_C_LW_IMM(insn
);
1415 } else { /* C.LD (RV64/RV128) */
1416 xinsn
= OPC_RISC_LD
;
1417 xinsn
= SET_RD(xinsn
, GET_C_RS2S(insn
));
1418 access_rs1
= GET_C_RS1S(insn
);
1419 access_imm
= GET_C_LD_IMM(insn
);
1423 case OPC_RISC_C_FUNC_FSD_SQ
:
1424 if (riscv_cpu_xlen(env
) != 128) { /* C.FSD (RV32/64) */
1425 xinsn
= OPC_RISC_FSD
;
1426 xinsn
= SET_RS2(xinsn
, GET_C_RS2S(insn
));
1427 access_rs1
= GET_C_RS1S(insn
);
1428 access_imm
= GET_C_SD_IMM(insn
);
1432 case OPC_RISC_C_FUNC_SW
: /* C.SW */
1433 xinsn
= OPC_RISC_SW
;
1434 xinsn
= SET_RS2(xinsn
, GET_C_RS2S(insn
));
1435 access_rs1
= GET_C_RS1S(insn
);
1436 access_imm
= GET_C_SW_IMM(insn
);
1439 case OPC_RISC_C_FUNC_FSW_SD
:
1440 if (riscv_cpu_xlen(env
) == 32) { /* C.FSW (RV32) */
1441 xinsn
= OPC_RISC_FSW
;
1442 xinsn
= SET_RS2(xinsn
, GET_C_RS2S(insn
));
1443 access_rs1
= GET_C_RS1S(insn
);
1444 access_imm
= GET_C_SW_IMM(insn
);
1446 } else { /* C.SD (RV64/RV128) */
1447 xinsn
= OPC_RISC_SD
;
1448 xinsn
= SET_RS2(xinsn
, GET_C_RS2S(insn
));
1449 access_rs1
= GET_C_RS1S(insn
);
1450 access_imm
= GET_C_SD_IMM(insn
);
1458 case OPC_RISC_C_OP_QUAD2
: /* Quadrant 2 */
1459 switch (GET_C_FUNC(insn
)) {
1460 case OPC_RISC_C_FUNC_FLDSP_LQSP
:
1461 if (riscv_cpu_xlen(env
) != 128) { /* C.FLDSP (RV32/64) */
1462 xinsn
= OPC_RISC_FLD
;
1463 xinsn
= SET_RD(xinsn
, GET_C_RD(insn
));
1465 access_imm
= GET_C_LDSP_IMM(insn
);
1469 case OPC_RISC_C_FUNC_LWSP
: /* C.LWSP */
1470 xinsn
= OPC_RISC_LW
;
1471 xinsn
= SET_RD(xinsn
, GET_C_RD(insn
));
1473 access_imm
= GET_C_LWSP_IMM(insn
);
1476 case OPC_RISC_C_FUNC_FLWSP_LDSP
:
1477 if (riscv_cpu_xlen(env
) == 32) { /* C.FLWSP (RV32) */
1478 xinsn
= OPC_RISC_FLW
;
1479 xinsn
= SET_RD(xinsn
, GET_C_RD(insn
));
1481 access_imm
= GET_C_LWSP_IMM(insn
);
1483 } else { /* C.LDSP (RV64/RV128) */
1484 xinsn
= OPC_RISC_LD
;
1485 xinsn
= SET_RD(xinsn
, GET_C_RD(insn
));
1487 access_imm
= GET_C_LDSP_IMM(insn
);
1491 case OPC_RISC_C_FUNC_FSDSP_SQSP
:
1492 if (riscv_cpu_xlen(env
) != 128) { /* C.FSDSP (RV32/64) */
1493 xinsn
= OPC_RISC_FSD
;
1494 xinsn
= SET_RS2(xinsn
, GET_C_RS2(insn
));
1496 access_imm
= GET_C_SDSP_IMM(insn
);
1500 case OPC_RISC_C_FUNC_SWSP
: /* C.SWSP */
1501 xinsn
= OPC_RISC_SW
;
1502 xinsn
= SET_RS2(xinsn
, GET_C_RS2(insn
));
1504 access_imm
= GET_C_SWSP_IMM(insn
);
1508 if (riscv_cpu_xlen(env
) == 32) { /* C.FSWSP (RV32) */
1509 xinsn
= OPC_RISC_FSW
;
1510 xinsn
= SET_RS2(xinsn
, GET_C_RS2(insn
));
1512 access_imm
= GET_C_SWSP_IMM(insn
);
1514 } else { /* C.SDSP (RV64/RV128) */
1515 xinsn
= OPC_RISC_SD
;
1516 xinsn
= SET_RS2(xinsn
, GET_C_RS2(insn
));
1518 access_imm
= GET_C_SDSP_IMM(insn
);
1531 * Clear Bit1 of transformed instruction to indicate that
1532 * original insruction was a 16bit instruction
1534 xinsn
&= ~((target_ulong
)0x2);
1536 /* Transform 32bit (or wider) instructions */
1537 switch (MASK_OP_MAJOR(insn
)) {
1538 case OPC_RISC_ATOMIC
:
1540 access_rs1
= GET_RS1(insn
);
1541 access_size
= 1 << GET_FUNCT3(insn
);
1544 case OPC_RISC_FP_LOAD
:
1545 xinsn
= SET_I_IMM(insn
, 0);
1546 access_rs1
= GET_RS1(insn
);
1547 access_imm
= GET_IMM(insn
);
1548 access_size
= 1 << GET_FUNCT3(insn
);
1550 case OPC_RISC_STORE
:
1551 case OPC_RISC_FP_STORE
:
1552 xinsn
= SET_S_IMM(insn
, 0);
1553 access_rs1
= GET_RS1(insn
);
1554 access_imm
= GET_STORE_IMM(insn
);
1555 access_size
= 1 << GET_FUNCT3(insn
);
1557 case OPC_RISC_SYSTEM
:
1558 if (MASK_OP_SYSTEM(insn
) == OPC_RISC_HLVHSV
) {
1560 access_rs1
= GET_RS1(insn
);
1561 access_size
= 1 << ((GET_FUNCT7(insn
) >> 1) & 0x3);
1562 access_size
= 1 << access_size
;
1571 xinsn
= SET_RS1(xinsn
, (taddr
- (env
->gpr
[access_rs1
] + access_imm
)) &
1577 #endif /* !CONFIG_USER_ONLY */
1582 * Adapted from Spike's processor_t::take_trap.
1585 void riscv_cpu_do_interrupt(CPUState
*cs
)
1587 #if !defined(CONFIG_USER_ONLY)
1589 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1590 CPURISCVState
*env
= &cpu
->env
;
1591 bool write_gva
= false;
1595 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
1596 * so we mask off the MSB and separate into trap type and cause.
1598 bool async
= !!(cs
->exception_index
& RISCV_EXCP_INT_FLAG
);
1599 target_ulong cause
= cs
->exception_index
& RISCV_EXCP_INT_MASK
;
1600 uint64_t deleg
= async
? env
->mideleg
: env
->medeleg
;
1601 target_ulong tval
= 0;
1602 target_ulong tinst
= 0;
1603 target_ulong htval
= 0;
1604 target_ulong mtval2
= 0;
1606 if (cause
== RISCV_EXCP_SEMIHOST
) {
1607 do_common_semihosting(cs
);
1613 /* set tval to badaddr for traps with address information */
1615 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
:
1616 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
:
1617 case RISCV_EXCP_LOAD_ADDR_MIS
:
1618 case RISCV_EXCP_STORE_AMO_ADDR_MIS
:
1619 case RISCV_EXCP_LOAD_ACCESS_FAULT
:
1620 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT
:
1621 case RISCV_EXCP_LOAD_PAGE_FAULT
:
1622 case RISCV_EXCP_STORE_PAGE_FAULT
:
1623 write_gva
= env
->two_stage_lookup
;
1624 tval
= env
->badaddr
;
1625 if (env
->two_stage_indirect_lookup
) {
1627 * special pseudoinstruction for G-stage fault taken while
1628 * doing VS-stage page table walk.
1630 tinst
= (riscv_cpu_xlen(env
) == 32) ? 0x00002000 : 0x00003000;
1633 * The "Addr. Offset" field in transformed instruction is
1634 * non-zero only for misaligned access.
1636 tinst
= riscv_transformed_insn(env
, env
->bins
, tval
);
1639 case RISCV_EXCP_INST_GUEST_PAGE_FAULT
:
1640 case RISCV_EXCP_INST_ADDR_MIS
:
1641 case RISCV_EXCP_INST_ACCESS_FAULT
:
1642 case RISCV_EXCP_INST_PAGE_FAULT
:
1643 write_gva
= env
->two_stage_lookup
;
1644 tval
= env
->badaddr
;
1645 if (env
->two_stage_indirect_lookup
) {
1647 * special pseudoinstruction for G-stage fault taken while
1648 * doing VS-stage page table walk.
1650 tinst
= (riscv_cpu_xlen(env
) == 32) ? 0x00002000 : 0x00003000;
1653 case RISCV_EXCP_ILLEGAL_INST
:
1654 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT
:
1657 case RISCV_EXCP_BREAKPOINT
:
1658 if (cs
->watchpoint_hit
) {
1659 tval
= cs
->watchpoint_hit
->hitaddr
;
1660 cs
->watchpoint_hit
= NULL
;
1666 /* ecall is dispatched as one cause so translate based on mode */
1667 if (cause
== RISCV_EXCP_U_ECALL
) {
1668 assert(env
->priv
<= 3);
1670 if (env
->priv
== PRV_M
) {
1671 cause
= RISCV_EXCP_M_ECALL
;
1672 } else if (env
->priv
== PRV_S
&& env
->virt_enabled
) {
1673 cause
= RISCV_EXCP_VS_ECALL
;
1674 } else if (env
->priv
== PRV_S
&& !env
->virt_enabled
) {
1675 cause
= RISCV_EXCP_S_ECALL
;
1676 } else if (env
->priv
== PRV_U
) {
1677 cause
= RISCV_EXCP_U_ECALL
;
1682 trace_riscv_trap(env
->mhartid
, async
, cause
, env
->pc
, tval
,
1683 riscv_cpu_get_trap_name(cause
, async
));
1685 qemu_log_mask(CPU_LOG_INT
,
1686 "%s: hart:"TARGET_FMT_ld
", async:%d, cause:"TARGET_FMT_lx
", "
1687 "epc:0x"TARGET_FMT_lx
", tval:0x"TARGET_FMT_lx
", desc=%s\n",
1688 __func__
, env
->mhartid
, async
, cause
, env
->pc
, tval
,
1689 riscv_cpu_get_trap_name(cause
, async
));
1691 if (env
->priv
<= PRV_S
&&
1692 cause
< TARGET_LONG_BITS
&& ((deleg
>> cause
) & 1)) {
1693 /* handle the trap in S-mode */
1694 if (riscv_has_ext(env
, RVH
)) {
1695 uint64_t hdeleg
= async
? env
->hideleg
: env
->hedeleg
;
1697 if (env
->virt_enabled
&& ((hdeleg
>> cause
) & 1)) {
1698 /* Trap to VS mode */
1700 * See if we need to adjust cause. Yes if its VS mode interrupt
1701 * no if hypervisor has delegated one of hs mode's interrupt
1703 if (cause
== IRQ_VS_TIMER
|| cause
== IRQ_VS_SOFT
||
1704 cause
== IRQ_VS_EXT
) {
1708 } else if (env
->virt_enabled
) {
1709 /* Trap into HS mode, from virt */
1710 riscv_cpu_swap_hypervisor_regs(env
);
1711 env
->hstatus
= set_field(env
->hstatus
, HSTATUS_SPVP
,
1713 env
->hstatus
= set_field(env
->hstatus
, HSTATUS_SPV
, true);
1715 htval
= env
->guest_phys_fault_addr
;
1717 riscv_cpu_set_virt_enabled(env
, 0);
1719 /* Trap into HS mode */
1720 env
->hstatus
= set_field(env
->hstatus
, HSTATUS_SPV
, false);
1721 htval
= env
->guest_phys_fault_addr
;
1723 env
->hstatus
= set_field(env
->hstatus
, HSTATUS_GVA
, write_gva
);
1727 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
1728 s
= set_field(s
, MSTATUS_SPP
, env
->priv
);
1729 s
= set_field(s
, MSTATUS_SIE
, 0);
1731 env
->scause
= cause
| ((target_ulong
)async
<< (TARGET_LONG_BITS
- 1));
1732 env
->sepc
= env
->pc
;
1735 env
->htinst
= tinst
;
1736 env
->pc
= (env
->stvec
>> 2 << 2) +
1737 ((async
&& (env
->stvec
& 3) == 1) ? cause
* 4 : 0);
1738 riscv_cpu_set_mode(env
, PRV_S
);
1740 /* handle the trap in M-mode */
1741 if (riscv_has_ext(env
, RVH
)) {
1742 if (env
->virt_enabled
) {
1743 riscv_cpu_swap_hypervisor_regs(env
);
1745 env
->mstatus
= set_field(env
->mstatus
, MSTATUS_MPV
,
1747 if (env
->virt_enabled
&& tval
) {
1748 env
->mstatus
= set_field(env
->mstatus
, MSTATUS_GVA
, 1);
1751 mtval2
= env
->guest_phys_fault_addr
;
1753 /* Trapping to M mode, virt is disabled */
1754 riscv_cpu_set_virt_enabled(env
, 0);
1758 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
1759 s
= set_field(s
, MSTATUS_MPP
, env
->priv
);
1760 s
= set_field(s
, MSTATUS_MIE
, 0);
1762 env
->mcause
= cause
| ~(((target_ulong
)-1) >> async
);
1763 env
->mepc
= env
->pc
;
1765 env
->mtval2
= mtval2
;
1766 env
->mtinst
= tinst
;
1767 env
->pc
= (env
->mtvec
>> 2 << 2) +
1768 ((async
&& (env
->mtvec
& 3) == 1) ? cause
* 4 : 0);
1769 riscv_cpu_set_mode(env
, PRV_M
);
1773 * NOTE: it is not necessary to yield load reservations here. It is only
1774 * necessary for an SC from "another hart" to cause a load reservation
1775 * to be yielded. Refer to the memory consistency model section of the
1776 * RISC-V ISA Specification.
1779 env
->two_stage_lookup
= false;
1780 env
->two_stage_indirect_lookup
= false;
1782 cs
->exception_index
= RISCV_EXCP_NONE
; /* mark handled to qemu */