target/riscv/cpu_helper.c

   1 /*
   2  * RISC-V CPU helpers for qemu.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "qemu/main-loop.h"
  23 #include "cpu.h"
  24 #include "exec/exec-all.h"
  25 #include "tcg/tcg-op.h"
  26 #include "trace.h"
  27
  28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
  29 {
  30 #ifdef CONFIG_USER_ONLY
  31     return 0;
  32 #else
  33     return env->priv;
  34 #endif
  35 }
  36
  37 #ifndef CONFIG_USER_ONLY
  38 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
  39 {
  40     target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
  41     target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
  42     target_ulong pending = env->mip & env->mie;
  43     target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie);
  44     target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie);
  45     target_ulong irqs = (pending & ~env->mideleg & -mie) |
  46                         (pending &  env->mideleg & -sie);
  47
  48     if (irqs) {
  49         return ctz64(irqs); /* since non-zero */
  50     } else {
  51         return EXCP_NONE; /* indicates no pending interrupt */
  52     }
  53 }
  54 #endif
  55
  56 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  57 {
  58 #if !defined(CONFIG_USER_ONLY)
  59     if (interrupt_request & CPU_INTERRUPT_HARD) {
  60         RISCVCPU *cpu = RISCV_CPU(cs);
  61         CPURISCVState *env = &cpu->env;
  62         int interruptno = riscv_cpu_local_irq_pending(env);
  63         if (interruptno >= 0) {
  64             cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
  65             riscv_cpu_do_interrupt(cs);
  66             return true;
  67         }
  68     }
  69 #endif
  70     return false;
  71 }
  72
  73 #if !defined(CONFIG_USER_ONLY)
  74
  75 /* Return true is floating point support is currently enabled */
  76 bool riscv_cpu_fp_enabled(CPURISCVState *env)
  77 {
  78     if (env->mstatus & MSTATUS_FS) {
  79         return true;
  80     }
  81
  82     return false;
  83 }
  84
  85 bool riscv_cpu_virt_enabled(CPURISCVState *env)
  86 {
  87     if (!riscv_has_ext(env, RVH)) {
  88         return false;
  89     }
  90
  91     return get_field(env->virt, VIRT_ONOFF);
  92 }
  93
  94 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
  95 {
  96     if (!riscv_has_ext(env, RVH)) {
  97         return;
  98     }
  99
 100     env->virt = set_field(env->virt, VIRT_ONOFF, enable);
 101 }
 102
 103 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
 104 {
 105     if (!riscv_has_ext(env, RVH)) {
 106         return false;
 107     }
 108
 109     return get_field(env->virt, FORCE_HS_EXCEP);
 110 }
 111
 112 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
 113 {
 114     if (!riscv_has_ext(env, RVH)) {
 115         return;
 116     }
 117
 118     env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
 119 }
 120
 121 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
 122 {
 123     CPURISCVState *env = &cpu->env;
 124     if (env->miclaim & interrupts) {
 125         return -1;
 126     } else {
 127         env->miclaim |= interrupts;
 128         return 0;
 129     }
 130 }
 131
 132 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
 133 {
 134     CPURISCVState *env = &cpu->env;
 135     CPUState *cs = CPU(cpu);
 136     uint32_t old = env->mip;
 137     bool locked = false;
 138
 139     if (!qemu_mutex_iothread_locked()) {
 140         locked = true;
 141         qemu_mutex_lock_iothread();
 142     }
 143
 144     env->mip = (env->mip & ~mask) | (value & mask);
 145
 146     if (env->mip) {
 147         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 148     } else {
 149         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 150     }
 151
 152     if (locked) {
 153         qemu_mutex_unlock_iothread();
 154     }
 155
 156     return old;
 157 }
 158
 159 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
 160 {
 161     if (newpriv > PRV_M) {
 162         g_assert_not_reached();
 163     }
 164     if (newpriv == PRV_H) {
 165         newpriv = PRV_U;
 166     }
 167     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
 168     env->priv = newpriv;
 169
 170     /*
 171      * Clear the load reservation - otherwise a reservation placed in one
 172      * context/process can be used by another, resulting in an SC succeeding
 173      * incorrectly. Version 2.2 of the ISA specification explicitly requires
 174      * this behaviour, while later revisions say that the kernel "should" use
 175      * an SC instruction to force the yielding of a load reservation on a
 176      * preemptive context switch. As a result, do both.
 177      */
 178     env->load_res = -1;
 179 }
 180
 181 /* get_physical_address - get the physical address for this virtual address
 182  *
 183  * Do a page table walk to obtain the physical address corresponding to a
 184  * virtual address. Returns 0 if the translation was successful
 185  *
 186  * Adapted from Spike's mmu_t::translate and mmu_t::walk
 187  *
 188  */
 189 static int get_physical_address(CPURISCVState *env, hwaddr *physical,
 190                                 int *prot, target_ulong addr,
 191                                 int access_type, int mmu_idx)
 192 {
 193     /* NOTE: the env->pc value visible here will not be
 194      * correct, but the value visible to the exception handler
 195      * (riscv_cpu_do_interrupt) is correct */
 196     MemTxResult res;
 197     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
 198     int mode = mmu_idx;
 199
 200     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 201         if (get_field(env->mstatus, MSTATUS_MPRV)) {
 202             mode = get_field(env->mstatus, MSTATUS_MPP);
 203         }
 204     }
 205
 206     if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
 207         *physical = addr;
 208         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 209         return TRANSLATE_SUCCESS;
 210     }
 211
 212     *prot = 0;
 213
 214     hwaddr base;
 215     int levels, ptidxbits, ptesize, vm, sum;
 216     int mxr = get_field(env->mstatus, MSTATUS_MXR);
 217
 218     if (env->priv_ver >= PRIV_VERSION_1_10_0) {
 219         base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
 220         sum = get_field(env->mstatus, MSTATUS_SUM);
 221         vm = get_field(env->satp, SATP_MODE);
 222         switch (vm) {
 223         case VM_1_10_SV32:
 224           levels = 2; ptidxbits = 10; ptesize = 4; break;
 225         case VM_1_10_SV39:
 226           levels = 3; ptidxbits = 9; ptesize = 8; break;
 227         case VM_1_10_SV48:
 228           levels = 4; ptidxbits = 9; ptesize = 8; break;
 229         case VM_1_10_SV57:
 230           levels = 5; ptidxbits = 9; ptesize = 8; break;
 231         case VM_1_10_MBARE:
 232             *physical = addr;
 233             *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 234             return TRANSLATE_SUCCESS;
 235         default:
 236           g_assert_not_reached();
 237         }
 238     } else {
 239         base = (hwaddr)(env->sptbr) << PGSHIFT;
 240         sum = !get_field(env->mstatus, MSTATUS_PUM);
 241         vm = get_field(env->mstatus, MSTATUS_VM);
 242         switch (vm) {
 243         case VM_1_09_SV32:
 244           levels = 2; ptidxbits = 10; ptesize = 4; break;
 245         case VM_1_09_SV39:
 246           levels = 3; ptidxbits = 9; ptesize = 8; break;
 247         case VM_1_09_SV48:
 248           levels = 4; ptidxbits = 9; ptesize = 8; break;
 249         case VM_1_09_MBARE:
 250             *physical = addr;
 251             *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 252             return TRANSLATE_SUCCESS;
 253         default:
 254           g_assert_not_reached();
 255         }
 256     }
 257
 258     CPUState *cs = env_cpu(env);
 259     int va_bits = PGSHIFT + levels * ptidxbits;
 260     target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
 261     target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask;
 262     if (masked_msbs != 0 && masked_msbs != mask) {
 263         return TRANSLATE_FAIL;
 264     }
 265
 266     int ptshift = (levels - 1) * ptidxbits;
 267     int i;
 268
 269 #if !TCG_OVERSIZED_GUEST
 270 restart:
 271 #endif
 272     for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
 273         target_ulong idx = (addr >> (PGSHIFT + ptshift)) &
 274                            ((1 << ptidxbits) - 1);
 275
 276         /* check that physical address of PTE is legal */
 277         hwaddr pte_addr = base + idx * ptesize;
 278
 279         if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 280             !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
 281             1 << MMU_DATA_LOAD, PRV_S)) {
 282             return TRANSLATE_PMP_FAIL;
 283         }
 284
 285 #if defined(TARGET_RISCV32)
 286         target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
 287 #elif defined(TARGET_RISCV64)
 288         target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
 289 #endif
 290         if (res != MEMTX_OK) {
 291             return TRANSLATE_FAIL;
 292         }
 293
 294         hwaddr ppn = pte >> PTE_PPN_SHIFT;
 295
 296         if (!(pte & PTE_V)) {
 297             /* Invalid PTE */
 298             return TRANSLATE_FAIL;
 299         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
 300             /* Inner PTE, continue walking */
 301             base = ppn << PGSHIFT;
 302         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
 303             /* Reserved leaf PTE flags: PTE_W */
 304             return TRANSLATE_FAIL;
 305         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
 306             /* Reserved leaf PTE flags: PTE_W + PTE_X */
 307             return TRANSLATE_FAIL;
 308         } else if ((pte & PTE_U) && ((mode != PRV_U) &&
 309                    (!sum || access_type == MMU_INST_FETCH))) {
 310             /* User PTE flags when not U mode and mstatus.SUM is not set,
 311                or the access type is an instruction fetch */
 312             return TRANSLATE_FAIL;
 313         } else if (!(pte & PTE_U) && (mode != PRV_S)) {
 314             /* Supervisor PTE flags when not S mode */
 315             return TRANSLATE_FAIL;
 316         } else if (ppn & ((1ULL << ptshift) - 1)) {
 317             /* Misaligned PPN */
 318             return TRANSLATE_FAIL;
 319         } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
 320                    ((pte & PTE_X) && mxr))) {
 321             /* Read access check failed */
 322             return TRANSLATE_FAIL;
 323         } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
 324             /* Write access check failed */
 325             return TRANSLATE_FAIL;
 326         } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
 327             /* Fetch access check failed */
 328             return TRANSLATE_FAIL;
 329         } else {
 330             /* if necessary, set accessed and dirty bits. */
 331             target_ulong updated_pte = pte | PTE_A |
 332                 (access_type == MMU_DATA_STORE ? PTE_D : 0);
 333
 334             /* Page table updates need to be atomic with MTTCG enabled */
 335             if (updated_pte != pte) {
 336                 /*
 337                  * - if accessed or dirty bits need updating, and the PTE is
 338                  *   in RAM, then we do so atomically with a compare and swap.
 339                  * - if the PTE is in IO space or ROM, then it can't be updated
 340                  *   and we return TRANSLATE_FAIL.
 341                  * - if the PTE changed by the time we went to update it, then
 342                  *   it is no longer valid and we must re-walk the page table.
 343                  */
 344                 MemoryRegion *mr;
 345                 hwaddr l = sizeof(target_ulong), addr1;
 346                 mr = address_space_translate(cs->as, pte_addr,
 347                     &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
 348                 if (memory_region_is_ram(mr)) {
 349                     target_ulong *pte_pa =
 350                         qemu_map_ram_ptr(mr->ram_block, addr1);
 351 #if TCG_OVERSIZED_GUEST
 352                     /* MTTCG is not enabled on oversized TCG guests so
 353                      * page table updates do not need to be atomic */
 354                     *pte_pa = pte = updated_pte;
 355 #else
 356                     target_ulong old_pte =
 357                         atomic_cmpxchg(pte_pa, pte, updated_pte);
 358                     if (old_pte != pte) {
 359                         goto restart;
 360                     } else {
 361                         pte = updated_pte;
 362                     }
 363 #endif
 364                 } else {
 365                     /* misconfigured PTE in ROM (AD bits are not preset) or
 366                      * PTE is in IO space and can't be updated atomically */
 367                     return TRANSLATE_FAIL;
 368                 }
 369             }
 370
 371             /* for superpage mappings, make a fake leaf PTE for the TLB's
 372                benefit. */
 373             target_ulong vpn = addr >> PGSHIFT;
 374             *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
 375
 376             /* set permissions on the TLB entry */
 377             if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
 378                 *prot |= PAGE_READ;
 379             }
 380             if ((pte & PTE_X)) {
 381                 *prot |= PAGE_EXEC;
 382             }
 383             /* add write permission on stores or if the page is already dirty,
 384                so that we TLB miss on later writes to update the dirty bit */
 385             if ((pte & PTE_W) &&
 386                     (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
 387                 *prot |= PAGE_WRITE;
 388             }
 389             return TRANSLATE_SUCCESS;
 390         }
 391     }
 392     return TRANSLATE_FAIL;
 393 }
 394
 395 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 396                                 MMUAccessType access_type, bool pmp_violation)
 397 {
 398     CPUState *cs = env_cpu(env);
 399     int page_fault_exceptions =
 400         (env->priv_ver >= PRIV_VERSION_1_10_0) &&
 401         get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
 402         !pmp_violation;
 403     switch (access_type) {
 404     case MMU_INST_FETCH:
 405         cs->exception_index = page_fault_exceptions ?
 406             RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
 407         break;
 408     case MMU_DATA_LOAD:
 409         cs->exception_index = page_fault_exceptions ?
 410             RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
 411         break;
 412     case MMU_DATA_STORE:
 413         cs->exception_index = page_fault_exceptions ?
 414             RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 415         break;
 416     default:
 417         g_assert_not_reached();
 418     }
 419     env->badaddr = address;
 420 }
 421
 422 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 423 {
 424     RISCVCPU *cpu = RISCV_CPU(cs);
 425     hwaddr phys_addr;
 426     int prot;
 427     int mmu_idx = cpu_mmu_index(&cpu->env, false);
 428
 429     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
 430         return -1;
 431     }
 432     return phys_addr;
 433 }
 434
 435 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 436                                      vaddr addr, unsigned size,
 437                                      MMUAccessType access_type,
 438                                      int mmu_idx, MemTxAttrs attrs,
 439                                      MemTxResult response, uintptr_t retaddr)
 440 {
 441     RISCVCPU *cpu = RISCV_CPU(cs);
 442     CPURISCVState *env = &cpu->env;
 443
 444     if (access_type == MMU_DATA_STORE) {
 445         cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 446     } else {
 447         cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
 448     }
 449
 450     env->badaddr = addr;
 451     riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
 452 }
 453
 454 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 455                                    MMUAccessType access_type, int mmu_idx,
 456                                    uintptr_t retaddr)
 457 {
 458     RISCVCPU *cpu = RISCV_CPU(cs);
 459     CPURISCVState *env = &cpu->env;
 460     switch (access_type) {
 461     case MMU_INST_FETCH:
 462         cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
 463         break;
 464     case MMU_DATA_LOAD:
 465         cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
 466         break;
 467     case MMU_DATA_STORE:
 468         cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
 469         break;
 470     default:
 471         g_assert_not_reached();
 472     }
 473     env->badaddr = addr;
 474     riscv_raise_exception(env, cs->exception_index, retaddr);
 475 }
 476 #endif
 477
 478 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 479                         MMUAccessType access_type, int mmu_idx,
 480                         bool probe, uintptr_t retaddr)
 481 {
 482     RISCVCPU *cpu = RISCV_CPU(cs);
 483     CPURISCVState *env = &cpu->env;
 484 #ifndef CONFIG_USER_ONLY
 485     hwaddr pa = 0;
 486     int prot;
 487     bool pmp_violation = false;
 488     int ret = TRANSLATE_FAIL;
 489     int mode = mmu_idx;
 490
 491     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 492                   __func__, address, access_type, mmu_idx);
 493
 494     ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);
 495
 496     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
 497         if (get_field(env->mstatus, MSTATUS_MPRV)) {
 498             mode = get_field(env->mstatus, MSTATUS_MPP);
 499         }
 500     }
 501
 502     qemu_log_mask(CPU_LOG_MMU,
 503                   "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 504                   " prot %d\n", __func__, address, ret, pa, prot);
 505
 506     if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 507         (ret == TRANSLATE_SUCCESS) &&
 508         !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 509         ret = TRANSLATE_PMP_FAIL;
 510     }
 511     if (ret == TRANSLATE_PMP_FAIL) {
 512         pmp_violation = true;
 513     }
 514     if (ret == TRANSLATE_SUCCESS) {
 515         tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
 516                      prot, mmu_idx, TARGET_PAGE_SIZE);
 517         return true;
 518     } else if (probe) {
 519         return false;
 520     } else {
 521         raise_mmu_exception(env, address, access_type, pmp_violation);
 522         riscv_raise_exception(env, cs->exception_index, retaddr);
 523     }
 524 #else
 525     switch (access_type) {
 526     case MMU_INST_FETCH:
 527         cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
 528         break;
 529     case MMU_DATA_LOAD:
 530         cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
 531         break;
 532     case MMU_DATA_STORE:
 533         cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
 534         break;
 535     default:
 536         g_assert_not_reached();
 537     }
 538     env->badaddr = address;
 539     cpu_loop_exit_restore(cs, retaddr);
 540 #endif
 541 }
 542
 543 /*
 544  * Handle Traps
 545  *
 546  * Adapted from Spike's processor_t::take_trap.
 547  *
 548  */
 549 void riscv_cpu_do_interrupt(CPUState *cs)
 550 {
 551 #if !defined(CONFIG_USER_ONLY)
 552
 553     RISCVCPU *cpu = RISCV_CPU(cs);
 554     CPURISCVState *env = &cpu->env;
 555
 556     /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
 557      * so we mask off the MSB and separate into trap type and cause.
 558      */
 559     bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
 560     target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
 561     target_ulong deleg = async ? env->mideleg : env->medeleg;
 562     target_ulong tval = 0;
 563
 564     static const int ecall_cause_map[] = {
 565         [PRV_U] = RISCV_EXCP_U_ECALL,
 566         [PRV_S] = RISCV_EXCP_S_ECALL,
 567         [PRV_H] = RISCV_EXCP_VS_ECALL,
 568         [PRV_M] = RISCV_EXCP_M_ECALL
 569     };
 570
 571     if (!async) {
 572         /* set tval to badaddr for traps with address information */
 573         switch (cause) {
 574         case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
 575         case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
 576         case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
 577         case RISCV_EXCP_INST_ADDR_MIS:
 578         case RISCV_EXCP_INST_ACCESS_FAULT:
 579         case RISCV_EXCP_LOAD_ADDR_MIS:
 580         case RISCV_EXCP_STORE_AMO_ADDR_MIS:
 581         case RISCV_EXCP_LOAD_ACCESS_FAULT:
 582         case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
 583         case RISCV_EXCP_INST_PAGE_FAULT:
 584         case RISCV_EXCP_LOAD_PAGE_FAULT:
 585         case RISCV_EXCP_STORE_PAGE_FAULT:
 586             tval = env->badaddr;
 587             break;
 588         default:
 589             break;
 590         }
 591         /* ecall is dispatched as one cause so translate based on mode */
 592         if (cause == RISCV_EXCP_U_ECALL) {
 593             assert(env->priv <= 3);
 594             cause = ecall_cause_map[env->priv];
 595         }
 596     }
 597
 598     trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
 599         (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
 600
 601     if (env->priv <= PRV_S &&
 602             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
 603         /* handle the trap in S-mode */
 604         target_ulong s = env->mstatus;
 605         s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
 606             get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
 607         s = set_field(s, MSTATUS_SPP, env->priv);
 608         s = set_field(s, MSTATUS_SIE, 0);
 609         env->mstatus = s;
 610         env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
 611         env->sepc = env->pc;
 612         env->sbadaddr = tval;
 613         env->pc = (env->stvec >> 2 << 2) +
 614             ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
 615         riscv_cpu_set_mode(env, PRV_S);
 616     } else {
 617         /* handle the trap in M-mode */
 618         target_ulong s = env->mstatus;
 619         s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
 620             get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
 621         s = set_field(s, MSTATUS_MPP, env->priv);
 622         s = set_field(s, MSTATUS_MIE, 0);
 623         env->mstatus = s;
 624         env->mcause = cause | ~(((target_ulong)-1) >> async);
 625         env->mepc = env->pc;
 626         env->mbadaddr = tval;
 627         env->pc = (env->mtvec >> 2 << 2) +
 628             ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
 629         riscv_cpu_set_mode(env, PRV_M);
 630     }
 631
 632     /* NOTE: it is not necessary to yield load reservations here. It is only
 633      * necessary for an SC from "another hart" to cause a load reservation
 634      * to be yielded. Refer to the memory consistency model section of the
 635      * RISC-V ISA Specification.
 636      */
 637
 638 #endif
 639     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 640 }