2 * RISC-V Control and Status Registers.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/timer.h"
25 #include "time_helper.h"
26 #include "qemu/main-loop.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/cpu-timers.h"
29 #include "qemu/guest-random.h"
30 #include "qapi/error.h"
32 /* CSR function table public API */
33 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
)
35 *ops
= csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)];
38 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
)
40 csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)] = *ops
;
44 #if !defined(CONFIG_USER_ONLY)
45 static RISCVException
smstateen_acc_ok(CPURISCVState
*env
, int index
,
48 bool virt
= riscv_cpu_virt_enabled(env
);
49 CPUState
*cs
= env_cpu(env
);
50 RISCVCPU
*cpu
= RISCV_CPU(cs
);
52 if (env
->priv
== PRV_M
|| !cpu
->cfg
.ext_smstateen
) {
53 return RISCV_EXCP_NONE
;
56 if (!(env
->mstateen
[index
] & bit
)) {
57 return RISCV_EXCP_ILLEGAL_INST
;
61 if (!(env
->hstateen
[index
] & bit
)) {
62 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
65 if (env
->priv
== PRV_U
&& !(env
->sstateen
[index
] & bit
)) {
66 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
70 if (env
->priv
== PRV_U
&& riscv_has_ext(env
, RVS
)) {
71 if (!(env
->sstateen
[index
] & bit
)) {
72 return RISCV_EXCP_ILLEGAL_INST
;
76 return RISCV_EXCP_NONE
;
80 static RISCVException
fs(CPURISCVState
*env
, int csrno
)
82 #if !defined(CONFIG_USER_ONLY)
83 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
) &&
84 !RISCV_CPU(env_cpu(env
))->cfg
.ext_zfinx
) {
85 return RISCV_EXCP_ILLEGAL_INST
;
88 return RISCV_EXCP_NONE
;
91 static RISCVException
vs(CPURISCVState
*env
, int csrno
)
93 CPUState
*cs
= env_cpu(env
);
94 RISCVCPU
*cpu
= RISCV_CPU(cs
);
96 if (env
->misa_ext
& RVV
||
97 cpu
->cfg
.ext_zve32f
|| cpu
->cfg
.ext_zve64f
) {
98 #if !defined(CONFIG_USER_ONLY)
99 if (!env
->debugger
&& !riscv_cpu_vector_enabled(env
)) {
100 return RISCV_EXCP_ILLEGAL_INST
;
103 return RISCV_EXCP_NONE
;
105 return RISCV_EXCP_ILLEGAL_INST
;
108 static RISCVException
ctr(CPURISCVState
*env
, int csrno
)
110 #if !defined(CONFIG_USER_ONLY)
111 CPUState
*cs
= env_cpu(env
);
112 RISCVCPU
*cpu
= RISCV_CPU(cs
);
114 target_ulong ctr_mask
;
115 int base_csrno
= CSR_CYCLE
;
116 bool rv32
= riscv_cpu_mxl(env
) == MXL_RV32
? true : false;
118 if (rv32
&& csrno
>= CSR_CYCLEH
) {
119 /* Offset for RV32 hpmcounternh counters */
122 ctr_index
= csrno
- base_csrno
;
123 ctr_mask
= BIT(ctr_index
);
125 if ((csrno
>= CSR_CYCLE
&& csrno
<= CSR_INSTRET
) ||
126 (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_INSTRETH
)) {
127 goto skip_ext_pmu_check
;
130 if (!(cpu
->pmu_avail_ctrs
& ctr_mask
)) {
131 /* No counter is enabled in PMU or the counter is out of range */
132 return RISCV_EXCP_ILLEGAL_INST
;
137 if (env
->priv
< PRV_M
&& !get_field(env
->mcounteren
, ctr_mask
)) {
138 return RISCV_EXCP_ILLEGAL_INST
;
141 if (riscv_cpu_virt_enabled(env
)) {
142 if (!get_field(env
->hcounteren
, ctr_mask
) ||
143 (env
->priv
== PRV_U
&& !get_field(env
->scounteren
, ctr_mask
))) {
144 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
148 if (riscv_has_ext(env
, RVS
) && env
->priv
== PRV_U
&&
149 !get_field(env
->scounteren
, ctr_mask
)) {
150 return RISCV_EXCP_ILLEGAL_INST
;
154 return RISCV_EXCP_NONE
;
157 static RISCVException
ctr32(CPURISCVState
*env
, int csrno
)
159 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
160 return RISCV_EXCP_ILLEGAL_INST
;
163 return ctr(env
, csrno
);
166 #if !defined(CONFIG_USER_ONLY)
167 static RISCVException
mctr(CPURISCVState
*env
, int csrno
)
169 CPUState
*cs
= env_cpu(env
);
170 RISCVCPU
*cpu
= RISCV_CPU(cs
);
172 int base_csrno
= CSR_MHPMCOUNTER3
;
174 if ((riscv_cpu_mxl(env
) == MXL_RV32
) && csrno
>= CSR_MCYCLEH
) {
175 /* Offset for RV32 mhpmcounternh counters */
178 ctr_index
= csrno
- base_csrno
;
179 if (!cpu
->cfg
.pmu_num
|| ctr_index
>= cpu
->cfg
.pmu_num
) {
180 /* The PMU is not enabled or counter is out of range*/
181 return RISCV_EXCP_ILLEGAL_INST
;
184 return RISCV_EXCP_NONE
;
187 static RISCVException
mctr32(CPURISCVState
*env
, int csrno
)
189 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
190 return RISCV_EXCP_ILLEGAL_INST
;
193 return mctr(env
, csrno
);
196 static RISCVException
sscofpmf(CPURISCVState
*env
, int csrno
)
198 CPUState
*cs
= env_cpu(env
);
199 RISCVCPU
*cpu
= RISCV_CPU(cs
);
201 if (!cpu
->cfg
.ext_sscofpmf
) {
202 return RISCV_EXCP_ILLEGAL_INST
;
205 return RISCV_EXCP_NONE
;
208 static RISCVException
any(CPURISCVState
*env
, int csrno
)
210 return RISCV_EXCP_NONE
;
213 static RISCVException
any32(CPURISCVState
*env
, int csrno
)
215 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
216 return RISCV_EXCP_ILLEGAL_INST
;
219 return any(env
, csrno
);
223 static int aia_any(CPURISCVState
*env
, int csrno
)
225 RISCVCPU
*cpu
= env_archcpu(env
);
227 if (!cpu
->cfg
.ext_smaia
) {
228 return RISCV_EXCP_ILLEGAL_INST
;
231 return any(env
, csrno
);
234 static int aia_any32(CPURISCVState
*env
, int csrno
)
236 RISCVCPU
*cpu
= env_archcpu(env
);
238 if (!cpu
->cfg
.ext_smaia
) {
239 return RISCV_EXCP_ILLEGAL_INST
;
242 return any32(env
, csrno
);
245 static RISCVException
smode(CPURISCVState
*env
, int csrno
)
247 if (riscv_has_ext(env
, RVS
)) {
248 return RISCV_EXCP_NONE
;
251 return RISCV_EXCP_ILLEGAL_INST
;
254 static int smode32(CPURISCVState
*env
, int csrno
)
256 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
257 return RISCV_EXCP_ILLEGAL_INST
;
260 return smode(env
, csrno
);
263 static int aia_smode(CPURISCVState
*env
, int csrno
)
265 RISCVCPU
*cpu
= env_archcpu(env
);
267 if (!cpu
->cfg
.ext_ssaia
) {
268 return RISCV_EXCP_ILLEGAL_INST
;
271 return smode(env
, csrno
);
274 static int aia_smode32(CPURISCVState
*env
, int csrno
)
276 RISCVCPU
*cpu
= env_archcpu(env
);
278 if (!cpu
->cfg
.ext_ssaia
) {
279 return RISCV_EXCP_ILLEGAL_INST
;
282 return smode32(env
, csrno
);
285 static RISCVException
hmode(CPURISCVState
*env
, int csrno
)
287 if (riscv_has_ext(env
, RVH
)) {
288 return RISCV_EXCP_NONE
;
291 return RISCV_EXCP_ILLEGAL_INST
;
294 static RISCVException
hmode32(CPURISCVState
*env
, int csrno
)
296 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
297 return RISCV_EXCP_ILLEGAL_INST
;
300 return hmode(env
, csrno
);
304 static RISCVException
umode(CPURISCVState
*env
, int csrno
)
306 if (riscv_has_ext(env
, RVU
)) {
307 return RISCV_EXCP_NONE
;
310 return RISCV_EXCP_ILLEGAL_INST
;
313 static RISCVException
umode32(CPURISCVState
*env
, int csrno
)
315 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
316 return RISCV_EXCP_ILLEGAL_INST
;
319 return umode(env
, csrno
);
322 static RISCVException
mstateen(CPURISCVState
*env
, int csrno
)
324 CPUState
*cs
= env_cpu(env
);
325 RISCVCPU
*cpu
= RISCV_CPU(cs
);
327 if (!cpu
->cfg
.ext_smstateen
) {
328 return RISCV_EXCP_ILLEGAL_INST
;
331 return any(env
, csrno
);
334 static RISCVException
hstateen_pred(CPURISCVState
*env
, int csrno
, int base
)
336 CPUState
*cs
= env_cpu(env
);
337 RISCVCPU
*cpu
= RISCV_CPU(cs
);
339 if (!cpu
->cfg
.ext_smstateen
) {
340 return RISCV_EXCP_ILLEGAL_INST
;
343 if (env
->priv
< PRV_M
) {
344 if (!(env
->mstateen
[csrno
- base
] & SMSTATEEN_STATEEN
)) {
345 return RISCV_EXCP_ILLEGAL_INST
;
349 return hmode(env
, csrno
);
352 static RISCVException
hstateen(CPURISCVState
*env
, int csrno
)
354 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0
);
357 static RISCVException
hstateenh(CPURISCVState
*env
, int csrno
)
359 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0H
);
362 static RISCVException
sstateen(CPURISCVState
*env
, int csrno
)
364 bool virt
= riscv_cpu_virt_enabled(env
);
365 int index
= csrno
- CSR_SSTATEEN0
;
366 CPUState
*cs
= env_cpu(env
);
367 RISCVCPU
*cpu
= RISCV_CPU(cs
);
369 if (!cpu
->cfg
.ext_smstateen
) {
370 return RISCV_EXCP_ILLEGAL_INST
;
373 if (env
->priv
< PRV_M
) {
374 if (!(env
->mstateen
[index
] & SMSTATEEN_STATEEN
)) {
375 return RISCV_EXCP_ILLEGAL_INST
;
379 if (!(env
->hstateen
[index
] & SMSTATEEN_STATEEN
)) {
380 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
385 return smode(env
, csrno
);
388 /* Checks if PointerMasking registers could be accessed */
389 static RISCVException
pointer_masking(CPURISCVState
*env
, int csrno
)
391 /* Check if j-ext is present */
392 if (riscv_has_ext(env
, RVJ
)) {
393 return RISCV_EXCP_NONE
;
395 return RISCV_EXCP_ILLEGAL_INST
;
398 static int aia_hmode(CPURISCVState
*env
, int csrno
)
400 RISCVCPU
*cpu
= env_archcpu(env
);
402 if (!cpu
->cfg
.ext_ssaia
) {
403 return RISCV_EXCP_ILLEGAL_INST
;
406 return hmode(env
, csrno
);
409 static int aia_hmode32(CPURISCVState
*env
, int csrno
)
411 RISCVCPU
*cpu
= env_archcpu(env
);
413 if (!cpu
->cfg
.ext_ssaia
) {
414 return RISCV_EXCP_ILLEGAL_INST
;
417 return hmode32(env
, csrno
);
420 static RISCVException
pmp(CPURISCVState
*env
, int csrno
)
422 if (riscv_feature(env
, RISCV_FEATURE_PMP
)) {
423 return RISCV_EXCP_NONE
;
426 return RISCV_EXCP_ILLEGAL_INST
;
429 static RISCVException
epmp(CPURISCVState
*env
, int csrno
)
431 if (env
->priv
== PRV_M
&& riscv_feature(env
, RISCV_FEATURE_EPMP
)) {
432 return RISCV_EXCP_NONE
;
435 return RISCV_EXCP_ILLEGAL_INST
;
438 static RISCVException
debug(CPURISCVState
*env
, int csrno
)
440 if (riscv_cpu_cfg(env
)->debug
) {
441 return RISCV_EXCP_NONE
;
444 return RISCV_EXCP_ILLEGAL_INST
;
448 static RISCVException
seed(CPURISCVState
*env
, int csrno
)
450 RISCVCPU
*cpu
= env_archcpu(env
);
452 if (!cpu
->cfg
.ext_zkr
) {
453 return RISCV_EXCP_ILLEGAL_INST
;
456 #if !defined(CONFIG_USER_ONLY)
458 * With a CSR read-write instruction:
459 * 1) The seed CSR is always available in machine mode as normal.
460 * 2) Attempted access to seed from virtual modes VS and VU always raises
461 * an exception(virtual instruction exception only if mseccfg.sseed=1).
462 * 3) Without the corresponding access control bit set to 1, any attempted
463 * access to seed from U, S or HS modes will raise an illegal instruction
466 if (env
->priv
== PRV_M
) {
467 return RISCV_EXCP_NONE
;
468 } else if (riscv_cpu_virt_enabled(env
)) {
469 if (env
->mseccfg
& MSECCFG_SSEED
) {
470 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
472 return RISCV_EXCP_ILLEGAL_INST
;
475 if (env
->priv
== PRV_S
&& (env
->mseccfg
& MSECCFG_SSEED
)) {
476 return RISCV_EXCP_NONE
;
477 } else if (env
->priv
== PRV_U
&& (env
->mseccfg
& MSECCFG_USEED
)) {
478 return RISCV_EXCP_NONE
;
480 return RISCV_EXCP_ILLEGAL_INST
;
484 return RISCV_EXCP_NONE
;
488 /* User Floating-Point CSRs */
489 static RISCVException
read_fflags(CPURISCVState
*env
, int csrno
,
492 *val
= riscv_cpu_get_fflags(env
);
493 return RISCV_EXCP_NONE
;
496 static RISCVException
write_fflags(CPURISCVState
*env
, int csrno
,
499 #if !defined(CONFIG_USER_ONLY)
500 if (riscv_has_ext(env
, RVF
)) {
501 env
->mstatus
|= MSTATUS_FS
;
504 riscv_cpu_set_fflags(env
, val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
));
505 return RISCV_EXCP_NONE
;
508 static RISCVException
read_frm(CPURISCVState
*env
, int csrno
,
512 return RISCV_EXCP_NONE
;
515 static RISCVException
write_frm(CPURISCVState
*env
, int csrno
,
518 #if !defined(CONFIG_USER_ONLY)
519 if (riscv_has_ext(env
, RVF
)) {
520 env
->mstatus
|= MSTATUS_FS
;
523 env
->frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
524 return RISCV_EXCP_NONE
;
527 static RISCVException
read_fcsr(CPURISCVState
*env
, int csrno
,
530 *val
= (riscv_cpu_get_fflags(env
) << FSR_AEXC_SHIFT
)
531 | (env
->frm
<< FSR_RD_SHIFT
);
532 return RISCV_EXCP_NONE
;
535 static RISCVException
write_fcsr(CPURISCVState
*env
, int csrno
,
538 #if !defined(CONFIG_USER_ONLY)
539 if (riscv_has_ext(env
, RVF
)) {
540 env
->mstatus
|= MSTATUS_FS
;
543 env
->frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
544 riscv_cpu_set_fflags(env
, (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
);
545 return RISCV_EXCP_NONE
;
548 static RISCVException
read_vtype(CPURISCVState
*env
, int csrno
,
554 vill
= (uint32_t)env
->vill
<< 31;
557 vill
= (uint64_t)env
->vill
<< 63;
560 g_assert_not_reached();
562 *val
= (target_ulong
)vill
| env
->vtype
;
563 return RISCV_EXCP_NONE
;
566 static RISCVException
read_vl(CPURISCVState
*env
, int csrno
,
570 return RISCV_EXCP_NONE
;
573 static int read_vlenb(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
575 *val
= env_archcpu(env
)->cfg
.vlen
>> 3;
576 return RISCV_EXCP_NONE
;
579 static RISCVException
read_vxrm(CPURISCVState
*env
, int csrno
,
583 return RISCV_EXCP_NONE
;
586 static RISCVException
write_vxrm(CPURISCVState
*env
, int csrno
,
589 #if !defined(CONFIG_USER_ONLY)
590 env
->mstatus
|= MSTATUS_VS
;
593 return RISCV_EXCP_NONE
;
596 static RISCVException
read_vxsat(CPURISCVState
*env
, int csrno
,
600 return RISCV_EXCP_NONE
;
603 static RISCVException
write_vxsat(CPURISCVState
*env
, int csrno
,
606 #if !defined(CONFIG_USER_ONLY)
607 env
->mstatus
|= MSTATUS_VS
;
610 return RISCV_EXCP_NONE
;
613 static RISCVException
read_vstart(CPURISCVState
*env
, int csrno
,
617 return RISCV_EXCP_NONE
;
620 static RISCVException
write_vstart(CPURISCVState
*env
, int csrno
,
623 #if !defined(CONFIG_USER_ONLY)
624 env
->mstatus
|= MSTATUS_VS
;
627 * The vstart CSR is defined to have only enough writable bits
628 * to hold the largest element index, i.e. lg2(VLEN) bits.
630 env
->vstart
= val
& ~(~0ULL << ctzl(env_archcpu(env
)->cfg
.vlen
));
631 return RISCV_EXCP_NONE
;
634 static int read_vcsr(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
636 *val
= (env
->vxrm
<< VCSR_VXRM_SHIFT
) | (env
->vxsat
<< VCSR_VXSAT_SHIFT
);
637 return RISCV_EXCP_NONE
;
640 static int write_vcsr(CPURISCVState
*env
, int csrno
, target_ulong val
)
642 #if !defined(CONFIG_USER_ONLY)
643 env
->mstatus
|= MSTATUS_VS
;
645 env
->vxrm
= (val
& VCSR_VXRM
) >> VCSR_VXRM_SHIFT
;
646 env
->vxsat
= (val
& VCSR_VXSAT
) >> VCSR_VXSAT_SHIFT
;
647 return RISCV_EXCP_NONE
;
650 /* User Timers and Counters */
651 static target_ulong
get_ticks(bool shift
)
656 #if !defined(CONFIG_USER_ONLY)
657 if (icount_enabled()) {
660 val
= cpu_get_host_ticks();
663 val
= cpu_get_host_ticks();
675 #if defined(CONFIG_USER_ONLY)
676 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
679 *val
= cpu_get_host_ticks();
680 return RISCV_EXCP_NONE
;
683 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
686 *val
= cpu_get_host_ticks() >> 32;
687 return RISCV_EXCP_NONE
;
690 static int read_hpmcounter(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
692 *val
= get_ticks(false);
693 return RISCV_EXCP_NONE
;
696 static int read_hpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
698 *val
= get_ticks(true);
699 return RISCV_EXCP_NONE
;
702 #else /* CONFIG_USER_ONLY */
704 static int read_mhpmevent(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
706 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
708 *val
= env
->mhpmevent_val
[evt_index
];
710 return RISCV_EXCP_NONE
;
713 static int write_mhpmevent(CPURISCVState
*env
, int csrno
, target_ulong val
)
715 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
716 uint64_t mhpmevt_val
= val
;
718 env
->mhpmevent_val
[evt_index
] = val
;
720 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
721 mhpmevt_val
= mhpmevt_val
|
722 ((uint64_t)env
->mhpmeventh_val
[evt_index
] << 32);
724 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
726 return RISCV_EXCP_NONE
;
729 static int read_mhpmeventh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
731 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
733 *val
= env
->mhpmeventh_val
[evt_index
];
735 return RISCV_EXCP_NONE
;
738 static int write_mhpmeventh(CPURISCVState
*env
, int csrno
, target_ulong val
)
740 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
741 uint64_t mhpmevth_val
= val
;
742 uint64_t mhpmevt_val
= env
->mhpmevent_val
[evt_index
];
744 mhpmevt_val
= mhpmevt_val
| (mhpmevth_val
<< 32);
745 env
->mhpmeventh_val
[evt_index
] = val
;
747 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
749 return RISCV_EXCP_NONE
;
752 static int write_mhpmcounter(CPURISCVState
*env
, int csrno
, target_ulong val
)
754 int ctr_idx
= csrno
- CSR_MCYCLE
;
755 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
756 uint64_t mhpmctr_val
= val
;
758 counter
->mhpmcounter_val
= val
;
759 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
760 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
761 counter
->mhpmcounter_prev
= get_ticks(false);
763 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
764 mhpmctr_val
= mhpmctr_val
|
765 ((uint64_t)counter
->mhpmcounterh_val
<< 32);
767 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
770 /* Other counters can keep incrementing from the given value */
771 counter
->mhpmcounter_prev
= val
;
774 return RISCV_EXCP_NONE
;
777 static int write_mhpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong val
)
779 int ctr_idx
= csrno
- CSR_MCYCLEH
;
780 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
781 uint64_t mhpmctr_val
= counter
->mhpmcounter_val
;
782 uint64_t mhpmctrh_val
= val
;
784 counter
->mhpmcounterh_val
= val
;
785 mhpmctr_val
= mhpmctr_val
| (mhpmctrh_val
<< 32);
786 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
787 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
788 counter
->mhpmcounterh_prev
= get_ticks(true);
790 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
793 counter
->mhpmcounterh_prev
= val
;
796 return RISCV_EXCP_NONE
;
799 static RISCVException
riscv_pmu_read_ctr(CPURISCVState
*env
, target_ulong
*val
,
800 bool upper_half
, uint32_t ctr_idx
)
802 PMUCTRState counter
= env
->pmu_ctrs
[ctr_idx
];
803 target_ulong ctr_prev
= upper_half
? counter
.mhpmcounterh_prev
:
804 counter
.mhpmcounter_prev
;
805 target_ulong ctr_val
= upper_half
? counter
.mhpmcounterh_val
:
806 counter
.mhpmcounter_val
;
808 if (get_field(env
->mcountinhibit
, BIT(ctr_idx
))) {
810 * Counter should not increment if inhibit bit is set. We can't really
811 * stop the icount counting. Just return the counter value written by
812 * the supervisor to indicate that counter was not incremented.
814 if (!counter
.started
) {
816 return RISCV_EXCP_NONE
;
818 /* Mark that the counter has been stopped */
819 counter
.started
= false;
824 * The kernel computes the perf delta by subtracting the current value from
825 * the value it initialized previously (ctr_val).
827 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
828 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
829 *val
= get_ticks(upper_half
) - ctr_prev
+ ctr_val
;
834 return RISCV_EXCP_NONE
;
837 static int read_hpmcounter(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
841 if (csrno
>= CSR_MCYCLE
&& csrno
<= CSR_MHPMCOUNTER31
) {
842 ctr_index
= csrno
- CSR_MCYCLE
;
843 } else if (csrno
>= CSR_CYCLE
&& csrno
<= CSR_HPMCOUNTER31
) {
844 ctr_index
= csrno
- CSR_CYCLE
;
846 return RISCV_EXCP_ILLEGAL_INST
;
849 return riscv_pmu_read_ctr(env
, val
, false, ctr_index
);
852 static int read_hpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
856 if (csrno
>= CSR_MCYCLEH
&& csrno
<= CSR_MHPMCOUNTER31H
) {
857 ctr_index
= csrno
- CSR_MCYCLEH
;
858 } else if (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_HPMCOUNTER31H
) {
859 ctr_index
= csrno
- CSR_CYCLEH
;
861 return RISCV_EXCP_ILLEGAL_INST
;
864 return riscv_pmu_read_ctr(env
, val
, true, ctr_index
);
867 static int read_scountovf(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
869 int mhpmevt_start
= CSR_MHPMEVENT3
- CSR_MCOUNTINHIBIT
;
872 target_ulong
*mhpm_evt_val
;
873 uint64_t of_bit_mask
;
875 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
876 mhpm_evt_val
= env
->mhpmeventh_val
;
877 of_bit_mask
= MHPMEVENTH_BIT_OF
;
879 mhpm_evt_val
= env
->mhpmevent_val
;
880 of_bit_mask
= MHPMEVENT_BIT_OF
;
883 for (i
= mhpmevt_start
; i
< RV_MAX_MHPMEVENTS
; i
++) {
884 if ((get_field(env
->mcounteren
, BIT(i
))) &&
885 (mhpm_evt_val
[i
] & of_bit_mask
)) {
890 return RISCV_EXCP_NONE
;
893 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
896 uint64_t delta
= riscv_cpu_virt_enabled(env
) ? env
->htimedelta
: 0;
898 if (!env
->rdtime_fn
) {
899 return RISCV_EXCP_ILLEGAL_INST
;
902 *val
= env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
;
903 return RISCV_EXCP_NONE
;
906 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
909 uint64_t delta
= riscv_cpu_virt_enabled(env
) ? env
->htimedelta
: 0;
911 if (!env
->rdtime_fn
) {
912 return RISCV_EXCP_ILLEGAL_INST
;
915 *val
= (env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
) >> 32;
916 return RISCV_EXCP_NONE
;
919 static RISCVException
sstc(CPURISCVState
*env
, int csrno
)
921 CPUState
*cs
= env_cpu(env
);
922 RISCVCPU
*cpu
= RISCV_CPU(cs
);
923 bool hmode_check
= false;
925 if (!cpu
->cfg
.ext_sstc
|| !env
->rdtime_fn
) {
926 return RISCV_EXCP_ILLEGAL_INST
;
929 if (env
->priv
== PRV_M
) {
930 return RISCV_EXCP_NONE
;
934 * No need of separate function for rv32 as menvcfg stores both menvcfg
937 if (!(get_field(env
->mcounteren
, COUNTEREN_TM
) &&
938 get_field(env
->menvcfg
, MENVCFG_STCE
))) {
939 return RISCV_EXCP_ILLEGAL_INST
;
942 if (riscv_cpu_virt_enabled(env
)) {
943 if (!(get_field(env
->hcounteren
, COUNTEREN_TM
) &&
944 get_field(env
->henvcfg
, HENVCFG_STCE
))) {
945 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
949 if ((csrno
== CSR_VSTIMECMP
) || (csrno
== CSR_VSTIMECMPH
)) {
953 return hmode_check
? hmode(env
, csrno
) : smode(env
, csrno
);
956 static RISCVException
sstc_32(CPURISCVState
*env
, int csrno
)
958 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
959 return RISCV_EXCP_ILLEGAL_INST
;
962 return sstc(env
, csrno
);
965 static RISCVException
read_vstimecmp(CPURISCVState
*env
, int csrno
,
968 *val
= env
->vstimecmp
;
970 return RISCV_EXCP_NONE
;
973 static RISCVException
read_vstimecmph(CPURISCVState
*env
, int csrno
,
976 *val
= env
->vstimecmp
>> 32;
978 return RISCV_EXCP_NONE
;
981 static RISCVException
write_vstimecmp(CPURISCVState
*env
, int csrno
,
984 RISCVCPU
*cpu
= env_archcpu(env
);
986 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
987 env
->vstimecmp
= deposit64(env
->vstimecmp
, 0, 32, (uint64_t)val
);
989 env
->vstimecmp
= val
;
992 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
993 env
->htimedelta
, MIP_VSTIP
);
995 return RISCV_EXCP_NONE
;
998 static RISCVException
write_vstimecmph(CPURISCVState
*env
, int csrno
,
1001 RISCVCPU
*cpu
= env_archcpu(env
);
1003 env
->vstimecmp
= deposit64(env
->vstimecmp
, 32, 32, (uint64_t)val
);
1004 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
1005 env
->htimedelta
, MIP_VSTIP
);
1007 return RISCV_EXCP_NONE
;
1010 static RISCVException
read_stimecmp(CPURISCVState
*env
, int csrno
,
1013 if (riscv_cpu_virt_enabled(env
)) {
1014 *val
= env
->vstimecmp
;
1016 *val
= env
->stimecmp
;
1019 return RISCV_EXCP_NONE
;
1022 static RISCVException
read_stimecmph(CPURISCVState
*env
, int csrno
,
1025 if (riscv_cpu_virt_enabled(env
)) {
1026 *val
= env
->vstimecmp
>> 32;
1028 *val
= env
->stimecmp
>> 32;
1031 return RISCV_EXCP_NONE
;
1034 static RISCVException
write_stimecmp(CPURISCVState
*env
, int csrno
,
1037 RISCVCPU
*cpu
= env_archcpu(env
);
1039 if (riscv_cpu_virt_enabled(env
)) {
1040 if (env
->hvictl
& HVICTL_VTI
) {
1041 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1043 return write_vstimecmp(env
, csrno
, val
);
1046 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1047 env
->stimecmp
= deposit64(env
->stimecmp
, 0, 32, (uint64_t)val
);
1049 env
->stimecmp
= val
;
1052 riscv_timer_write_timecmp(cpu
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1054 return RISCV_EXCP_NONE
;
1057 static RISCVException
write_stimecmph(CPURISCVState
*env
, int csrno
,
1060 RISCVCPU
*cpu
= env_archcpu(env
);
1062 if (riscv_cpu_virt_enabled(env
)) {
1063 if (env
->hvictl
& HVICTL_VTI
) {
1064 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1066 return write_vstimecmph(env
, csrno
, val
);
1069 env
->stimecmp
= deposit64(env
->stimecmp
, 32, 32, (uint64_t)val
);
1070 riscv_timer_write_timecmp(cpu
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1072 return RISCV_EXCP_NONE
;
1075 /* Machine constants */
1077 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
1078 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \
1080 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
1081 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
1083 #define VSTOPI_NUM_SRCS 5
1085 static const uint64_t delegable_ints
= S_MODE_INTERRUPTS
|
1087 static const uint64_t vs_delegable_ints
= VS_MODE_INTERRUPTS
;
1088 static const uint64_t all_ints
= M_MODE_INTERRUPTS
| S_MODE_INTERRUPTS
|
1090 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
1091 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
1092 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
1093 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
1094 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
1095 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
1096 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
1097 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
1098 (1ULL << (RISCV_EXCP_U_ECALL)) | \
1099 (1ULL << (RISCV_EXCP_S_ECALL)) | \
1100 (1ULL << (RISCV_EXCP_VS_ECALL)) | \
1101 (1ULL << (RISCV_EXCP_M_ECALL)) | \
1102 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
1103 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
1104 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
1105 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
1106 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
1107 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
1108 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
1109 static const target_ulong vs_delegable_excps
= DELEGABLE_EXCPS
&
1110 ~((1ULL << (RISCV_EXCP_S_ECALL
)) |
1111 (1ULL << (RISCV_EXCP_VS_ECALL
)) |
1112 (1ULL << (RISCV_EXCP_M_ECALL
)) |
1113 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT
)) |
1114 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
)) |
1115 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT
)) |
1116 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
)));
1117 static const target_ulong sstatus_v1_10_mask
= SSTATUS_SIE
| SSTATUS_SPIE
|
1118 SSTATUS_UIE
| SSTATUS_UPIE
| SSTATUS_SPP
| SSTATUS_FS
| SSTATUS_XS
|
1119 SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_VS
;
1120 static const target_ulong sip_writable_mask
= SIP_SSIP
| MIP_USIP
| MIP_UEIP
|
1122 static const target_ulong hip_writable_mask
= MIP_VSSIP
;
1123 static const target_ulong hvip_writable_mask
= MIP_VSSIP
| MIP_VSTIP
| MIP_VSEIP
;
1124 static const target_ulong vsip_writable_mask
= MIP_VSSIP
;
1126 static const char valid_vm_1_10_32
[16] = {
1127 [VM_1_10_MBARE
] = 1,
1131 static const char valid_vm_1_10_64
[16] = {
1132 [VM_1_10_MBARE
] = 1,
1138 /* Machine Information Registers */
1139 static RISCVException
read_zero(CPURISCVState
*env
, int csrno
,
1143 return RISCV_EXCP_NONE
;
1146 static RISCVException
write_ignore(CPURISCVState
*env
, int csrno
,
1149 return RISCV_EXCP_NONE
;
1152 static RISCVException
read_mvendorid(CPURISCVState
*env
, int csrno
,
1155 CPUState
*cs
= env_cpu(env
);
1156 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1158 *val
= cpu
->cfg
.mvendorid
;
1159 return RISCV_EXCP_NONE
;
1162 static RISCVException
read_marchid(CPURISCVState
*env
, int csrno
,
1165 CPUState
*cs
= env_cpu(env
);
1166 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1168 *val
= cpu
->cfg
.marchid
;
1169 return RISCV_EXCP_NONE
;
1172 static RISCVException
read_mimpid(CPURISCVState
*env
, int csrno
,
1175 CPUState
*cs
= env_cpu(env
);
1176 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1178 *val
= cpu
->cfg
.mimpid
;
1179 return RISCV_EXCP_NONE
;
1182 static RISCVException
read_mhartid(CPURISCVState
*env
, int csrno
,
1185 *val
= env
->mhartid
;
1186 return RISCV_EXCP_NONE
;
1189 /* Machine Trap Setup */
1191 /* We do not store SD explicitly, only compute it on demand. */
1192 static uint64_t add_status_sd(RISCVMXL xl
, uint64_t status
)
1194 if ((status
& MSTATUS_FS
) == MSTATUS_FS
||
1195 (status
& MSTATUS_VS
) == MSTATUS_VS
||
1196 (status
& MSTATUS_XS
) == MSTATUS_XS
) {
1199 return status
| MSTATUS32_SD
;
1201 return status
| MSTATUS64_SD
;
1203 return MSTATUSH128_SD
;
1205 g_assert_not_reached();
1211 static RISCVException
read_mstatus(CPURISCVState
*env
, int csrno
,
1214 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
);
1215 return RISCV_EXCP_NONE
;
1218 static int validate_vm(CPURISCVState
*env
, target_ulong vm
)
1220 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1221 return valid_vm_1_10_32
[vm
& 0xf];
1223 return valid_vm_1_10_64
[vm
& 0xf];
1227 static RISCVException
write_mstatus(CPURISCVState
*env
, int csrno
,
1230 uint64_t mstatus
= env
->mstatus
;
1232 RISCVMXL xl
= riscv_cpu_mxl(env
);
1234 /* flush tlb on mstatus fields that affect VM */
1235 if ((val
^ mstatus
) & (MSTATUS_MXR
| MSTATUS_MPP
| MSTATUS_MPV
|
1236 MSTATUS_MPRV
| MSTATUS_SUM
)) {
1237 tlb_flush(env_cpu(env
));
1239 mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
|
1240 MSTATUS_SPP
| MSTATUS_MPRV
| MSTATUS_SUM
|
1241 MSTATUS_MPP
| MSTATUS_MXR
| MSTATUS_TVM
| MSTATUS_TSR
|
1242 MSTATUS_TW
| MSTATUS_VS
;
1244 if (riscv_has_ext(env
, RVF
)) {
1248 if (xl
!= MXL_RV32
|| env
->debugger
) {
1250 * RV32: MPV and GVA are not in mstatus. The current plan is to
1251 * add them to mstatush. For now, we just don't support it.
1253 mask
|= MSTATUS_MPV
| MSTATUS_GVA
;
1254 if ((val
& MSTATUS64_UXL
) != 0) {
1255 mask
|= MSTATUS64_UXL
;
1259 mstatus
= (mstatus
& ~mask
) | (val
& mask
);
1261 if (xl
> MXL_RV32
) {
1262 /* SXL field is for now read only */
1263 mstatus
= set_field(mstatus
, MSTATUS64_SXL
, xl
);
1265 env
->mstatus
= mstatus
;
1266 env
->xl
= cpu_recompute_xl(env
);
1268 return RISCV_EXCP_NONE
;
1271 static RISCVException
read_mstatush(CPURISCVState
*env
, int csrno
,
1274 *val
= env
->mstatus
>> 32;
1275 return RISCV_EXCP_NONE
;
1278 static RISCVException
write_mstatush(CPURISCVState
*env
, int csrno
,
1281 uint64_t valh
= (uint64_t)val
<< 32;
1282 uint64_t mask
= MSTATUS_MPV
| MSTATUS_GVA
;
1284 if ((valh
^ env
->mstatus
) & (MSTATUS_MPV
)) {
1285 tlb_flush(env_cpu(env
));
1288 env
->mstatus
= (env
->mstatus
& ~mask
) | (valh
& mask
);
1290 return RISCV_EXCP_NONE
;
1293 static RISCVException
read_mstatus_i128(CPURISCVState
*env
, int csrno
,
1296 *val
= int128_make128(env
->mstatus
, add_status_sd(MXL_RV128
, env
->mstatus
));
1297 return RISCV_EXCP_NONE
;
1300 static RISCVException
read_misa_i128(CPURISCVState
*env
, int csrno
,
1303 *val
= int128_make128(env
->misa_ext
, (uint64_t)MXL_RV128
<< 62);
1304 return RISCV_EXCP_NONE
;
1307 static RISCVException
read_misa(CPURISCVState
*env
, int csrno
,
1312 switch (env
->misa_mxl
) {
1314 misa
= (target_ulong
)MXL_RV32
<< 30;
1316 #ifdef TARGET_RISCV64
1318 misa
= (target_ulong
)MXL_RV64
<< 62;
1322 g_assert_not_reached();
1325 *val
= misa
| env
->misa_ext
;
1326 return RISCV_EXCP_NONE
;
1329 static RISCVException
write_misa(CPURISCVState
*env
, int csrno
,
1332 if (!riscv_cpu_cfg(env
)->misa_w
) {
1333 /* drop write to misa */
1334 return RISCV_EXCP_NONE
;
1337 /* 'I' or 'E' must be present */
1338 if (!(val
& (RVI
| RVE
))) {
1339 /* It is not, drop write to misa */
1340 return RISCV_EXCP_NONE
;
1343 /* 'E' excludes all other extensions */
1345 /* when we support 'E' we can do "val = RVE;" however
1346 * for now we just drop writes if 'E' is present.
1348 return RISCV_EXCP_NONE
;
1352 * misa.MXL writes are not supported by QEMU.
1353 * Drop writes to those bits.
1356 /* Mask extensions that are not supported by this hart */
1357 val
&= env
->misa_ext_mask
;
1359 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
1360 if ((val
& RVD
) && !(val
& RVF
)) {
1364 /* Suppress 'C' if next instruction is not aligned
1365 * TODO: this should check next_pc
1367 if ((val
& RVC
) && (GETPC() & ~3) != 0) {
1371 /* If nothing changed, do nothing. */
1372 if (val
== env
->misa_ext
) {
1373 return RISCV_EXCP_NONE
;
1377 env
->mstatus
&= ~MSTATUS_FS
;
1380 /* flush translation cache */
1381 tb_flush(env_cpu(env
));
1382 env
->misa_ext
= val
;
1383 env
->xl
= riscv_cpu_mxl(env
);
1384 return RISCV_EXCP_NONE
;
1387 static RISCVException
read_medeleg(CPURISCVState
*env
, int csrno
,
1390 *val
= env
->medeleg
;
1391 return RISCV_EXCP_NONE
;
1394 static RISCVException
write_medeleg(CPURISCVState
*env
, int csrno
,
1397 env
->medeleg
= (env
->medeleg
& ~DELEGABLE_EXCPS
) | (val
& DELEGABLE_EXCPS
);
1398 return RISCV_EXCP_NONE
;
1401 static RISCVException
rmw_mideleg64(CPURISCVState
*env
, int csrno
,
1403 uint64_t new_val
, uint64_t wr_mask
)
1405 uint64_t mask
= wr_mask
& delegable_ints
;
1408 *ret_val
= env
->mideleg
;
1411 env
->mideleg
= (env
->mideleg
& ~mask
) | (new_val
& mask
);
1413 if (riscv_has_ext(env
, RVH
)) {
1414 env
->mideleg
|= HS_MODE_INTERRUPTS
;
1417 return RISCV_EXCP_NONE
;
1420 static RISCVException
rmw_mideleg(CPURISCVState
*env
, int csrno
,
1421 target_ulong
*ret_val
,
1422 target_ulong new_val
, target_ulong wr_mask
)
1427 ret
= rmw_mideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
1435 static RISCVException
rmw_midelegh(CPURISCVState
*env
, int csrno
,
1436 target_ulong
*ret_val
,
1437 target_ulong new_val
,
1438 target_ulong wr_mask
)
1443 ret
= rmw_mideleg64(env
, csrno
, &rval
,
1444 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1446 *ret_val
= rval
>> 32;
1452 static RISCVException
rmw_mie64(CPURISCVState
*env
, int csrno
,
1454 uint64_t new_val
, uint64_t wr_mask
)
1456 uint64_t mask
= wr_mask
& all_ints
;
1459 *ret_val
= env
->mie
;
1462 env
->mie
= (env
->mie
& ~mask
) | (new_val
& mask
);
1464 if (!riscv_has_ext(env
, RVH
)) {
1465 env
->mie
&= ~((uint64_t)MIP_SGEIP
);
1468 return RISCV_EXCP_NONE
;
1471 static RISCVException
rmw_mie(CPURISCVState
*env
, int csrno
,
1472 target_ulong
*ret_val
,
1473 target_ulong new_val
, target_ulong wr_mask
)
1478 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
);
1486 static RISCVException
rmw_mieh(CPURISCVState
*env
, int csrno
,
1487 target_ulong
*ret_val
,
1488 target_ulong new_val
, target_ulong wr_mask
)
1493 ret
= rmw_mie64(env
, csrno
, &rval
,
1494 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1496 *ret_val
= rval
>> 32;
1502 static int read_mtopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1507 irq
= riscv_cpu_mirq_pending(env
);
1508 if (irq
<= 0 || irq
> 63) {
1511 iprio
= env
->miprio
[irq
];
1513 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_M
) {
1514 iprio
= IPRIO_MMAXIPRIO
;
1517 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
1521 return RISCV_EXCP_NONE
;
1524 static int aia_xlate_vs_csrno(CPURISCVState
*env
, int csrno
)
1526 if (!riscv_cpu_virt_enabled(env
)) {
1532 return CSR_VSISELECT
;
1542 static int rmw_xiselect(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1543 target_ulong new_val
, target_ulong wr_mask
)
1545 target_ulong
*iselect
;
1547 /* Translate CSR number for VS-mode */
1548 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1550 /* Find the iselect CSR based on CSR number */
1553 iselect
= &env
->miselect
;
1556 iselect
= &env
->siselect
;
1559 iselect
= &env
->vsiselect
;
1562 return RISCV_EXCP_ILLEGAL_INST
;
1569 wr_mask
&= ISELECT_MASK
;
1571 *iselect
= (*iselect
& ~wr_mask
) | (new_val
& wr_mask
);
1574 return RISCV_EXCP_NONE
;
1577 static int rmw_iprio(target_ulong xlen
,
1578 target_ulong iselect
, uint8_t *iprio
,
1579 target_ulong
*val
, target_ulong new_val
,
1580 target_ulong wr_mask
, int ext_irq_no
)
1583 target_ulong old_val
;
1585 if (iselect
< ISELECT_IPRIO0
|| ISELECT_IPRIO15
< iselect
) {
1588 if (xlen
!= 32 && iselect
& 0x1) {
1592 nirqs
= 4 * (xlen
/ 32);
1593 firq
= ((iselect
- ISELECT_IPRIO0
) / (xlen
/ 32)) * (nirqs
);
1596 for (i
= 0; i
< nirqs
; i
++) {
1597 old_val
|= ((target_ulong
)iprio
[firq
+ i
]) << (IPRIO_IRQ_BITS
* i
);
1605 new_val
= (old_val
& ~wr_mask
) | (new_val
& wr_mask
);
1606 for (i
= 0; i
< nirqs
; i
++) {
1608 * M-level and S-level external IRQ priority always read-only
1609 * zero. This means default priority order is always preferred
1610 * for M-level and S-level external IRQs.
1612 if ((firq
+ i
) == ext_irq_no
) {
1615 iprio
[firq
+ i
] = (new_val
>> (IPRIO_IRQ_BITS
* i
)) & 0xff;
1622 static int rmw_xireg(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1623 target_ulong new_val
, target_ulong wr_mask
)
1628 target_ulong priv
, isel
, vgein
;
1630 /* Translate CSR number for VS-mode */
1631 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1633 /* Decode register details from CSR number */
1637 iprio
= env
->miprio
;
1638 isel
= env
->miselect
;
1642 iprio
= env
->siprio
;
1643 isel
= env
->siselect
;
1647 iprio
= env
->hviprio
;
1648 isel
= env
->vsiselect
;
1656 /* Find the selected guest interrupt file */
1657 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1659 if (ISELECT_IPRIO0
<= isel
&& isel
<= ISELECT_IPRIO15
) {
1660 /* Local interrupt priority registers not available for VS-mode */
1662 ret
= rmw_iprio(riscv_cpu_mxl_bits(env
),
1663 isel
, iprio
, val
, new_val
, wr_mask
,
1664 (priv
== PRV_M
) ? IRQ_M_EXT
: IRQ_S_EXT
);
1666 } else if (ISELECT_IMSIC_FIRST
<= isel
&& isel
<= ISELECT_IMSIC_LAST
) {
1667 /* IMSIC registers only available when machine implements it. */
1668 if (env
->aia_ireg_rmw_fn
[priv
]) {
1669 /* Selected guest interrupt file should not be zero */
1670 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1673 /* Call machine specific IMSIC register emulation */
1674 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1675 AIA_MAKE_IREG(isel
, priv
, virt
, vgein
,
1676 riscv_cpu_mxl_bits(env
)),
1677 val
, new_val
, wr_mask
);
1683 return (riscv_cpu_virt_enabled(env
) && virt
) ?
1684 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1686 return RISCV_EXCP_NONE
;
1689 static int rmw_xtopei(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1690 target_ulong new_val
, target_ulong wr_mask
)
1694 target_ulong priv
, vgein
;
1696 /* Translate CSR number for VS-mode */
1697 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1699 /* Decode register details from CSR number */
1716 /* IMSIC CSRs only available when machine implements IMSIC. */
1717 if (!env
->aia_ireg_rmw_fn
[priv
]) {
1721 /* Find the selected guest interrupt file */
1722 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1724 /* Selected guest interrupt file should be valid */
1725 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1729 /* Call machine specific IMSIC register emulation for TOPEI */
1730 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1731 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, priv
, virt
, vgein
,
1732 riscv_cpu_mxl_bits(env
)),
1733 val
, new_val
, wr_mask
);
1737 return (riscv_cpu_virt_enabled(env
) && virt
) ?
1738 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1740 return RISCV_EXCP_NONE
;
1743 static RISCVException
read_mtvec(CPURISCVState
*env
, int csrno
,
1747 return RISCV_EXCP_NONE
;
1750 static RISCVException
write_mtvec(CPURISCVState
*env
, int csrno
,
1753 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1754 if ((val
& 3) < 2) {
1757 qemu_log_mask(LOG_UNIMP
, "CSR_MTVEC: reserved mode not supported\n");
1759 return RISCV_EXCP_NONE
;
1762 static RISCVException
read_mcountinhibit(CPURISCVState
*env
, int csrno
,
1765 *val
= env
->mcountinhibit
;
1766 return RISCV_EXCP_NONE
;
1769 static RISCVException
write_mcountinhibit(CPURISCVState
*env
, int csrno
,
1773 PMUCTRState
*counter
;
1775 env
->mcountinhibit
= val
;
1777 /* Check if any other counter is also monitoring cycles/instructions */
1778 for (cidx
= 0; cidx
< RV_MAX_MHPMCOUNTERS
; cidx
++) {
1779 if (!get_field(env
->mcountinhibit
, BIT(cidx
))) {
1780 counter
= &env
->pmu_ctrs
[cidx
];
1781 counter
->started
= true;
1785 return RISCV_EXCP_NONE
;
1788 static RISCVException
read_mcounteren(CPURISCVState
*env
, int csrno
,
1791 *val
= env
->mcounteren
;
1792 return RISCV_EXCP_NONE
;
1795 static RISCVException
write_mcounteren(CPURISCVState
*env
, int csrno
,
1798 env
->mcounteren
= val
;
1799 return RISCV_EXCP_NONE
;
1802 /* Machine Trap Handling */
1803 static RISCVException
read_mscratch_i128(CPURISCVState
*env
, int csrno
,
1806 *val
= int128_make128(env
->mscratch
, env
->mscratchh
);
1807 return RISCV_EXCP_NONE
;
1810 static RISCVException
write_mscratch_i128(CPURISCVState
*env
, int csrno
,
1813 env
->mscratch
= int128_getlo(val
);
1814 env
->mscratchh
= int128_gethi(val
);
1815 return RISCV_EXCP_NONE
;
1818 static RISCVException
read_mscratch(CPURISCVState
*env
, int csrno
,
1821 *val
= env
->mscratch
;
1822 return RISCV_EXCP_NONE
;
1825 static RISCVException
write_mscratch(CPURISCVState
*env
, int csrno
,
1828 env
->mscratch
= val
;
1829 return RISCV_EXCP_NONE
;
1832 static RISCVException
read_mepc(CPURISCVState
*env
, int csrno
,
1836 return RISCV_EXCP_NONE
;
1839 static RISCVException
write_mepc(CPURISCVState
*env
, int csrno
,
1843 return RISCV_EXCP_NONE
;
1846 static RISCVException
read_mcause(CPURISCVState
*env
, int csrno
,
1850 return RISCV_EXCP_NONE
;
1853 static RISCVException
write_mcause(CPURISCVState
*env
, int csrno
,
1857 return RISCV_EXCP_NONE
;
1860 static RISCVException
read_mtval(CPURISCVState
*env
, int csrno
,
1864 return RISCV_EXCP_NONE
;
1867 static RISCVException
write_mtval(CPURISCVState
*env
, int csrno
,
1871 return RISCV_EXCP_NONE
;
1874 /* Execution environment configuration setup */
1875 static RISCVException
read_menvcfg(CPURISCVState
*env
, int csrno
,
1878 *val
= env
->menvcfg
;
1879 return RISCV_EXCP_NONE
;
1882 static RISCVException
write_menvcfg(CPURISCVState
*env
, int csrno
,
1885 uint64_t mask
= MENVCFG_FIOM
| MENVCFG_CBIE
| MENVCFG_CBCFE
| MENVCFG_CBZE
;
1887 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
1888 mask
|= MENVCFG_PBMTE
| MENVCFG_STCE
;
1890 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (val
& mask
);
1892 return RISCV_EXCP_NONE
;
1895 static RISCVException
read_menvcfgh(CPURISCVState
*env
, int csrno
,
1898 *val
= env
->menvcfg
>> 32;
1899 return RISCV_EXCP_NONE
;
1902 static RISCVException
write_menvcfgh(CPURISCVState
*env
, int csrno
,
1905 uint64_t mask
= MENVCFG_PBMTE
| MENVCFG_STCE
;
1906 uint64_t valh
= (uint64_t)val
<< 32;
1908 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (valh
& mask
);
1910 return RISCV_EXCP_NONE
;
1913 static RISCVException
read_senvcfg(CPURISCVState
*env
, int csrno
,
1918 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1919 if (ret
!= RISCV_EXCP_NONE
) {
1923 *val
= env
->senvcfg
;
1924 return RISCV_EXCP_NONE
;
1927 static RISCVException
write_senvcfg(CPURISCVState
*env
, int csrno
,
1930 uint64_t mask
= SENVCFG_FIOM
| SENVCFG_CBIE
| SENVCFG_CBCFE
| SENVCFG_CBZE
;
1933 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1934 if (ret
!= RISCV_EXCP_NONE
) {
1938 env
->senvcfg
= (env
->senvcfg
& ~mask
) | (val
& mask
);
1939 return RISCV_EXCP_NONE
;
1942 static RISCVException
read_henvcfg(CPURISCVState
*env
, int csrno
,
1947 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1948 if (ret
!= RISCV_EXCP_NONE
) {
1952 *val
= env
->henvcfg
;
1953 return RISCV_EXCP_NONE
;
1956 static RISCVException
write_henvcfg(CPURISCVState
*env
, int csrno
,
1959 uint64_t mask
= HENVCFG_FIOM
| HENVCFG_CBIE
| HENVCFG_CBCFE
| HENVCFG_CBZE
;
1962 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1963 if (ret
!= RISCV_EXCP_NONE
) {
1967 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
1968 mask
|= HENVCFG_PBMTE
| HENVCFG_STCE
;
1971 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (val
& mask
);
1973 return RISCV_EXCP_NONE
;
1976 static RISCVException
read_henvcfgh(CPURISCVState
*env
, int csrno
,
1981 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1982 if (ret
!= RISCV_EXCP_NONE
) {
1986 *val
= env
->henvcfg
>> 32;
1987 return RISCV_EXCP_NONE
;
1990 static RISCVException
write_henvcfgh(CPURISCVState
*env
, int csrno
,
1993 uint64_t mask
= HENVCFG_PBMTE
| HENVCFG_STCE
;
1994 uint64_t valh
= (uint64_t)val
<< 32;
1997 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1998 if (ret
!= RISCV_EXCP_NONE
) {
2002 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (valh
& mask
);
2003 return RISCV_EXCP_NONE
;
2006 static RISCVException
read_mstateen(CPURISCVState
*env
, int csrno
,
2009 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2011 return RISCV_EXCP_NONE
;
2014 static RISCVException
write_mstateen(CPURISCVState
*env
, int csrno
,
2015 uint64_t wr_mask
, target_ulong new_val
)
2019 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2020 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2022 return RISCV_EXCP_NONE
;
2025 static RISCVException
write_mstateen0(CPURISCVState
*env
, int csrno
,
2026 target_ulong new_val
)
2028 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2030 return write_mstateen(env
, csrno
, wr_mask
, new_val
);
2033 static RISCVException
write_mstateen_1_3(CPURISCVState
*env
, int csrno
,
2034 target_ulong new_val
)
2036 return write_mstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2039 static RISCVException
read_mstateenh(CPURISCVState
*env
, int csrno
,
2042 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0H
] >> 32;
2044 return RISCV_EXCP_NONE
;
2047 static RISCVException
write_mstateenh(CPURISCVState
*env
, int csrno
,
2048 uint64_t wr_mask
, target_ulong new_val
)
2052 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0H
];
2053 val
= (uint64_t)new_val
<< 32;
2054 val
|= *reg
& 0xFFFFFFFF;
2055 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2057 return RISCV_EXCP_NONE
;
2060 static RISCVException
write_mstateen0h(CPURISCVState
*env
, int csrno
,
2061 target_ulong new_val
)
2063 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2065 return write_mstateenh(env
, csrno
, wr_mask
, new_val
);
2068 static RISCVException
write_mstateenh_1_3(CPURISCVState
*env
, int csrno
,
2069 target_ulong new_val
)
2071 return write_mstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2074 static RISCVException
read_hstateen(CPURISCVState
*env
, int csrno
,
2077 int index
= csrno
- CSR_HSTATEEN0
;
2079 *val
= env
->hstateen
[index
] & env
->mstateen
[index
];
2081 return RISCV_EXCP_NONE
;
2084 static RISCVException
write_hstateen(CPURISCVState
*env
, int csrno
,
2085 uint64_t mask
, target_ulong new_val
)
2087 int index
= csrno
- CSR_HSTATEEN0
;
2088 uint64_t *reg
, wr_mask
;
2090 reg
= &env
->hstateen
[index
];
2091 wr_mask
= env
->mstateen
[index
] & mask
;
2092 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2094 return RISCV_EXCP_NONE
;
2097 static RISCVException
write_hstateen0(CPURISCVState
*env
, int csrno
,
2098 target_ulong new_val
)
2100 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2102 return write_hstateen(env
, csrno
, wr_mask
, new_val
);
2105 static RISCVException
write_hstateen_1_3(CPURISCVState
*env
, int csrno
,
2106 target_ulong new_val
)
2108 return write_hstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2111 static RISCVException
read_hstateenh(CPURISCVState
*env
, int csrno
,
2114 int index
= csrno
- CSR_HSTATEEN0H
;
2116 *val
= (env
->hstateen
[index
] >> 32) & (env
->mstateen
[index
] >> 32);
2118 return RISCV_EXCP_NONE
;
2121 static RISCVException
write_hstateenh(CPURISCVState
*env
, int csrno
,
2122 uint64_t mask
, target_ulong new_val
)
2124 int index
= csrno
- CSR_HSTATEEN0H
;
2125 uint64_t *reg
, wr_mask
, val
;
2127 reg
= &env
->hstateen
[index
];
2128 val
= (uint64_t)new_val
<< 32;
2129 val
|= *reg
& 0xFFFFFFFF;
2130 wr_mask
= env
->mstateen
[index
] & mask
;
2131 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2133 return RISCV_EXCP_NONE
;
2136 static RISCVException
write_hstateen0h(CPURISCVState
*env
, int csrno
,
2137 target_ulong new_val
)
2139 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2141 return write_hstateenh(env
, csrno
, wr_mask
, new_val
);
2144 static RISCVException
write_hstateenh_1_3(CPURISCVState
*env
, int csrno
,
2145 target_ulong new_val
)
2147 return write_hstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2150 static RISCVException
read_sstateen(CPURISCVState
*env
, int csrno
,
2153 bool virt
= riscv_cpu_virt_enabled(env
);
2154 int index
= csrno
- CSR_SSTATEEN0
;
2156 *val
= env
->sstateen
[index
] & env
->mstateen
[index
];
2158 *val
&= env
->hstateen
[index
];
2161 return RISCV_EXCP_NONE
;
2164 static RISCVException
write_sstateen(CPURISCVState
*env
, int csrno
,
2165 uint64_t mask
, target_ulong new_val
)
2167 bool virt
= riscv_cpu_virt_enabled(env
);
2168 int index
= csrno
- CSR_SSTATEEN0
;
2172 wr_mask
= env
->mstateen
[index
] & mask
;
2174 wr_mask
&= env
->hstateen
[index
];
2177 reg
= &env
->sstateen
[index
];
2178 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2180 return RISCV_EXCP_NONE
;
2183 static RISCVException
write_sstateen0(CPURISCVState
*env
, int csrno
,
2184 target_ulong new_val
)
2186 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2188 return write_sstateen(env
, csrno
, wr_mask
, new_val
);
2191 static RISCVException
write_sstateen_1_3(CPURISCVState
*env
, int csrno
,
2192 target_ulong new_val
)
2194 return write_sstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2197 static RISCVException
rmw_mip64(CPURISCVState
*env
, int csrno
,
2199 uint64_t new_val
, uint64_t wr_mask
)
2201 RISCVCPU
*cpu
= env_archcpu(env
);
2202 uint64_t old_mip
, mask
= wr_mask
& delegable_ints
;
2205 if (mask
& MIP_SEIP
) {
2206 env
->software_seip
= new_val
& MIP_SEIP
;
2207 new_val
|= env
->external_seip
* MIP_SEIP
;
2210 if (cpu
->cfg
.ext_sstc
&& (env
->priv
== PRV_M
) &&
2211 get_field(env
->menvcfg
, MENVCFG_STCE
)) {
2212 /* sstc extension forbids STIP & VSTIP to be writeable in mip */
2213 mask
= mask
& ~(MIP_STIP
| MIP_VSTIP
);
2217 old_mip
= riscv_cpu_update_mip(cpu
, mask
, (new_val
& mask
));
2222 if (csrno
!= CSR_HVIP
) {
2223 gin
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
2224 old_mip
|= (env
->hgeip
& ((target_ulong
)1 << gin
)) ? MIP_VSEIP
: 0;
2225 old_mip
|= env
->vstime_irq
? MIP_VSTIP
: 0;
2232 return RISCV_EXCP_NONE
;
2235 static RISCVException
rmw_mip(CPURISCVState
*env
, int csrno
,
2236 target_ulong
*ret_val
,
2237 target_ulong new_val
, target_ulong wr_mask
)
2242 ret
= rmw_mip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2250 static RISCVException
rmw_miph(CPURISCVState
*env
, int csrno
,
2251 target_ulong
*ret_val
,
2252 target_ulong new_val
, target_ulong wr_mask
)
2257 ret
= rmw_mip64(env
, csrno
, &rval
,
2258 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2260 *ret_val
= rval
>> 32;
2266 /* Supervisor Trap Setup */
2267 static RISCVException
read_sstatus_i128(CPURISCVState
*env
, int csrno
,
2270 uint64_t mask
= sstatus_v1_10_mask
;
2271 uint64_t sstatus
= env
->mstatus
& mask
;
2272 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2273 mask
|= SSTATUS64_UXL
;
2276 *val
= int128_make128(sstatus
, add_status_sd(MXL_RV128
, sstatus
));
2277 return RISCV_EXCP_NONE
;
2280 static RISCVException
read_sstatus(CPURISCVState
*env
, int csrno
,
2283 target_ulong mask
= (sstatus_v1_10_mask
);
2284 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2285 mask
|= SSTATUS64_UXL
;
2287 /* TODO: Use SXL not MXL. */
2288 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
& mask
);
2289 return RISCV_EXCP_NONE
;
2292 static RISCVException
write_sstatus(CPURISCVState
*env
, int csrno
,
2295 target_ulong mask
= (sstatus_v1_10_mask
);
2297 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2298 if ((val
& SSTATUS64_UXL
) != 0) {
2299 mask
|= SSTATUS64_UXL
;
2302 target_ulong newval
= (env
->mstatus
& ~mask
) | (val
& mask
);
2303 return write_mstatus(env
, CSR_MSTATUS
, newval
);
2306 static RISCVException
rmw_vsie64(CPURISCVState
*env
, int csrno
,
2308 uint64_t new_val
, uint64_t wr_mask
)
2311 uint64_t rval
, mask
= env
->hideleg
& VS_MODE_INTERRUPTS
;
2313 /* Bring VS-level bits to correct position */
2314 new_val
= (new_val
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2315 wr_mask
= (wr_mask
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2317 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
& mask
);
2319 *ret_val
= (rval
& mask
) >> 1;
2325 static RISCVException
rmw_vsie(CPURISCVState
*env
, int csrno
,
2326 target_ulong
*ret_val
,
2327 target_ulong new_val
, target_ulong wr_mask
)
2332 ret
= rmw_vsie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2340 static RISCVException
rmw_vsieh(CPURISCVState
*env
, int csrno
,
2341 target_ulong
*ret_val
,
2342 target_ulong new_val
, target_ulong wr_mask
)
2347 ret
= rmw_vsie64(env
, csrno
, &rval
,
2348 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2350 *ret_val
= rval
>> 32;
2356 static RISCVException
rmw_sie64(CPURISCVState
*env
, int csrno
,
2358 uint64_t new_val
, uint64_t wr_mask
)
2361 uint64_t mask
= env
->mideleg
& S_MODE_INTERRUPTS
;
2363 if (riscv_cpu_virt_enabled(env
)) {
2364 if (env
->hvictl
& HVICTL_VTI
) {
2365 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2367 ret
= rmw_vsie64(env
, CSR_VSIE
, ret_val
, new_val
, wr_mask
);
2369 ret
= rmw_mie64(env
, csrno
, ret_val
, new_val
, wr_mask
& mask
);
2379 static RISCVException
rmw_sie(CPURISCVState
*env
, int csrno
,
2380 target_ulong
*ret_val
,
2381 target_ulong new_val
, target_ulong wr_mask
)
2386 ret
= rmw_sie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2387 if (ret
== RISCV_EXCP_NONE
&& ret_val
) {
2394 static RISCVException
rmw_sieh(CPURISCVState
*env
, int csrno
,
2395 target_ulong
*ret_val
,
2396 target_ulong new_val
, target_ulong wr_mask
)
2401 ret
= rmw_sie64(env
, csrno
, &rval
,
2402 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2404 *ret_val
= rval
>> 32;
2410 static RISCVException
read_stvec(CPURISCVState
*env
, int csrno
,
2414 return RISCV_EXCP_NONE
;
2417 static RISCVException
write_stvec(CPURISCVState
*env
, int csrno
,
2420 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
2421 if ((val
& 3) < 2) {
2424 qemu_log_mask(LOG_UNIMP
, "CSR_STVEC: reserved mode not supported\n");
2426 return RISCV_EXCP_NONE
;
2429 static RISCVException
read_scounteren(CPURISCVState
*env
, int csrno
,
2432 *val
= env
->scounteren
;
2433 return RISCV_EXCP_NONE
;
2436 static RISCVException
write_scounteren(CPURISCVState
*env
, int csrno
,
2439 env
->scounteren
= val
;
2440 return RISCV_EXCP_NONE
;
2443 /* Supervisor Trap Handling */
2444 static RISCVException
read_sscratch_i128(CPURISCVState
*env
, int csrno
,
2447 *val
= int128_make128(env
->sscratch
, env
->sscratchh
);
2448 return RISCV_EXCP_NONE
;
2451 static RISCVException
write_sscratch_i128(CPURISCVState
*env
, int csrno
,
2454 env
->sscratch
= int128_getlo(val
);
2455 env
->sscratchh
= int128_gethi(val
);
2456 return RISCV_EXCP_NONE
;
2459 static RISCVException
read_sscratch(CPURISCVState
*env
, int csrno
,
2462 *val
= env
->sscratch
;
2463 return RISCV_EXCP_NONE
;
2466 static RISCVException
write_sscratch(CPURISCVState
*env
, int csrno
,
2469 env
->sscratch
= val
;
2470 return RISCV_EXCP_NONE
;
2473 static RISCVException
read_sepc(CPURISCVState
*env
, int csrno
,
2477 return RISCV_EXCP_NONE
;
2480 static RISCVException
write_sepc(CPURISCVState
*env
, int csrno
,
2484 return RISCV_EXCP_NONE
;
2487 static RISCVException
read_scause(CPURISCVState
*env
, int csrno
,
2491 return RISCV_EXCP_NONE
;
2494 static RISCVException
write_scause(CPURISCVState
*env
, int csrno
,
2498 return RISCV_EXCP_NONE
;
2501 static RISCVException
read_stval(CPURISCVState
*env
, int csrno
,
2505 return RISCV_EXCP_NONE
;
2508 static RISCVException
write_stval(CPURISCVState
*env
, int csrno
,
2512 return RISCV_EXCP_NONE
;
2515 static RISCVException
rmw_vsip64(CPURISCVState
*env
, int csrno
,
2517 uint64_t new_val
, uint64_t wr_mask
)
2520 uint64_t rval
, mask
= env
->hideleg
& VS_MODE_INTERRUPTS
;
2522 /* Bring VS-level bits to correct position */
2523 new_val
= (new_val
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2524 wr_mask
= (wr_mask
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2526 ret
= rmw_mip64(env
, csrno
, &rval
, new_val
,
2527 wr_mask
& mask
& vsip_writable_mask
);
2529 *ret_val
= (rval
& mask
) >> 1;
2535 static RISCVException
rmw_vsip(CPURISCVState
*env
, int csrno
,
2536 target_ulong
*ret_val
,
2537 target_ulong new_val
, target_ulong wr_mask
)
2542 ret
= rmw_vsip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2550 static RISCVException
rmw_vsiph(CPURISCVState
*env
, int csrno
,
2551 target_ulong
*ret_val
,
2552 target_ulong new_val
, target_ulong wr_mask
)
2557 ret
= rmw_vsip64(env
, csrno
, &rval
,
2558 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2560 *ret_val
= rval
>> 32;
2566 static RISCVException
rmw_sip64(CPURISCVState
*env
, int csrno
,
2568 uint64_t new_val
, uint64_t wr_mask
)
2571 uint64_t mask
= env
->mideleg
& sip_writable_mask
;
2573 if (riscv_cpu_virt_enabled(env
)) {
2574 if (env
->hvictl
& HVICTL_VTI
) {
2575 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2577 ret
= rmw_vsip64(env
, CSR_VSIP
, ret_val
, new_val
, wr_mask
);
2579 ret
= rmw_mip64(env
, csrno
, ret_val
, new_val
, wr_mask
& mask
);
2583 *ret_val
&= env
->mideleg
& S_MODE_INTERRUPTS
;
2589 static RISCVException
rmw_sip(CPURISCVState
*env
, int csrno
,
2590 target_ulong
*ret_val
,
2591 target_ulong new_val
, target_ulong wr_mask
)
2596 ret
= rmw_sip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2604 static RISCVException
rmw_siph(CPURISCVState
*env
, int csrno
,
2605 target_ulong
*ret_val
,
2606 target_ulong new_val
, target_ulong wr_mask
)
2611 ret
= rmw_sip64(env
, csrno
, &rval
,
2612 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2614 *ret_val
= rval
>> 32;
2620 /* Supervisor Protection and Translation */
2621 static RISCVException
read_satp(CPURISCVState
*env
, int csrno
,
2624 if (!riscv_feature(env
, RISCV_FEATURE_MMU
)) {
2626 return RISCV_EXCP_NONE
;
2629 if (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_TVM
)) {
2630 return RISCV_EXCP_ILLEGAL_INST
;
2635 return RISCV_EXCP_NONE
;
2638 static RISCVException
write_satp(CPURISCVState
*env
, int csrno
,
2641 target_ulong vm
, mask
;
2643 if (!riscv_feature(env
, RISCV_FEATURE_MMU
)) {
2644 return RISCV_EXCP_NONE
;
2647 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
2648 vm
= validate_vm(env
, get_field(val
, SATP32_MODE
));
2649 mask
= (val
^ env
->satp
) & (SATP32_MODE
| SATP32_ASID
| SATP32_PPN
);
2651 vm
= validate_vm(env
, get_field(val
, SATP64_MODE
));
2652 mask
= (val
^ env
->satp
) & (SATP64_MODE
| SATP64_ASID
| SATP64_PPN
);
2656 if (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_TVM
)) {
2657 return RISCV_EXCP_ILLEGAL_INST
;
2660 * The ISA defines SATP.MODE=Bare as "no translation", but we still
2661 * pass these through QEMU's TLB emulation as it improves
2662 * performance. Flushing the TLB on SATP writes with paging
2663 * enabled avoids leaking those invalid cached mappings.
2665 tlb_flush(env_cpu(env
));
2669 return RISCV_EXCP_NONE
;
2672 static int read_vstopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
2676 uint64_t vseip
, vsgein
;
2677 uint32_t iid
, iprio
, hviid
, hviprio
, gein
;
2678 uint32_t s
, scount
= 0, siid
[VSTOPI_NUM_SRCS
], siprio
[VSTOPI_NUM_SRCS
];
2680 gein
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
2681 hviid
= get_field(env
->hvictl
, HVICTL_IID
);
2682 hviprio
= get_field(env
->hvictl
, HVICTL_IPRIO
);
2685 vsgein
= (env
->hgeip
& (1ULL << gein
)) ? MIP_VSEIP
: 0;
2686 vseip
= env
->mie
& (env
->mip
| vsgein
) & MIP_VSEIP
;
2687 if (gein
<= env
->geilen
&& vseip
) {
2688 siid
[scount
] = IRQ_S_EXT
;
2689 siprio
[scount
] = IPRIO_MMAXIPRIO
+ 1;
2690 if (env
->aia_ireg_rmw_fn
[PRV_S
]) {
2692 * Call machine specific IMSIC register emulation for
2695 ret
= env
->aia_ireg_rmw_fn
[PRV_S
](
2696 env
->aia_ireg_rmw_fn_arg
[PRV_S
],
2697 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, PRV_S
, true, gein
,
2698 riscv_cpu_mxl_bits(env
)),
2700 if (!ret
&& topei
) {
2701 siprio
[scount
] = topei
& IMSIC_TOPEI_IPRIO_MASK
;
2707 if (hviid
== IRQ_S_EXT
&& hviprio
) {
2708 siid
[scount
] = IRQ_S_EXT
;
2709 siprio
[scount
] = hviprio
;
2714 if (env
->hvictl
& HVICTL_VTI
) {
2715 if (hviid
!= IRQ_S_EXT
) {
2716 siid
[scount
] = hviid
;
2717 siprio
[scount
] = hviprio
;
2721 irq
= riscv_cpu_vsirq_pending(env
);
2722 if (irq
!= IRQ_S_EXT
&& 0 < irq
&& irq
<= 63) {
2724 siprio
[scount
] = env
->hviprio
[irq
];
2731 for (s
= 0; s
< scount
; s
++) {
2732 if (siprio
[s
] < iprio
) {
2739 if (env
->hvictl
& HVICTL_IPRIOM
) {
2740 if (iprio
> IPRIO_MMAXIPRIO
) {
2741 iprio
= IPRIO_MMAXIPRIO
;
2744 if (riscv_cpu_default_priority(iid
) > IPRIO_DEFAULT_S
) {
2745 iprio
= IPRIO_MMAXIPRIO
;
2755 *val
= (iid
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
2757 return RISCV_EXCP_NONE
;
2760 static int read_stopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
2765 if (riscv_cpu_virt_enabled(env
)) {
2766 return read_vstopi(env
, CSR_VSTOPI
, val
);
2769 irq
= riscv_cpu_sirq_pending(env
);
2770 if (irq
<= 0 || irq
> 63) {
2773 iprio
= env
->siprio
[irq
];
2775 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_S
) {
2776 iprio
= IPRIO_MMAXIPRIO
;
2779 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
2783 return RISCV_EXCP_NONE
;
2786 /* Hypervisor Extensions */
2787 static RISCVException
read_hstatus(CPURISCVState
*env
, int csrno
,
2790 *val
= env
->hstatus
;
2791 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
2792 /* We only support 64-bit VSXL */
2793 *val
= set_field(*val
, HSTATUS_VSXL
, 2);
2795 /* We only support little endian */
2796 *val
= set_field(*val
, HSTATUS_VSBE
, 0);
2797 return RISCV_EXCP_NONE
;
2800 static RISCVException
write_hstatus(CPURISCVState
*env
, int csrno
,
2804 if (riscv_cpu_mxl(env
) != MXL_RV32
&& get_field(val
, HSTATUS_VSXL
) != 2) {
2805 qemu_log_mask(LOG_UNIMP
, "QEMU does not support mixed HSXLEN options.");
2807 if (get_field(val
, HSTATUS_VSBE
) != 0) {
2808 qemu_log_mask(LOG_UNIMP
, "QEMU does not support big endian guests.");
2810 return RISCV_EXCP_NONE
;
2813 static RISCVException
read_hedeleg(CPURISCVState
*env
, int csrno
,
2816 *val
= env
->hedeleg
;
2817 return RISCV_EXCP_NONE
;
2820 static RISCVException
write_hedeleg(CPURISCVState
*env
, int csrno
,
2823 env
->hedeleg
= val
& vs_delegable_excps
;
2824 return RISCV_EXCP_NONE
;
2827 static RISCVException
rmw_hideleg64(CPURISCVState
*env
, int csrno
,
2829 uint64_t new_val
, uint64_t wr_mask
)
2831 uint64_t mask
= wr_mask
& vs_delegable_ints
;
2834 *ret_val
= env
->hideleg
& vs_delegable_ints
;
2837 env
->hideleg
= (env
->hideleg
& ~mask
) | (new_val
& mask
);
2838 return RISCV_EXCP_NONE
;
2841 static RISCVException
rmw_hideleg(CPURISCVState
*env
, int csrno
,
2842 target_ulong
*ret_val
,
2843 target_ulong new_val
, target_ulong wr_mask
)
2848 ret
= rmw_hideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
2856 static RISCVException
rmw_hidelegh(CPURISCVState
*env
, int csrno
,
2857 target_ulong
*ret_val
,
2858 target_ulong new_val
, target_ulong wr_mask
)
2863 ret
= rmw_hideleg64(env
, csrno
, &rval
,
2864 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2866 *ret_val
= rval
>> 32;
2872 static RISCVException
rmw_hvip64(CPURISCVState
*env
, int csrno
,
2874 uint64_t new_val
, uint64_t wr_mask
)
2878 ret
= rmw_mip64(env
, csrno
, ret_val
, new_val
,
2879 wr_mask
& hvip_writable_mask
);
2881 *ret_val
&= VS_MODE_INTERRUPTS
;
2887 static RISCVException
rmw_hvip(CPURISCVState
*env
, int csrno
,
2888 target_ulong
*ret_val
,
2889 target_ulong new_val
, target_ulong wr_mask
)
2894 ret
= rmw_hvip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2902 static RISCVException
rmw_hviph(CPURISCVState
*env
, int csrno
,
2903 target_ulong
*ret_val
,
2904 target_ulong new_val
, target_ulong wr_mask
)
2909 ret
= rmw_hvip64(env
, csrno
, &rval
,
2910 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2912 *ret_val
= rval
>> 32;
2918 static RISCVException
rmw_hip(CPURISCVState
*env
, int csrno
,
2919 target_ulong
*ret_value
,
2920 target_ulong new_value
, target_ulong write_mask
)
2922 int ret
= rmw_mip(env
, csrno
, ret_value
, new_value
,
2923 write_mask
& hip_writable_mask
);
2926 *ret_value
&= HS_MODE_INTERRUPTS
;
2931 static RISCVException
rmw_hie(CPURISCVState
*env
, int csrno
,
2932 target_ulong
*ret_val
,
2933 target_ulong new_val
, target_ulong wr_mask
)
2938 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
& HS_MODE_INTERRUPTS
);
2940 *ret_val
= rval
& HS_MODE_INTERRUPTS
;
2946 static RISCVException
read_hcounteren(CPURISCVState
*env
, int csrno
,
2949 *val
= env
->hcounteren
;
2950 return RISCV_EXCP_NONE
;
2953 static RISCVException
write_hcounteren(CPURISCVState
*env
, int csrno
,
2956 env
->hcounteren
= val
;
2957 return RISCV_EXCP_NONE
;
2960 static RISCVException
read_hgeie(CPURISCVState
*env
, int csrno
,
2966 return RISCV_EXCP_NONE
;
2969 static RISCVException
write_hgeie(CPURISCVState
*env
, int csrno
,
2972 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
2973 val
&= ((((target_ulong
)1) << env
->geilen
) - 1) << 1;
2975 /* Update mip.SGEIP bit */
2976 riscv_cpu_update_mip(env_archcpu(env
), MIP_SGEIP
,
2977 BOOL_TO_MASK(!!(env
->hgeie
& env
->hgeip
)));
2978 return RISCV_EXCP_NONE
;
2981 static RISCVException
read_htval(CPURISCVState
*env
, int csrno
,
2985 return RISCV_EXCP_NONE
;
2988 static RISCVException
write_htval(CPURISCVState
*env
, int csrno
,
2992 return RISCV_EXCP_NONE
;
2995 static RISCVException
read_htinst(CPURISCVState
*env
, int csrno
,
2999 return RISCV_EXCP_NONE
;
3002 static RISCVException
write_htinst(CPURISCVState
*env
, int csrno
,
3005 return RISCV_EXCP_NONE
;
3008 static RISCVException
read_hgeip(CPURISCVState
*env
, int csrno
,
3014 return RISCV_EXCP_NONE
;
3017 static RISCVException
read_hgatp(CPURISCVState
*env
, int csrno
,
3021 return RISCV_EXCP_NONE
;
3024 static RISCVException
write_hgatp(CPURISCVState
*env
, int csrno
,
3028 return RISCV_EXCP_NONE
;
3031 static RISCVException
read_htimedelta(CPURISCVState
*env
, int csrno
,
3034 if (!env
->rdtime_fn
) {
3035 return RISCV_EXCP_ILLEGAL_INST
;
3038 *val
= env
->htimedelta
;
3039 return RISCV_EXCP_NONE
;
3042 static RISCVException
write_htimedelta(CPURISCVState
*env
, int csrno
,
3045 RISCVCPU
*cpu
= env_archcpu(env
);
3047 if (!env
->rdtime_fn
) {
3048 return RISCV_EXCP_ILLEGAL_INST
;
3051 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
3052 env
->htimedelta
= deposit64(env
->htimedelta
, 0, 32, (uint64_t)val
);
3054 env
->htimedelta
= val
;
3057 if (cpu
->cfg
.ext_sstc
&& env
->rdtime_fn
) {
3058 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
3059 env
->htimedelta
, MIP_VSTIP
);
3062 return RISCV_EXCP_NONE
;
3065 static RISCVException
read_htimedeltah(CPURISCVState
*env
, int csrno
,
3068 if (!env
->rdtime_fn
) {
3069 return RISCV_EXCP_ILLEGAL_INST
;
3072 *val
= env
->htimedelta
>> 32;
3073 return RISCV_EXCP_NONE
;
3076 static RISCVException
write_htimedeltah(CPURISCVState
*env
, int csrno
,
3079 RISCVCPU
*cpu
= env_archcpu(env
);
3081 if (!env
->rdtime_fn
) {
3082 return RISCV_EXCP_ILLEGAL_INST
;
3085 env
->htimedelta
= deposit64(env
->htimedelta
, 32, 32, (uint64_t)val
);
3087 if (cpu
->cfg
.ext_sstc
&& env
->rdtime_fn
) {
3088 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
3089 env
->htimedelta
, MIP_VSTIP
);
3092 return RISCV_EXCP_NONE
;
3095 static int read_hvictl(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3098 return RISCV_EXCP_NONE
;
3101 static int write_hvictl(CPURISCVState
*env
, int csrno
, target_ulong val
)
3103 env
->hvictl
= val
& HVICTL_VALID_MASK
;
3104 return RISCV_EXCP_NONE
;
3107 static int read_hvipriox(CPURISCVState
*env
, int first_index
,
3108 uint8_t *iprio
, target_ulong
*val
)
3110 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3112 /* First index has to be a multiple of number of irqs per register */
3113 if (first_index
% num_irqs
) {
3114 return (riscv_cpu_virt_enabled(env
)) ?
3115 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3118 /* Fill-up return value */
3120 for (i
= 0; i
< num_irqs
; i
++) {
3121 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3127 *val
|= ((target_ulong
)iprio
[irq
]) << (i
* 8);
3130 return RISCV_EXCP_NONE
;
3133 static int write_hvipriox(CPURISCVState
*env
, int first_index
,
3134 uint8_t *iprio
, target_ulong val
)
3136 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3138 /* First index has to be a multiple of number of irqs per register */
3139 if (first_index
% num_irqs
) {
3140 return (riscv_cpu_virt_enabled(env
)) ?
3141 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3144 /* Fill-up priority arrary */
3145 for (i
= 0; i
< num_irqs
; i
++) {
3146 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3152 iprio
[irq
] = (val
>> (i
* 8)) & 0xff;
3156 return RISCV_EXCP_NONE
;
3159 static int read_hviprio1(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3161 return read_hvipriox(env
, 0, env
->hviprio
, val
);
3164 static int write_hviprio1(CPURISCVState
*env
, int csrno
, target_ulong val
)
3166 return write_hvipriox(env
, 0, env
->hviprio
, val
);
3169 static int read_hviprio1h(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3171 return read_hvipriox(env
, 4, env
->hviprio
, val
);
3174 static int write_hviprio1h(CPURISCVState
*env
, int csrno
, target_ulong val
)
3176 return write_hvipriox(env
, 4, env
->hviprio
, val
);
3179 static int read_hviprio2(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3181 return read_hvipriox(env
, 8, env
->hviprio
, val
);
3184 static int write_hviprio2(CPURISCVState
*env
, int csrno
, target_ulong val
)
3186 return write_hvipriox(env
, 8, env
->hviprio
, val
);
3189 static int read_hviprio2h(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3191 return read_hvipriox(env
, 12, env
->hviprio
, val
);
3194 static int write_hviprio2h(CPURISCVState
*env
, int csrno
, target_ulong val
)
3196 return write_hvipriox(env
, 12, env
->hviprio
, val
);
3199 /* Virtual CSR Registers */
3200 static RISCVException
read_vsstatus(CPURISCVState
*env
, int csrno
,
3203 *val
= env
->vsstatus
;
3204 return RISCV_EXCP_NONE
;
3207 static RISCVException
write_vsstatus(CPURISCVState
*env
, int csrno
,
3210 uint64_t mask
= (target_ulong
)-1;
3211 if ((val
& VSSTATUS64_UXL
) == 0) {
3212 mask
&= ~VSSTATUS64_UXL
;
3214 env
->vsstatus
= (env
->vsstatus
& ~mask
) | (uint64_t)val
;
3215 return RISCV_EXCP_NONE
;
3218 static int read_vstvec(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3221 return RISCV_EXCP_NONE
;
3224 static RISCVException
write_vstvec(CPURISCVState
*env
, int csrno
,
3228 return RISCV_EXCP_NONE
;
3231 static RISCVException
read_vsscratch(CPURISCVState
*env
, int csrno
,
3234 *val
= env
->vsscratch
;
3235 return RISCV_EXCP_NONE
;
3238 static RISCVException
write_vsscratch(CPURISCVState
*env
, int csrno
,
3241 env
->vsscratch
= val
;
3242 return RISCV_EXCP_NONE
;
3245 static RISCVException
read_vsepc(CPURISCVState
*env
, int csrno
,
3249 return RISCV_EXCP_NONE
;
3252 static RISCVException
write_vsepc(CPURISCVState
*env
, int csrno
,
3256 return RISCV_EXCP_NONE
;
3259 static RISCVException
read_vscause(CPURISCVState
*env
, int csrno
,
3262 *val
= env
->vscause
;
3263 return RISCV_EXCP_NONE
;
3266 static RISCVException
write_vscause(CPURISCVState
*env
, int csrno
,
3270 return RISCV_EXCP_NONE
;
3273 static RISCVException
read_vstval(CPURISCVState
*env
, int csrno
,
3277 return RISCV_EXCP_NONE
;
3280 static RISCVException
write_vstval(CPURISCVState
*env
, int csrno
,
3284 return RISCV_EXCP_NONE
;
3287 static RISCVException
read_vsatp(CPURISCVState
*env
, int csrno
,
3291 return RISCV_EXCP_NONE
;
3294 static RISCVException
write_vsatp(CPURISCVState
*env
, int csrno
,
3298 return RISCV_EXCP_NONE
;
3301 static RISCVException
read_mtval2(CPURISCVState
*env
, int csrno
,
3305 return RISCV_EXCP_NONE
;
3308 static RISCVException
write_mtval2(CPURISCVState
*env
, int csrno
,
3312 return RISCV_EXCP_NONE
;
3315 static RISCVException
read_mtinst(CPURISCVState
*env
, int csrno
,
3319 return RISCV_EXCP_NONE
;
3322 static RISCVException
write_mtinst(CPURISCVState
*env
, int csrno
,
3326 return RISCV_EXCP_NONE
;
3329 /* Physical Memory Protection */
3330 static RISCVException
read_mseccfg(CPURISCVState
*env
, int csrno
,
3333 *val
= mseccfg_csr_read(env
);
3334 return RISCV_EXCP_NONE
;
3337 static RISCVException
write_mseccfg(CPURISCVState
*env
, int csrno
,
3340 mseccfg_csr_write(env
, val
);
3341 return RISCV_EXCP_NONE
;
3344 static bool check_pmp_reg_index(CPURISCVState
*env
, uint32_t reg_index
)
3346 /* TODO: RV128 restriction check */
3347 if ((reg_index
& 1) && (riscv_cpu_mxl(env
) == MXL_RV64
)) {
3353 static RISCVException
read_pmpcfg(CPURISCVState
*env
, int csrno
,
3356 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3358 if (!check_pmp_reg_index(env
, reg_index
)) {
3359 return RISCV_EXCP_ILLEGAL_INST
;
3361 *val
= pmpcfg_csr_read(env
, csrno
- CSR_PMPCFG0
);
3362 return RISCV_EXCP_NONE
;
3365 static RISCVException
write_pmpcfg(CPURISCVState
*env
, int csrno
,
3368 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3370 if (!check_pmp_reg_index(env
, reg_index
)) {
3371 return RISCV_EXCP_ILLEGAL_INST
;
3373 pmpcfg_csr_write(env
, csrno
- CSR_PMPCFG0
, val
);
3374 return RISCV_EXCP_NONE
;
3377 static RISCVException
read_pmpaddr(CPURISCVState
*env
, int csrno
,
3380 *val
= pmpaddr_csr_read(env
, csrno
- CSR_PMPADDR0
);
3381 return RISCV_EXCP_NONE
;
3384 static RISCVException
write_pmpaddr(CPURISCVState
*env
, int csrno
,
3387 pmpaddr_csr_write(env
, csrno
- CSR_PMPADDR0
, val
);
3388 return RISCV_EXCP_NONE
;
3391 static RISCVException
read_tselect(CPURISCVState
*env
, int csrno
,
3394 *val
= tselect_csr_read(env
);
3395 return RISCV_EXCP_NONE
;
3398 static RISCVException
write_tselect(CPURISCVState
*env
, int csrno
,
3401 tselect_csr_write(env
, val
);
3402 return RISCV_EXCP_NONE
;
3405 static RISCVException
read_tdata(CPURISCVState
*env
, int csrno
,
3408 /* return 0 in tdata1 to end the trigger enumeration */
3409 if (env
->trigger_cur
>= RV_MAX_TRIGGERS
&& csrno
== CSR_TDATA1
) {
3411 return RISCV_EXCP_NONE
;
3414 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3415 return RISCV_EXCP_ILLEGAL_INST
;
3418 *val
= tdata_csr_read(env
, csrno
- CSR_TDATA1
);
3419 return RISCV_EXCP_NONE
;
3422 static RISCVException
write_tdata(CPURISCVState
*env
, int csrno
,
3425 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3426 return RISCV_EXCP_ILLEGAL_INST
;
3429 tdata_csr_write(env
, csrno
- CSR_TDATA1
, val
);
3430 return RISCV_EXCP_NONE
;
3433 static RISCVException
read_tinfo(CPURISCVState
*env
, int csrno
,
3436 *val
= tinfo_csr_read(env
);
3437 return RISCV_EXCP_NONE
;
3441 * Functions to access Pointer Masking feature registers
3442 * We have to check if current priv lvl could modify
3445 static bool check_pm_current_disabled(CPURISCVState
*env
, int csrno
)
3447 int csr_priv
= get_field(csrno
, 0x300);
3450 if (env
->debugger
) {
3454 * If priv lvls differ that means we're accessing csr from higher priv lvl,
3455 * so allow the access
3457 if (env
->priv
!= csr_priv
) {
3460 switch (env
->priv
) {
3462 pm_current
= get_field(env
->mmte
, M_PM_CURRENT
);
3465 pm_current
= get_field(env
->mmte
, S_PM_CURRENT
);
3468 pm_current
= get_field(env
->mmte
, U_PM_CURRENT
);
3471 g_assert_not_reached();
3473 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
3477 static RISCVException
read_mmte(CPURISCVState
*env
, int csrno
,
3480 *val
= env
->mmte
& MMTE_MASK
;
3481 return RISCV_EXCP_NONE
;
3484 static RISCVException
write_mmte(CPURISCVState
*env
, int csrno
,
3488 target_ulong wpri_val
= val
& MMTE_MASK
;
3490 if (val
!= wpri_val
) {
3491 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s" TARGET_FMT_lx
"\n",
3492 "MMTE: WPRI violation written 0x", val
,
3493 "vs expected 0x", wpri_val
);
3495 /* for machine mode pm.current is hardwired to 1 */
3496 wpri_val
|= MMTE_M_PM_CURRENT
;
3498 /* hardwiring pm.instruction bit to 0, since it's not supported yet */
3499 wpri_val
&= ~(MMTE_M_PM_INSN
| MMTE_S_PM_INSN
| MMTE_U_PM_INSN
);
3500 env
->mmte
= wpri_val
| PM_EXT_DIRTY
;
3501 riscv_cpu_update_mask(env
);
3503 /* Set XS and SD bits, since PM CSRs are dirty */
3504 mstatus
= env
->mstatus
| MSTATUS_XS
;
3505 write_mstatus(env
, csrno
, mstatus
);
3506 return RISCV_EXCP_NONE
;
3509 static RISCVException
read_smte(CPURISCVState
*env
, int csrno
,
3512 *val
= env
->mmte
& SMTE_MASK
;
3513 return RISCV_EXCP_NONE
;
3516 static RISCVException
write_smte(CPURISCVState
*env
, int csrno
,
3519 target_ulong wpri_val
= val
& SMTE_MASK
;
3521 if (val
!= wpri_val
) {
3522 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s" TARGET_FMT_lx
"\n",
3523 "SMTE: WPRI violation written 0x", val
,
3524 "vs expected 0x", wpri_val
);
3527 /* if pm.current==0 we can't modify current PM CSRs */
3528 if (check_pm_current_disabled(env
, csrno
)) {
3529 return RISCV_EXCP_NONE
;
3532 wpri_val
|= (env
->mmte
& ~SMTE_MASK
);
3533 write_mmte(env
, csrno
, wpri_val
);
3534 return RISCV_EXCP_NONE
;
3537 static RISCVException
read_umte(CPURISCVState
*env
, int csrno
,
3540 *val
= env
->mmte
& UMTE_MASK
;
3541 return RISCV_EXCP_NONE
;
3544 static RISCVException
write_umte(CPURISCVState
*env
, int csrno
,
3547 target_ulong wpri_val
= val
& UMTE_MASK
;
3549 if (val
!= wpri_val
) {
3550 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s" TARGET_FMT_lx
"\n",
3551 "UMTE: WPRI violation written 0x", val
,
3552 "vs expected 0x", wpri_val
);
3555 if (check_pm_current_disabled(env
, csrno
)) {
3556 return RISCV_EXCP_NONE
;
3559 wpri_val
|= (env
->mmte
& ~UMTE_MASK
);
3560 write_mmte(env
, csrno
, wpri_val
);
3561 return RISCV_EXCP_NONE
;
3564 static RISCVException
read_mpmmask(CPURISCVState
*env
, int csrno
,
3567 *val
= env
->mpmmask
;
3568 return RISCV_EXCP_NONE
;
3571 static RISCVException
write_mpmmask(CPURISCVState
*env
, int csrno
,
3577 if ((env
->priv
== PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
3578 env
->cur_pmmask
= val
;
3580 env
->mmte
|= PM_EXT_DIRTY
;
3582 /* Set XS and SD bits, since PM CSRs are dirty */
3583 mstatus
= env
->mstatus
| MSTATUS_XS
;
3584 write_mstatus(env
, csrno
, mstatus
);
3585 return RISCV_EXCP_NONE
;
3588 static RISCVException
read_spmmask(CPURISCVState
*env
, int csrno
,
3591 *val
= env
->spmmask
;
3592 return RISCV_EXCP_NONE
;
3595 static RISCVException
write_spmmask(CPURISCVState
*env
, int csrno
,
3600 /* if pm.current==0 we can't modify current PM CSRs */
3601 if (check_pm_current_disabled(env
, csrno
)) {
3602 return RISCV_EXCP_NONE
;
3605 if ((env
->priv
== PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
3606 env
->cur_pmmask
= val
;
3608 env
->mmte
|= PM_EXT_DIRTY
;
3610 /* Set XS and SD bits, since PM CSRs are dirty */
3611 mstatus
= env
->mstatus
| MSTATUS_XS
;
3612 write_mstatus(env
, csrno
, mstatus
);
3613 return RISCV_EXCP_NONE
;
3616 static RISCVException
read_upmmask(CPURISCVState
*env
, int csrno
,
3619 *val
= env
->upmmask
;
3620 return RISCV_EXCP_NONE
;
3623 static RISCVException
write_upmmask(CPURISCVState
*env
, int csrno
,
3628 /* if pm.current==0 we can't modify current PM CSRs */
3629 if (check_pm_current_disabled(env
, csrno
)) {
3630 return RISCV_EXCP_NONE
;
3633 if ((env
->priv
== PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
3634 env
->cur_pmmask
= val
;
3636 env
->mmte
|= PM_EXT_DIRTY
;
3638 /* Set XS and SD bits, since PM CSRs are dirty */
3639 mstatus
= env
->mstatus
| MSTATUS_XS
;
3640 write_mstatus(env
, csrno
, mstatus
);
3641 return RISCV_EXCP_NONE
;
3644 static RISCVException
read_mpmbase(CPURISCVState
*env
, int csrno
,
3647 *val
= env
->mpmbase
;
3648 return RISCV_EXCP_NONE
;
3651 static RISCVException
write_mpmbase(CPURISCVState
*env
, int csrno
,
3657 if ((env
->priv
== PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
3658 env
->cur_pmbase
= val
;
3660 env
->mmte
|= PM_EXT_DIRTY
;
3662 /* Set XS and SD bits, since PM CSRs are dirty */
3663 mstatus
= env
->mstatus
| MSTATUS_XS
;
3664 write_mstatus(env
, csrno
, mstatus
);
3665 return RISCV_EXCP_NONE
;
3668 static RISCVException
read_spmbase(CPURISCVState
*env
, int csrno
,
3671 *val
= env
->spmbase
;
3672 return RISCV_EXCP_NONE
;
3675 static RISCVException
write_spmbase(CPURISCVState
*env
, int csrno
,
3680 /* if pm.current==0 we can't modify current PM CSRs */
3681 if (check_pm_current_disabled(env
, csrno
)) {
3682 return RISCV_EXCP_NONE
;
3685 if ((env
->priv
== PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
3686 env
->cur_pmbase
= val
;
3688 env
->mmte
|= PM_EXT_DIRTY
;
3690 /* Set XS and SD bits, since PM CSRs are dirty */
3691 mstatus
= env
->mstatus
| MSTATUS_XS
;
3692 write_mstatus(env
, csrno
, mstatus
);
3693 return RISCV_EXCP_NONE
;
3696 static RISCVException
read_upmbase(CPURISCVState
*env
, int csrno
,
3699 *val
= env
->upmbase
;
3700 return RISCV_EXCP_NONE
;
3703 static RISCVException
write_upmbase(CPURISCVState
*env
, int csrno
,
3708 /* if pm.current==0 we can't modify current PM CSRs */
3709 if (check_pm_current_disabled(env
, csrno
)) {
3710 return RISCV_EXCP_NONE
;
3713 if ((env
->priv
== PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
3714 env
->cur_pmbase
= val
;
3716 env
->mmte
|= PM_EXT_DIRTY
;
3718 /* Set XS and SD bits, since PM CSRs are dirty */
3719 mstatus
= env
->mstatus
| MSTATUS_XS
;
3720 write_mstatus(env
, csrno
, mstatus
);
3721 return RISCV_EXCP_NONE
;
3726 /* Crypto Extension */
3727 static RISCVException
rmw_seed(CPURISCVState
*env
, int csrno
,
3728 target_ulong
*ret_value
,
3729 target_ulong new_value
,
3730 target_ulong write_mask
)
3733 Error
*random_e
= NULL
;
3737 random_r
= qemu_guest_getrandom(&random_v
, 2, &random_e
);
3738 if (unlikely(random_r
< 0)) {
3740 * Failed, for unknown reasons in the crypto subsystem.
3741 * The best we can do is log the reason and return a
3742 * failure indication to the guest. There is no reason
3743 * we know to expect the failure to be transitory, so
3744 * indicate DEAD to avoid having the guest spin on WAIT.
3746 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
3747 __func__
, error_get_pretty(random_e
));
3748 error_free(random_e
);
3749 rval
= SEED_OPST_DEAD
;
3751 rval
= random_v
| SEED_OPST_ES16
;
3758 return RISCV_EXCP_NONE
;
3762 * riscv_csrrw - read and/or update control and status register
3764 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
3765 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
3766 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
3767 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
3770 static inline RISCVException
riscv_csrrw_check(CPURISCVState
*env
,
3775 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
3776 int read_only
= get_field(csrno
, 0xC00) == 3;
3777 int csr_min_priv
= csr_ops
[csrno
].min_priv_ver
;
3779 /* ensure the CSR extension is enabled. */
3780 if (!cpu
->cfg
.ext_icsr
) {
3781 return RISCV_EXCP_ILLEGAL_INST
;
3784 if (env
->priv_ver
< csr_min_priv
) {
3785 return RISCV_EXCP_ILLEGAL_INST
;
3788 /* check predicate */
3789 if (!csr_ops
[csrno
].predicate
) {
3790 return RISCV_EXCP_ILLEGAL_INST
;
3793 if (write_mask
&& read_only
) {
3794 return RISCV_EXCP_ILLEGAL_INST
;
3797 RISCVException ret
= csr_ops
[csrno
].predicate(env
, csrno
);
3798 if (ret
!= RISCV_EXCP_NONE
) {
3802 #if !defined(CONFIG_USER_ONLY)
3803 int csr_priv
, effective_priv
= env
->priv
;
3805 if (riscv_has_ext(env
, RVH
) && env
->priv
== PRV_S
&&
3806 !riscv_cpu_virt_enabled(env
)) {
3808 * We are in HS mode. Add 1 to the effective privledge level to
3809 * allow us to access the Hypervisor CSRs.
3814 csr_priv
= get_field(csrno
, 0x300);
3815 if (!env
->debugger
&& (effective_priv
< csr_priv
)) {
3816 if (csr_priv
== (PRV_S
+ 1) && riscv_cpu_virt_enabled(env
)) {
3817 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
3819 return RISCV_EXCP_ILLEGAL_INST
;
3822 return RISCV_EXCP_NONE
;
3825 static RISCVException
riscv_csrrw_do64(CPURISCVState
*env
, int csrno
,
3826 target_ulong
*ret_value
,
3827 target_ulong new_value
,
3828 target_ulong write_mask
)
3831 target_ulong old_value
;
3833 /* execute combined read/write operation if it exists */
3834 if (csr_ops
[csrno
].op
) {
3835 return csr_ops
[csrno
].op(env
, csrno
, ret_value
, new_value
, write_mask
);
3838 /* if no accessor exists then return failure */
3839 if (!csr_ops
[csrno
].read
) {
3840 return RISCV_EXCP_ILLEGAL_INST
;
3842 /* read old value */
3843 ret
= csr_ops
[csrno
].read(env
, csrno
, &old_value
);
3844 if (ret
!= RISCV_EXCP_NONE
) {
3848 /* write value if writable and write mask set, otherwise drop writes */
3850 new_value
= (old_value
& ~write_mask
) | (new_value
& write_mask
);
3851 if (csr_ops
[csrno
].write
) {
3852 ret
= csr_ops
[csrno
].write(env
, csrno
, new_value
);
3853 if (ret
!= RISCV_EXCP_NONE
) {
3859 /* return old value */
3861 *ret_value
= old_value
;
3864 return RISCV_EXCP_NONE
;
3867 RISCVException
riscv_csrrw(CPURISCVState
*env
, int csrno
,
3868 target_ulong
*ret_value
,
3869 target_ulong new_value
, target_ulong write_mask
)
3871 RISCVCPU
*cpu
= env_archcpu(env
);
3873 RISCVException ret
= riscv_csrrw_check(env
, csrno
, write_mask
, cpu
);
3874 if (ret
!= RISCV_EXCP_NONE
) {
3878 return riscv_csrrw_do64(env
, csrno
, ret_value
, new_value
, write_mask
);
3881 static RISCVException
riscv_csrrw_do128(CPURISCVState
*env
, int csrno
,
3889 /* read old value */
3890 ret
= csr_ops
[csrno
].read128(env
, csrno
, &old_value
);
3891 if (ret
!= RISCV_EXCP_NONE
) {
3895 /* write value if writable and write mask set, otherwise drop writes */
3896 if (int128_nz(write_mask
)) {
3897 new_value
= int128_or(int128_and(old_value
, int128_not(write_mask
)),
3898 int128_and(new_value
, write_mask
));
3899 if (csr_ops
[csrno
].write128
) {
3900 ret
= csr_ops
[csrno
].write128(env
, csrno
, new_value
);
3901 if (ret
!= RISCV_EXCP_NONE
) {
3904 } else if (csr_ops
[csrno
].write
) {
3905 /* avoids having to write wrappers for all registers */
3906 ret
= csr_ops
[csrno
].write(env
, csrno
, int128_getlo(new_value
));
3907 if (ret
!= RISCV_EXCP_NONE
) {
3913 /* return old value */
3915 *ret_value
= old_value
;
3918 return RISCV_EXCP_NONE
;
3921 RISCVException
riscv_csrrw_i128(CPURISCVState
*env
, int csrno
,
3923 Int128 new_value
, Int128 write_mask
)
3926 RISCVCPU
*cpu
= env_archcpu(env
);
3928 ret
= riscv_csrrw_check(env
, csrno
, int128_nz(write_mask
), cpu
);
3929 if (ret
!= RISCV_EXCP_NONE
) {
3933 if (csr_ops
[csrno
].read128
) {
3934 return riscv_csrrw_do128(env
, csrno
, ret_value
, new_value
, write_mask
);
3938 * Fall back to 64-bit version for now, if the 128-bit alternative isn't
3940 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
3941 * significant), for those, this fallback is correctly handling the accesses
3943 target_ulong old_value
;
3944 ret
= riscv_csrrw_do64(env
, csrno
, &old_value
,
3945 int128_getlo(new_value
),
3946 int128_getlo(write_mask
));
3947 if (ret
== RISCV_EXCP_NONE
&& ret_value
) {
3948 *ret_value
= int128_make64(old_value
);
3954 * Debugger support. If not in user mode, set env->debugger before the
3955 * riscv_csrrw call and clear it after the call.
3957 RISCVException
riscv_csrrw_debug(CPURISCVState
*env
, int csrno
,
3958 target_ulong
*ret_value
,
3959 target_ulong new_value
,
3960 target_ulong write_mask
)
3963 #if !defined(CONFIG_USER_ONLY)
3964 env
->debugger
= true;
3966 ret
= riscv_csrrw(env
, csrno
, ret_value
, new_value
, write_mask
);
3967 #if !defined(CONFIG_USER_ONLY)
3968 env
->debugger
= false;
3973 /* Control and Status Register function table */
3974 riscv_csr_operations csr_ops
[CSR_TABLE_SIZE
] = {
3975 /* User Floating-Point CSRs */
3976 [CSR_FFLAGS
] = { "fflags", fs
, read_fflags
, write_fflags
},
3977 [CSR_FRM
] = { "frm", fs
, read_frm
, write_frm
},
3978 [CSR_FCSR
] = { "fcsr", fs
, read_fcsr
, write_fcsr
},
3980 [CSR_VSTART
] = { "vstart", vs
, read_vstart
, write_vstart
},
3981 [CSR_VXSAT
] = { "vxsat", vs
, read_vxsat
, write_vxsat
},
3982 [CSR_VXRM
] = { "vxrm", vs
, read_vxrm
, write_vxrm
},
3983 [CSR_VCSR
] = { "vcsr", vs
, read_vcsr
, write_vcsr
},
3984 [CSR_VL
] = { "vl", vs
, read_vl
},
3985 [CSR_VTYPE
] = { "vtype", vs
, read_vtype
},
3986 [CSR_VLENB
] = { "vlenb", vs
, read_vlenb
},
3987 /* User Timers and Counters */
3988 [CSR_CYCLE
] = { "cycle", ctr
, read_hpmcounter
},
3989 [CSR_INSTRET
] = { "instret", ctr
, read_hpmcounter
},
3990 [CSR_CYCLEH
] = { "cycleh", ctr32
, read_hpmcounterh
},
3991 [CSR_INSTRETH
] = { "instreth", ctr32
, read_hpmcounterh
},
3994 * In privileged mode, the monitor will have to emulate TIME CSRs only if
3995 * rdtime callback is not provided by machine/platform emulation.
3997 [CSR_TIME
] = { "time", ctr
, read_time
},
3998 [CSR_TIMEH
] = { "timeh", ctr32
, read_timeh
},
4000 /* Crypto Extension */
4001 [CSR_SEED
] = { "seed", seed
, NULL
, NULL
, rmw_seed
},
4003 #if !defined(CONFIG_USER_ONLY)
4004 /* Machine Timers and Counters */
4005 [CSR_MCYCLE
] = { "mcycle", any
, read_hpmcounter
,
4006 write_mhpmcounter
},
4007 [CSR_MINSTRET
] = { "minstret", any
, read_hpmcounter
,
4008 write_mhpmcounter
},
4009 [CSR_MCYCLEH
] = { "mcycleh", any32
, read_hpmcounterh
,
4010 write_mhpmcounterh
},
4011 [CSR_MINSTRETH
] = { "minstreth", any32
, read_hpmcounterh
,
4012 write_mhpmcounterh
},
4014 /* Machine Information Registers */
4015 [CSR_MVENDORID
] = { "mvendorid", any
, read_mvendorid
},
4016 [CSR_MARCHID
] = { "marchid", any
, read_marchid
},
4017 [CSR_MIMPID
] = { "mimpid", any
, read_mimpid
},
4018 [CSR_MHARTID
] = { "mhartid", any
, read_mhartid
},
4020 [CSR_MCONFIGPTR
] = { "mconfigptr", any
, read_zero
,
4021 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4022 /* Machine Trap Setup */
4023 [CSR_MSTATUS
] = { "mstatus", any
, read_mstatus
, write_mstatus
,
4024 NULL
, read_mstatus_i128
},
4025 [CSR_MISA
] = { "misa", any
, read_misa
, write_misa
,
4026 NULL
, read_misa_i128
},
4027 [CSR_MIDELEG
] = { "mideleg", any
, NULL
, NULL
, rmw_mideleg
},
4028 [CSR_MEDELEG
] = { "medeleg", any
, read_medeleg
, write_medeleg
},
4029 [CSR_MIE
] = { "mie", any
, NULL
, NULL
, rmw_mie
},
4030 [CSR_MTVEC
] = { "mtvec", any
, read_mtvec
, write_mtvec
},
4031 [CSR_MCOUNTEREN
] = { "mcounteren", umode
, read_mcounteren
,
4034 [CSR_MSTATUSH
] = { "mstatush", any32
, read_mstatush
,
4037 /* Machine Trap Handling */
4038 [CSR_MSCRATCH
] = { "mscratch", any
, read_mscratch
, write_mscratch
,
4039 NULL
, read_mscratch_i128
, write_mscratch_i128
},
4040 [CSR_MEPC
] = { "mepc", any
, read_mepc
, write_mepc
},
4041 [CSR_MCAUSE
] = { "mcause", any
, read_mcause
, write_mcause
},
4042 [CSR_MTVAL
] = { "mtval", any
, read_mtval
, write_mtval
},
4043 [CSR_MIP
] = { "mip", any
, NULL
, NULL
, rmw_mip
},
4045 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
4046 [CSR_MISELECT
] = { "miselect", aia_any
, NULL
, NULL
, rmw_xiselect
},
4047 [CSR_MIREG
] = { "mireg", aia_any
, NULL
, NULL
, rmw_xireg
},
4049 /* Machine-Level Interrupts (AIA) */
4050 [CSR_MTOPEI
] = { "mtopei", aia_any
, NULL
, NULL
, rmw_xtopei
},
4051 [CSR_MTOPI
] = { "mtopi", aia_any
, read_mtopi
},
4053 /* Virtual Interrupts for Supervisor Level (AIA) */
4054 [CSR_MVIEN
] = { "mvien", aia_any
, read_zero
, write_ignore
},
4055 [CSR_MVIP
] = { "mvip", aia_any
, read_zero
, write_ignore
},
4057 /* Machine-Level High-Half CSRs (AIA) */
4058 [CSR_MIDELEGH
] = { "midelegh", aia_any32
, NULL
, NULL
, rmw_midelegh
},
4059 [CSR_MIEH
] = { "mieh", aia_any32
, NULL
, NULL
, rmw_mieh
},
4060 [CSR_MVIENH
] = { "mvienh", aia_any32
, read_zero
, write_ignore
},
4061 [CSR_MVIPH
] = { "mviph", aia_any32
, read_zero
, write_ignore
},
4062 [CSR_MIPH
] = { "miph", aia_any32
, NULL
, NULL
, rmw_miph
},
4064 /* Execution environment configuration */
4065 [CSR_MENVCFG
] = { "menvcfg", umode
, read_menvcfg
, write_menvcfg
,
4066 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4067 [CSR_MENVCFGH
] = { "menvcfgh", umode32
, read_menvcfgh
, write_menvcfgh
,
4068 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4069 [CSR_SENVCFG
] = { "senvcfg", smode
, read_senvcfg
, write_senvcfg
,
4070 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4071 [CSR_HENVCFG
] = { "henvcfg", hmode
, read_henvcfg
, write_henvcfg
,
4072 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4073 [CSR_HENVCFGH
] = { "henvcfgh", hmode32
, read_henvcfgh
, write_henvcfgh
,
4074 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4076 /* Smstateen extension CSRs */
4077 [CSR_MSTATEEN0
] = { "mstateen0", mstateen
, read_mstateen
, write_mstateen0
,
4078 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4079 [CSR_MSTATEEN0H
] = { "mstateen0h", mstateen
, read_mstateenh
,
4081 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4082 [CSR_MSTATEEN1
] = { "mstateen1", mstateen
, read_mstateen
,
4084 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4085 [CSR_MSTATEEN1H
] = { "mstateen1h", mstateen
, read_mstateenh
,
4086 write_mstateenh_1_3
,
4087 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4088 [CSR_MSTATEEN2
] = { "mstateen2", mstateen
, read_mstateen
,
4090 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4091 [CSR_MSTATEEN2H
] = { "mstateen2h", mstateen
, read_mstateenh
,
4092 write_mstateenh_1_3
,
4093 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4094 [CSR_MSTATEEN3
] = { "mstateen3", mstateen
, read_mstateen
,
4096 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4097 [CSR_MSTATEEN3H
] = { "mstateen3h", mstateen
, read_mstateenh
,
4098 write_mstateenh_1_3
,
4099 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4100 [CSR_HSTATEEN0
] = { "hstateen0", hstateen
, read_hstateen
, write_hstateen0
,
4101 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4102 [CSR_HSTATEEN0H
] = { "hstateen0h", hstateenh
, read_hstateenh
,
4104 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4105 [CSR_HSTATEEN1
] = { "hstateen1", hstateen
, read_hstateen
,
4107 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4108 [CSR_HSTATEEN1H
] = { "hstateen1h", hstateenh
, read_hstateenh
,
4109 write_hstateenh_1_3
,
4110 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4111 [CSR_HSTATEEN2
] = { "hstateen2", hstateen
, read_hstateen
,
4113 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4114 [CSR_HSTATEEN2H
] = { "hstateen2h", hstateenh
, read_hstateenh
,
4115 write_hstateenh_1_3
,
4116 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4117 [CSR_HSTATEEN3
] = { "hstateen3", hstateen
, read_hstateen
,
4119 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4120 [CSR_HSTATEEN3H
] = { "hstateen3h", hstateenh
, read_hstateenh
,
4121 write_hstateenh_1_3
,
4122 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4123 [CSR_SSTATEEN0
] = { "sstateen0", sstateen
, read_sstateen
, write_sstateen0
,
4124 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4125 [CSR_SSTATEEN1
] = { "sstateen1", sstateen
, read_sstateen
,
4127 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4128 [CSR_SSTATEEN2
] = { "sstateen2", sstateen
, read_sstateen
,
4130 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4131 [CSR_SSTATEEN3
] = { "sstateen3", sstateen
, read_sstateen
,
4133 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4135 /* Supervisor Trap Setup */
4136 [CSR_SSTATUS
] = { "sstatus", smode
, read_sstatus
, write_sstatus
,
4137 NULL
, read_sstatus_i128
},
4138 [CSR_SIE
] = { "sie", smode
, NULL
, NULL
, rmw_sie
},
4139 [CSR_STVEC
] = { "stvec", smode
, read_stvec
, write_stvec
},
4140 [CSR_SCOUNTEREN
] = { "scounteren", smode
, read_scounteren
,
4143 /* Supervisor Trap Handling */
4144 [CSR_SSCRATCH
] = { "sscratch", smode
, read_sscratch
, write_sscratch
,
4145 NULL
, read_sscratch_i128
, write_sscratch_i128
},
4146 [CSR_SEPC
] = { "sepc", smode
, read_sepc
, write_sepc
},
4147 [CSR_SCAUSE
] = { "scause", smode
, read_scause
, write_scause
},
4148 [CSR_STVAL
] = { "stval", smode
, read_stval
, write_stval
},
4149 [CSR_SIP
] = { "sip", smode
, NULL
, NULL
, rmw_sip
},
4150 [CSR_STIMECMP
] = { "stimecmp", sstc
, read_stimecmp
, write_stimecmp
,
4151 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4152 [CSR_STIMECMPH
] = { "stimecmph", sstc_32
, read_stimecmph
, write_stimecmph
,
4153 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4154 [CSR_VSTIMECMP
] = { "vstimecmp", sstc
, read_vstimecmp
,
4156 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4157 [CSR_VSTIMECMPH
] = { "vstimecmph", sstc_32
, read_vstimecmph
,
4159 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4161 /* Supervisor Protection and Translation */
4162 [CSR_SATP
] = { "satp", smode
, read_satp
, write_satp
},
4164 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
4165 [CSR_SISELECT
] = { "siselect", aia_smode
, NULL
, NULL
, rmw_xiselect
},
4166 [CSR_SIREG
] = { "sireg", aia_smode
, NULL
, NULL
, rmw_xireg
},
4168 /* Supervisor-Level Interrupts (AIA) */
4169 [CSR_STOPEI
] = { "stopei", aia_smode
, NULL
, NULL
, rmw_xtopei
},
4170 [CSR_STOPI
] = { "stopi", aia_smode
, read_stopi
},
4172 /* Supervisor-Level High-Half CSRs (AIA) */
4173 [CSR_SIEH
] = { "sieh", aia_smode32
, NULL
, NULL
, rmw_sieh
},
4174 [CSR_SIPH
] = { "siph", aia_smode32
, NULL
, NULL
, rmw_siph
},
4176 [CSR_HSTATUS
] = { "hstatus", hmode
, read_hstatus
, write_hstatus
,
4177 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4178 [CSR_HEDELEG
] = { "hedeleg", hmode
, read_hedeleg
, write_hedeleg
,
4179 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4180 [CSR_HIDELEG
] = { "hideleg", hmode
, NULL
, NULL
, rmw_hideleg
,
4181 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4182 [CSR_HVIP
] = { "hvip", hmode
, NULL
, NULL
, rmw_hvip
,
4183 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4184 [CSR_HIP
] = { "hip", hmode
, NULL
, NULL
, rmw_hip
,
4185 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4186 [CSR_HIE
] = { "hie", hmode
, NULL
, NULL
, rmw_hie
,
4187 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4188 [CSR_HCOUNTEREN
] = { "hcounteren", hmode
, read_hcounteren
,
4190 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4191 [CSR_HGEIE
] = { "hgeie", hmode
, read_hgeie
, write_hgeie
,
4192 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4193 [CSR_HTVAL
] = { "htval", hmode
, read_htval
, write_htval
,
4194 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4195 [CSR_HTINST
] = { "htinst", hmode
, read_htinst
, write_htinst
,
4196 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4197 [CSR_HGEIP
] = { "hgeip", hmode
, read_hgeip
,
4198 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4199 [CSR_HGATP
] = { "hgatp", hmode
, read_hgatp
, write_hgatp
,
4200 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4201 [CSR_HTIMEDELTA
] = { "htimedelta", hmode
, read_htimedelta
,
4203 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4204 [CSR_HTIMEDELTAH
] = { "htimedeltah", hmode32
, read_htimedeltah
,
4206 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4208 [CSR_VSSTATUS
] = { "vsstatus", hmode
, read_vsstatus
,
4210 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4211 [CSR_VSIP
] = { "vsip", hmode
, NULL
, NULL
, rmw_vsip
,
4212 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4213 [CSR_VSIE
] = { "vsie", hmode
, NULL
, NULL
, rmw_vsie
,
4214 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4215 [CSR_VSTVEC
] = { "vstvec", hmode
, read_vstvec
, write_vstvec
,
4216 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4217 [CSR_VSSCRATCH
] = { "vsscratch", hmode
, read_vsscratch
,
4219 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4220 [CSR_VSEPC
] = { "vsepc", hmode
, read_vsepc
, write_vsepc
,
4221 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4222 [CSR_VSCAUSE
] = { "vscause", hmode
, read_vscause
, write_vscause
,
4223 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4224 [CSR_VSTVAL
] = { "vstval", hmode
, read_vstval
, write_vstval
,
4225 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4226 [CSR_VSATP
] = { "vsatp", hmode
, read_vsatp
, write_vsatp
,
4227 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4229 [CSR_MTVAL2
] = { "mtval2", hmode
, read_mtval2
, write_mtval2
,
4230 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4231 [CSR_MTINST
] = { "mtinst", hmode
, read_mtinst
, write_mtinst
,
4232 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4234 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
4235 [CSR_HVIEN
] = { "hvien", aia_hmode
, read_zero
, write_ignore
},
4236 [CSR_HVICTL
] = { "hvictl", aia_hmode
, read_hvictl
,
4238 [CSR_HVIPRIO1
] = { "hviprio1", aia_hmode
, read_hviprio1
,
4240 [CSR_HVIPRIO2
] = { "hviprio2", aia_hmode
, read_hviprio2
,
4244 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
4246 [CSR_VSISELECT
] = { "vsiselect", aia_hmode
, NULL
, NULL
,
4248 [CSR_VSIREG
] = { "vsireg", aia_hmode
, NULL
, NULL
, rmw_xireg
},
4250 /* VS-Level Interrupts (H-extension with AIA) */
4251 [CSR_VSTOPEI
] = { "vstopei", aia_hmode
, NULL
, NULL
, rmw_xtopei
},
4252 [CSR_VSTOPI
] = { "vstopi", aia_hmode
, read_vstopi
},
4254 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
4255 [CSR_HIDELEGH
] = { "hidelegh", aia_hmode32
, NULL
, NULL
,
4257 [CSR_HVIENH
] = { "hvienh", aia_hmode32
, read_zero
,
4259 [CSR_HVIPH
] = { "hviph", aia_hmode32
, NULL
, NULL
, rmw_hviph
},
4260 [CSR_HVIPRIO1H
] = { "hviprio1h", aia_hmode32
, read_hviprio1h
,
4262 [CSR_HVIPRIO2H
] = { "hviprio2h", aia_hmode32
, read_hviprio2h
,
4264 [CSR_VSIEH
] = { "vsieh", aia_hmode32
, NULL
, NULL
, rmw_vsieh
},
4265 [CSR_VSIPH
] = { "vsiph", aia_hmode32
, NULL
, NULL
, rmw_vsiph
},
4267 /* Physical Memory Protection */
4268 [CSR_MSECCFG
] = { "mseccfg", epmp
, read_mseccfg
, write_mseccfg
,
4269 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4270 [CSR_PMPCFG0
] = { "pmpcfg0", pmp
, read_pmpcfg
, write_pmpcfg
},
4271 [CSR_PMPCFG1
] = { "pmpcfg1", pmp
, read_pmpcfg
, write_pmpcfg
},
4272 [CSR_PMPCFG2
] = { "pmpcfg2", pmp
, read_pmpcfg
, write_pmpcfg
},
4273 [CSR_PMPCFG3
] = { "pmpcfg3", pmp
, read_pmpcfg
, write_pmpcfg
},
4274 [CSR_PMPADDR0
] = { "pmpaddr0", pmp
, read_pmpaddr
, write_pmpaddr
},
4275 [CSR_PMPADDR1
] = { "pmpaddr1", pmp
, read_pmpaddr
, write_pmpaddr
},
4276 [CSR_PMPADDR2
] = { "pmpaddr2", pmp
, read_pmpaddr
, write_pmpaddr
},
4277 [CSR_PMPADDR3
] = { "pmpaddr3", pmp
, read_pmpaddr
, write_pmpaddr
},
4278 [CSR_PMPADDR4
] = { "pmpaddr4", pmp
, read_pmpaddr
, write_pmpaddr
},
4279 [CSR_PMPADDR5
] = { "pmpaddr5", pmp
, read_pmpaddr
, write_pmpaddr
},
4280 [CSR_PMPADDR6
] = { "pmpaddr6", pmp
, read_pmpaddr
, write_pmpaddr
},
4281 [CSR_PMPADDR7
] = { "pmpaddr7", pmp
, read_pmpaddr
, write_pmpaddr
},
4282 [CSR_PMPADDR8
] = { "pmpaddr8", pmp
, read_pmpaddr
, write_pmpaddr
},
4283 [CSR_PMPADDR9
] = { "pmpaddr9", pmp
, read_pmpaddr
, write_pmpaddr
},
4284 [CSR_PMPADDR10
] = { "pmpaddr10", pmp
, read_pmpaddr
, write_pmpaddr
},
4285 [CSR_PMPADDR11
] = { "pmpaddr11", pmp
, read_pmpaddr
, write_pmpaddr
},
4286 [CSR_PMPADDR12
] = { "pmpaddr12", pmp
, read_pmpaddr
, write_pmpaddr
},
4287 [CSR_PMPADDR13
] = { "pmpaddr13", pmp
, read_pmpaddr
, write_pmpaddr
},
4288 [CSR_PMPADDR14
] = { "pmpaddr14", pmp
, read_pmpaddr
, write_pmpaddr
},
4289 [CSR_PMPADDR15
] = { "pmpaddr15", pmp
, read_pmpaddr
, write_pmpaddr
},
4292 [CSR_TSELECT
] = { "tselect", debug
, read_tselect
, write_tselect
},
4293 [CSR_TDATA1
] = { "tdata1", debug
, read_tdata
, write_tdata
},
4294 [CSR_TDATA2
] = { "tdata2", debug
, read_tdata
, write_tdata
},
4295 [CSR_TDATA3
] = { "tdata3", debug
, read_tdata
, write_tdata
},
4296 [CSR_TINFO
] = { "tinfo", debug
, read_tinfo
, write_ignore
},
4298 /* User Pointer Masking */
4299 [CSR_UMTE
] = { "umte", pointer_masking
, read_umte
, write_umte
},
4300 [CSR_UPMMASK
] = { "upmmask", pointer_masking
, read_upmmask
,
4302 [CSR_UPMBASE
] = { "upmbase", pointer_masking
, read_upmbase
,
4304 /* Machine Pointer Masking */
4305 [CSR_MMTE
] = { "mmte", pointer_masking
, read_mmte
, write_mmte
},
4306 [CSR_MPMMASK
] = { "mpmmask", pointer_masking
, read_mpmmask
,
4308 [CSR_MPMBASE
] = { "mpmbase", pointer_masking
, read_mpmbase
,
4310 /* Supervisor Pointer Masking */
4311 [CSR_SMTE
] = { "smte", pointer_masking
, read_smte
, write_smte
},
4312 [CSR_SPMMASK
] = { "spmmask", pointer_masking
, read_spmmask
,
4314 [CSR_SPMBASE
] = { "spmbase", pointer_masking
, read_spmbase
,
4317 /* Performance Counters */
4318 [CSR_HPMCOUNTER3
] = { "hpmcounter3", ctr
, read_hpmcounter
},
4319 [CSR_HPMCOUNTER4
] = { "hpmcounter4", ctr
, read_hpmcounter
},
4320 [CSR_HPMCOUNTER5
] = { "hpmcounter5", ctr
, read_hpmcounter
},
4321 [CSR_HPMCOUNTER6
] = { "hpmcounter6", ctr
, read_hpmcounter
},
4322 [CSR_HPMCOUNTER7
] = { "hpmcounter7", ctr
, read_hpmcounter
},
4323 [CSR_HPMCOUNTER8
] = { "hpmcounter8", ctr
, read_hpmcounter
},
4324 [CSR_HPMCOUNTER9
] = { "hpmcounter9", ctr
, read_hpmcounter
},
4325 [CSR_HPMCOUNTER10
] = { "hpmcounter10", ctr
, read_hpmcounter
},
4326 [CSR_HPMCOUNTER11
] = { "hpmcounter11", ctr
, read_hpmcounter
},
4327 [CSR_HPMCOUNTER12
] = { "hpmcounter12", ctr
, read_hpmcounter
},
4328 [CSR_HPMCOUNTER13
] = { "hpmcounter13", ctr
, read_hpmcounter
},
4329 [CSR_HPMCOUNTER14
] = { "hpmcounter14", ctr
, read_hpmcounter
},
4330 [CSR_HPMCOUNTER15
] = { "hpmcounter15", ctr
, read_hpmcounter
},
4331 [CSR_HPMCOUNTER16
] = { "hpmcounter16", ctr
, read_hpmcounter
},
4332 [CSR_HPMCOUNTER17
] = { "hpmcounter17", ctr
, read_hpmcounter
},
4333 [CSR_HPMCOUNTER18
] = { "hpmcounter18", ctr
, read_hpmcounter
},
4334 [CSR_HPMCOUNTER19
] = { "hpmcounter19", ctr
, read_hpmcounter
},
4335 [CSR_HPMCOUNTER20
] = { "hpmcounter20", ctr
, read_hpmcounter
},
4336 [CSR_HPMCOUNTER21
] = { "hpmcounter21", ctr
, read_hpmcounter
},
4337 [CSR_HPMCOUNTER22
] = { "hpmcounter22", ctr
, read_hpmcounter
},
4338 [CSR_HPMCOUNTER23
] = { "hpmcounter23", ctr
, read_hpmcounter
},
4339 [CSR_HPMCOUNTER24
] = { "hpmcounter24", ctr
, read_hpmcounter
},
4340 [CSR_HPMCOUNTER25
] = { "hpmcounter25", ctr
, read_hpmcounter
},
4341 [CSR_HPMCOUNTER26
] = { "hpmcounter26", ctr
, read_hpmcounter
},
4342 [CSR_HPMCOUNTER27
] = { "hpmcounter27", ctr
, read_hpmcounter
},
4343 [CSR_HPMCOUNTER28
] = { "hpmcounter28", ctr
, read_hpmcounter
},
4344 [CSR_HPMCOUNTER29
] = { "hpmcounter29", ctr
, read_hpmcounter
},
4345 [CSR_HPMCOUNTER30
] = { "hpmcounter30", ctr
, read_hpmcounter
},
4346 [CSR_HPMCOUNTER31
] = { "hpmcounter31", ctr
, read_hpmcounter
},
4348 [CSR_MHPMCOUNTER3
] = { "mhpmcounter3", mctr
, read_hpmcounter
,
4349 write_mhpmcounter
},
4350 [CSR_MHPMCOUNTER4
] = { "mhpmcounter4", mctr
, read_hpmcounter
,
4351 write_mhpmcounter
},
4352 [CSR_MHPMCOUNTER5
] = { "mhpmcounter5", mctr
, read_hpmcounter
,
4353 write_mhpmcounter
},
4354 [CSR_MHPMCOUNTER6
] = { "mhpmcounter6", mctr
, read_hpmcounter
,
4355 write_mhpmcounter
},
4356 [CSR_MHPMCOUNTER7
] = { "mhpmcounter7", mctr
, read_hpmcounter
,
4357 write_mhpmcounter
},
4358 [CSR_MHPMCOUNTER8
] = { "mhpmcounter8", mctr
, read_hpmcounter
,
4359 write_mhpmcounter
},
4360 [CSR_MHPMCOUNTER9
] = { "mhpmcounter9", mctr
, read_hpmcounter
,
4361 write_mhpmcounter
},
4362 [CSR_MHPMCOUNTER10
] = { "mhpmcounter10", mctr
, read_hpmcounter
,
4363 write_mhpmcounter
},
4364 [CSR_MHPMCOUNTER11
] = { "mhpmcounter11", mctr
, read_hpmcounter
,
4365 write_mhpmcounter
},
4366 [CSR_MHPMCOUNTER12
] = { "mhpmcounter12", mctr
, read_hpmcounter
,
4367 write_mhpmcounter
},
4368 [CSR_MHPMCOUNTER13
] = { "mhpmcounter13", mctr
, read_hpmcounter
,
4369 write_mhpmcounter
},
4370 [CSR_MHPMCOUNTER14
] = { "mhpmcounter14", mctr
, read_hpmcounter
,
4371 write_mhpmcounter
},
4372 [CSR_MHPMCOUNTER15
] = { "mhpmcounter15", mctr
, read_hpmcounter
,
4373 write_mhpmcounter
},
4374 [CSR_MHPMCOUNTER16
] = { "mhpmcounter16", mctr
, read_hpmcounter
,
4375 write_mhpmcounter
},
4376 [CSR_MHPMCOUNTER17
] = { "mhpmcounter17", mctr
, read_hpmcounter
,
4377 write_mhpmcounter
},
4378 [CSR_MHPMCOUNTER18
] = { "mhpmcounter18", mctr
, read_hpmcounter
,
4379 write_mhpmcounter
},
4380 [CSR_MHPMCOUNTER19
] = { "mhpmcounter19", mctr
, read_hpmcounter
,
4381 write_mhpmcounter
},
4382 [CSR_MHPMCOUNTER20
] = { "mhpmcounter20", mctr
, read_hpmcounter
,
4383 write_mhpmcounter
},
4384 [CSR_MHPMCOUNTER21
] = { "mhpmcounter21", mctr
, read_hpmcounter
,
4385 write_mhpmcounter
},
4386 [CSR_MHPMCOUNTER22
] = { "mhpmcounter22", mctr
, read_hpmcounter
,
4387 write_mhpmcounter
},
4388 [CSR_MHPMCOUNTER23
] = { "mhpmcounter23", mctr
, read_hpmcounter
,
4389 write_mhpmcounter
},
4390 [CSR_MHPMCOUNTER24
] = { "mhpmcounter24", mctr
, read_hpmcounter
,
4391 write_mhpmcounter
},
4392 [CSR_MHPMCOUNTER25
] = { "mhpmcounter25", mctr
, read_hpmcounter
,
4393 write_mhpmcounter
},
4394 [CSR_MHPMCOUNTER26
] = { "mhpmcounter26", mctr
, read_hpmcounter
,
4395 write_mhpmcounter
},
4396 [CSR_MHPMCOUNTER27
] = { "mhpmcounter27", mctr
, read_hpmcounter
,
4397 write_mhpmcounter
},
4398 [CSR_MHPMCOUNTER28
] = { "mhpmcounter28", mctr
, read_hpmcounter
,
4399 write_mhpmcounter
},
4400 [CSR_MHPMCOUNTER29
] = { "mhpmcounter29", mctr
, read_hpmcounter
,
4401 write_mhpmcounter
},
4402 [CSR_MHPMCOUNTER30
] = { "mhpmcounter30", mctr
, read_hpmcounter
,
4403 write_mhpmcounter
},
4404 [CSR_MHPMCOUNTER31
] = { "mhpmcounter31", mctr
, read_hpmcounter
,
4405 write_mhpmcounter
},
4407 [CSR_MCOUNTINHIBIT
] = { "mcountinhibit", any
, read_mcountinhibit
,
4408 write_mcountinhibit
,
4409 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4411 [CSR_MHPMEVENT3
] = { "mhpmevent3", any
, read_mhpmevent
,
4413 [CSR_MHPMEVENT4
] = { "mhpmevent4", any
, read_mhpmevent
,
4415 [CSR_MHPMEVENT5
] = { "mhpmevent5", any
, read_mhpmevent
,
4417 [CSR_MHPMEVENT6
] = { "mhpmevent6", any
, read_mhpmevent
,
4419 [CSR_MHPMEVENT7
] = { "mhpmevent7", any
, read_mhpmevent
,
4421 [CSR_MHPMEVENT8
] = { "mhpmevent8", any
, read_mhpmevent
,
4423 [CSR_MHPMEVENT9
] = { "mhpmevent9", any
, read_mhpmevent
,
4425 [CSR_MHPMEVENT10
] = { "mhpmevent10", any
, read_mhpmevent
,
4427 [CSR_MHPMEVENT11
] = { "mhpmevent11", any
, read_mhpmevent
,
4429 [CSR_MHPMEVENT12
] = { "mhpmevent12", any
, read_mhpmevent
,
4431 [CSR_MHPMEVENT13
] = { "mhpmevent13", any
, read_mhpmevent
,
4433 [CSR_MHPMEVENT14
] = { "mhpmevent14", any
, read_mhpmevent
,
4435 [CSR_MHPMEVENT15
] = { "mhpmevent15", any
, read_mhpmevent
,
4437 [CSR_MHPMEVENT16
] = { "mhpmevent16", any
, read_mhpmevent
,
4439 [CSR_MHPMEVENT17
] = { "mhpmevent17", any
, read_mhpmevent
,
4441 [CSR_MHPMEVENT18
] = { "mhpmevent18", any
, read_mhpmevent
,
4443 [CSR_MHPMEVENT19
] = { "mhpmevent19", any
, read_mhpmevent
,
4445 [CSR_MHPMEVENT20
] = { "mhpmevent20", any
, read_mhpmevent
,
4447 [CSR_MHPMEVENT21
] = { "mhpmevent21", any
, read_mhpmevent
,
4449 [CSR_MHPMEVENT22
] = { "mhpmevent22", any
, read_mhpmevent
,
4451 [CSR_MHPMEVENT23
] = { "mhpmevent23", any
, read_mhpmevent
,
4453 [CSR_MHPMEVENT24
] = { "mhpmevent24", any
, read_mhpmevent
,
4455 [CSR_MHPMEVENT25
] = { "mhpmevent25", any
, read_mhpmevent
,
4457 [CSR_MHPMEVENT26
] = { "mhpmevent26", any
, read_mhpmevent
,
4459 [CSR_MHPMEVENT27
] = { "mhpmevent27", any
, read_mhpmevent
,
4461 [CSR_MHPMEVENT28
] = { "mhpmevent28", any
, read_mhpmevent
,
4463 [CSR_MHPMEVENT29
] = { "mhpmevent29", any
, read_mhpmevent
,
4465 [CSR_MHPMEVENT30
] = { "mhpmevent30", any
, read_mhpmevent
,
4467 [CSR_MHPMEVENT31
] = { "mhpmevent31", any
, read_mhpmevent
,
4470 [CSR_MHPMEVENT3H
] = { "mhpmevent3h", sscofpmf
, read_mhpmeventh
,
4472 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4473 [CSR_MHPMEVENT4H
] = { "mhpmevent4h", sscofpmf
, read_mhpmeventh
,
4475 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4476 [CSR_MHPMEVENT5H
] = { "mhpmevent5h", sscofpmf
, read_mhpmeventh
,
4478 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4479 [CSR_MHPMEVENT6H
] = { "mhpmevent6h", sscofpmf
, read_mhpmeventh
,
4481 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4482 [CSR_MHPMEVENT7H
] = { "mhpmevent7h", sscofpmf
, read_mhpmeventh
,
4484 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4485 [CSR_MHPMEVENT8H
] = { "mhpmevent8h", sscofpmf
, read_mhpmeventh
,
4487 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4488 [CSR_MHPMEVENT9H
] = { "mhpmevent9h", sscofpmf
, read_mhpmeventh
,
4490 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4491 [CSR_MHPMEVENT10H
] = { "mhpmevent10h", sscofpmf
, read_mhpmeventh
,
4493 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4494 [CSR_MHPMEVENT11H
] = { "mhpmevent11h", sscofpmf
, read_mhpmeventh
,
4496 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4497 [CSR_MHPMEVENT12H
] = { "mhpmevent12h", sscofpmf
, read_mhpmeventh
,
4499 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4500 [CSR_MHPMEVENT13H
] = { "mhpmevent13h", sscofpmf
, read_mhpmeventh
,
4502 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4503 [CSR_MHPMEVENT14H
] = { "mhpmevent14h", sscofpmf
, read_mhpmeventh
,
4505 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4506 [CSR_MHPMEVENT15H
] = { "mhpmevent15h", sscofpmf
, read_mhpmeventh
,
4508 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4509 [CSR_MHPMEVENT16H
] = { "mhpmevent16h", sscofpmf
, read_mhpmeventh
,
4511 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4512 [CSR_MHPMEVENT17H
] = { "mhpmevent17h", sscofpmf
, read_mhpmeventh
,
4514 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4515 [CSR_MHPMEVENT18H
] = { "mhpmevent18h", sscofpmf
, read_mhpmeventh
,
4517 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4518 [CSR_MHPMEVENT19H
] = { "mhpmevent19h", sscofpmf
, read_mhpmeventh
,
4520 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4521 [CSR_MHPMEVENT20H
] = { "mhpmevent20h", sscofpmf
, read_mhpmeventh
,
4523 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4524 [CSR_MHPMEVENT21H
] = { "mhpmevent21h", sscofpmf
, read_mhpmeventh
,
4526 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4527 [CSR_MHPMEVENT22H
] = { "mhpmevent22h", sscofpmf
, read_mhpmeventh
,
4529 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4530 [CSR_MHPMEVENT23H
] = { "mhpmevent23h", sscofpmf
, read_mhpmeventh
,
4532 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4533 [CSR_MHPMEVENT24H
] = { "mhpmevent24h", sscofpmf
, read_mhpmeventh
,
4535 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4536 [CSR_MHPMEVENT25H
] = { "mhpmevent25h", sscofpmf
, read_mhpmeventh
,
4538 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4539 [CSR_MHPMEVENT26H
] = { "mhpmevent26h", sscofpmf
, read_mhpmeventh
,
4541 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4542 [CSR_MHPMEVENT27H
] = { "mhpmevent27h", sscofpmf
, read_mhpmeventh
,
4544 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4545 [CSR_MHPMEVENT28H
] = { "mhpmevent28h", sscofpmf
, read_mhpmeventh
,
4547 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4548 [CSR_MHPMEVENT29H
] = { "mhpmevent29h", sscofpmf
, read_mhpmeventh
,
4550 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4551 [CSR_MHPMEVENT30H
] = { "mhpmevent30h", sscofpmf
, read_mhpmeventh
,
4553 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4554 [CSR_MHPMEVENT31H
] = { "mhpmevent31h", sscofpmf
, read_mhpmeventh
,
4556 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4558 [CSR_HPMCOUNTER3H
] = { "hpmcounter3h", ctr32
, read_hpmcounterh
},
4559 [CSR_HPMCOUNTER4H
] = { "hpmcounter4h", ctr32
, read_hpmcounterh
},
4560 [CSR_HPMCOUNTER5H
] = { "hpmcounter5h", ctr32
, read_hpmcounterh
},
4561 [CSR_HPMCOUNTER6H
] = { "hpmcounter6h", ctr32
, read_hpmcounterh
},
4562 [CSR_HPMCOUNTER7H
] = { "hpmcounter7h", ctr32
, read_hpmcounterh
},
4563 [CSR_HPMCOUNTER8H
] = { "hpmcounter8h", ctr32
, read_hpmcounterh
},
4564 [CSR_HPMCOUNTER9H
] = { "hpmcounter9h", ctr32
, read_hpmcounterh
},
4565 [CSR_HPMCOUNTER10H
] = { "hpmcounter10h", ctr32
, read_hpmcounterh
},
4566 [CSR_HPMCOUNTER11H
] = { "hpmcounter11h", ctr32
, read_hpmcounterh
},
4567 [CSR_HPMCOUNTER12H
] = { "hpmcounter12h", ctr32
, read_hpmcounterh
},
4568 [CSR_HPMCOUNTER13H
] = { "hpmcounter13h", ctr32
, read_hpmcounterh
},
4569 [CSR_HPMCOUNTER14H
] = { "hpmcounter14h", ctr32
, read_hpmcounterh
},
4570 [CSR_HPMCOUNTER15H
] = { "hpmcounter15h", ctr32
, read_hpmcounterh
},
4571 [CSR_HPMCOUNTER16H
] = { "hpmcounter16h", ctr32
, read_hpmcounterh
},
4572 [CSR_HPMCOUNTER17H
] = { "hpmcounter17h", ctr32
, read_hpmcounterh
},
4573 [CSR_HPMCOUNTER18H
] = { "hpmcounter18h", ctr32
, read_hpmcounterh
},
4574 [CSR_HPMCOUNTER19H
] = { "hpmcounter19h", ctr32
, read_hpmcounterh
},
4575 [CSR_HPMCOUNTER20H
] = { "hpmcounter20h", ctr32
, read_hpmcounterh
},
4576 [CSR_HPMCOUNTER21H
] = { "hpmcounter21h", ctr32
, read_hpmcounterh
},
4577 [CSR_HPMCOUNTER22H
] = { "hpmcounter22h", ctr32
, read_hpmcounterh
},
4578 [CSR_HPMCOUNTER23H
] = { "hpmcounter23h", ctr32
, read_hpmcounterh
},
4579 [CSR_HPMCOUNTER24H
] = { "hpmcounter24h", ctr32
, read_hpmcounterh
},
4580 [CSR_HPMCOUNTER25H
] = { "hpmcounter25h", ctr32
, read_hpmcounterh
},
4581 [CSR_HPMCOUNTER26H
] = { "hpmcounter26h", ctr32
, read_hpmcounterh
},
4582 [CSR_HPMCOUNTER27H
] = { "hpmcounter27h", ctr32
, read_hpmcounterh
},
4583 [CSR_HPMCOUNTER28H
] = { "hpmcounter28h", ctr32
, read_hpmcounterh
},
4584 [CSR_HPMCOUNTER29H
] = { "hpmcounter29h", ctr32
, read_hpmcounterh
},
4585 [CSR_HPMCOUNTER30H
] = { "hpmcounter30h", ctr32
, read_hpmcounterh
},
4586 [CSR_HPMCOUNTER31H
] = { "hpmcounter31h", ctr32
, read_hpmcounterh
},
4588 [CSR_MHPMCOUNTER3H
] = { "mhpmcounter3h", mctr32
, read_hpmcounterh
,
4589 write_mhpmcounterh
},
4590 [CSR_MHPMCOUNTER4H
] = { "mhpmcounter4h", mctr32
, read_hpmcounterh
,
4591 write_mhpmcounterh
},
4592 [CSR_MHPMCOUNTER5H
] = { "mhpmcounter5h", mctr32
, read_hpmcounterh
,
4593 write_mhpmcounterh
},
4594 [CSR_MHPMCOUNTER6H
] = { "mhpmcounter6h", mctr32
, read_hpmcounterh
,
4595 write_mhpmcounterh
},
4596 [CSR_MHPMCOUNTER7H
] = { "mhpmcounter7h", mctr32
, read_hpmcounterh
,
4597 write_mhpmcounterh
},
4598 [CSR_MHPMCOUNTER8H
] = { "mhpmcounter8h", mctr32
, read_hpmcounterh
,
4599 write_mhpmcounterh
},
4600 [CSR_MHPMCOUNTER9H
] = { "mhpmcounter9h", mctr32
, read_hpmcounterh
,
4601 write_mhpmcounterh
},
4602 [CSR_MHPMCOUNTER10H
] = { "mhpmcounter10h", mctr32
, read_hpmcounterh
,
4603 write_mhpmcounterh
},
4604 [CSR_MHPMCOUNTER11H
] = { "mhpmcounter11h", mctr32
, read_hpmcounterh
,
4605 write_mhpmcounterh
},
4606 [CSR_MHPMCOUNTER12H
] = { "mhpmcounter12h", mctr32
, read_hpmcounterh
,
4607 write_mhpmcounterh
},
4608 [CSR_MHPMCOUNTER13H
] = { "mhpmcounter13h", mctr32
, read_hpmcounterh
,
4609 write_mhpmcounterh
},
4610 [CSR_MHPMCOUNTER14H
] = { "mhpmcounter14h", mctr32
, read_hpmcounterh
,
4611 write_mhpmcounterh
},
4612 [CSR_MHPMCOUNTER15H
] = { "mhpmcounter15h", mctr32
, read_hpmcounterh
,
4613 write_mhpmcounterh
},
4614 [CSR_MHPMCOUNTER16H
] = { "mhpmcounter16h", mctr32
, read_hpmcounterh
,
4615 write_mhpmcounterh
},
4616 [CSR_MHPMCOUNTER17H
] = { "mhpmcounter17h", mctr32
, read_hpmcounterh
,
4617 write_mhpmcounterh
},
4618 [CSR_MHPMCOUNTER18H
] = { "mhpmcounter18h", mctr32
, read_hpmcounterh
,
4619 write_mhpmcounterh
},
4620 [CSR_MHPMCOUNTER19H
] = { "mhpmcounter19h", mctr32
, read_hpmcounterh
,
4621 write_mhpmcounterh
},
4622 [CSR_MHPMCOUNTER20H
] = { "mhpmcounter20h", mctr32
, read_hpmcounterh
,
4623 write_mhpmcounterh
},
4624 [CSR_MHPMCOUNTER21H
] = { "mhpmcounter21h", mctr32
, read_hpmcounterh
,
4625 write_mhpmcounterh
},
4626 [CSR_MHPMCOUNTER22H
] = { "mhpmcounter22h", mctr32
, read_hpmcounterh
,
4627 write_mhpmcounterh
},
4628 [CSR_MHPMCOUNTER23H
] = { "mhpmcounter23h", mctr32
, read_hpmcounterh
,
4629 write_mhpmcounterh
},
4630 [CSR_MHPMCOUNTER24H
] = { "mhpmcounter24h", mctr32
, read_hpmcounterh
,
4631 write_mhpmcounterh
},
4632 [CSR_MHPMCOUNTER25H
] = { "mhpmcounter25h", mctr32
, read_hpmcounterh
,
4633 write_mhpmcounterh
},
4634 [CSR_MHPMCOUNTER26H
] = { "mhpmcounter26h", mctr32
, read_hpmcounterh
,
4635 write_mhpmcounterh
},
4636 [CSR_MHPMCOUNTER27H
] = { "mhpmcounter27h", mctr32
, read_hpmcounterh
,
4637 write_mhpmcounterh
},
4638 [CSR_MHPMCOUNTER28H
] = { "mhpmcounter28h", mctr32
, read_hpmcounterh
,
4639 write_mhpmcounterh
},
4640 [CSR_MHPMCOUNTER29H
] = { "mhpmcounter29h", mctr32
, read_hpmcounterh
,
4641 write_mhpmcounterh
},
4642 [CSR_MHPMCOUNTER30H
] = { "mhpmcounter30h", mctr32
, read_hpmcounterh
,
4643 write_mhpmcounterh
},
4644 [CSR_MHPMCOUNTER31H
] = { "mhpmcounter31h", mctr32
, read_hpmcounterh
,
4645 write_mhpmcounterh
},
4646 [CSR_SCOUNTOVF
] = { "scountovf", sscofpmf
, read_scountovf
,
4647 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4649 #endif /* !CONFIG_USER_ONLY */