target/riscv/insn16.decode

   1 #
   2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3 #
   4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5 #                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6 #
   7 # This program is free software; you can redistribute it and/or modify it
   8 # under the terms and conditions of the GNU General Public License,
   9 # version 2 or later, as published by the Free Software Foundation.
  10 #
  11 # This program is distributed in the hope it will be useful, but WITHOUT
  12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 # more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along with
  17 # this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19 # Fields:
  20 %rd        7:5
  21 %rs1_3     7:3                !function=ex_rvc_register
  22 %rs2_3     2:3                !function=ex_rvc_register
  23 %rs2_5     2:5
  24
  25 # Immediates:
  26 %imm_ci        12:s1 2:5
  27 %nzuimm_ciw    7:4 11:2 5:1 6:1   !function=ex_shift_2
  28 %uimm_cl_q     10:1 5:2 11:2      !function=ex_shift_4
  29 %uimm_cl_d     5:2 10:3           !function=ex_shift_3
  30 %uimm_cl_w     5:1 10:3 6:1       !function=ex_shift_2
  31 %imm_cb        12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
  32 %imm_cj        12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
  33
  34 %shimm_6bit   12:1 2:5               !function=ex_rvc_shifti
  35 %uimm_6bit_lq 2:4 12:1 6:1           !function=ex_shift_4
  36 %uimm_6bit_ld 2:3 12:1 5:2           !function=ex_shift_3
  37 %uimm_6bit_lw 2:2 12:1 4:3           !function=ex_shift_2
  38 %uimm_6bit_sq 7:4 11:2               !function=ex_shift_4
  39 %uimm_6bit_sd 7:3 10:3               !function=ex_shift_3
  40 %uimm_6bit_sw 7:2 9:4                !function=ex_shift_2
  41
  42 %imm_addi16sp  12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
  43 %imm_lui       12:s1 2:5             !function=ex_shift_12
  44
  45
  46 # Argument sets imported from insn32.decode:
  47 &empty                  !extern
  48 &r         rd rs1 rs2   !extern
  49 &i         imm rs1 rd   !extern
  50 &s         imm rs1 rs2  !extern
  51 &j         imm rd       !extern
  52 &b         imm rs2 rs1  !extern
  53 &u         imm rd       !extern
  54 &shift     shamt rs1 rd !extern
  55
  56
  57 # Formats 16:
  58 @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
  59 @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
  60 @cl_q      ... . .....  ..... .. &i      imm=%uimm_cl_q   rs1=%rs1_3  rd=%rs2_3
  61 @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
  62 @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
  63 @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
  64 @cs_q      ... ... ... .. ... .. &s      imm=%uimm_cl_q   rs1=%rs1_3  rs2=%rs2_3
  65 @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
  66 @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
  67 @cj        ...    ........... .. &j      imm=%imm_cj
  68 @cb_z      ... ... ... .. ... .. &b      imm=%imm_cb      rs1=%rs1_3  rs2=0
  69
  70 @c_lqsp    ... . .....  ..... .. &i      imm=%uimm_6bit_lq rs1=2 %rd
  71 @c_ldsp    ... . .....  ..... .. &i      imm=%uimm_6bit_ld rs1=2 %rd
  72 @c_lwsp    ... . .....  ..... .. &i      imm=%uimm_6bit_lw rs1=2 %rd
  73 @c_sqsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sq rs1=2 rs2=%rs2_5
  74 @c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
  75 @c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
  76 @c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
  77 @c_lui     ... . .....  ..... .. &u      imm=%imm_lui %rd
  78 @c_jalr    ... . .....  ..... .. &i      imm=0 rs1=%rd
  79 @c_mv      ... . ..... .....  .. &i      imm=0 rs1=%rs2_5 %rd
  80
  81 @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
  82 @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
  83
  84 @c_shift        ... . .. ... ..... .. \
  85                 &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
  86 @c_shift2       ... . .. ... ..... .. \
  87                 &shift rd=%rd rs1=%rd shamt=%shimm_6bit
  88
  89 @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
  90
  91 # *** RV32/64C Standard Extension (Quadrant 0) ***
  92 {
  93   # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
  94   illegal         000  000 000 00 --- 00
  95   addi            000  ... ... .. ... 00 @c_addi4spn
  96 }
  97 {
  98   lq              001  ... ... .. ... 00 @cl_q
  99   fld             001  ... ... .. ... 00 @cl_d
 100 }
 101 lw                010  ... ... .. ... 00 @cl_w
 102 {
 103   sq              101  ... ... .. ... 00 @cs_q
 104   fsd             101  ... ... .. ... 00 @cs_d
 105 }
 106 sw                110  ... ... .. ... 00 @cs_w
 107
 108 # *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
 109 {
 110   ld              011  ... ... .. ... 00 @cl_d
 111   flw             011  ... ... .. ... 00 @cl_w
 112 }
 113 {
 114   sd              111  ... ... .. ... 00 @cs_d
 115   fsw             111  ... ... .. ... 00 @cs_w
 116 }
 117
 118 # *** RV32/64C Standard Extension (Quadrant 1) ***
 119 addi              000 .  .....  ..... 01 @ci
 120 addi              010 .  .....  ..... 01 @c_li
 121 {
 122   illegal         011 0  -----  00000 01 # c.addi16sp and c.lui, RES nzimm=0
 123   addi            011 .  00010  ..... 01 @c_addi16sp
 124   lui             011 .  .....  ..... 01 @c_lui
 125 }
 126 srli              100 . 00 ...  ..... 01 @c_shift
 127 srai              100 . 01 ...  ..... 01 @c_shift
 128 andi              100 . 10 ...  ..... 01 @c_andi
 129 sub               100 0 11 ... 00 ... 01 @cs_2
 130 xor               100 0 11 ... 01 ... 01 @cs_2
 131 or                100 0 11 ... 10 ... 01 @cs_2
 132 and               100 0 11 ... 11 ... 01 @cs_2
 133 jal               101     ........... 01 @cj    rd=0  # C.J
 134 beq               110  ... ...  ..... 01 @cb_z
 135 bne               111  ... ...  ..... 01 @cb_z
 136
 137 # *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
 138 {
 139   c64_illegal     001 -  00000  ----- 01 # c.addiw, RES rd=0
 140   addiw           001 .  .....  ..... 01 @ci
 141   jal             001     ........... 01 @cj    rd=1  # C.JAL
 142 }
 143 subw              100 1 11 ... 00 ... 01 @cs_2
 144 addw              100 1 11 ... 01 ... 01 @cs_2
 145
 146 # *** RV32/64C Standard Extension (Quadrant 2) ***
 147 slli              000 .  .....  ..... 10 @c_shift2
 148 {
 149   lq              001  ... ... .. ... 10 @c_lqsp
 150   fld             001 .  .....  ..... 10 @c_ldsp
 151 }
 152 {
 153   illegal         010 -  00000  ----- 10 # c.lwsp, RES rd=0
 154   lw              010 .  .....  ..... 10 @c_lwsp
 155 }
 156 {
 157   illegal         100 0  00000  00000 10 # c.jr, RES rs1=0
 158   jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
 159   addi            100 0  .....  ..... 10 @c_mv
 160 }
 161 {
 162   ebreak          100 1  00000  00000 10
 163   jalr            100 1  .....  00000 10 @c_jalr rd=1  # C.JALR
 164   add             100 1  .....  ..... 10 @cr
 165 }
 166 {
 167   sq              101  ... ... .. ... 10 @c_sqsp
 168   fsd             101   ......  ..... 10 @c_sdsp
 169 }
 170 sw                110 .  .....  ..... 10 @c_swsp
 171
 172 # *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
 173 {
 174   c64_illegal     011 -  00000  ----- 10 # c.ldsp, RES rd=0
 175   ld              011 .  .....  ..... 10 @c_ldsp
 176   flw             011 .  .....  ..... 10 @c_lwsp
 177 }
 178 {
 179   sd              111 .  .....  ..... 10 @c_sdsp
 180   fsw             111 .  .....  ..... 10 @c_swsp
 181 }