target/riscv/insn16.decode

   1 #
   2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3 #
   4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5 #                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6 #
   7 # This program is free software; you can redistribute it and/or modify it
   8 # under the terms and conditions of the GNU General Public License,
   9 # version 2 or later, as published by the Free Software Foundation.
  10 #
  11 # This program is distributed in the hope it will be useful, but WITHOUT
  12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 # more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along with
  17 # this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19 # Fields:
  20 %rd        7:5
  21 %rs1_3     7:3                !function=ex_rvc_register
  22 %rs2_3     2:3                !function=ex_rvc_register
  23 %rs2_5     2:5
  24
  25 # Immediates:
  26 %imm_ci        12:s1 2:5
  27 %nzuimm_ciw    7:4 11:2 5:1 6:1   !function=ex_shift_2
  28 %uimm_cl_d     5:2 10:3           !function=ex_shift_3
  29 %uimm_cl_w     5:1 10:3 6:1       !function=ex_shift_2
  30 %imm_cb        12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
  31 %imm_cj        12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
  32
  33 %nzuimm_6bit   12:1 2:5
  34 %uimm_6bit_ld 2:3 12:1 5:2           !function=ex_shift_3
  35 %uimm_6bit_lw 2:2 12:1 4:3           !function=ex_shift_2
  36 %uimm_6bit_sd 7:3 10:3               !function=ex_shift_3
  37 %uimm_6bit_sw 7:2 9:4                !function=ex_shift_2
  38
  39 %imm_addi16sp  12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
  40 %imm_lui       12:s1 2:5             !function=ex_shift_12
  41
  42
  43
  44 # Argument sets:
  45 &cl               rs1 rd
  46 &cl_dw     uimm   rs1 rd
  47 &ci        imm        rd
  48 &ciw       nzuimm     rd
  49 &cs               rs1 rs2
  50 &cs_dw     uimm   rs1 rs2
  51 &cb        imm    rs1
  52 &cr               rd  rs2
  53 &cj       imm
  54 &c_shift   shamt      rd
  55
  56 &c_ld      uimm  rd
  57 &c_sd      uimm  rs2
  58
  59 &caddi16sp_lui  imm_lui imm_addi16sp rd
  60 &cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
  61 &cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
  62
  63 # Formats 16:
  64 @cr        ....  ..... .....  .. &cr                      rs2=%rs2_5  %rd
  65 @ci        ... . ..... .....  .. &ci     imm=%imm_ci                  %rd
  66 @ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
  67 @cl_d      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
  68 @cl_w      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
  69 @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
  70 @cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
  71 @cs_2      ... ... ... .. ... .. &cr                      rd=%rs1_3   rs2=%rs2_3
  72 @cs_d      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
  73 @cs_w      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
  74 @cb        ... ... ... .. ... .. &cb     imm=%imm_cb      rs1=%rs1_3
  75 @cj        ...    ........... .. &cj     imm=%imm_cj
  76
  77 @c_ld      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_ld  %rd
  78 @c_lw      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_lw  %rd
  79 @c_sd      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sd  rs2=%rs2_5
  80 @c_sw      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sw  rs2=%rs2_5
  81
  82 @c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
  83 @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
  84     uimm_ldsp=%uimm_6bit_ld %rd
  85 @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
  86     uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
  87
  88 @c_shift        ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
  89 @c_shift2       ... . .. ... ..... .. &c_shift rd=%rd    shamt=%nzuimm_6bit
  90
  91 @c_andi         ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
  92
  93 # *** RV64C Standard Extension (Quadrant 0) ***
  94 c_addi4spn        000    ........ ... 00 @ciw
  95 c_fld             001  ... ... .. ... 00 @cl_d
  96 c_lw              010  ... ... .. ... 00 @cl_w
  97 c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
  98 c_fsd             101  ... ... .. ... 00 @cs_d
  99 c_sw              110  ... ... .. ... 00 @cs_w
 100 c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
 101
 102 # *** RV64C Standard Extension (Quadrant 1) ***
 103 c_addi            000 .  .....  ..... 01 @ci
 104 c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
 105 c_li              010 .  .....  ..... 01 @ci
 106 c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
 107 c_srli            100 . 00 ...  ..... 01 @c_shift
 108 c_srai            100 . 01 ...  ..... 01 @c_shift
 109 c_andi            100 . 10 ...  ..... 01 @c_andi
 110 c_sub             100 0 11 ... 00 ... 01 @cs_2
 111 c_xor             100 0 11 ... 01 ... 01 @cs_2
 112 c_or              100 0 11 ... 10 ... 01 @cs_2
 113 c_and             100 0 11 ... 11 ... 01 @cs_2
 114 c_subw            100 1 11 ... 00 ... 01 @cs_2
 115 c_addw            100 1 11 ... 01 ... 01 @cs_2
 116 c_j               101     ........... 01 @cj
 117 c_beqz            110  ... ...  ..... 01 @cb
 118 c_bnez            111  ... ...  ..... 01 @cb
 119
 120 # *** RV64C Standard Extension (Quadrant 2) ***
 121 c_slli            000 .  .....  ..... 10 @c_shift2
 122 c_fldsp           001 .  .....  ..... 10 @c_ld
 123 c_lwsp            010 .  .....  ..... 10 @c_lw
 124 c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
 125 c_jr_mv           100 0  .....  ..... 10 @cr
 126 c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
 127 c_fsdsp           101   ......  ..... 10 @c_sd
 128 c_swsp            110 .  .....  ..... 10 @c_sw
 129 c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32