target/riscv/insn32.decode

   1 #
   2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3 #
   4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5 #                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6 #
   7 # This program is free software; you can redistribute it and/or modify it
   8 # under the terms and conditions of the GNU General Public License,
   9 # version 2 or later, as published by the Free Software Foundation.
  10 #
  11 # This program is distributed in the hope it will be useful, but WITHOUT
  12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 # more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along with
  17 # this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19 # Fields:
  20 %rs3       27:5
  21 %rs2       20:5
  22 %rs1       15:5
  23 %rd        7:5
  24
  25 %sh10    20:10
  26 %csr    20:12
  27 %rm     12:3
  28
  29 # immediates:
  30 %imm_i    20:s12
  31 %imm_s    25:s7 7:5
  32 %imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
  33 %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
  34 %imm_u    12:s20                 !function=ex_shift_12
  35
  36 # Argument sets:
  37 &empty
  38 &b    imm rs2 rs1
  39 &i    imm rs1 rd
  40 &j    imm rd
  41 &r    rd rs1 rs2
  42 &s    imm rs1 rs2
  43 &u    imm rd
  44 &shift     shamt rs1 rd
  45 &atomic    aq rl rs2 rs1 rd
  46
  47 # Formats 32:
  48 @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
  49 @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
  50 @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
  51 @s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
  52 @u       ....................      ..... ....... &u      imm=%imm_u          %rd
  53 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
  54
  55 @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
  56 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
  57
  58 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
  59 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd
  60
  61 @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  62 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  63 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
  64 @r2      .......   ..... ..... ... ..... ....... %rs1 %rd
  65
  66 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
  67 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
  68
  69
  70 # *** Privileged Instructions ***
  71 ecall      000000000000     00000 000 00000 1110011
  72 ebreak     000000000001     00000 000 00000 1110011
  73 uret       0000000    00010 00000 000 00000 1110011
  74 sret       0001000    00010 00000 000 00000 1110011
  75 hret       0010000    00010 00000 000 00000 1110011
  76 mret       0011000    00010 00000 000 00000 1110011
  77 wfi        0001000    00101 00000 000 00000 1110011
  78 sfence_vma 0001001    ..... ..... 000 00000 1110011 @sfence_vma
  79 sfence_vm  0001000    00100 ..... 000 00000 1110011 @sfence_vm
  80
  81 # *** RV32I Base Instruction Set ***
  82 lui      ....................       ..... 0110111 @u
  83 auipc    ....................       ..... 0010111 @u
  84 jal      ....................       ..... 1101111 @j
  85 jalr     ............     ..... 000 ..... 1100111 @i
  86 beq      ....... .....    ..... 000 ..... 1100011 @b
  87 bne      ....... .....    ..... 001 ..... 1100011 @b
  88 blt      ....... .....    ..... 100 ..... 1100011 @b
  89 bge      ....... .....    ..... 101 ..... 1100011 @b
  90 bltu     ....... .....    ..... 110 ..... 1100011 @b
  91 bgeu     ....... .....    ..... 111 ..... 1100011 @b
  92 lb       ............     ..... 000 ..... 0000011 @i
  93 lh       ............     ..... 001 ..... 0000011 @i
  94 lw       ............     ..... 010 ..... 0000011 @i
  95 lbu      ............     ..... 100 ..... 0000011 @i
  96 lhu      ............     ..... 101 ..... 0000011 @i
  97 sb       .......  .....   ..... 000 ..... 0100011 @s
  98 sh       .......  .....   ..... 001 ..... 0100011 @s
  99 sw       .......  .....   ..... 010 ..... 0100011 @s
 100 addi     ............     ..... 000 ..... 0010011 @i
 101 slti     ............     ..... 010 ..... 0010011 @i
 102 sltiu    ............     ..... 011 ..... 0010011 @i
 103 xori     ............     ..... 100 ..... 0010011 @i
 104 ori      ............     ..... 110 ..... 0010011 @i
 105 andi     ............     ..... 111 ..... 0010011 @i
 106 slli     00.... ......    ..... 001 ..... 0010011 @sh
 107 srli     00.... ......    ..... 101 ..... 0010011 @sh
 108 srai     01.... ......    ..... 101 ..... 0010011 @sh
 109 add      0000000 .....    ..... 000 ..... 0110011 @r
 110 sub      0100000 .....    ..... 000 ..... 0110011 @r
 111 sll      0000000 .....    ..... 001 ..... 0110011 @r
 112 slt      0000000 .....    ..... 010 ..... 0110011 @r
 113 sltu     0000000 .....    ..... 011 ..... 0110011 @r
 114 xor      0000000 .....    ..... 100 ..... 0110011 @r
 115 srl      0000000 .....    ..... 101 ..... 0110011 @r
 116 sra      0100000 .....    ..... 101 ..... 0110011 @r
 117 or       0000000 .....    ..... 110 ..... 0110011 @r
 118 and      0000000 .....    ..... 111 ..... 0110011 @r
 119 fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
 120 fence_i  ---- ----   ----   ----- 001 ----- 0001111
 121 csrrw    ............     ..... 001 ..... 1110011 @csr
 122 csrrs    ............     ..... 010 ..... 1110011 @csr
 123 csrrc    ............     ..... 011 ..... 1110011 @csr
 124 csrrwi   ............     ..... 101 ..... 1110011 @csr
 125 csrrsi   ............     ..... 110 ..... 1110011 @csr
 126 csrrci   ............     ..... 111 ..... 1110011 @csr
 127
 128 # *** RV32M Standard Extension ***
 129 mul      0000001 .....  ..... 000 ..... 0110011 @r
 130 mulh     0000001 .....  ..... 001 ..... 0110011 @r
 131 mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
 132 mulhu    0000001 .....  ..... 011 ..... 0110011 @r
 133 div      0000001 .....  ..... 100 ..... 0110011 @r
 134 divu     0000001 .....  ..... 101 ..... 0110011 @r
 135 rem      0000001 .....  ..... 110 ..... 0110011 @r
 136 remu     0000001 .....  ..... 111 ..... 0110011 @r
 137
 138 # *** RV32A Standard Extension ***
 139 lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
 140 sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
 141 amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
 142 amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
 143 amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
 144 amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
 145 amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
 146 amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
 147 amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
 148 amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
 149 amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 150
 151 # *** RV32F Standard Extension ***
 152 flw        ............   ..... 010 ..... 0000111 @i
 153 fsw        .......  ..... ..... 010 ..... 0100111 @s
 154 fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
 155 fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
 156 fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
 157 fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
 158 fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
 159 fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
 160 fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
 161 fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
 162 fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
 163 fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
 164 fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
 165 fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
 166 fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
 167 fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
 168 fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
 169 fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
 170 fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
 171 feq_s      1010000  ..... ..... 010 ..... 1010011 @r
 172 flt_s      1010000  ..... ..... 001 ..... 1010011 @r
 173 fle_s      1010000  ..... ..... 000 ..... 1010011 @r
 174 fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
 175 fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 176 fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 177 fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 178
 179 # *** RV32D Standard Extension ***
 180 fld        ............   ..... 011 ..... 0000111 @i
 181 fsd        ....... .....  ..... 011 ..... 0100111 @s
 182 fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
 183 fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
 184 fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
 185 fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
 186 fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
 187 fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
 188 fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
 189 fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
 190 fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
 191 fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
 192 fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
 193 fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
 194 fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
 195 fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
 196 fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
 197 fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
 198 feq_d      1010001  ..... ..... 010 ..... 1010011 @r
 199 flt_d      1010001  ..... ..... 001 ..... 1010011 @r
 200 fle_d      1010001  ..... ..... 000 ..... 1010011 @r
 201 fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
 202 fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
 203 fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 204 fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 205 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm