target/riscv/insn32.decode

   1 #
   2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3 #
   4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5 #                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6 #
   7 # This program is free software; you can redistribute it and/or modify it
   8 # under the terms and conditions of the GNU General Public License,
   9 # version 2 or later, as published by the Free Software Foundation.
  10 #
  11 # This program is distributed in the hope it will be useful, but WITHOUT
  12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 # more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along with
  17 # this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19 # Fields:
  20 %rs3       27:5
  21 %rs2       20:5
  22 %rs1       15:5
  23 %rd        7:5
  24
  25 %sh10    20:10
  26 %csr    20:12
  27 %rm     12:3
  28 %nf     29:3                     !function=ex_plus_1
  29
  30 # immediates:
  31 %imm_i    20:s12
  32 %imm_s    25:s7 7:5
  33 %imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
  34 %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
  35 %imm_u    12:s20                 !function=ex_shift_12
  36
  37 # Argument sets:
  38 &empty
  39 &b    imm rs2 rs1
  40 &i    imm rs1 rd
  41 &j    imm rd
  42 &r    rd rs1 rs2
  43 &s    imm rs1 rs2
  44 &u    imm rd
  45 &shift     shamt rs1 rd
  46 &atomic    aq rl rs2 rs1 rd
  47 &rmrr      vm rd rs1 rs2
  48 &rwdvm     vm wd rd rs1 rs2
  49 &r2nfvm    vm rd rs1 nf
  50 &rnfvm     vm rd rs1 rs2 nf
  51
  52 # Formats 32:
  53 @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
  54 @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
  55 @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
  56 @s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
  57 @u       ....................      ..... ....... &u      imm=%imm_u          %rd
  58 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
  59
  60 @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
  61 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
  62
  63 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
  64 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd
  65
  66 @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  67 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  68 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
  69 @r2      .......   ..... ..... ... ..... ....... %rs1 %rd
  70 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
  71 @r_nfvm  ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
  72 @r_vm    ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
  73 @r_vm_1  ...... . ..... ..... ... ..... .......    &rmrr vm=1 %rs2 %rs1 %rd
  74 @r_wdvm  ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
  75 @r2_zimm . zimm:11  ..... ... ..... ....... %rs1 %rd
  76
  77 @hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  78 @hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  79
  80 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
  81 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
  82
  83
  84 # *** Privileged Instructions ***
  85 ecall       000000000000     00000 000 00000 1110011
  86 ebreak      000000000001     00000 000 00000 1110011
  87 uret        0000000    00010 00000 000 00000 1110011
  88 sret        0001000    00010 00000 000 00000 1110011
  89 mret        0011000    00010 00000 000 00000 1110011
  90 wfi         0001000    00101 00000 000 00000 1110011
  91 sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
  92 sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
  93
  94 # *** RV32I Base Instruction Set ***
  95 lui      ....................       ..... 0110111 @u
  96 auipc    ....................       ..... 0010111 @u
  97 jal      ....................       ..... 1101111 @j
  98 jalr     ............     ..... 000 ..... 1100111 @i
  99 beq      ....... .....    ..... 000 ..... 1100011 @b
 100 bne      ....... .....    ..... 001 ..... 1100011 @b
 101 blt      ....... .....    ..... 100 ..... 1100011 @b
 102 bge      ....... .....    ..... 101 ..... 1100011 @b
 103 bltu     ....... .....    ..... 110 ..... 1100011 @b
 104 bgeu     ....... .....    ..... 111 ..... 1100011 @b
 105 lb       ............     ..... 000 ..... 0000011 @i
 106 lh       ............     ..... 001 ..... 0000011 @i
 107 lw       ............     ..... 010 ..... 0000011 @i
 108 lbu      ............     ..... 100 ..... 0000011 @i
 109 lhu      ............     ..... 101 ..... 0000011 @i
 110 sb       .......  .....   ..... 000 ..... 0100011 @s
 111 sh       .......  .....   ..... 001 ..... 0100011 @s
 112 sw       .......  .....   ..... 010 ..... 0100011 @s
 113 addi     ............     ..... 000 ..... 0010011 @i
 114 slti     ............     ..... 010 ..... 0010011 @i
 115 sltiu    ............     ..... 011 ..... 0010011 @i
 116 xori     ............     ..... 100 ..... 0010011 @i
 117 ori      ............     ..... 110 ..... 0010011 @i
 118 andi     ............     ..... 111 ..... 0010011 @i
 119 slli     00.... ......    ..... 001 ..... 0010011 @sh
 120 srli     00.... ......    ..... 101 ..... 0010011 @sh
 121 srai     01.... ......    ..... 101 ..... 0010011 @sh
 122 add      0000000 .....    ..... 000 ..... 0110011 @r
 123 sub      0100000 .....    ..... 000 ..... 0110011 @r
 124 sll      0000000 .....    ..... 001 ..... 0110011 @r
 125 slt      0000000 .....    ..... 010 ..... 0110011 @r
 126 sltu     0000000 .....    ..... 011 ..... 0110011 @r
 127 xor      0000000 .....    ..... 100 ..... 0110011 @r
 128 srl      0000000 .....    ..... 101 ..... 0110011 @r
 129 sra      0100000 .....    ..... 101 ..... 0110011 @r
 130 or       0000000 .....    ..... 110 ..... 0110011 @r
 131 and      0000000 .....    ..... 111 ..... 0110011 @r
 132 fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
 133 fence_i  ---- ----   ----   ----- 001 ----- 0001111
 134 csrrw    ............     ..... 001 ..... 1110011 @csr
 135 csrrs    ............     ..... 010 ..... 1110011 @csr
 136 csrrc    ............     ..... 011 ..... 1110011 @csr
 137 csrrwi   ............     ..... 101 ..... 1110011 @csr
 138 csrrsi   ............     ..... 110 ..... 1110011 @csr
 139 csrrci   ............     ..... 111 ..... 1110011 @csr
 140
 141 # *** RV32M Standard Extension ***
 142 mul      0000001 .....  ..... 000 ..... 0110011 @r
 143 mulh     0000001 .....  ..... 001 ..... 0110011 @r
 144 mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
 145 mulhu    0000001 .....  ..... 011 ..... 0110011 @r
 146 div      0000001 .....  ..... 100 ..... 0110011 @r
 147 divu     0000001 .....  ..... 101 ..... 0110011 @r
 148 rem      0000001 .....  ..... 110 ..... 0110011 @r
 149 remu     0000001 .....  ..... 111 ..... 0110011 @r
 150
 151 # *** RV32A Standard Extension ***
 152 lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
 153 sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
 154 amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
 155 amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
 156 amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
 157 amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
 158 amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
 159 amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
 160 amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
 161 amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
 162 amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 163
 164 # *** RV32F Standard Extension ***
 165 flw        ............   ..... 010 ..... 0000111 @i
 166 fsw        .......  ..... ..... 010 ..... 0100111 @s
 167 fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
 168 fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
 169 fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
 170 fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
 171 fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
 172 fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
 173 fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
 174 fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
 175 fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
 176 fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
 177 fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
 178 fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
 179 fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
 180 fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
 181 fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
 182 fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
 183 fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
 184 feq_s      1010000  ..... ..... 010 ..... 1010011 @r
 185 flt_s      1010000  ..... ..... 001 ..... 1010011 @r
 186 fle_s      1010000  ..... ..... 000 ..... 1010011 @r
 187 fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
 188 fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 189 fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 190 fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 191
 192 # *** RV32D Standard Extension ***
 193 fld        ............   ..... 011 ..... 0000111 @i
 194 fsd        ....... .....  ..... 011 ..... 0100111 @s
 195 fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
 196 fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
 197 fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
 198 fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
 199 fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
 200 fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
 201 fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
 202 fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
 203 fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
 204 fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
 205 fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
 206 fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
 207 fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
 208 fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
 209 fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
 210 fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
 211 feq_d      1010001  ..... ..... 010 ..... 1010011 @r
 212 flt_d      1010001  ..... ..... 001 ..... 1010011 @r
 213 fle_d      1010001  ..... ..... 000 ..... 1010011 @r
 214 fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
 215 fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
 216 fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 217 fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 218 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 219
 220 # *** RV32H Base Instruction Set ***
 221 hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
 222 hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 223
 224 # *** RV32V Extension ***
 225
 226 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
 227 vlb_v      ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
 228 vlh_v      ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
 229 vlw_v      ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
 230 vle_v      ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
 231 vlbu_v     ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
 232 vlhu_v     ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
 233 vlwu_v     ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
 234 vlbff_v    ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
 235 vlhff_v    ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
 236 vlwff_v    ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
 237 vleff_v    ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
 238 vlbuff_v   ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
 239 vlhuff_v   ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
 240 vlwuff_v   ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
 241 vsb_v      ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
 242 vsh_v      ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
 243 vsw_v      ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
 244 vse_v      ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
 245
 246 vlsb_v     ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
 247 vlsh_v     ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
 248 vlsw_v     ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
 249 vlse_v     ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
 250 vlsbu_v    ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
 251 vlshu_v    ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
 252 vlswu_v    ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
 253 vssb_v     ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
 254 vssh_v     ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
 255 vssw_v     ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
 256 vsse_v     ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
 257
 258 vlxb_v     ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
 259 vlxh_v     ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
 260 vlxw_v     ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
 261 vlxe_v     ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
 262 vlxbu_v    ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
 263 vlxhu_v    ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
 264 vlxwu_v    ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
 265 # Vector ordered-indexed and unordered-indexed store insns.
 266 vsxb_v     ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
 267 vsxh_v     ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
 268 vsxw_v     ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
 269 vsxe_v     ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
 270
 271 #*** Vector AMO operations are encoded under the standard AMO major opcode ***
 272 vamoswapw_v     00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
 273 vamoaddw_v      00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
 274 vamoxorw_v      00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
 275 vamoandw_v      01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
 276 vamoorw_v       01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
 277 vamominw_v      10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
 278 vamomaxw_v      10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
 279 vamominuw_v     11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
 280 vamomaxuw_v     11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
 281
 282 # *** new major opcode OP-V ***
 283 vadd_vv         000000 . ..... ..... 000 ..... 1010111 @r_vm
 284 vadd_vx         000000 . ..... ..... 100 ..... 1010111 @r_vm
 285 vadd_vi         000000 . ..... ..... 011 ..... 1010111 @r_vm
 286 vsub_vv         000010 . ..... ..... 000 ..... 1010111 @r_vm
 287 vsub_vx         000010 . ..... ..... 100 ..... 1010111 @r_vm
 288 vrsub_vx        000011 . ..... ..... 100 ..... 1010111 @r_vm
 289 vrsub_vi        000011 . ..... ..... 011 ..... 1010111 @r_vm
 290 vwaddu_vv       110000 . ..... ..... 010 ..... 1010111 @r_vm
 291 vwaddu_vx       110000 . ..... ..... 110 ..... 1010111 @r_vm
 292 vwadd_vv        110001 . ..... ..... 010 ..... 1010111 @r_vm
 293 vwadd_vx        110001 . ..... ..... 110 ..... 1010111 @r_vm
 294 vwsubu_vv       110010 . ..... ..... 010 ..... 1010111 @r_vm
 295 vwsubu_vx       110010 . ..... ..... 110 ..... 1010111 @r_vm
 296 vwsub_vv        110011 . ..... ..... 010 ..... 1010111 @r_vm
 297 vwsub_vx        110011 . ..... ..... 110 ..... 1010111 @r_vm
 298 vwaddu_wv       110100 . ..... ..... 010 ..... 1010111 @r_vm
 299 vwaddu_wx       110100 . ..... ..... 110 ..... 1010111 @r_vm
 300 vwadd_wv        110101 . ..... ..... 010 ..... 1010111 @r_vm
 301 vwadd_wx        110101 . ..... ..... 110 ..... 1010111 @r_vm
 302 vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
 303 vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
 304 vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
 305 vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
 306 vadc_vvm        010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
 307 vadc_vxm        010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
 308 vadc_vim        010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
 309 vmadc_vvm       010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
 310 vmadc_vxm       010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
 311 vmadc_vim       010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
 312 vsbc_vvm        010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
 313 vsbc_vxm        010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
 314 vmsbc_vvm       010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
 315 vmsbc_vxm       010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
 316 vand_vv         001001 . ..... ..... 000 ..... 1010111 @r_vm
 317 vand_vx         001001 . ..... ..... 100 ..... 1010111 @r_vm
 318 vand_vi         001001 . ..... ..... 011 ..... 1010111 @r_vm
 319 vor_vv          001010 . ..... ..... 000 ..... 1010111 @r_vm
 320 vor_vx          001010 . ..... ..... 100 ..... 1010111 @r_vm
 321 vor_vi          001010 . ..... ..... 011 ..... 1010111 @r_vm
 322 vxor_vv         001011 . ..... ..... 000 ..... 1010111 @r_vm
 323 vxor_vx         001011 . ..... ..... 100 ..... 1010111 @r_vm
 324 vxor_vi         001011 . ..... ..... 011 ..... 1010111 @r_vm
 325 vsll_vv         100101 . ..... ..... 000 ..... 1010111 @r_vm
 326 vsll_vx         100101 . ..... ..... 100 ..... 1010111 @r_vm
 327 vsll_vi         100101 . ..... ..... 011 ..... 1010111 @r_vm
 328 vsrl_vv         101000 . ..... ..... 000 ..... 1010111 @r_vm
 329 vsrl_vx         101000 . ..... ..... 100 ..... 1010111 @r_vm
 330 vsrl_vi         101000 . ..... ..... 011 ..... 1010111 @r_vm
 331 vsra_vv         101001 . ..... ..... 000 ..... 1010111 @r_vm
 332 vsra_vx         101001 . ..... ..... 100 ..... 1010111 @r_vm
 333 vsra_vi         101001 . ..... ..... 011 ..... 1010111 @r_vm
 334
 335 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 336 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r