target/riscv/insn32.decode

   1 #
   2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3 #
   4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5 #                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6 #
   7 # This program is free software; you can redistribute it and/or modify it
   8 # under the terms and conditions of the GNU General Public License,
   9 # version 2 or later, as published by the Free Software Foundation.
  10 #
  11 # This program is distributed in the hope it will be useful, but WITHOUT
  12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 # more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along with
  17 # this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19 # Fields:
  20 %rs3       27:5
  21 %rs2       20:5
  22 %rs1       15:5
  23 %rd        7:5
  24 %sh5       20:5
  25 %sh6       20:6
  26
  27 %sh7    20:7
  28 %csr    20:12
  29 %rm     12:3
  30 %nf     29:3                     !function=ex_plus_1
  31
  32 # immediates:
  33 %imm_i    20:s12
  34 %imm_s    25:s7 7:5
  35 %imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
  36 %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
  37 %imm_u    12:s20                 !function=ex_shift_12
  38
  39 # Argument sets:
  40 &empty
  41 &b    imm rs2 rs1
  42 &i    imm rs1 rd
  43 &j    imm rd
  44 &r    rd rs1 rs2
  45 &r2   rd rs1
  46 &r2_s rs1 rs2
  47 &s    imm rs1 rs2
  48 &u    imm rd
  49 &shift     shamt rs1 rd
  50 &atomic    aq rl rs2 rs1 rd
  51 &rmrr      vm rd rs1 rs2
  52 &rmr       vm rd rs2
  53 &r2nfvm    vm rd rs1 nf
  54 &rnfvm     vm rd rs1 rs2 nf
  55
  56 # Formats 32:
  57 @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
  58 @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
  59 @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
  60 @s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
  61 @u       ....................      ..... ....... &u      imm=%imm_u          %rd
  62 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
  63
  64 @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh7     %rs1 %rd
  65 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
  66
  67 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
  68 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd
  69
  70 @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  71 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  72 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
  73 @r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
  74 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
  75 @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
  76 @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
  77 @r_nfvm  ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
  78 @r2rd    .......   ..... ..... ... ..... ....... %rs2 %rd
  79 @r_vm    ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
  80 @r_vm_1  ...... . ..... ..... ... ..... .......    &rmrr vm=1 %rs2 %rs1 %rd
  81 @r_vm_0  ...... . ..... ..... ... ..... .......    &rmrr vm=0 %rs2 %rs1 %rd
  82 @r2_zimm11 . zimm:11  ..... ... ..... ....... %rs1 %rd
  83 @r2_zimm10 .. zimm:10  ..... ... ..... ....... %rs1 %rd
  84 @r2_s    .......   ..... ..... ... ..... ....... %rs2 %rs1
  85
  86 @hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  87 @hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  88
  89 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
  90 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
  91
  92 # Formats 64:
  93 @sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
  94
  95 # Formats 128:
  96 @sh6       ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
  97
  98 # *** Privileged Instructions ***
  99 ecall       000000000000     00000 000 00000 1110011
 100 ebreak      000000000001     00000 000 00000 1110011
 101 uret        0000000    00010 00000 000 00000 1110011
 102 sret        0001000    00010 00000 000 00000 1110011
 103 mret        0011000    00010 00000 000 00000 1110011
 104 wfi         0001000    00101 00000 000 00000 1110011
 105 sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
 106 sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
 107
 108 # *** RV32I Base Instruction Set ***
 109 lui      ....................       ..... 0110111 @u
 110 auipc    ....................       ..... 0010111 @u
 111 jal      ....................       ..... 1101111 @j
 112 jalr     ............     ..... 000 ..... 1100111 @i
 113 beq      ....... .....    ..... 000 ..... 1100011 @b
 114 bne      ....... .....    ..... 001 ..... 1100011 @b
 115 blt      ....... .....    ..... 100 ..... 1100011 @b
 116 bge      ....... .....    ..... 101 ..... 1100011 @b
 117 bltu     ....... .....    ..... 110 ..... 1100011 @b
 118 bgeu     ....... .....    ..... 111 ..... 1100011 @b
 119 lb       ............     ..... 000 ..... 0000011 @i
 120 lh       ............     ..... 001 ..... 0000011 @i
 121 lw       ............     ..... 010 ..... 0000011 @i
 122 lbu      ............     ..... 100 ..... 0000011 @i
 123 lhu      ............     ..... 101 ..... 0000011 @i
 124 sb       .......  .....   ..... 000 ..... 0100011 @s
 125 sh       .......  .....   ..... 001 ..... 0100011 @s
 126 sw       .......  .....   ..... 010 ..... 0100011 @s
 127 addi     ............     ..... 000 ..... 0010011 @i
 128 slti     ............     ..... 010 ..... 0010011 @i
 129 sltiu    ............     ..... 011 ..... 0010011 @i
 130 xori     ............     ..... 100 ..... 0010011 @i
 131 ori      ............     ..... 110 ..... 0010011 @i
 132 andi     ............     ..... 111 ..... 0010011 @i
 133 slli     00000. ......    ..... 001 ..... 0010011 @sh
 134 srli     00000. ......    ..... 101 ..... 0010011 @sh
 135 srai     01000. ......    ..... 101 ..... 0010011 @sh
 136 add      0000000 .....    ..... 000 ..... 0110011 @r
 137 sub      0100000 .....    ..... 000 ..... 0110011 @r
 138 sll      0000000 .....    ..... 001 ..... 0110011 @r
 139 slt      0000000 .....    ..... 010 ..... 0110011 @r
 140 sltu     0000000 .....    ..... 011 ..... 0110011 @r
 141 xor      0000000 .....    ..... 100 ..... 0110011 @r
 142 srl      0000000 .....    ..... 101 ..... 0110011 @r
 143 sra      0100000 .....    ..... 101 ..... 0110011 @r
 144 or       0000000 .....    ..... 110 ..... 0110011 @r
 145 and      0000000 .....    ..... 111 ..... 0110011 @r
 146 fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
 147 fence_i  ---- ----   ----   ----- 001 ----- 0001111
 148 csrrw    ............     ..... 001 ..... 1110011 @csr
 149 csrrs    ............     ..... 010 ..... 1110011 @csr
 150 csrrc    ............     ..... 011 ..... 1110011 @csr
 151 csrrwi   ............     ..... 101 ..... 1110011 @csr
 152 csrrsi   ............     ..... 110 ..... 1110011 @csr
 153 csrrci   ............     ..... 111 ..... 1110011 @csr
 154
 155 # *** RV64I Base Instruction Set (in addition to RV32I) ***
 156 lwu      ............   ..... 110 ..... 0000011 @i
 157 ld       ............   ..... 011 ..... 0000011 @i
 158 sd       ....... .....  ..... 011 ..... 0100011 @s
 159 addiw    ............   ..... 000 ..... 0011011 @i
 160 slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
 161 srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
 162 sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
 163 addw     0000000 .....  ..... 000 ..... 0111011 @r
 164 subw     0100000 .....  ..... 000 ..... 0111011 @r
 165 sllw     0000000 .....  ..... 001 ..... 0111011 @r
 166 srlw     0000000 .....  ..... 101 ..... 0111011 @r
 167 sraw     0100000 .....  ..... 101 ..... 0111011 @r
 168
 169 # *** RV128I Base Instruction Set (in addition to RV64I) ***
 170 ldu      ............   ..... 111 ..... 0000011 @i
 171 lq       ............   ..... 010 ..... 0001111 @i
 172 sq       ............   ..... 100 ..... 0100011 @s
 173 addid    ............  .....  000 ..... 1011011 @i
 174 sllid    000000 ......  ..... 001 ..... 1011011 @sh6
 175 srlid    000000 ......  ..... 101 ..... 1011011 @sh6
 176 sraid    010000 ......  ..... 101 ..... 1011011 @sh6
 177 addd     0000000 ..... .....  000 ..... 1111011 @r
 178 subd     0100000 ..... .....  000 ..... 1111011 @r
 179 slld     0000000 ..... .....  001 ..... 1111011 @r
 180 srld     0000000 ..... .....  101 ..... 1111011 @r
 181 srad     0100000 ..... .....  101 ..... 1111011 @r
 182
 183 # *** RV32M Standard Extension ***
 184 mul      0000001 .....  ..... 000 ..... 0110011 @r
 185 mulh     0000001 .....  ..... 001 ..... 0110011 @r
 186 mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
 187 mulhu    0000001 .....  ..... 011 ..... 0110011 @r
 188 div      0000001 .....  ..... 100 ..... 0110011 @r
 189 divu     0000001 .....  ..... 101 ..... 0110011 @r
 190 rem      0000001 .....  ..... 110 ..... 0110011 @r
 191 remu     0000001 .....  ..... 111 ..... 0110011 @r
 192
 193 # *** RV64M Standard Extension (in addition to RV32M) ***
 194 mulw     0000001 .....  ..... 000 ..... 0111011 @r
 195 divw     0000001 .....  ..... 100 ..... 0111011 @r
 196 divuw    0000001 .....  ..... 101 ..... 0111011 @r
 197 remw     0000001 .....  ..... 110 ..... 0111011 @r
 198 remuw    0000001 .....  ..... 111 ..... 0111011 @r
 199
 200 # *** RV128M Standard Extension (in addition to RV64M) ***
 201 muld     0000001 .....  ..... 000 ..... 1111011 @r
 202 divd     0000001 .....  ..... 100 ..... 1111011 @r
 203 divud    0000001 .....  ..... 101 ..... 1111011 @r
 204 remd     0000001 .....  ..... 110 ..... 1111011 @r
 205 remud    0000001 .....  ..... 111 ..... 1111011 @r
 206
 207 # *** RV32A Standard Extension ***
 208 lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
 209 sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
 210 amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
 211 amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
 212 amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
 213 amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
 214 amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
 215 amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
 216 amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
 217 amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
 218 amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 219
 220 # *** RV64A Standard Extension (in addition to RV32A) ***
 221 lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
 222 sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
 223 amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
 224 amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
 225 amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
 226 amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
 227 amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
 228 amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
 229 amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
 230 amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
 231 amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
 232
 233 # *** RV32F Standard Extension ***
 234 flw        ............   ..... 010 ..... 0000111 @i
 235 fsw        .......  ..... ..... 010 ..... 0100111 @s
 236 fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
 237 fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
 238 fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
 239 fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
 240 fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
 241 fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
 242 fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
 243 fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
 244 fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
 245 fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
 246 fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
 247 fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
 248 fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
 249 fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
 250 fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
 251 fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
 252 fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
 253 feq_s      1010000  ..... ..... 010 ..... 1010011 @r
 254 flt_s      1010000  ..... ..... 001 ..... 1010011 @r
 255 fle_s      1010000  ..... ..... 000 ..... 1010011 @r
 256 fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
 257 fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 258 fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 259 fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 260
 261 # *** RV64F Standard Extension (in addition to RV32F) ***
 262 fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
 263 fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
 264 fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
 265 fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
 266
 267 # *** RV32D Standard Extension ***
 268 fld        ............   ..... 011 ..... 0000111 @i
 269 fsd        ....... .....  ..... 011 ..... 0100111 @s
 270 fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
 271 fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
 272 fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
 273 fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
 274 fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
 275 fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
 276 fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
 277 fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
 278 fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
 279 fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
 280 fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
 281 fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
 282 fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
 283 fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
 284 fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
 285 fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
 286 feq_d      1010001  ..... ..... 010 ..... 1010011 @r
 287 flt_d      1010001  ..... ..... 001 ..... 1010011 @r
 288 fle_d      1010001  ..... ..... 000 ..... 1010011 @r
 289 fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
 290 fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
 291 fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 292 fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 293 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 294
 295 # *** RV64D Standard Extension (in addition to RV32D) ***
 296 fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
 297 fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
 298 fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
 299 fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
 300 fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
 301 fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 302
 303 # *** RV32H Base Instruction Set ***
 304 hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
 305 hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
 306 hlv_h       0110010  00000  ..... 100 ..... 1110011 @r2
 307 hlv_hu      0110010  00001  ..... 100 ..... 1110011 @r2
 308 hlvx_hu     0110010  00011  ..... 100 ..... 1110011 @r2
 309 hlv_w       0110100  00000  ..... 100 ..... 1110011 @r2
 310 hlvx_wu     0110100  00011  ..... 100 ..... 1110011 @r2
 311 hsv_b       0110001  .....  ..... 100 00000 1110011 @r2_s
 312 hsv_h       0110011  .....  ..... 100 00000 1110011 @r2_s
 313 hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
 314 hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
 315 hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 316
 317 # *** RV64H Base Instruction Set ***
 318 hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 319 hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 320 hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 321
 322 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
 323 # Vector unit-stride load/store insns.
 324 vle8_v     ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
 325 vle16_v    ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
 326 vle32_v    ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
 327 vle64_v    ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
 328 vse8_v     ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
 329 vse16_v    ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
 330 vse32_v    ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
 331 vse64_v    ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
 332
 333 # Vector unit-stride mask load/store insns.
 334 vlm_v      000 000 1 01011 ..... 000 ..... 0000111 @r2
 335 vsm_v      000 000 1 01011 ..... 000 ..... 0100111 @r2
 336
 337 # Vector strided insns.
 338 vlse8_v     ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
 339 vlse16_v    ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
 340 vlse32_v    ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
 341 vlse64_v    ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
 342 vsse8_v     ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
 343 vsse16_v    ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
 344 vsse32_v    ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
 345 vsse64_v    ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
 346
 347 # Vector ordered-indexed and unordered-indexed load insns.
 348 vlxei8_v      ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
 349 vlxei16_v     ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
 350 vlxei32_v     ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
 351 vlxei64_v     ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
 352
 353 # Vector ordered-indexed and unordered-indexed store insns.
 354 vsxei8_v      ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
 355 vsxei16_v     ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
 356 vsxei32_v     ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
 357 vsxei64_v     ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
 358
 359 # Vector unit-stride fault-only-first load insns.
 360 vle8ff_v      ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
 361 vle16ff_v     ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
 362 vle32ff_v     ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
 363 vle64ff_v     ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
 364
 365 # Vector whole register insns
 366 vl1re8_v      000 000 1 01000 ..... 000 ..... 0000111 @r2
 367 vl1re16_v     000 000 1 01000 ..... 101 ..... 0000111 @r2
 368 vl1re32_v     000 000 1 01000 ..... 110 ..... 0000111 @r2
 369 vl1re64_v     000 000 1 01000 ..... 111 ..... 0000111 @r2
 370 vl2re8_v      001 000 1 01000 ..... 000 ..... 0000111 @r2
 371 vl2re16_v     001 000 1 01000 ..... 101 ..... 0000111 @r2
 372 vl2re32_v     001 000 1 01000 ..... 110 ..... 0000111 @r2
 373 vl2re64_v     001 000 1 01000 ..... 111 ..... 0000111 @r2
 374 vl4re8_v      011 000 1 01000 ..... 000 ..... 0000111 @r2
 375 vl4re16_v     011 000 1 01000 ..... 101 ..... 0000111 @r2
 376 vl4re32_v     011 000 1 01000 ..... 110 ..... 0000111 @r2
 377 vl4re64_v     011 000 1 01000 ..... 111 ..... 0000111 @r2
 378 vl8re8_v      111 000 1 01000 ..... 000 ..... 0000111 @r2
 379 vl8re16_v     111 000 1 01000 ..... 101 ..... 0000111 @r2
 380 vl8re32_v     111 000 1 01000 ..... 110 ..... 0000111 @r2
 381 vl8re64_v     111 000 1 01000 ..... 111 ..... 0000111 @r2
 382 vs1r_v        000 000 1 01000 ..... 000 ..... 0100111 @r2
 383 vs2r_v        001 000 1 01000 ..... 000 ..... 0100111 @r2
 384 vs4r_v        011 000 1 01000 ..... 000 ..... 0100111 @r2
 385 vs8r_v        111 000 1 01000 ..... 000 ..... 0100111 @r2
 386
 387 # *** new major opcode OP-V ***
 388 vadd_vv         000000 . ..... ..... 000 ..... 1010111 @r_vm
 389 vadd_vx         000000 . ..... ..... 100 ..... 1010111 @r_vm
 390 vadd_vi         000000 . ..... ..... 011 ..... 1010111 @r_vm
 391 vsub_vv         000010 . ..... ..... 000 ..... 1010111 @r_vm
 392 vsub_vx         000010 . ..... ..... 100 ..... 1010111 @r_vm
 393 vrsub_vx        000011 . ..... ..... 100 ..... 1010111 @r_vm
 394 vrsub_vi        000011 . ..... ..... 011 ..... 1010111 @r_vm
 395 vwaddu_vv       110000 . ..... ..... 010 ..... 1010111 @r_vm
 396 vwaddu_vx       110000 . ..... ..... 110 ..... 1010111 @r_vm
 397 vwadd_vv        110001 . ..... ..... 010 ..... 1010111 @r_vm
 398 vwadd_vx        110001 . ..... ..... 110 ..... 1010111 @r_vm
 399 vwsubu_vv       110010 . ..... ..... 010 ..... 1010111 @r_vm
 400 vwsubu_vx       110010 . ..... ..... 110 ..... 1010111 @r_vm
 401 vwsub_vv        110011 . ..... ..... 010 ..... 1010111 @r_vm
 402 vwsub_vx        110011 . ..... ..... 110 ..... 1010111 @r_vm
 403 vwaddu_wv       110100 . ..... ..... 010 ..... 1010111 @r_vm
 404 vwaddu_wx       110100 . ..... ..... 110 ..... 1010111 @r_vm
 405 vwadd_wv        110101 . ..... ..... 010 ..... 1010111 @r_vm
 406 vwadd_wx        110101 . ..... ..... 110 ..... 1010111 @r_vm
 407 vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
 408 vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
 409 vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
 410 vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
 411 vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
 412 vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
 413 vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
 414 vmadc_vvm       010001 . ..... ..... 000 ..... 1010111 @r_vm
 415 vmadc_vxm       010001 . ..... ..... 100 ..... 1010111 @r_vm
 416 vmadc_vim       010001 . ..... ..... 011 ..... 1010111 @r_vm
 417 vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
 418 vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
 419 vmsbc_vvm       010011 . ..... ..... 000 ..... 1010111 @r_vm
 420 vmsbc_vxm       010011 . ..... ..... 100 ..... 1010111 @r_vm
 421 vand_vv         001001 . ..... ..... 000 ..... 1010111 @r_vm
 422 vand_vx         001001 . ..... ..... 100 ..... 1010111 @r_vm
 423 vand_vi         001001 . ..... ..... 011 ..... 1010111 @r_vm
 424 vor_vv          001010 . ..... ..... 000 ..... 1010111 @r_vm
 425 vor_vx          001010 . ..... ..... 100 ..... 1010111 @r_vm
 426 vor_vi          001010 . ..... ..... 011 ..... 1010111 @r_vm
 427 vxor_vv         001011 . ..... ..... 000 ..... 1010111 @r_vm
 428 vxor_vx         001011 . ..... ..... 100 ..... 1010111 @r_vm
 429 vxor_vi         001011 . ..... ..... 011 ..... 1010111 @r_vm
 430 vsll_vv         100101 . ..... ..... 000 ..... 1010111 @r_vm
 431 vsll_vx         100101 . ..... ..... 100 ..... 1010111 @r_vm
 432 vsll_vi         100101 . ..... ..... 011 ..... 1010111 @r_vm
 433 vsrl_vv         101000 . ..... ..... 000 ..... 1010111 @r_vm
 434 vsrl_vx         101000 . ..... ..... 100 ..... 1010111 @r_vm
 435 vsrl_vi         101000 . ..... ..... 011 ..... 1010111 @r_vm
 436 vsra_vv         101001 . ..... ..... 000 ..... 1010111 @r_vm
 437 vsra_vx         101001 . ..... ..... 100 ..... 1010111 @r_vm
 438 vsra_vi         101001 . ..... ..... 011 ..... 1010111 @r_vm
 439 vnsrl_wv        101100 . ..... ..... 000 ..... 1010111 @r_vm
 440 vnsrl_wx        101100 . ..... ..... 100 ..... 1010111 @r_vm
 441 vnsrl_wi        101100 . ..... ..... 011 ..... 1010111 @r_vm
 442 vnsra_wv        101101 . ..... ..... 000 ..... 1010111 @r_vm
 443 vnsra_wx        101101 . ..... ..... 100 ..... 1010111 @r_vm
 444 vnsra_wi        101101 . ..... ..... 011 ..... 1010111 @r_vm
 445 vmseq_vv        011000 . ..... ..... 000 ..... 1010111 @r_vm
 446 vmseq_vx        011000 . ..... ..... 100 ..... 1010111 @r_vm
 447 vmseq_vi        011000 . ..... ..... 011 ..... 1010111 @r_vm
 448 vmsne_vv        011001 . ..... ..... 000 ..... 1010111 @r_vm
 449 vmsne_vx        011001 . ..... ..... 100 ..... 1010111 @r_vm
 450 vmsne_vi        011001 . ..... ..... 011 ..... 1010111 @r_vm
 451 vmsltu_vv       011010 . ..... ..... 000 ..... 1010111 @r_vm
 452 vmsltu_vx       011010 . ..... ..... 100 ..... 1010111 @r_vm
 453 vmslt_vv        011011 . ..... ..... 000 ..... 1010111 @r_vm
 454 vmslt_vx        011011 . ..... ..... 100 ..... 1010111 @r_vm
 455 vmsleu_vv       011100 . ..... ..... 000 ..... 1010111 @r_vm
 456 vmsleu_vx       011100 . ..... ..... 100 ..... 1010111 @r_vm
 457 vmsleu_vi       011100 . ..... ..... 011 ..... 1010111 @r_vm
 458 vmsle_vv        011101 . ..... ..... 000 ..... 1010111 @r_vm
 459 vmsle_vx        011101 . ..... ..... 100 ..... 1010111 @r_vm
 460 vmsle_vi        011101 . ..... ..... 011 ..... 1010111 @r_vm
 461 vmsgtu_vx       011110 . ..... ..... 100 ..... 1010111 @r_vm
 462 vmsgtu_vi       011110 . ..... ..... 011 ..... 1010111 @r_vm
 463 vmsgt_vx        011111 . ..... ..... 100 ..... 1010111 @r_vm
 464 vmsgt_vi        011111 . ..... ..... 011 ..... 1010111 @r_vm
 465 vminu_vv        000100 . ..... ..... 000 ..... 1010111 @r_vm
 466 vminu_vx        000100 . ..... ..... 100 ..... 1010111 @r_vm
 467 vmin_vv         000101 . ..... ..... 000 ..... 1010111 @r_vm
 468 vmin_vx         000101 . ..... ..... 100 ..... 1010111 @r_vm
 469 vmaxu_vv        000110 . ..... ..... 000 ..... 1010111 @r_vm
 470 vmaxu_vx        000110 . ..... ..... 100 ..... 1010111 @r_vm
 471 vmax_vv         000111 . ..... ..... 000 ..... 1010111 @r_vm
 472 vmax_vx         000111 . ..... ..... 100 ..... 1010111 @r_vm
 473 vmul_vv         100101 . ..... ..... 010 ..... 1010111 @r_vm
 474 vmul_vx         100101 . ..... ..... 110 ..... 1010111 @r_vm
 475 vmulh_vv        100111 . ..... ..... 010 ..... 1010111 @r_vm
 476 vmulh_vx        100111 . ..... ..... 110 ..... 1010111 @r_vm
 477 vmulhu_vv       100100 . ..... ..... 010 ..... 1010111 @r_vm
 478 vmulhu_vx       100100 . ..... ..... 110 ..... 1010111 @r_vm
 479 vmulhsu_vv      100110 . ..... ..... 010 ..... 1010111 @r_vm
 480 vmulhsu_vx      100110 . ..... ..... 110 ..... 1010111 @r_vm
 481 vdivu_vv        100000 . ..... ..... 010 ..... 1010111 @r_vm
 482 vdivu_vx        100000 . ..... ..... 110 ..... 1010111 @r_vm
 483 vdiv_vv         100001 . ..... ..... 010 ..... 1010111 @r_vm
 484 vdiv_vx         100001 . ..... ..... 110 ..... 1010111 @r_vm
 485 vremu_vv        100010 . ..... ..... 010 ..... 1010111 @r_vm
 486 vremu_vx        100010 . ..... ..... 110 ..... 1010111 @r_vm
 487 vrem_vv         100011 . ..... ..... 010 ..... 1010111 @r_vm
 488 vrem_vx         100011 . ..... ..... 110 ..... 1010111 @r_vm
 489 vwmulu_vv       111000 . ..... ..... 010 ..... 1010111 @r_vm
 490 vwmulu_vx       111000 . ..... ..... 110 ..... 1010111 @r_vm
 491 vwmulsu_vv      111010 . ..... ..... 010 ..... 1010111 @r_vm
 492 vwmulsu_vx      111010 . ..... ..... 110 ..... 1010111 @r_vm
 493 vwmul_vv        111011 . ..... ..... 010 ..... 1010111 @r_vm
 494 vwmul_vx        111011 . ..... ..... 110 ..... 1010111 @r_vm
 495 vmacc_vv        101101 . ..... ..... 010 ..... 1010111 @r_vm
 496 vmacc_vx        101101 . ..... ..... 110 ..... 1010111 @r_vm
 497 vnmsac_vv       101111 . ..... ..... 010 ..... 1010111 @r_vm
 498 vnmsac_vx       101111 . ..... ..... 110 ..... 1010111 @r_vm
 499 vmadd_vv        101001 . ..... ..... 010 ..... 1010111 @r_vm
 500 vmadd_vx        101001 . ..... ..... 110 ..... 1010111 @r_vm
 501 vnmsub_vv       101011 . ..... ..... 010 ..... 1010111 @r_vm
 502 vnmsub_vx       101011 . ..... ..... 110 ..... 1010111 @r_vm
 503 vwmaccu_vv      111100 . ..... ..... 010 ..... 1010111 @r_vm
 504 vwmaccu_vx      111100 . ..... ..... 110 ..... 1010111 @r_vm
 505 vwmacc_vv       111101 . ..... ..... 010 ..... 1010111 @r_vm
 506 vwmacc_vx       111101 . ..... ..... 110 ..... 1010111 @r_vm
 507 vwmaccsu_vv     111111 . ..... ..... 010 ..... 1010111 @r_vm
 508 vwmaccsu_vx     111111 . ..... ..... 110 ..... 1010111 @r_vm
 509 vwmaccus_vx     111110 . ..... ..... 110 ..... 1010111 @r_vm
 510 vmv_v_v         010111 1 00000 ..... 000 ..... 1010111 @r2
 511 vmv_v_x         010111 1 00000 ..... 100 ..... 1010111 @r2
 512 vmv_v_i         010111 1 00000 ..... 011 ..... 1010111 @r2
 513 vmerge_vvm      010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
 514 vmerge_vxm      010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
 515 vmerge_vim      010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
 516 vsaddu_vv       100000 . ..... ..... 000 ..... 1010111 @r_vm
 517 vsaddu_vx       100000 . ..... ..... 100 ..... 1010111 @r_vm
 518 vsaddu_vi       100000 . ..... ..... 011 ..... 1010111 @r_vm
 519 vsadd_vv        100001 . ..... ..... 000 ..... 1010111 @r_vm
 520 vsadd_vx        100001 . ..... ..... 100 ..... 1010111 @r_vm
 521 vsadd_vi        100001 . ..... ..... 011 ..... 1010111 @r_vm
 522 vssubu_vv       100010 . ..... ..... 000 ..... 1010111 @r_vm
 523 vssubu_vx       100010 . ..... ..... 100 ..... 1010111 @r_vm
 524 vssub_vv        100011 . ..... ..... 000 ..... 1010111 @r_vm
 525 vssub_vx        100011 . ..... ..... 100 ..... 1010111 @r_vm
 526 vaadd_vv        001001 . ..... ..... 010 ..... 1010111 @r_vm
 527 vaadd_vx        001001 . ..... ..... 110 ..... 1010111 @r_vm
 528 vaaddu_vv       001000 . ..... ..... 010 ..... 1010111 @r_vm
 529 vaaddu_vx       001000 . ..... ..... 110 ..... 1010111 @r_vm
 530 vasub_vv        001011 . ..... ..... 010 ..... 1010111 @r_vm
 531 vasub_vx        001011 . ..... ..... 110 ..... 1010111 @r_vm
 532 vasubu_vv       001010 . ..... ..... 010 ..... 1010111 @r_vm
 533 vasubu_vx       001010 . ..... ..... 110 ..... 1010111 @r_vm
 534 vsmul_vv        100111 . ..... ..... 000 ..... 1010111 @r_vm
 535 vsmul_vx        100111 . ..... ..... 100 ..... 1010111 @r_vm
 536 vssrl_vv        101010 . ..... ..... 000 ..... 1010111 @r_vm
 537 vssrl_vx        101010 . ..... ..... 100 ..... 1010111 @r_vm
 538 vssrl_vi        101010 . ..... ..... 011 ..... 1010111 @r_vm
 539 vssra_vv        101011 . ..... ..... 000 ..... 1010111 @r_vm
 540 vssra_vx        101011 . ..... ..... 100 ..... 1010111 @r_vm
 541 vssra_vi        101011 . ..... ..... 011 ..... 1010111 @r_vm
 542 vnclipu_wv      101110 . ..... ..... 000 ..... 1010111 @r_vm
 543 vnclipu_wx      101110 . ..... ..... 100 ..... 1010111 @r_vm
 544 vnclipu_wi      101110 . ..... ..... 011 ..... 1010111 @r_vm
 545 vnclip_wv       101111 . ..... ..... 000 ..... 1010111 @r_vm
 546 vnclip_wx       101111 . ..... ..... 100 ..... 1010111 @r_vm
 547 vnclip_wi       101111 . ..... ..... 011 ..... 1010111 @r_vm
 548 vfadd_vv        000000 . ..... ..... 001 ..... 1010111 @r_vm
 549 vfadd_vf        000000 . ..... ..... 101 ..... 1010111 @r_vm
 550 vfsub_vv        000010 . ..... ..... 001 ..... 1010111 @r_vm
 551 vfsub_vf        000010 . ..... ..... 101 ..... 1010111 @r_vm
 552 vfrsub_vf       100111 . ..... ..... 101 ..... 1010111 @r_vm
 553 vfwadd_vv       110000 . ..... ..... 001 ..... 1010111 @r_vm
 554 vfwadd_vf       110000 . ..... ..... 101 ..... 1010111 @r_vm
 555 vfwadd_wv       110100 . ..... ..... 001 ..... 1010111 @r_vm
 556 vfwadd_wf       110100 . ..... ..... 101 ..... 1010111 @r_vm
 557 vfwsub_vv       110010 . ..... ..... 001 ..... 1010111 @r_vm
 558 vfwsub_vf       110010 . ..... ..... 101 ..... 1010111 @r_vm
 559 vfwsub_wv       110110 . ..... ..... 001 ..... 1010111 @r_vm
 560 vfwsub_wf       110110 . ..... ..... 101 ..... 1010111 @r_vm
 561 vfmul_vv        100100 . ..... ..... 001 ..... 1010111 @r_vm
 562 vfmul_vf        100100 . ..... ..... 101 ..... 1010111 @r_vm
 563 vfdiv_vv        100000 . ..... ..... 001 ..... 1010111 @r_vm
 564 vfdiv_vf        100000 . ..... ..... 101 ..... 1010111 @r_vm
 565 vfrdiv_vf       100001 . ..... ..... 101 ..... 1010111 @r_vm
 566 vfwmul_vv       111000 . ..... ..... 001 ..... 1010111 @r_vm
 567 vfwmul_vf       111000 . ..... ..... 101 ..... 1010111 @r_vm
 568 vfmacc_vv       101100 . ..... ..... 001 ..... 1010111 @r_vm
 569 vfnmacc_vv      101101 . ..... ..... 001 ..... 1010111 @r_vm
 570 vfnmacc_vf      101101 . ..... ..... 101 ..... 1010111 @r_vm
 571 vfmacc_vf       101100 . ..... ..... 101 ..... 1010111 @r_vm
 572 vfmsac_vv       101110 . ..... ..... 001 ..... 1010111 @r_vm
 573 vfmsac_vf       101110 . ..... ..... 101 ..... 1010111 @r_vm
 574 vfnmsac_vv      101111 . ..... ..... 001 ..... 1010111 @r_vm
 575 vfnmsac_vf      101111 . ..... ..... 101 ..... 1010111 @r_vm
 576 vfmadd_vv       101000 . ..... ..... 001 ..... 1010111 @r_vm
 577 vfmadd_vf       101000 . ..... ..... 101 ..... 1010111 @r_vm
 578 vfnmadd_vv      101001 . ..... ..... 001 ..... 1010111 @r_vm
 579 vfnmadd_vf      101001 . ..... ..... 101 ..... 1010111 @r_vm
 580 vfmsub_vv       101010 . ..... ..... 001 ..... 1010111 @r_vm
 581 vfmsub_vf       101010 . ..... ..... 101 ..... 1010111 @r_vm
 582 vfnmsub_vv      101011 . ..... ..... 001 ..... 1010111 @r_vm
 583 vfnmsub_vf      101011 . ..... ..... 101 ..... 1010111 @r_vm
 584 vfwmacc_vv      111100 . ..... ..... 001 ..... 1010111 @r_vm
 585 vfwmacc_vf      111100 . ..... ..... 101 ..... 1010111 @r_vm
 586 vfwnmacc_vv     111101 . ..... ..... 001 ..... 1010111 @r_vm
 587 vfwnmacc_vf     111101 . ..... ..... 101 ..... 1010111 @r_vm
 588 vfwmsac_vv      111110 . ..... ..... 001 ..... 1010111 @r_vm
 589 vfwmsac_vf      111110 . ..... ..... 101 ..... 1010111 @r_vm
 590 vfwnmsac_vv     111111 . ..... ..... 001 ..... 1010111 @r_vm
 591 vfwnmsac_vf     111111 . ..... ..... 101 ..... 1010111 @r_vm
 592 vfsqrt_v        010011 . ..... 00000 001 ..... 1010111 @r2_vm
 593 vfrsqrt7_v      010011 . ..... 00100 001 ..... 1010111 @r2_vm
 594 vfrec7_v        010011 . ..... 00101 001 ..... 1010111 @r2_vm
 595 vfmin_vv        000100 . ..... ..... 001 ..... 1010111 @r_vm
 596 vfmin_vf        000100 . ..... ..... 101 ..... 1010111 @r_vm
 597 vfmax_vv        000110 . ..... ..... 001 ..... 1010111 @r_vm
 598 vfmax_vf        000110 . ..... ..... 101 ..... 1010111 @r_vm
 599 vfsgnj_vv       001000 . ..... ..... 001 ..... 1010111 @r_vm
 600 vfsgnj_vf       001000 . ..... ..... 101 ..... 1010111 @r_vm
 601 vfsgnjn_vv      001001 . ..... ..... 001 ..... 1010111 @r_vm
 602 vfsgnjn_vf      001001 . ..... ..... 101 ..... 1010111 @r_vm
 603 vfsgnjx_vv      001010 . ..... ..... 001 ..... 1010111 @r_vm
 604 vfsgnjx_vf      001010 . ..... ..... 101 ..... 1010111 @r_vm
 605 vfslide1up_vf   001110 . ..... ..... 101 ..... 1010111 @r_vm
 606 vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
 607 vmfeq_vv        011000 . ..... ..... 001 ..... 1010111 @r_vm
 608 vmfeq_vf        011000 . ..... ..... 101 ..... 1010111 @r_vm
 609 vmfne_vv        011100 . ..... ..... 001 ..... 1010111 @r_vm
 610 vmfne_vf        011100 . ..... ..... 101 ..... 1010111 @r_vm
 611 vmflt_vv        011011 . ..... ..... 001 ..... 1010111 @r_vm
 612 vmflt_vf        011011 . ..... ..... 101 ..... 1010111 @r_vm
 613 vmfle_vv        011001 . ..... ..... 001 ..... 1010111 @r_vm
 614 vmfle_vf        011001 . ..... ..... 101 ..... 1010111 @r_vm
 615 vmfgt_vf        011101 . ..... ..... 101 ..... 1010111 @r_vm
 616 vmfge_vf        011111 . ..... ..... 101 ..... 1010111 @r_vm
 617 vfclass_v       010011 . ..... 10000 001 ..... 1010111 @r2_vm
 618 vfmerge_vfm     010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
 619 vfmv_v_f        010111 1 00000 ..... 101 ..... 1010111 @r2
 620
 621 vfcvt_xu_f_v       010010 . ..... 00000 001 ..... 1010111 @r2_vm
 622 vfcvt_x_f_v        010010 . ..... 00001 001 ..... 1010111 @r2_vm
 623 vfcvt_f_xu_v       010010 . ..... 00010 001 ..... 1010111 @r2_vm
 624 vfcvt_f_x_v        010010 . ..... 00011 001 ..... 1010111 @r2_vm
 625 vfcvt_rtz_xu_f_v   010010 . ..... 00110 001 ..... 1010111 @r2_vm
 626 vfcvt_rtz_x_f_v    010010 . ..... 00111 001 ..... 1010111 @r2_vm
 627
 628 vfwcvt_xu_f_v      010010 . ..... 01000 001 ..... 1010111 @r2_vm
 629 vfwcvt_x_f_v       010010 . ..... 01001 001 ..... 1010111 @r2_vm
 630 vfwcvt_f_xu_v      010010 . ..... 01010 001 ..... 1010111 @r2_vm
 631 vfwcvt_f_x_v       010010 . ..... 01011 001 ..... 1010111 @r2_vm
 632 vfwcvt_f_f_v       010010 . ..... 01100 001 ..... 1010111 @r2_vm
 633 vfwcvt_rtz_xu_f_v  010010 . ..... 01110 001 ..... 1010111 @r2_vm
 634 vfwcvt_rtz_x_f_v   010010 . ..... 01111 001 ..... 1010111 @r2_vm
 635
 636 vfncvt_xu_f_w      010010 . ..... 10000 001 ..... 1010111 @r2_vm
 637 vfncvt_x_f_w       010010 . ..... 10001 001 ..... 1010111 @r2_vm
 638 vfncvt_f_xu_w      010010 . ..... 10010 001 ..... 1010111 @r2_vm
 639 vfncvt_f_x_w       010010 . ..... 10011 001 ..... 1010111 @r2_vm
 640 vfncvt_f_f_w       010010 . ..... 10100 001 ..... 1010111 @r2_vm
 641 vfncvt_rod_f_f_w   010010 . ..... 10101 001 ..... 1010111 @r2_vm
 642 vfncvt_rtz_xu_f_w  010010 . ..... 10110 001 ..... 1010111 @r2_vm
 643 vfncvt_rtz_x_f_w   010010 . ..... 10111 001 ..... 1010111 @r2_vm
 644
 645 vredsum_vs      000000 . ..... ..... 010 ..... 1010111 @r_vm
 646 vredand_vs      000001 . ..... ..... 010 ..... 1010111 @r_vm
 647 vredor_vs       000010 . ..... ..... 010 ..... 1010111 @r_vm
 648 vredxor_vs      000011 . ..... ..... 010 ..... 1010111 @r_vm
 649 vredminu_vs     000100 . ..... ..... 010 ..... 1010111 @r_vm
 650 vredmin_vs      000101 . ..... ..... 010 ..... 1010111 @r_vm
 651 vredmaxu_vs     000110 . ..... ..... 010 ..... 1010111 @r_vm
 652 vredmax_vs      000111 . ..... ..... 010 ..... 1010111 @r_vm
 653 vwredsumu_vs    110000 . ..... ..... 000 ..... 1010111 @r_vm
 654 vwredsum_vs     110001 . ..... ..... 000 ..... 1010111 @r_vm
 655 # Vector ordered and unordered reduction sum
 656 vfredsum_vs     0000-1 . ..... ..... 001 ..... 1010111 @r_vm
 657 vfredmin_vs     000101 . ..... ..... 001 ..... 1010111 @r_vm
 658 vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
 659 # Vector widening ordered and unordered float reduction sum
 660 vfwredsum_vs    1100-1 . ..... ..... 001 ..... 1010111 @r_vm
 661 vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
 662 vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
 663 vmandn_mm       011000 - ..... ..... 010 ..... 1010111 @r
 664 vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
 665 vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
 666 vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
 667 vmorn_mm        011100 - ..... ..... 010 ..... 1010111 @r
 668 vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
 669 vcpop_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
 670 vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
 671 vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
 672 vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
 673 vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
 674 viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
 675 vid_v           010100 . 00000 10001 010 ..... 1010111 @r1_vm
 676 vmv_x_s         010000 1 ..... 00000 010 ..... 1010111 @r2rd
 677 vmv_s_x         010000 1 00000 ..... 110 ..... 1010111 @r2
 678 vfmv_f_s        010000 1 ..... 00000 001 ..... 1010111 @r2rd
 679 vfmv_s_f        010000 1 00000 ..... 101 ..... 1010111 @r2
 680 vslideup_vx     001110 . ..... ..... 100 ..... 1010111 @r_vm
 681 vslideup_vi     001110 . ..... ..... 011 ..... 1010111 @r_vm
 682 vslide1up_vx    001110 . ..... ..... 110 ..... 1010111 @r_vm
 683 vslidedown_vx   001111 . ..... ..... 100 ..... 1010111 @r_vm
 684 vslidedown_vi   001111 . ..... ..... 011 ..... 1010111 @r_vm
 685 vslide1down_vx  001111 . ..... ..... 110 ..... 1010111 @r_vm
 686 vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
 687 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
 688 vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
 689 vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
 690 vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
 691 vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
 692 vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
 693 vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd
 694 vmv8r_v         100111 1 ..... 00111 011 ..... 1010111 @r2rd
 695
 696 # Vector Integer Extension
 697 vzext_vf2       010010 . ..... 00110 010 ..... 1010111 @r2_vm
 698 vzext_vf4       010010 . ..... 00100 010 ..... 1010111 @r2_vm
 699 vzext_vf8       010010 . ..... 00010 010 ..... 1010111 @r2_vm
 700 vsext_vf2       010010 . ..... 00111 010 ..... 1010111 @r2_vm
 701 vsext_vf4       010010 . ..... 00101 010 ..... 1010111 @r2_vm
 702 vsext_vf8       010010 . ..... 00011 010 ..... 1010111 @r2_vm
 703
 704 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm11
 705 vsetivli        11 .......... ..... 111 ..... 1010111  @r2_zimm10
 706 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 707
 708 # *** RV32 Zba Standard Extension ***
 709 sh1add     0010000 .......... 010 ..... 0110011 @r
 710 sh2add     0010000 .......... 100 ..... 0110011 @r
 711 sh3add     0010000 .......... 110 ..... 0110011 @r
 712
 713 # *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
 714 add_uw     0000100 .......... 000 ..... 0111011 @r
 715 sh1add_uw  0010000 .......... 010 ..... 0111011 @r
 716 sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 717 sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 718 slli_uw    00001 ............ 001 ..... 0011011 @sh
 719
 720 # *** RV32 Zbb Standard Extension ***
 721 andn       0100000 .......... 111 ..... 0110011 @r
 722 clz        011000 000000 ..... 001 ..... 0010011 @r2
 723 cpop       011000 000010 ..... 001 ..... 0010011 @r2
 724 ctz        011000 000001 ..... 001 ..... 0010011 @r2
 725 max        0000101 .......... 110 ..... 0110011 @r
 726 maxu       0000101 .......... 111 ..... 0110011 @r
 727 min        0000101 .......... 100 ..... 0110011 @r
 728 minu       0000101 .......... 101 ..... 0110011 @r
 729 orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 730 orn        0100000 .......... 110 ..... 0110011 @r
 731 # The encoding for rev8 differs between RV32 and RV64.
 732 # rev8_32 denotes the RV32 variant.
 733 rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
 734 rol        0110000 .......... 001 ..... 0110011 @r
 735 ror        0110000 .......... 101 ..... 0110011 @r
 736 rori       01100 ............ 101 ..... 0010011 @sh
 737 sext_b     011000 000100 ..... 001 ..... 0010011 @r2
 738 sext_h     011000 000101 ..... 001 ..... 0010011 @r2
 739 xnor       0100000 .......... 100 ..... 0110011 @r
 740 # The encoding for zext.h differs between RV32 and RV64.
 741 # zext_h_32 denotes the RV32 variant.
 742 zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
 743
 744 # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
 745 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 746 ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 747 cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 748 # The encoding for rev8 differs between RV32 and RV64.
 749 # When executing on RV64, the encoding used in RV32 is an illegal
 750 # instruction, so we use different handler functions to differentiate.
 751 rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
 752 rolw       0110000 .......... 001 ..... 0111011 @r
 753 roriw      0110000 .......... 101 ..... 0011011 @sh5
 754 rorw       0110000 .......... 101 ..... 0111011 @r
 755 # The encoding for zext.h differs between RV32 and RV64.
 756 # When executing on RV64, the encoding used in RV32 is an illegal
 757 # instruction, so we use different handler functions to differentiate.
 758 zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 759
 760 # *** RV32 Zbc Standard Extension ***
 761 clmul      0000101 .......... 001 ..... 0110011 @r
 762 clmulh     0000101 .......... 011 ..... 0110011 @r
 763 clmulr     0000101 .......... 010 ..... 0110011 @r
 764
 765 # *** RV32 Zbs Standard Extension ***
 766 bclr       0100100 .......... 001 ..... 0110011 @r
 767 bclri      01001. ........... 001 ..... 0010011 @sh
 768 bext       0100100 .......... 101 ..... 0110011 @r
 769 bexti      01001. ........... 101 ..... 0010011 @sh
 770 binv       0110100 .......... 001 ..... 0110011 @r
 771 binvi      01101. ........... 001 ..... 0010011 @sh
 772 bset       0010100 .......... 001 ..... 0110011 @r
 773 bseti      00101. ........... 001 ..... 0010011 @sh
 774
 775 # *** RV32 Zfh Extension ***
 776 flh        ............   ..... 001 ..... 0000111 @i
 777 fsh        .......  ..... ..... 001 ..... 0100111 @s
 778 fmadd_h    ..... 10 ..... ..... ... ..... 1000011 @r4_rm
 779 fmsub_h    ..... 10 ..... ..... ... ..... 1000111 @r4_rm
 780 fnmsub_h   ..... 10 ..... ..... ... ..... 1001011 @r4_rm
 781 fnmadd_h   ..... 10 ..... ..... ... ..... 1001111 @r4_rm
 782 fadd_h     0000010  ..... ..... ... ..... 1010011 @r_rm
 783 fsub_h     0000110  ..... ..... ... ..... 1010011 @r_rm
 784 fmul_h     0001010  ..... ..... ... ..... 1010011 @r_rm
 785 fdiv_h     0001110  ..... ..... ... ..... 1010011 @r_rm
 786 fsqrt_h    0101110  00000 ..... ... ..... 1010011 @r2_rm
 787 fsgnj_h    0010010  ..... ..... 000 ..... 1010011 @r
 788 fsgnjn_h   0010010  ..... ..... 001 ..... 1010011 @r
 789 fsgnjx_h   0010010  ..... ..... 010 ..... 1010011 @r
 790 fmin_h     0010110  ..... ..... 000 ..... 1010011 @r
 791 fmax_h     0010110  ..... ..... 001 ..... 1010011 @r
 792 fcvt_h_s   0100010  00000 ..... ... ..... 1010011 @r2_rm
 793 fcvt_s_h   0100000  00010 ..... ... ..... 1010011 @r2_rm
 794 fcvt_h_d   0100010  00001 ..... ... ..... 1010011 @r2_rm
 795 fcvt_d_h   0100001  00010 ..... ... ..... 1010011 @r2_rm
 796 fcvt_w_h   1100010  00000 ..... ... ..... 1010011 @r2_rm
 797 fcvt_wu_h  1100010  00001 ..... ... ..... 1010011 @r2_rm
 798 fmv_x_h    1110010  00000 ..... 000 ..... 1010011 @r2
 799 feq_h      1010010  ..... ..... 010 ..... 1010011 @r
 800 flt_h      1010010  ..... ..... 001 ..... 1010011 @r
 801 fle_h      1010010  ..... ..... 000 ..... 1010011 @r
 802 fclass_h   1110010  00000 ..... 001 ..... 1010011 @r2
 803 fcvt_h_w   1101010  00000 ..... ... ..... 1010011 @r2_rm
 804 fcvt_h_wu  1101010  00001 ..... ... ..... 1010011 @r2_rm
 805 fmv_h_x    1111010  00000 ..... 000 ..... 1010011 @r2
 806
 807 # *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
 808 fcvt_l_h   1100010  00010 ..... ... ..... 1010011 @r2_rm
 809 fcvt_lu_h  1100010  00011 ..... ... ..... 1010011 @r2_rm
 810 fcvt_h_l   1101010  00010 ..... ... ..... 1010011 @r2_rm
 811 fcvt_h_lu  1101010  00011 ..... ... ..... 1010011 @r2_rm
 812
 813 # *** Svinval Standard Extension ***
 814 sinval_vma        0001011 ..... ..... 000 00000 1110011 @sfence_vma
 815 sfence_w_inval    0001100 00000 00000 000 00000 1110011
 816 sfence_inval_ir   0001100 00001 00000 000 00000 1110011
 817 hinval_vvma       0010011 ..... ..... 000 00000 1110011 @hfence_vvma
 818 hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma