target/riscv/insn32.decode

   1 #
   2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3 #
   4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5 #                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6 #
   7 # This program is free software; you can redistribute it and/or modify it
   8 # under the terms and conditions of the GNU General Public License,
   9 # version 2 or later, as published by the Free Software Foundation.
  10 #
  11 # This program is distributed in the hope it will be useful, but WITHOUT
  12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 # more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along with
  17 # this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19 # Fields:
  20 %rs3       27:5
  21 %rs2       20:5
  22 %rs1       15:5
  23 %rd        7:5
  24 %sh5       20:5
  25
  26 %sh7    20:7
  27 %csr    20:12
  28 %rm     12:3
  29 %nf     29:3                     !function=ex_plus_1
  30
  31 # immediates:
  32 %imm_i    20:s12
  33 %imm_s    25:s7 7:5
  34 %imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
  35 %imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
  36 %imm_u    12:s20                 !function=ex_shift_12
  37
  38 # Argument sets:
  39 &empty
  40 &b    imm rs2 rs1
  41 &i    imm rs1 rd
  42 &j    imm rd
  43 &r    rd rs1 rs2
  44 &r2   rd rs1
  45 &r2_s rs1 rs2
  46 &s    imm rs1 rs2
  47 &u    imm rd
  48 &shift     shamt rs1 rd
  49 &atomic    aq rl rs2 rs1 rd
  50 &rmrr      vm rd rs1 rs2
  51 &rmr       vm rd rs2
  52 &r2nfvm    vm rd rs1 nf
  53 &rnfvm     vm rd rs1 rs2 nf
  54
  55 # Formats 32:
  56 @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
  57 @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
  58 @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
  59 @s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
  60 @u       ....................      ..... ....... &u      imm=%imm_u          %rd
  61 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
  62
  63 @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh7     %rs1 %rd
  64 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
  65
  66 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
  67 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd
  68
  69 @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  70 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  71 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
  72 @r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
  73 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
  74 @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
  75 @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
  76 @r_nfvm  ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
  77 @r2rd    .......   ..... ..... ... ..... ....... %rs2 %rd
  78 @r_vm    ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
  79 @r_vm_1  ...... . ..... ..... ... ..... .......    &rmrr vm=1 %rs2 %rs1 %rd
  80 @r_vm_0  ...... . ..... ..... ... ..... .......    &rmrr vm=0 %rs2 %rs1 %rd
  81 @r2_zimm11 . zimm:11  ..... ... ..... ....... %rs1 %rd
  82 @r2_zimm10 .. zimm:10  ..... ... ..... ....... %rs1 %rd
  83 @r2_s    .......   ..... ..... ... ..... ....... %rs2 %rs1
  84
  85 @hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  86 @hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  87
  88 @sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
  89 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
  90
  91 # Formats 64:
  92 @sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
  93
  94 # *** Privileged Instructions ***
  95 ecall       000000000000     00000 000 00000 1110011
  96 ebreak      000000000001     00000 000 00000 1110011
  97 uret        0000000    00010 00000 000 00000 1110011
  98 sret        0001000    00010 00000 000 00000 1110011
  99 mret        0011000    00010 00000 000 00000 1110011
 100 wfi         0001000    00101 00000 000 00000 1110011
 101 sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
 102 sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
 103
 104 # *** RV32I Base Instruction Set ***
 105 lui      ....................       ..... 0110111 @u
 106 auipc    ....................       ..... 0010111 @u
 107 jal      ....................       ..... 1101111 @j
 108 jalr     ............     ..... 000 ..... 1100111 @i
 109 beq      ....... .....    ..... 000 ..... 1100011 @b
 110 bne      ....... .....    ..... 001 ..... 1100011 @b
 111 blt      ....... .....    ..... 100 ..... 1100011 @b
 112 bge      ....... .....    ..... 101 ..... 1100011 @b
 113 bltu     ....... .....    ..... 110 ..... 1100011 @b
 114 bgeu     ....... .....    ..... 111 ..... 1100011 @b
 115 lb       ............     ..... 000 ..... 0000011 @i
 116 lh       ............     ..... 001 ..... 0000011 @i
 117 lw       ............     ..... 010 ..... 0000011 @i
 118 lbu      ............     ..... 100 ..... 0000011 @i
 119 lhu      ............     ..... 101 ..... 0000011 @i
 120 sb       .......  .....   ..... 000 ..... 0100011 @s
 121 sh       .......  .....   ..... 001 ..... 0100011 @s
 122 sw       .......  .....   ..... 010 ..... 0100011 @s
 123 addi     ............     ..... 000 ..... 0010011 @i
 124 slti     ............     ..... 010 ..... 0010011 @i
 125 sltiu    ............     ..... 011 ..... 0010011 @i
 126 xori     ............     ..... 100 ..... 0010011 @i
 127 ori      ............     ..... 110 ..... 0010011 @i
 128 andi     ............     ..... 111 ..... 0010011 @i
 129 slli     00000. ......    ..... 001 ..... 0010011 @sh
 130 srli     00000. ......    ..... 101 ..... 0010011 @sh
 131 srai     01000. ......    ..... 101 ..... 0010011 @sh
 132 add      0000000 .....    ..... 000 ..... 0110011 @r
 133 sub      0100000 .....    ..... 000 ..... 0110011 @r
 134 sll      0000000 .....    ..... 001 ..... 0110011 @r
 135 slt      0000000 .....    ..... 010 ..... 0110011 @r
 136 sltu     0000000 .....    ..... 011 ..... 0110011 @r
 137 xor      0000000 .....    ..... 100 ..... 0110011 @r
 138 srl      0000000 .....    ..... 101 ..... 0110011 @r
 139 sra      0100000 .....    ..... 101 ..... 0110011 @r
 140 or       0000000 .....    ..... 110 ..... 0110011 @r
 141 and      0000000 .....    ..... 111 ..... 0110011 @r
 142 fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
 143 fence_i  ---- ----   ----   ----- 001 ----- 0001111
 144 csrrw    ............     ..... 001 ..... 1110011 @csr
 145 csrrs    ............     ..... 010 ..... 1110011 @csr
 146 csrrc    ............     ..... 011 ..... 1110011 @csr
 147 csrrwi   ............     ..... 101 ..... 1110011 @csr
 148 csrrsi   ............     ..... 110 ..... 1110011 @csr
 149 csrrci   ............     ..... 111 ..... 1110011 @csr
 150
 151 # *** RV64I Base Instruction Set (in addition to RV32I) ***
 152 lwu      ............   ..... 110 ..... 0000011 @i
 153 ld       ............   ..... 011 ..... 0000011 @i
 154 sd       ....... .....  ..... 011 ..... 0100011 @s
 155 addiw    ............   ..... 000 ..... 0011011 @i
 156 slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
 157 srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
 158 sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
 159 addw     0000000 .....  ..... 000 ..... 0111011 @r
 160 subw     0100000 .....  ..... 000 ..... 0111011 @r
 161 sllw     0000000 .....  ..... 001 ..... 0111011 @r
 162 srlw     0000000 .....  ..... 101 ..... 0111011 @r
 163 sraw     0100000 .....  ..... 101 ..... 0111011 @r
 164
 165 # *** RV32M Standard Extension ***
 166 mul      0000001 .....  ..... 000 ..... 0110011 @r
 167 mulh     0000001 .....  ..... 001 ..... 0110011 @r
 168 mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
 169 mulhu    0000001 .....  ..... 011 ..... 0110011 @r
 170 div      0000001 .....  ..... 100 ..... 0110011 @r
 171 divu     0000001 .....  ..... 101 ..... 0110011 @r
 172 rem      0000001 .....  ..... 110 ..... 0110011 @r
 173 remu     0000001 .....  ..... 111 ..... 0110011 @r
 174
 175 # *** RV64M Standard Extension (in addition to RV32M) ***
 176 mulw     0000001 .....  ..... 000 ..... 0111011 @r
 177 divw     0000001 .....  ..... 100 ..... 0111011 @r
 178 divuw    0000001 .....  ..... 101 ..... 0111011 @r
 179 remw     0000001 .....  ..... 110 ..... 0111011 @r
 180 remuw    0000001 .....  ..... 111 ..... 0111011 @r
 181
 182 # *** RV32A Standard Extension ***
 183 lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
 184 sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
 185 amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
 186 amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
 187 amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
 188 amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
 189 amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
 190 amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
 191 amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
 192 amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
 193 amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
 194
 195 # *** RV64A Standard Extension (in addition to RV32A) ***
 196 lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
 197 sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
 198 amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
 199 amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
 200 amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
 201 amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
 202 amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
 203 amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
 204 amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
 205 amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
 206 amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
 207
 208 # *** RV32F Standard Extension ***
 209 flw        ............   ..... 010 ..... 0000111 @i
 210 fsw        .......  ..... ..... 010 ..... 0100111 @s
 211 fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
 212 fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
 213 fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
 214 fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
 215 fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
 216 fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
 217 fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
 218 fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
 219 fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
 220 fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
 221 fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
 222 fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
 223 fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
 224 fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
 225 fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
 226 fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
 227 fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
 228 feq_s      1010000  ..... ..... 010 ..... 1010011 @r
 229 flt_s      1010000  ..... ..... 001 ..... 1010011 @r
 230 fle_s      1010000  ..... ..... 000 ..... 1010011 @r
 231 fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
 232 fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 233 fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 234 fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
 235
 236 # *** RV64F Standard Extension (in addition to RV32F) ***
 237 fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
 238 fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
 239 fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
 240 fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
 241
 242 # *** RV32D Standard Extension ***
 243 fld        ............   ..... 011 ..... 0000111 @i
 244 fsd        ....... .....  ..... 011 ..... 0100111 @s
 245 fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
 246 fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
 247 fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
 248 fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
 249 fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
 250 fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
 251 fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
 252 fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
 253 fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
 254 fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
 255 fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
 256 fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
 257 fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
 258 fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
 259 fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
 260 fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
 261 feq_d      1010001  ..... ..... 010 ..... 1010011 @r
 262 flt_d      1010001  ..... ..... 001 ..... 1010011 @r
 263 fle_d      1010001  ..... ..... 000 ..... 1010011 @r
 264 fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
 265 fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
 266 fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
 267 fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 268 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 269
 270 # *** RV64D Standard Extension (in addition to RV32D) ***
 271 fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
 272 fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
 273 fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
 274 fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
 275 fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
 276 fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 277
 278 # *** RV32H Base Instruction Set ***
 279 hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
 280 hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
 281 hlv_h       0110010  00000  ..... 100 ..... 1110011 @r2
 282 hlv_hu      0110010  00001  ..... 100 ..... 1110011 @r2
 283 hlvx_hu     0110010  00011  ..... 100 ..... 1110011 @r2
 284 hlv_w       0110100  00000  ..... 100 ..... 1110011 @r2
 285 hlvx_wu     0110100  00011  ..... 100 ..... 1110011 @r2
 286 hsv_b       0110001  .....  ..... 100 00000 1110011 @r2_s
 287 hsv_h       0110011  .....  ..... 100 00000 1110011 @r2_s
 288 hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
 289 hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
 290 hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 291
 292 # *** RV64H Base Instruction Set ***
 293 hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 294 hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 295 hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 296
 297 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
 298 # Vector unit-stride load/store insns.
 299 vle8_v     ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
 300 vle16_v    ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
 301 vle32_v    ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
 302 vle64_v    ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
 303 vse8_v     ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
 304 vse16_v    ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
 305 vse32_v    ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
 306 vse64_v    ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
 307
 308 # Vector unit-stride mask load/store insns.
 309 vlm_v      000 000 1 01011 ..... 000 ..... 0000111 @r2
 310 vsm_v      000 000 1 01011 ..... 000 ..... 0100111 @r2
 311
 312 # Vector strided insns.
 313 vlse8_v     ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
 314 vlse16_v    ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
 315 vlse32_v    ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
 316 vlse64_v    ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
 317 vsse8_v     ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
 318 vsse16_v    ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
 319 vsse32_v    ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
 320 vsse64_v    ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
 321
 322 # Vector ordered-indexed and unordered-indexed load insns.
 323 vlxei8_v      ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
 324 vlxei16_v     ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
 325 vlxei32_v     ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
 326 vlxei64_v     ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
 327
 328 # Vector ordered-indexed and unordered-indexed store insns.
 329 vsxei8_v      ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
 330 vsxei16_v     ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
 331 vsxei32_v     ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
 332 vsxei64_v     ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
 333
 334 # Vector unit-stride fault-only-first load insns.
 335 vle8ff_v      ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
 336 vle16ff_v     ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
 337 vle32ff_v     ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
 338 vle64ff_v     ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
 339
 340 # Vector whole register insns
 341 vl1re8_v      000 000 1 01000 ..... 000 ..... 0000111 @r2
 342 vl1re16_v     000 000 1 01000 ..... 101 ..... 0000111 @r2
 343 vl1re32_v     000 000 1 01000 ..... 110 ..... 0000111 @r2
 344 vl1re64_v     000 000 1 01000 ..... 111 ..... 0000111 @r2
 345 vl2re8_v      001 000 1 01000 ..... 000 ..... 0000111 @r2
 346 vl2re16_v     001 000 1 01000 ..... 101 ..... 0000111 @r2
 347 vl2re32_v     001 000 1 01000 ..... 110 ..... 0000111 @r2
 348 vl2re64_v     001 000 1 01000 ..... 111 ..... 0000111 @r2
 349 vl4re8_v      011 000 1 01000 ..... 000 ..... 0000111 @r2
 350 vl4re16_v     011 000 1 01000 ..... 101 ..... 0000111 @r2
 351 vl4re32_v     011 000 1 01000 ..... 110 ..... 0000111 @r2
 352 vl4re64_v     011 000 1 01000 ..... 111 ..... 0000111 @r2
 353 vl8re8_v      111 000 1 01000 ..... 000 ..... 0000111 @r2
 354 vl8re16_v     111 000 1 01000 ..... 101 ..... 0000111 @r2
 355 vl8re32_v     111 000 1 01000 ..... 110 ..... 0000111 @r2
 356 vl8re64_v     111 000 1 01000 ..... 111 ..... 0000111 @r2
 357 vs1r_v        000 000 1 01000 ..... 000 ..... 0100111 @r2
 358 vs2r_v        001 000 1 01000 ..... 000 ..... 0100111 @r2
 359 vs4r_v        011 000 1 01000 ..... 000 ..... 0100111 @r2
 360 vs8r_v        111 000 1 01000 ..... 000 ..... 0100111 @r2
 361
 362 # *** new major opcode OP-V ***
 363 vadd_vv         000000 . ..... ..... 000 ..... 1010111 @r_vm
 364 vadd_vx         000000 . ..... ..... 100 ..... 1010111 @r_vm
 365 vadd_vi         000000 . ..... ..... 011 ..... 1010111 @r_vm
 366 vsub_vv         000010 . ..... ..... 000 ..... 1010111 @r_vm
 367 vsub_vx         000010 . ..... ..... 100 ..... 1010111 @r_vm
 368 vrsub_vx        000011 . ..... ..... 100 ..... 1010111 @r_vm
 369 vrsub_vi        000011 . ..... ..... 011 ..... 1010111 @r_vm
 370 vwaddu_vv       110000 . ..... ..... 010 ..... 1010111 @r_vm
 371 vwaddu_vx       110000 . ..... ..... 110 ..... 1010111 @r_vm
 372 vwadd_vv        110001 . ..... ..... 010 ..... 1010111 @r_vm
 373 vwadd_vx        110001 . ..... ..... 110 ..... 1010111 @r_vm
 374 vwsubu_vv       110010 . ..... ..... 010 ..... 1010111 @r_vm
 375 vwsubu_vx       110010 . ..... ..... 110 ..... 1010111 @r_vm
 376 vwsub_vv        110011 . ..... ..... 010 ..... 1010111 @r_vm
 377 vwsub_vx        110011 . ..... ..... 110 ..... 1010111 @r_vm
 378 vwaddu_wv       110100 . ..... ..... 010 ..... 1010111 @r_vm
 379 vwaddu_wx       110100 . ..... ..... 110 ..... 1010111 @r_vm
 380 vwadd_wv        110101 . ..... ..... 010 ..... 1010111 @r_vm
 381 vwadd_wx        110101 . ..... ..... 110 ..... 1010111 @r_vm
 382 vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
 383 vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
 384 vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
 385 vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
 386 vadc_vvm        010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
 387 vadc_vxm        010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
 388 vadc_vim        010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
 389 vmadc_vvm       010001 . ..... ..... 000 ..... 1010111 @r_vm
 390 vmadc_vxm       010001 . ..... ..... 100 ..... 1010111 @r_vm
 391 vmadc_vim       010001 . ..... ..... 011 ..... 1010111 @r_vm
 392 vsbc_vvm        010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
 393 vsbc_vxm        010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
 394 vmsbc_vvm       010011 . ..... ..... 000 ..... 1010111 @r_vm
 395 vmsbc_vxm       010011 . ..... ..... 100 ..... 1010111 @r_vm
 396 vand_vv         001001 . ..... ..... 000 ..... 1010111 @r_vm
 397 vand_vx         001001 . ..... ..... 100 ..... 1010111 @r_vm
 398 vand_vi         001001 . ..... ..... 011 ..... 1010111 @r_vm
 399 vor_vv          001010 . ..... ..... 000 ..... 1010111 @r_vm
 400 vor_vx          001010 . ..... ..... 100 ..... 1010111 @r_vm
 401 vor_vi          001010 . ..... ..... 011 ..... 1010111 @r_vm
 402 vxor_vv         001011 . ..... ..... 000 ..... 1010111 @r_vm
 403 vxor_vx         001011 . ..... ..... 100 ..... 1010111 @r_vm
 404 vxor_vi         001011 . ..... ..... 011 ..... 1010111 @r_vm
 405 vsll_vv         100101 . ..... ..... 000 ..... 1010111 @r_vm
 406 vsll_vx         100101 . ..... ..... 100 ..... 1010111 @r_vm
 407 vsll_vi         100101 . ..... ..... 011 ..... 1010111 @r_vm
 408 vsrl_vv         101000 . ..... ..... 000 ..... 1010111 @r_vm
 409 vsrl_vx         101000 . ..... ..... 100 ..... 1010111 @r_vm
 410 vsrl_vi         101000 . ..... ..... 011 ..... 1010111 @r_vm
 411 vsra_vv         101001 . ..... ..... 000 ..... 1010111 @r_vm
 412 vsra_vx         101001 . ..... ..... 100 ..... 1010111 @r_vm
 413 vsra_vi         101001 . ..... ..... 011 ..... 1010111 @r_vm
 414 vnsrl_wv        101100 . ..... ..... 000 ..... 1010111 @r_vm
 415 vnsrl_wx        101100 . ..... ..... 100 ..... 1010111 @r_vm
 416 vnsrl_wi        101100 . ..... ..... 011 ..... 1010111 @r_vm
 417 vnsra_wv        101101 . ..... ..... 000 ..... 1010111 @r_vm
 418 vnsra_wx        101101 . ..... ..... 100 ..... 1010111 @r_vm
 419 vnsra_wi        101101 . ..... ..... 011 ..... 1010111 @r_vm
 420 vmseq_vv        011000 . ..... ..... 000 ..... 1010111 @r_vm
 421 vmseq_vx        011000 . ..... ..... 100 ..... 1010111 @r_vm
 422 vmseq_vi        011000 . ..... ..... 011 ..... 1010111 @r_vm
 423 vmsne_vv        011001 . ..... ..... 000 ..... 1010111 @r_vm
 424 vmsne_vx        011001 . ..... ..... 100 ..... 1010111 @r_vm
 425 vmsne_vi        011001 . ..... ..... 011 ..... 1010111 @r_vm
 426 vmsltu_vv       011010 . ..... ..... 000 ..... 1010111 @r_vm
 427 vmsltu_vx       011010 . ..... ..... 100 ..... 1010111 @r_vm
 428 vmslt_vv        011011 . ..... ..... 000 ..... 1010111 @r_vm
 429 vmslt_vx        011011 . ..... ..... 100 ..... 1010111 @r_vm
 430 vmsleu_vv       011100 . ..... ..... 000 ..... 1010111 @r_vm
 431 vmsleu_vx       011100 . ..... ..... 100 ..... 1010111 @r_vm
 432 vmsleu_vi       011100 . ..... ..... 011 ..... 1010111 @r_vm
 433 vmsle_vv        011101 . ..... ..... 000 ..... 1010111 @r_vm
 434 vmsle_vx        011101 . ..... ..... 100 ..... 1010111 @r_vm
 435 vmsle_vi        011101 . ..... ..... 011 ..... 1010111 @r_vm
 436 vmsgtu_vx       011110 . ..... ..... 100 ..... 1010111 @r_vm
 437 vmsgtu_vi       011110 . ..... ..... 011 ..... 1010111 @r_vm
 438 vmsgt_vx        011111 . ..... ..... 100 ..... 1010111 @r_vm
 439 vmsgt_vi        011111 . ..... ..... 011 ..... 1010111 @r_vm
 440 vminu_vv        000100 . ..... ..... 000 ..... 1010111 @r_vm
 441 vminu_vx        000100 . ..... ..... 100 ..... 1010111 @r_vm
 442 vmin_vv         000101 . ..... ..... 000 ..... 1010111 @r_vm
 443 vmin_vx         000101 . ..... ..... 100 ..... 1010111 @r_vm
 444 vmaxu_vv        000110 . ..... ..... 000 ..... 1010111 @r_vm
 445 vmaxu_vx        000110 . ..... ..... 100 ..... 1010111 @r_vm
 446 vmax_vv         000111 . ..... ..... 000 ..... 1010111 @r_vm
 447 vmax_vx         000111 . ..... ..... 100 ..... 1010111 @r_vm
 448 vmul_vv         100101 . ..... ..... 010 ..... 1010111 @r_vm
 449 vmul_vx         100101 . ..... ..... 110 ..... 1010111 @r_vm
 450 vmulh_vv        100111 . ..... ..... 010 ..... 1010111 @r_vm
 451 vmulh_vx        100111 . ..... ..... 110 ..... 1010111 @r_vm
 452 vmulhu_vv       100100 . ..... ..... 010 ..... 1010111 @r_vm
 453 vmulhu_vx       100100 . ..... ..... 110 ..... 1010111 @r_vm
 454 vmulhsu_vv      100110 . ..... ..... 010 ..... 1010111 @r_vm
 455 vmulhsu_vx      100110 . ..... ..... 110 ..... 1010111 @r_vm
 456 vdivu_vv        100000 . ..... ..... 010 ..... 1010111 @r_vm
 457 vdivu_vx        100000 . ..... ..... 110 ..... 1010111 @r_vm
 458 vdiv_vv         100001 . ..... ..... 010 ..... 1010111 @r_vm
 459 vdiv_vx         100001 . ..... ..... 110 ..... 1010111 @r_vm
 460 vremu_vv        100010 . ..... ..... 010 ..... 1010111 @r_vm
 461 vremu_vx        100010 . ..... ..... 110 ..... 1010111 @r_vm
 462 vrem_vv         100011 . ..... ..... 010 ..... 1010111 @r_vm
 463 vrem_vx         100011 . ..... ..... 110 ..... 1010111 @r_vm
 464 vwmulu_vv       111000 . ..... ..... 010 ..... 1010111 @r_vm
 465 vwmulu_vx       111000 . ..... ..... 110 ..... 1010111 @r_vm
 466 vwmulsu_vv      111010 . ..... ..... 010 ..... 1010111 @r_vm
 467 vwmulsu_vx      111010 . ..... ..... 110 ..... 1010111 @r_vm
 468 vwmul_vv        111011 . ..... ..... 010 ..... 1010111 @r_vm
 469 vwmul_vx        111011 . ..... ..... 110 ..... 1010111 @r_vm
 470 vmacc_vv        101101 . ..... ..... 010 ..... 1010111 @r_vm
 471 vmacc_vx        101101 . ..... ..... 110 ..... 1010111 @r_vm
 472 vnmsac_vv       101111 . ..... ..... 010 ..... 1010111 @r_vm
 473 vnmsac_vx       101111 . ..... ..... 110 ..... 1010111 @r_vm
 474 vmadd_vv        101001 . ..... ..... 010 ..... 1010111 @r_vm
 475 vmadd_vx        101001 . ..... ..... 110 ..... 1010111 @r_vm
 476 vnmsub_vv       101011 . ..... ..... 010 ..... 1010111 @r_vm
 477 vnmsub_vx       101011 . ..... ..... 110 ..... 1010111 @r_vm
 478 vwmaccu_vv      111100 . ..... ..... 010 ..... 1010111 @r_vm
 479 vwmaccu_vx      111100 . ..... ..... 110 ..... 1010111 @r_vm
 480 vwmacc_vv       111101 . ..... ..... 010 ..... 1010111 @r_vm
 481 vwmacc_vx       111101 . ..... ..... 110 ..... 1010111 @r_vm
 482 vwmaccsu_vv     111111 . ..... ..... 010 ..... 1010111 @r_vm
 483 vwmaccsu_vx     111111 . ..... ..... 110 ..... 1010111 @r_vm
 484 vwmaccus_vx     111110 . ..... ..... 110 ..... 1010111 @r_vm
 485 vmv_v_v         010111 1 00000 ..... 000 ..... 1010111 @r2
 486 vmv_v_x         010111 1 00000 ..... 100 ..... 1010111 @r2
 487 vmv_v_i         010111 1 00000 ..... 011 ..... 1010111 @r2
 488 vmerge_vvm      010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
 489 vmerge_vxm      010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
 490 vmerge_vim      010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
 491 vsaddu_vv       100000 . ..... ..... 000 ..... 1010111 @r_vm
 492 vsaddu_vx       100000 . ..... ..... 100 ..... 1010111 @r_vm
 493 vsaddu_vi       100000 . ..... ..... 011 ..... 1010111 @r_vm
 494 vsadd_vv        100001 . ..... ..... 000 ..... 1010111 @r_vm
 495 vsadd_vx        100001 . ..... ..... 100 ..... 1010111 @r_vm
 496 vsadd_vi        100001 . ..... ..... 011 ..... 1010111 @r_vm
 497 vssubu_vv       100010 . ..... ..... 000 ..... 1010111 @r_vm
 498 vssubu_vx       100010 . ..... ..... 100 ..... 1010111 @r_vm
 499 vssub_vv        100011 . ..... ..... 000 ..... 1010111 @r_vm
 500 vssub_vx        100011 . ..... ..... 100 ..... 1010111 @r_vm
 501 vaadd_vv        001001 . ..... ..... 010 ..... 1010111 @r_vm
 502 vaadd_vx        001001 . ..... ..... 110 ..... 1010111 @r_vm
 503 vaaddu_vv       001000 . ..... ..... 010 ..... 1010111 @r_vm
 504 vaaddu_vx       001000 . ..... ..... 110 ..... 1010111 @r_vm
 505 vasub_vv        001011 . ..... ..... 010 ..... 1010111 @r_vm
 506 vasub_vx        001011 . ..... ..... 110 ..... 1010111 @r_vm
 507 vasubu_vv       001010 . ..... ..... 010 ..... 1010111 @r_vm
 508 vasubu_vx       001010 . ..... ..... 110 ..... 1010111 @r_vm
 509 vsmul_vv        100111 . ..... ..... 000 ..... 1010111 @r_vm
 510 vsmul_vx        100111 . ..... ..... 100 ..... 1010111 @r_vm
 511 vssrl_vv        101010 . ..... ..... 000 ..... 1010111 @r_vm
 512 vssrl_vx        101010 . ..... ..... 100 ..... 1010111 @r_vm
 513 vssrl_vi        101010 . ..... ..... 011 ..... 1010111 @r_vm
 514 vssra_vv        101011 . ..... ..... 000 ..... 1010111 @r_vm
 515 vssra_vx        101011 . ..... ..... 100 ..... 1010111 @r_vm
 516 vssra_vi        101011 . ..... ..... 011 ..... 1010111 @r_vm
 517 vnclipu_wv      101110 . ..... ..... 000 ..... 1010111 @r_vm
 518 vnclipu_wx      101110 . ..... ..... 100 ..... 1010111 @r_vm
 519 vnclipu_wi      101110 . ..... ..... 011 ..... 1010111 @r_vm
 520 vnclip_wv       101111 . ..... ..... 000 ..... 1010111 @r_vm
 521 vnclip_wx       101111 . ..... ..... 100 ..... 1010111 @r_vm
 522 vnclip_wi       101111 . ..... ..... 011 ..... 1010111 @r_vm
 523 vfadd_vv        000000 . ..... ..... 001 ..... 1010111 @r_vm
 524 vfadd_vf        000000 . ..... ..... 101 ..... 1010111 @r_vm
 525 vfsub_vv        000010 . ..... ..... 001 ..... 1010111 @r_vm
 526 vfsub_vf        000010 . ..... ..... 101 ..... 1010111 @r_vm
 527 vfrsub_vf       100111 . ..... ..... 101 ..... 1010111 @r_vm
 528 vfwadd_vv       110000 . ..... ..... 001 ..... 1010111 @r_vm
 529 vfwadd_vf       110000 . ..... ..... 101 ..... 1010111 @r_vm
 530 vfwadd_wv       110100 . ..... ..... 001 ..... 1010111 @r_vm
 531 vfwadd_wf       110100 . ..... ..... 101 ..... 1010111 @r_vm
 532 vfwsub_vv       110010 . ..... ..... 001 ..... 1010111 @r_vm
 533 vfwsub_vf       110010 . ..... ..... 101 ..... 1010111 @r_vm
 534 vfwsub_wv       110110 . ..... ..... 001 ..... 1010111 @r_vm
 535 vfwsub_wf       110110 . ..... ..... 101 ..... 1010111 @r_vm
 536 vfmul_vv        100100 . ..... ..... 001 ..... 1010111 @r_vm
 537 vfmul_vf        100100 . ..... ..... 101 ..... 1010111 @r_vm
 538 vfdiv_vv        100000 . ..... ..... 001 ..... 1010111 @r_vm
 539 vfdiv_vf        100000 . ..... ..... 101 ..... 1010111 @r_vm
 540 vfrdiv_vf       100001 . ..... ..... 101 ..... 1010111 @r_vm
 541 vfwmul_vv       111000 . ..... ..... 001 ..... 1010111 @r_vm
 542 vfwmul_vf       111000 . ..... ..... 101 ..... 1010111 @r_vm
 543 vfmacc_vv       101100 . ..... ..... 001 ..... 1010111 @r_vm
 544 vfnmacc_vv      101101 . ..... ..... 001 ..... 1010111 @r_vm
 545 vfnmacc_vf      101101 . ..... ..... 101 ..... 1010111 @r_vm
 546 vfmacc_vf       101100 . ..... ..... 101 ..... 1010111 @r_vm
 547 vfmsac_vv       101110 . ..... ..... 001 ..... 1010111 @r_vm
 548 vfmsac_vf       101110 . ..... ..... 101 ..... 1010111 @r_vm
 549 vfnmsac_vv      101111 . ..... ..... 001 ..... 1010111 @r_vm
 550 vfnmsac_vf      101111 . ..... ..... 101 ..... 1010111 @r_vm
 551 vfmadd_vv       101000 . ..... ..... 001 ..... 1010111 @r_vm
 552 vfmadd_vf       101000 . ..... ..... 101 ..... 1010111 @r_vm
 553 vfnmadd_vv      101001 . ..... ..... 001 ..... 1010111 @r_vm
 554 vfnmadd_vf      101001 . ..... ..... 101 ..... 1010111 @r_vm
 555 vfmsub_vv       101010 . ..... ..... 001 ..... 1010111 @r_vm
 556 vfmsub_vf       101010 . ..... ..... 101 ..... 1010111 @r_vm
 557 vfnmsub_vv      101011 . ..... ..... 001 ..... 1010111 @r_vm
 558 vfnmsub_vf      101011 . ..... ..... 101 ..... 1010111 @r_vm
 559 vfwmacc_vv      111100 . ..... ..... 001 ..... 1010111 @r_vm
 560 vfwmacc_vf      111100 . ..... ..... 101 ..... 1010111 @r_vm
 561 vfwnmacc_vv     111101 . ..... ..... 001 ..... 1010111 @r_vm
 562 vfwnmacc_vf     111101 . ..... ..... 101 ..... 1010111 @r_vm
 563 vfwmsac_vv      111110 . ..... ..... 001 ..... 1010111 @r_vm
 564 vfwmsac_vf      111110 . ..... ..... 101 ..... 1010111 @r_vm
 565 vfwnmsac_vv     111111 . ..... ..... 001 ..... 1010111 @r_vm
 566 vfwnmsac_vf     111111 . ..... ..... 101 ..... 1010111 @r_vm
 567 vfsqrt_v        010011 . ..... 00000 001 ..... 1010111 @r2_vm
 568 vfrsqrt7_v      010011 . ..... 00100 001 ..... 1010111 @r2_vm
 569 vfrec7_v        010011 . ..... 00101 001 ..... 1010111 @r2_vm
 570 vfmin_vv        000100 . ..... ..... 001 ..... 1010111 @r_vm
 571 vfmin_vf        000100 . ..... ..... 101 ..... 1010111 @r_vm
 572 vfmax_vv        000110 . ..... ..... 001 ..... 1010111 @r_vm
 573 vfmax_vf        000110 . ..... ..... 101 ..... 1010111 @r_vm
 574 vfsgnj_vv       001000 . ..... ..... 001 ..... 1010111 @r_vm
 575 vfsgnj_vf       001000 . ..... ..... 101 ..... 1010111 @r_vm
 576 vfsgnjn_vv      001001 . ..... ..... 001 ..... 1010111 @r_vm
 577 vfsgnjn_vf      001001 . ..... ..... 101 ..... 1010111 @r_vm
 578 vfsgnjx_vv      001010 . ..... ..... 001 ..... 1010111 @r_vm
 579 vfsgnjx_vf      001010 . ..... ..... 101 ..... 1010111 @r_vm
 580 vfslide1up_vf   001110 . ..... ..... 101 ..... 1010111 @r_vm
 581 vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
 582 vmfeq_vv        011000 . ..... ..... 001 ..... 1010111 @r_vm
 583 vmfeq_vf        011000 . ..... ..... 101 ..... 1010111 @r_vm
 584 vmfne_vv        011100 . ..... ..... 001 ..... 1010111 @r_vm
 585 vmfne_vf        011100 . ..... ..... 101 ..... 1010111 @r_vm
 586 vmflt_vv        011011 . ..... ..... 001 ..... 1010111 @r_vm
 587 vmflt_vf        011011 . ..... ..... 101 ..... 1010111 @r_vm
 588 vmfle_vv        011001 . ..... ..... 001 ..... 1010111 @r_vm
 589 vmfle_vf        011001 . ..... ..... 101 ..... 1010111 @r_vm
 590 vmfgt_vf        011101 . ..... ..... 101 ..... 1010111 @r_vm
 591 vmfge_vf        011111 . ..... ..... 101 ..... 1010111 @r_vm
 592 vfclass_v       010011 . ..... 10000 001 ..... 1010111 @r2_vm
 593 vfmerge_vfm     010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
 594 vfmv_v_f        010111 1 00000 ..... 101 ..... 1010111 @r2
 595
 596 vfcvt_xu_f_v       010010 . ..... 00000 001 ..... 1010111 @r2_vm
 597 vfcvt_x_f_v        010010 . ..... 00001 001 ..... 1010111 @r2_vm
 598 vfcvt_f_xu_v       010010 . ..... 00010 001 ..... 1010111 @r2_vm
 599 vfcvt_f_x_v        010010 . ..... 00011 001 ..... 1010111 @r2_vm
 600 vfcvt_rtz_xu_f_v   010010 . ..... 00110 001 ..... 1010111 @r2_vm
 601 vfcvt_rtz_x_f_v    010010 . ..... 00111 001 ..... 1010111 @r2_vm
 602
 603 vfwcvt_xu_f_v      010010 . ..... 01000 001 ..... 1010111 @r2_vm
 604 vfwcvt_x_f_v       010010 . ..... 01001 001 ..... 1010111 @r2_vm
 605 vfwcvt_f_xu_v      010010 . ..... 01010 001 ..... 1010111 @r2_vm
 606 vfwcvt_f_x_v       010010 . ..... 01011 001 ..... 1010111 @r2_vm
 607 vfwcvt_f_f_v       010010 . ..... 01100 001 ..... 1010111 @r2_vm
 608 vfwcvt_rtz_xu_f_v  010010 . ..... 01110 001 ..... 1010111 @r2_vm
 609 vfwcvt_rtz_x_f_v   010010 . ..... 01111 001 ..... 1010111 @r2_vm
 610
 611 vfncvt_xu_f_w      010010 . ..... 10000 001 ..... 1010111 @r2_vm
 612 vfncvt_x_f_w       010010 . ..... 10001 001 ..... 1010111 @r2_vm
 613 vfncvt_f_xu_w      010010 . ..... 10010 001 ..... 1010111 @r2_vm
 614 vfncvt_f_x_w       010010 . ..... 10011 001 ..... 1010111 @r2_vm
 615 vfncvt_f_f_w       010010 . ..... 10100 001 ..... 1010111 @r2_vm
 616 vfncvt_rod_f_f_w   010010 . ..... 10101 001 ..... 1010111 @r2_vm
 617 vfncvt_rtz_xu_f_w  010010 . ..... 10110 001 ..... 1010111 @r2_vm
 618 vfncvt_rtz_x_f_w   010010 . ..... 10111 001 ..... 1010111 @r2_vm
 619
 620 vredsum_vs      000000 . ..... ..... 010 ..... 1010111 @r_vm
 621 vredand_vs      000001 . ..... ..... 010 ..... 1010111 @r_vm
 622 vredor_vs       000010 . ..... ..... 010 ..... 1010111 @r_vm
 623 vredxor_vs      000011 . ..... ..... 010 ..... 1010111 @r_vm
 624 vredminu_vs     000100 . ..... ..... 010 ..... 1010111 @r_vm
 625 vredmin_vs      000101 . ..... ..... 010 ..... 1010111 @r_vm
 626 vredmaxu_vs     000110 . ..... ..... 010 ..... 1010111 @r_vm
 627 vredmax_vs      000111 . ..... ..... 010 ..... 1010111 @r_vm
 628 vwredsumu_vs    110000 . ..... ..... 000 ..... 1010111 @r_vm
 629 vwredsum_vs     110001 . ..... ..... 000 ..... 1010111 @r_vm
 630 # Vector ordered and unordered reduction sum
 631 vfredsum_vs     0000-1 . ..... ..... 001 ..... 1010111 @r_vm
 632 vfredmin_vs     000101 . ..... ..... 001 ..... 1010111 @r_vm
 633 vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
 634 # Vector widening ordered and unordered float reduction sum
 635 vfwredsum_vs    1100-1 . ..... ..... 001 ..... 1010111 @r_vm
 636 vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
 637 vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
 638 vmandn_mm       011000 - ..... ..... 010 ..... 1010111 @r
 639 vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
 640 vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
 641 vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
 642 vmorn_mm        011100 - ..... ..... 010 ..... 1010111 @r
 643 vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
 644 vcpop_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
 645 vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
 646 vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
 647 vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
 648 vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
 649 viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
 650 vid_v           010100 . 00000 10001 010 ..... 1010111 @r1_vm
 651 vmv_x_s         010000 1 ..... 00000 010 ..... 1010111 @r2rd
 652 vmv_s_x         010000 1 00000 ..... 110 ..... 1010111 @r2
 653 vfmv_f_s        010000 1 ..... 00000 001 ..... 1010111 @r2rd
 654 vfmv_s_f        010000 1 00000 ..... 101 ..... 1010111 @r2
 655 vslideup_vx     001110 . ..... ..... 100 ..... 1010111 @r_vm
 656 vslideup_vi     001110 . ..... ..... 011 ..... 1010111 @r_vm
 657 vslide1up_vx    001110 . ..... ..... 110 ..... 1010111 @r_vm
 658 vslidedown_vx   001111 . ..... ..... 100 ..... 1010111 @r_vm
 659 vslidedown_vi   001111 . ..... ..... 011 ..... 1010111 @r_vm
 660 vslide1down_vx  001111 . ..... ..... 110 ..... 1010111 @r_vm
 661 vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
 662 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
 663 vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
 664 vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
 665 vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
 666 vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
 667 vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
 668 vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd
 669 vmv8r_v         100111 1 ..... 00111 011 ..... 1010111 @r2rd
 670
 671 # Vector Integer Extension
 672 vzext_vf2       010010 . ..... 00110 010 ..... 1010111 @r2_vm
 673 vzext_vf4       010010 . ..... 00100 010 ..... 1010111 @r2_vm
 674 vzext_vf8       010010 . ..... 00010 010 ..... 1010111 @r2_vm
 675 vsext_vf2       010010 . ..... 00111 010 ..... 1010111 @r2_vm
 676 vsext_vf4       010010 . ..... 00101 010 ..... 1010111 @r2_vm
 677 vsext_vf8       010010 . ..... 00011 010 ..... 1010111 @r2_vm
 678
 679 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm11
 680 vsetivli        11 .......... ..... 111 ..... 1010111  @r2_zimm10
 681 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 682
 683 # *** RV32 Zba Standard Extension ***
 684 sh1add     0010000 .......... 010 ..... 0110011 @r
 685 sh2add     0010000 .......... 100 ..... 0110011 @r
 686 sh3add     0010000 .......... 110 ..... 0110011 @r
 687
 688 # *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
 689 add_uw     0000100 .......... 000 ..... 0111011 @r
 690 sh1add_uw  0010000 .......... 010 ..... 0111011 @r
 691 sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 692 sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 693 slli_uw    00001 ............ 001 ..... 0011011 @sh
 694
 695 # *** RV32 Zbb Standard Extension ***
 696 andn       0100000 .......... 111 ..... 0110011 @r
 697 clz        011000 000000 ..... 001 ..... 0010011 @r2
 698 cpop       011000 000010 ..... 001 ..... 0010011 @r2
 699 ctz        011000 000001 ..... 001 ..... 0010011 @r2
 700 max        0000101 .......... 110 ..... 0110011 @r
 701 maxu       0000101 .......... 111 ..... 0110011 @r
 702 min        0000101 .......... 100 ..... 0110011 @r
 703 minu       0000101 .......... 101 ..... 0110011 @r
 704 orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 705 orn        0100000 .......... 110 ..... 0110011 @r
 706 # The encoding for rev8 differs between RV32 and RV64.
 707 # rev8_32 denotes the RV32 variant.
 708 rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
 709 rol        0110000 .......... 001 ..... 0110011 @r
 710 ror        0110000 .......... 101 ..... 0110011 @r
 711 rori       01100 ............ 101 ..... 0010011 @sh
 712 sext_b     011000 000100 ..... 001 ..... 0010011 @r2
 713 sext_h     011000 000101 ..... 001 ..... 0010011 @r2
 714 xnor       0100000 .......... 100 ..... 0110011 @r
 715 # The encoding for zext.h differs between RV32 and RV64.
 716 # zext_h_32 denotes the RV32 variant.
 717 zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
 718
 719 # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
 720 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 721 ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 722 cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 723 # The encoding for rev8 differs between RV32 and RV64.
 724 # When executing on RV64, the encoding used in RV32 is an illegal
 725 # instruction, so we use different handler functions to differentiate.
 726 rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
 727 rolw       0110000 .......... 001 ..... 0111011 @r
 728 roriw      0110000 .......... 101 ..... 0011011 @sh5
 729 rorw       0110000 .......... 101 ..... 0111011 @r
 730 # The encoding for zext.h differs between RV32 and RV64.
 731 # When executing on RV64, the encoding used in RV32 is an illegal
 732 # instruction, so we use different handler functions to differentiate.
 733 zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 734
 735 # *** RV32 Zbc Standard Extension ***
 736 clmul      0000101 .......... 001 ..... 0110011 @r
 737 clmulh     0000101 .......... 011 ..... 0110011 @r
 738 clmulr     0000101 .......... 010 ..... 0110011 @r
 739
 740 # *** RV32 Zbs Standard Extension ***
 741 bclr       0100100 .......... 001 ..... 0110011 @r
 742 bclri      01001. ........... 001 ..... 0010011 @sh
 743 bext       0100100 .......... 101 ..... 0110011 @r
 744 bexti      01001. ........... 101 ..... 0010011 @sh
 745 binv       0110100 .......... 001 ..... 0110011 @r
 746 binvi      01101. ........... 001 ..... 0010011 @sh
 747 bset       0010100 .......... 001 ..... 0110011 @r
 748 bseti      00101. ........... 001 ..... 0010011 @sh
 749
 750 # *** RV32 Zfh Extension ***
 751 flh        ............   ..... 001 ..... 0000111 @i
 752 fsh        .......  ..... ..... 001 ..... 0100111 @s
 753 fmadd_h    ..... 10 ..... ..... ... ..... 1000011 @r4_rm
 754 fmsub_h    ..... 10 ..... ..... ... ..... 1000111 @r4_rm
 755 fnmsub_h   ..... 10 ..... ..... ... ..... 1001011 @r4_rm
 756 fnmadd_h   ..... 10 ..... ..... ... ..... 1001111 @r4_rm
 757 fadd_h     0000010  ..... ..... ... ..... 1010011 @r_rm
 758 fsub_h     0000110  ..... ..... ... ..... 1010011 @r_rm
 759 fmul_h     0001010  ..... ..... ... ..... 1010011 @r_rm
 760 fdiv_h     0001110  ..... ..... ... ..... 1010011 @r_rm
 761 fsqrt_h    0101110  00000 ..... ... ..... 1010011 @r2_rm
 762 fsgnj_h    0010010  ..... ..... 000 ..... 1010011 @r
 763 fsgnjn_h   0010010  ..... ..... 001 ..... 1010011 @r
 764 fsgnjx_h   0010010  ..... ..... 010 ..... 1010011 @r
 765 fmin_h     0010110  ..... ..... 000 ..... 1010011 @r
 766 fmax_h     0010110  ..... ..... 001 ..... 1010011 @r
 767 fcvt_h_s   0100010  00000 ..... ... ..... 1010011 @r2_rm
 768 fcvt_s_h   0100000  00010 ..... ... ..... 1010011 @r2_rm
 769 fcvt_h_d   0100010  00001 ..... ... ..... 1010011 @r2_rm
 770 fcvt_d_h   0100001  00010 ..... ... ..... 1010011 @r2_rm
 771 fcvt_w_h   1100010  00000 ..... ... ..... 1010011 @r2_rm
 772 fcvt_wu_h  1100010  00001 ..... ... ..... 1010011 @r2_rm
 773 fmv_x_h    1110010  00000 ..... 000 ..... 1010011 @r2
 774 feq_h      1010010  ..... ..... 010 ..... 1010011 @r
 775 flt_h      1010010  ..... ..... 001 ..... 1010011 @r
 776 fle_h      1010010  ..... ..... 000 ..... 1010011 @r
 777 fclass_h   1110010  00000 ..... 001 ..... 1010011 @r2
 778 fcvt_h_w   1101010  00000 ..... ... ..... 1010011 @r2_rm
 779 fcvt_h_wu  1101010  00001 ..... ... ..... 1010011 @r2_rm
 780 fmv_h_x    1111010  00000 ..... 000 ..... 1010011 @r2
 781
 782 # *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
 783 fcvt_l_h   1100010  00010 ..... ... ..... 1010011 @r2_rm
 784 fcvt_lu_h  1100010  00011 ..... ... ..... 1010011 @r2_rm
 785 fcvt_h_l   1101010  00010 ..... ... ..... 1010011 @r2_rm
 786 fcvt_h_lu  1101010  00011 ..... ... ..... 1010011 @r2_rm