]> git.proxmox.com Git - mirror_qemu.git/blob - target/riscv/insn32.decode
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target/riscv: rvv-1.0: widening integer multiply-add instructions
[mirror_qemu.git] / target / riscv / insn32.decode
1 #
2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 #
4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
5 # Bastian Koppelmann, kbastian@mail.uni-paderborn.de
6 #
7 # This program is free software; you can redistribute it and/or modify it
8 # under the terms and conditions of the GNU General Public License,
9 # version 2 or later, as published by the Free Software Foundation.
10 #
11 # This program is distributed in the hope it will be useful, but WITHOUT
12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 # more details.
15 #
16 # You should have received a copy of the GNU General Public License along with
17 # this program. If not, see <http://www.gnu.org/licenses/>.
18
19 # Fields:
20 %rs3 27:5
21 %rs2 20:5
22 %rs1 15:5
23 %rd 7:5
24 %sh5 20:5
25
26 %sh7 20:7
27 %csr 20:12
28 %rm 12:3
29 %nf 29:3 !function=ex_plus_1
30
31 # immediates:
32 %imm_i 20:s12
33 %imm_s 25:s7 7:5
34 %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
35 %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
36 %imm_u 12:s20 !function=ex_shift_12
37
38 # Argument sets:
39 &empty
40 &b imm rs2 rs1
41 &i imm rs1 rd
42 &j imm rd
43 &r rd rs1 rs2
44 &r2 rd rs1
45 &r2_s rs1 rs2
46 &s imm rs1 rs2
47 &u imm rd
48 &shift shamt rs1 rd
49 &atomic aq rl rs2 rs1 rd
50 &rmrr vm rd rs1 rs2
51 &rmr vm rd rs2
52 &r2nfvm vm rd rs1 nf
53 &rnfvm vm rd rs1 rs2 nf
54
55 # Formats 32:
56 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
57 @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
58 @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
59 @s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
60 @u .................... ..... ....... &u imm=%imm_u %rd
61 @j .................... ..... ....... &j imm=%imm_j %rd
62
63 @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
64 @csr ............ ..... ... ..... ....... %csr %rs1 %rd
65
66 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
67 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
68
69 @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
70 @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
71 @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
72 @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
73 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
74 @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
75 @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
76 @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
77 @r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
78 @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
79 @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
80 @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
81 @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
82 @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
83
84 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
85 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
86
87 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
88 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
89
90 # Formats 64:
91 @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
92
93 # *** Privileged Instructions ***
94 ecall 000000000000 00000 000 00000 1110011
95 ebreak 000000000001 00000 000 00000 1110011
96 uret 0000000 00010 00000 000 00000 1110011
97 sret 0001000 00010 00000 000 00000 1110011
98 mret 0011000 00010 00000 000 00000 1110011
99 wfi 0001000 00101 00000 000 00000 1110011
100 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
101 sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
102
103 # *** RV32I Base Instruction Set ***
104 lui .................... ..... 0110111 @u
105 auipc .................... ..... 0010111 @u
106 jal .................... ..... 1101111 @j
107 jalr ............ ..... 000 ..... 1100111 @i
108 beq ....... ..... ..... 000 ..... 1100011 @b
109 bne ....... ..... ..... 001 ..... 1100011 @b
110 blt ....... ..... ..... 100 ..... 1100011 @b
111 bge ....... ..... ..... 101 ..... 1100011 @b
112 bltu ....... ..... ..... 110 ..... 1100011 @b
113 bgeu ....... ..... ..... 111 ..... 1100011 @b
114 lb ............ ..... 000 ..... 0000011 @i
115 lh ............ ..... 001 ..... 0000011 @i
116 lw ............ ..... 010 ..... 0000011 @i
117 lbu ............ ..... 100 ..... 0000011 @i
118 lhu ............ ..... 101 ..... 0000011 @i
119 sb ....... ..... ..... 000 ..... 0100011 @s
120 sh ....... ..... ..... 001 ..... 0100011 @s
121 sw ....... ..... ..... 010 ..... 0100011 @s
122 addi ............ ..... 000 ..... 0010011 @i
123 slti ............ ..... 010 ..... 0010011 @i
124 sltiu ............ ..... 011 ..... 0010011 @i
125 xori ............ ..... 100 ..... 0010011 @i
126 ori ............ ..... 110 ..... 0010011 @i
127 andi ............ ..... 111 ..... 0010011 @i
128 slli 00000. ...... ..... 001 ..... 0010011 @sh
129 srli 00000. ...... ..... 101 ..... 0010011 @sh
130 srai 01000. ...... ..... 101 ..... 0010011 @sh
131 add 0000000 ..... ..... 000 ..... 0110011 @r
132 sub 0100000 ..... ..... 000 ..... 0110011 @r
133 sll 0000000 ..... ..... 001 ..... 0110011 @r
134 slt 0000000 ..... ..... 010 ..... 0110011 @r
135 sltu 0000000 ..... ..... 011 ..... 0110011 @r
136 xor 0000000 ..... ..... 100 ..... 0110011 @r
137 srl 0000000 ..... ..... 101 ..... 0110011 @r
138 sra 0100000 ..... ..... 101 ..... 0110011 @r
139 or 0000000 ..... ..... 110 ..... 0110011 @r
140 and 0000000 ..... ..... 111 ..... 0110011 @r
141 fence ---- pred:4 succ:4 ----- 000 ----- 0001111
142 fence_i ---- ---- ---- ----- 001 ----- 0001111
143 csrrw ............ ..... 001 ..... 1110011 @csr
144 csrrs ............ ..... 010 ..... 1110011 @csr
145 csrrc ............ ..... 011 ..... 1110011 @csr
146 csrrwi ............ ..... 101 ..... 1110011 @csr
147 csrrsi ............ ..... 110 ..... 1110011 @csr
148 csrrci ............ ..... 111 ..... 1110011 @csr
149
150 # *** RV64I Base Instruction Set (in addition to RV32I) ***
151 lwu ............ ..... 110 ..... 0000011 @i
152 ld ............ ..... 011 ..... 0000011 @i
153 sd ....... ..... ..... 011 ..... 0100011 @s
154 addiw ............ ..... 000 ..... 0011011 @i
155 slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
156 srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
157 sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
158 addw 0000000 ..... ..... 000 ..... 0111011 @r
159 subw 0100000 ..... ..... 000 ..... 0111011 @r
160 sllw 0000000 ..... ..... 001 ..... 0111011 @r
161 srlw 0000000 ..... ..... 101 ..... 0111011 @r
162 sraw 0100000 ..... ..... 101 ..... 0111011 @r
163
164 # *** RV32M Standard Extension ***
165 mul 0000001 ..... ..... 000 ..... 0110011 @r
166 mulh 0000001 ..... ..... 001 ..... 0110011 @r
167 mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
168 mulhu 0000001 ..... ..... 011 ..... 0110011 @r
169 div 0000001 ..... ..... 100 ..... 0110011 @r
170 divu 0000001 ..... ..... 101 ..... 0110011 @r
171 rem 0000001 ..... ..... 110 ..... 0110011 @r
172 remu 0000001 ..... ..... 111 ..... 0110011 @r
173
174 # *** RV64M Standard Extension (in addition to RV32M) ***
175 mulw 0000001 ..... ..... 000 ..... 0111011 @r
176 divw 0000001 ..... ..... 100 ..... 0111011 @r
177 divuw 0000001 ..... ..... 101 ..... 0111011 @r
178 remw 0000001 ..... ..... 110 ..... 0111011 @r
179 remuw 0000001 ..... ..... 111 ..... 0111011 @r
180
181 # *** RV32A Standard Extension ***
182 lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
183 sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
184 amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
185 amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
186 amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
187 amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
188 amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
189 amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
190 amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
191 amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
192 amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
193
194 # *** RV64A Standard Extension (in addition to RV32A) ***
195 lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
196 sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
197 amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
198 amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
199 amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
200 amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
201 amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
202 amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
203 amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
204 amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
205 amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
206
207 # *** RV32F Standard Extension ***
208 flw ............ ..... 010 ..... 0000111 @i
209 fsw ....... ..... ..... 010 ..... 0100111 @s
210 fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
211 fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
212 fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
213 fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
214 fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
215 fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
216 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
217 fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
218 fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
219 fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
220 fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
221 fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
222 fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
223 fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
224 fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
225 fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
226 fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
227 feq_s 1010000 ..... ..... 010 ..... 1010011 @r
228 flt_s 1010000 ..... ..... 001 ..... 1010011 @r
229 fle_s 1010000 ..... ..... 000 ..... 1010011 @r
230 fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
231 fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
232 fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
233 fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
234
235 # *** RV64F Standard Extension (in addition to RV32F) ***
236 fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
237 fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
238 fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
239 fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
240
241 # *** RV32D Standard Extension ***
242 fld ............ ..... 011 ..... 0000111 @i
243 fsd ....... ..... ..... 011 ..... 0100111 @s
244 fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
245 fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
246 fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
247 fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
248 fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
249 fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
250 fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
251 fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
252 fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
253 fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
254 fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
255 fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
256 fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
257 fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
258 fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
259 fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
260 feq_d 1010001 ..... ..... 010 ..... 1010011 @r
261 flt_d 1010001 ..... ..... 001 ..... 1010011 @r
262 fle_d 1010001 ..... ..... 000 ..... 1010011 @r
263 fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
264 fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
265 fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
266 fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
267 fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
268
269 # *** RV64D Standard Extension (in addition to RV32D) ***
270 fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
271 fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
272 fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
273 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
274 fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
275 fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
276
277 # *** RV32H Base Instruction Set ***
278 hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
279 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
280 hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
281 hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
282 hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
283 hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
284 hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
285 hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
286 hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
287 hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
288 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
289 hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
290
291 # *** RV64H Base Instruction Set ***
292 hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
293 hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
294 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
295
296 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
297 # Vector unit-stride load/store insns.
298 vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
299 vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
300 vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
301 vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
302 vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
303 vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
304 vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
305 vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
306
307 # Vector strided insns.
308 vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
309 vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
310 vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
311 vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
312 vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
313 vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
314 vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
315 vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
316
317 # Vector ordered-indexed and unordered-indexed load insns.
318 vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
319 vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
320 vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
321 vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
322
323 # Vector ordered-indexed and unordered-indexed store insns.
324 vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
325 vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
326 vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
327 vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
328
329 # Vector unit-stride fault-only-first load insns.
330 vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
331 vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
332 vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
333 vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
334
335 # Vector whole register insns
336 vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
337 vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
338 vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
339 vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
340 vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
341 vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
342 vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
343 vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
344 vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
345 vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
346 vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
347 vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
348 vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
349 vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
350 vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
351 vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
352 vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
353 vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
354 vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
355 vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
356
357 # *** new major opcode OP-V ***
358 vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
359 vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
360 vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
361 vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
362 vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
363 vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
364 vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
365 vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
366 vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
367 vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
368 vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
369 vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
370 vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
371 vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
372 vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
373 vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
374 vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
375 vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
376 vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
377 vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
378 vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
379 vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
380 vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
381 vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
382 vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
383 vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
384 vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
385 vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
386 vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
387 vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
388 vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
389 vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
390 vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
391 vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
392 vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
393 vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
394 vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
395 vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
396 vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
397 vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
398 vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
399 vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
400 vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
401 vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
402 vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
403 vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
404 vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
405 vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
406 vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
407 vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
408 vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
409 vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
410 vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
411 vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
412 vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
413 vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
414 vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
415 vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
416 vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
417 vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
418 vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
419 vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
420 vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
421 vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
422 vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
423 vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
424 vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
425 vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
426 vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
427 vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
428 vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
429 vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
430 vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
431 vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
432 vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
433 vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
434 vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
435 vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm
436 vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm
437 vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm
438 vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm
439 vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
440 vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
441 vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
442 vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
443 vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
444 vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
445 vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
446 vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
447 vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
448 vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
449 vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
450 vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
451 vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
452 vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
453 vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
454 vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
455 vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
456 vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
457 vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
458 vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
459 vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
460 vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
461 vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
462 vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
463 vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
464 vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
465 vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
466 vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
467 vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
468 vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
469 vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
470 vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
471 vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
472 vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
473 vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
474 vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
475 vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
476 vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
477 vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
478 vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
479 vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
480 vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
481 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
482 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
483 vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
484 vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
485 vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
486 vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm
487 vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm
488 vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm
489 vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm
490 vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm
491 vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm
492 vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
493 vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
494 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
495 vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
496 vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
497 vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
498 vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
499 vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
500 vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
501 vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
502 vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
503 vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
504 vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
505 vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
506 vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
507 vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
508 vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
509 vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
510 vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm
511 vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
512 vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
513 vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
514 vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
515 vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
516 vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
517 vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
518 vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
519 vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm
520 vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm
521 vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
522 vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
523 vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
524 vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
525 vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
526 vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
527 vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
528 vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
529 vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
530 vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
531 vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
532 vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
533 vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
534 vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
535 vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
536 vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
537 vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
538 vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm
539 vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
540 vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
541 vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
542 vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
543 vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
544 vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
545 vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
546 vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
547 vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
548 vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
549 vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
550 vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
551 vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
552 vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
553 vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
554 vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
555 vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
556 vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
557 vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
558 vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
559 vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
560 vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
561 vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
562 vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
563 vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
564 vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
565 vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
566 vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
567 vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
568 vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
569 vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
570 vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
571 vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
572 vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
573 vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
574 vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
575 vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
576 vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
577 vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
578 vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
579 vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
580 vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
581 vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
582 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
583 vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm
584 vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm
585 vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm
586 vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
587 vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
588 vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
589 vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
590 vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
591 vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
592 vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
593 vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
594 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
595 vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
596 vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
597 vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
598 vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
599 vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
600 vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
601 vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
602 vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm
603 vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm
604 vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
605 vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
606 vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
607 vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
608 vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
609 vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
610 vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
611 vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
612 vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm
613 vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
614 vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
615 vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
616 vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
617 vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
618 vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
619 # Vector ordered and unordered reduction sum
620 vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
621 vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
622 vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
623 # Vector widening ordered and unordered float reduction sum
624 vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
625 vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
626 vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
627 vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
628 vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
629 vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
630 vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
631 vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
632 vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
633 vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
634 vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
635 vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
636 vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
637 vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
638 viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
639 vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
640 vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
641 vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
642 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
643 vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
644 vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
645 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
646 vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
647 vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
648 vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
649 vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
650 vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
651 vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
652 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
653 vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
654 vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
655 vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
656 vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
657 vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
658 vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
659 vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
660
661 # Vector Integer Extension
662 vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
663 vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
664 vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
665 vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
666 vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
667 vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
668
669 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
670 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
671
672 # *** RV32 Zba Standard Extension ***
673 sh1add 0010000 .......... 010 ..... 0110011 @r
674 sh2add 0010000 .......... 100 ..... 0110011 @r
675 sh3add 0010000 .......... 110 ..... 0110011 @r
676
677 # *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
678 add_uw 0000100 .......... 000 ..... 0111011 @r
679 sh1add_uw 0010000 .......... 010 ..... 0111011 @r
680 sh2add_uw 0010000 .......... 100 ..... 0111011 @r
681 sh3add_uw 0010000 .......... 110 ..... 0111011 @r
682 slli_uw 00001 ............ 001 ..... 0011011 @sh
683
684 # *** RV32 Zbb Standard Extension ***
685 andn 0100000 .......... 111 ..... 0110011 @r
686 clz 011000 000000 ..... 001 ..... 0010011 @r2
687 cpop 011000 000010 ..... 001 ..... 0010011 @r2
688 ctz 011000 000001 ..... 001 ..... 0010011 @r2
689 max 0000101 .......... 110 ..... 0110011 @r
690 maxu 0000101 .......... 111 ..... 0110011 @r
691 min 0000101 .......... 100 ..... 0110011 @r
692 minu 0000101 .......... 101 ..... 0110011 @r
693 orc_b 001010 000111 ..... 101 ..... 0010011 @r2
694 orn 0100000 .......... 110 ..... 0110011 @r
695 # The encoding for rev8 differs between RV32 and RV64.
696 # rev8_32 denotes the RV32 variant.
697 rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
698 rol 0110000 .......... 001 ..... 0110011 @r
699 ror 0110000 .......... 101 ..... 0110011 @r
700 rori 01100 ............ 101 ..... 0010011 @sh
701 sext_b 011000 000100 ..... 001 ..... 0010011 @r2
702 sext_h 011000 000101 ..... 001 ..... 0010011 @r2
703 xnor 0100000 .......... 100 ..... 0110011 @r
704 # The encoding for zext.h differs between RV32 and RV64.
705 # zext_h_32 denotes the RV32 variant.
706 zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
707
708 # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
709 clzw 0110000 00000 ..... 001 ..... 0011011 @r2
710 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
711 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
712 # The encoding for rev8 differs between RV32 and RV64.
713 # When executing on RV64, the encoding used in RV32 is an illegal
714 # instruction, so we use different handler functions to differentiate.
715 rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
716 rolw 0110000 .......... 001 ..... 0111011 @r
717 roriw 0110000 .......... 101 ..... 0011011 @sh5
718 rorw 0110000 .......... 101 ..... 0111011 @r
719 # The encoding for zext.h differs between RV32 and RV64.
720 # When executing on RV64, the encoding used in RV32 is an illegal
721 # instruction, so we use different handler functions to differentiate.
722 zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
723
724 # *** RV32 Zbc Standard Extension ***
725 clmul 0000101 .......... 001 ..... 0110011 @r
726 clmulh 0000101 .......... 011 ..... 0110011 @r
727 clmulr 0000101 .......... 010 ..... 0110011 @r
728
729 # *** RV32 Zbs Standard Extension ***
730 bclr 0100100 .......... 001 ..... 0110011 @r
731 bclri 01001. ........... 001 ..... 0010011 @sh
732 bext 0100100 .......... 101 ..... 0110011 @r
733 bexti 01001. ........... 101 ..... 0010011 @sh
734 binv 0110100 .......... 001 ..... 0110011 @r
735 binvi 01101. ........... 001 ..... 0010011 @sh
736 bset 0010100 .......... 001 ..... 0110011 @r
737 bseti 00101. ........... 001 ..... 0010011 @sh
738
739 # *** RV32 Zfh Extension ***
740 flh ............ ..... 001 ..... 0000111 @i
741 fsh ....... ..... ..... 001 ..... 0100111 @s
742 fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm
743 fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm
744 fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm
745 fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm
746 fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm
747 fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
748 fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
749 fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
750 fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
751 fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r
752 fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r
753 fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r
754 fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
755 fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
756 fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm
757 fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm
758 fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm
759 fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
760 fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
761 fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
762 fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
763 feq_h 1010010 ..... ..... 010 ..... 1010011 @r
764 flt_h 1010010 ..... ..... 001 ..... 1010011 @r
765 fle_h 1010010 ..... ..... 000 ..... 1010011 @r
766 fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
767 fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
768 fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
769 fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
770
771 # *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
772 fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
773 fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
774 fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
775 fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
QEMU mirror