target/riscv/insn_trans/trans_privileged.c.inc

   1 /*
   2  * RISC-V translation routines for the RISC-V privileged instructions.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   6  *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
  22 {
  23     /* always generates U-level ECALL, fixed in do_interrupt handler */
  24     generate_exception(ctx, RISCV_EXCP_U_ECALL);
  25     return true;
  26 }
  27
  28 static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
  29 {
  30     target_ulong    ebreak_addr = ctx->base.pc_next;
  31     target_ulong    pre_addr = ebreak_addr - 4;
  32     target_ulong    post_addr = ebreak_addr + 4;
  33     uint32_t pre    = 0;
  34     uint32_t ebreak = 0;
  35     uint32_t post   = 0;
  36
  37     /*
  38      * The RISC-V semihosting spec specifies the following
  39      * three-instruction sequence to flag a semihosting call:
  40      *
  41      *      slli zero, zero, 0x1f       0x01f01013
  42      *      ebreak                      0x00100073
  43      *      srai zero, zero, 0x7        0x40705013
  44      *
  45      * The two shift operations on the zero register are no-ops, used
  46      * here to signify a semihosting exception, rather than a breakpoint.
  47      *
  48      * Uncompressed instructions are required so that the sequence is easy
  49      * to validate.
  50      *
  51      * The three instructions are required to lie in the same page so
  52      * that no exception will be raised when fetching them.
  53      */
  54
  55     if (semihosting_enabled(ctx->priv == PRV_U) &&
  56         (pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
  57         pre    = opcode_at(&ctx->base, pre_addr);
  58         ebreak = opcode_at(&ctx->base, ebreak_addr);
  59         post   = opcode_at(&ctx->base, post_addr);
  60     }
  61
  62     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
  63         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
  64     } else {
  65         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
  66     }
  67     return true;
  68 }
  69
  70 static bool trans_uret(DisasContext *ctx, arg_uret *a)
  71 {
  72     return false;
  73 }
  74
  75 static bool trans_sret(DisasContext *ctx, arg_sret *a)
  76 {
  77 #ifndef CONFIG_USER_ONLY
  78     if (has_ext(ctx, RVS)) {
  79         decode_save_opc(ctx);
  80         translator_io_start(&ctx->base);
  81         gen_helper_sret(cpu_pc, cpu_env);
  82         exit_tb(ctx); /* no chaining */
  83         ctx->base.is_jmp = DISAS_NORETURN;
  84     } else {
  85         return false;
  86     }
  87     return true;
  88 #else
  89     return false;
  90 #endif
  91 }
  92
  93 static bool trans_mret(DisasContext *ctx, arg_mret *a)
  94 {
  95 #ifndef CONFIG_USER_ONLY
  96     decode_save_opc(ctx);
  97     translator_io_start(&ctx->base);
  98     gen_helper_mret(cpu_pc, cpu_env);
  99     exit_tb(ctx); /* no chaining */
 100     ctx->base.is_jmp = DISAS_NORETURN;
 101     return true;
 102 #else
 103     return false;
 104 #endif
 105 }
 106
 107 static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 108 {
 109 #ifndef CONFIG_USER_ONLY
 110     decode_save_opc(ctx);
 111     gen_update_pc(ctx, ctx->cur_insn_len);
 112     gen_helper_wfi(cpu_env);
 113     return true;
 114 #else
 115     return false;
 116 #endif
 117 }
 118
 119 static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
 120 {
 121 #ifndef CONFIG_USER_ONLY
 122     decode_save_opc(ctx);
 123     gen_helper_tlb_flush(cpu_env);
 124     return true;
 125 #endif
 126     return false;
 127 }
 128
 129 static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
 130 {
 131     return false;
 132 }