target/riscv/insn_trans/trans_rvi.inc.c

   1 /*
   2  * RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   6  *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 static bool trans_lui(DisasContext *ctx, arg_lui *a)
  22 {
  23     if (a->rd != 0) {
  24         tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
  25     }
  26     return true;
  27 }
  28
  29 static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
  30 {
  31     if (a->rd != 0) {
  32         tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
  33     }
  34     return true;
  35 }
  36
  37 static bool trans_jal(DisasContext *ctx, arg_jal *a)
  38 {
  39     gen_jal(ctx, a->rd, a->imm);
  40     return true;
  41 }
  42
  43 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
  44 {
  45     /* no chaining with JALR */
  46     TCGLabel *misaligned = NULL;
  47     TCGv t0 = tcg_temp_new();
  48
  49
  50     gen_get_gpr(cpu_pc, a->rs1);
  51     tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
  52     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
  53
  54     if (!has_ext(ctx, RVC)) {
  55         misaligned = gen_new_label();
  56         tcg_gen_andi_tl(t0, cpu_pc, 0x2);
  57         tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
  58     }
  59
  60     if (a->rd != 0) {
  61         tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
  62     }
  63     tcg_gen_lookup_and_goto_ptr();
  64
  65     if (misaligned) {
  66         gen_set_label(misaligned);
  67         gen_exception_inst_addr_mis(ctx);
  68     }
  69     ctx->base.is_jmp = DISAS_NORETURN;
  70
  71     tcg_temp_free(t0);
  72     return true;
  73 }
  74
  75 static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
  76 {
  77     TCGLabel *l = gen_new_label();
  78     TCGv source1, source2;
  79     source1 = tcg_temp_new();
  80     source2 = tcg_temp_new();
  81     gen_get_gpr(source1, a->rs1);
  82     gen_get_gpr(source2, a->rs2);
  83
  84     tcg_gen_brcond_tl(cond, source1, source2, l);
  85     gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
  86     gen_set_label(l); /* branch taken */
  87
  88     if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
  89         /* misaligned */
  90         gen_exception_inst_addr_mis(ctx);
  91     } else {
  92         gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
  93     }
  94     ctx->base.is_jmp = DISAS_NORETURN;
  95
  96     tcg_temp_free(source1);
  97     tcg_temp_free(source2);
  98
  99     return true;
 100 }
 101
 102 static bool trans_beq(DisasContext *ctx, arg_beq *a)
 103 {
 104     return gen_branch(ctx, a, TCG_COND_EQ);
 105 }
 106
 107 static bool trans_bne(DisasContext *ctx, arg_bne *a)
 108 {
 109     return gen_branch(ctx, a, TCG_COND_NE);
 110 }
 111
 112 static bool trans_blt(DisasContext *ctx, arg_blt *a)
 113 {
 114     return gen_branch(ctx, a, TCG_COND_LT);
 115 }
 116
 117 static bool trans_bge(DisasContext *ctx, arg_bge *a)
 118 {
 119     return gen_branch(ctx, a, TCG_COND_GE);
 120 }
 121
 122 static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
 123 {
 124     return gen_branch(ctx, a, TCG_COND_LTU);
 125 }
 126
 127 static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 128 {
 129     return gen_branch(ctx, a, TCG_COND_GEU);
 130 }
 131
 132 static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)
 133 {
 134     TCGv t0 = tcg_temp_new();
 135     TCGv t1 = tcg_temp_new();
 136     gen_get_gpr(t0, a->rs1);
 137     tcg_gen_addi_tl(t0, t0, a->imm);
 138
 139     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 140     gen_set_gpr(a->rd, t1);
 141     tcg_temp_free(t0);
 142     tcg_temp_free(t1);
 143     return true;
 144 }
 145
 146 static bool trans_lb(DisasContext *ctx, arg_lb *a)
 147 {
 148     return gen_load(ctx, a, MO_SB);
 149 }
 150
 151 static bool trans_lh(DisasContext *ctx, arg_lh *a)
 152 {
 153     return gen_load(ctx, a, MO_TESW);
 154 }
 155
 156 static bool trans_lw(DisasContext *ctx, arg_lw *a)
 157 {
 158     return gen_load(ctx, a, MO_TESL);
 159 }
 160
 161 static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
 162 {
 163     return gen_load(ctx, a, MO_UB);
 164 }
 165
 166 static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
 167 {
 168     return gen_load(ctx, a, MO_TEUW);
 169 }
 170
 171 static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
 172 {
 173     TCGv t0 = tcg_temp_new();
 174     TCGv dat = tcg_temp_new();
 175     gen_get_gpr(t0, a->rs1);
 176     tcg_gen_addi_tl(t0, t0, a->imm);
 177     gen_get_gpr(dat, a->rs2);
 178
 179     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
 180     tcg_temp_free(t0);
 181     tcg_temp_free(dat);
 182     return true;
 183 }
 184
 185
 186 static bool trans_sb(DisasContext *ctx, arg_sb *a)
 187 {
 188     return gen_store(ctx, a, MO_SB);
 189 }
 190
 191 static bool trans_sh(DisasContext *ctx, arg_sh *a)
 192 {
 193     return gen_store(ctx, a, MO_TESW);
 194 }
 195
 196 static bool trans_sw(DisasContext *ctx, arg_sw *a)
 197 {
 198     return gen_store(ctx, a, MO_TESL);
 199 }
 200
 201 #ifdef TARGET_RISCV64
 202 static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
 203 {
 204     return gen_load(ctx, a, MO_TEUL);
 205 }
 206
 207 static bool trans_ld(DisasContext *ctx, arg_ld *a)
 208 {
 209     return gen_load(ctx, a, MO_TEQ);
 210 }
 211
 212 static bool trans_sd(DisasContext *ctx, arg_sd *a)
 213 {
 214     return gen_store(ctx, a, MO_TEQ);
 215 }
 216 #endif
 217
 218 static bool trans_addi(DisasContext *ctx, arg_addi *a)
 219 {
 220     return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
 221 }
 222
 223 static bool trans_slti(DisasContext *ctx, arg_slti *a)
 224 {
 225     TCGv source1;
 226     source1 = tcg_temp_new();
 227     gen_get_gpr(source1, a->rs1);
 228
 229     tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
 230
 231     gen_set_gpr(a->rd, source1);
 232     tcg_temp_free(source1);
 233     return true;
 234 }
 235
 236 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
 237 {
 238     TCGv source1;
 239     source1 = tcg_temp_new();
 240     gen_get_gpr(source1, a->rs1);
 241
 242     tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
 243
 244     gen_set_gpr(a->rd, source1);
 245     tcg_temp_free(source1);
 246     return true;
 247 }
 248
 249 static bool trans_xori(DisasContext *ctx, arg_xori *a)
 250 {
 251     return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
 252 }
 253 static bool trans_ori(DisasContext *ctx, arg_ori *a)
 254 {
 255     return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
 256 }
 257 static bool trans_andi(DisasContext *ctx, arg_andi *a)
 258 {
 259     return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
 260 }
 261 static bool trans_slli(DisasContext *ctx, arg_slli *a)
 262 {
 263     if (a->shamt >= TARGET_LONG_BITS) {
 264         return false;
 265     }
 266
 267     if (a->rd != 0) {
 268         TCGv t = tcg_temp_new();
 269         gen_get_gpr(t, a->rs1);
 270
 271         tcg_gen_shli_tl(t, t, a->shamt);
 272
 273         gen_set_gpr(a->rd, t);
 274         tcg_temp_free(t);
 275     } /* NOP otherwise */
 276     return true;
 277 }
 278
 279 static bool trans_srli(DisasContext *ctx, arg_srli *a)
 280 {
 281     if (a->shamt >= TARGET_LONG_BITS) {
 282         return false;
 283     }
 284
 285     if (a->rd != 0) {
 286         TCGv t = tcg_temp_new();
 287         gen_get_gpr(t, a->rs1);
 288
 289         tcg_gen_shri_tl(t, t, a->shamt);
 290         gen_set_gpr(a->rd, t);
 291         tcg_temp_free(t);
 292     } /* NOP otherwise */
 293     return true;
 294 }
 295
 296 static bool trans_srai(DisasContext *ctx, arg_srai *a)
 297 {
 298     if (a->shamt >= TARGET_LONG_BITS) {
 299         return false;
 300     }
 301
 302     if (a->rd != 0) {
 303         TCGv t = tcg_temp_new();
 304         gen_get_gpr(t, a->rs1);
 305
 306         tcg_gen_sari_tl(t, t, a->shamt);
 307         gen_set_gpr(a->rd, t);
 308         tcg_temp_free(t);
 309     } /* NOP otherwise */
 310     return true;
 311 }
 312
 313 static bool trans_add(DisasContext *ctx, arg_add *a)
 314 {
 315     gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
 316     return true;
 317 }
 318
 319 static bool trans_sub(DisasContext *ctx, arg_sub *a)
 320 {
 321     gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
 322     return true;
 323 }
 324
 325 static bool trans_sll(DisasContext *ctx, arg_sll *a)
 326 {
 327     gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
 328     return true;
 329 }
 330
 331 static bool trans_slt(DisasContext *ctx, arg_slt *a)
 332 {
 333     gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
 334     return true;
 335 }
 336
 337 static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
 338 {
 339     gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
 340     return true;
 341 }
 342
 343 static bool trans_xor(DisasContext *ctx, arg_xor *a)
 344 {
 345     gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
 346     return true;
 347 }
 348
 349 static bool trans_srl(DisasContext *ctx, arg_srl *a)
 350 {
 351     gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
 352     return true;
 353 }
 354
 355 static bool trans_sra(DisasContext *ctx, arg_sra *a)
 356 {
 357     gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
 358     return true;
 359 }
 360
 361 static bool trans_or(DisasContext *ctx, arg_or *a)
 362 {
 363     gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
 364     return true;
 365 }
 366
 367 static bool trans_and(DisasContext *ctx, arg_and *a)
 368 {
 369     gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
 370     return true;
 371 }
 372
 373 #ifdef TARGET_RISCV64
 374 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 375 {
 376     return gen_arith_imm(ctx, a, &gen_addw);
 377 }
 378
 379 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 380 {
 381     TCGv source1;
 382     source1 = tcg_temp_new();
 383     gen_get_gpr(source1, a->rs1);
 384
 385     tcg_gen_shli_tl(source1, source1, a->shamt);
 386     tcg_gen_ext32s_tl(source1, source1);
 387     gen_set_gpr(a->rd, source1);
 388
 389     tcg_temp_free(source1);
 390     return true;
 391 }
 392
 393 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 394 {
 395     TCGv t = tcg_temp_new();
 396     gen_get_gpr(t, a->rs1);
 397     tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
 398     /* sign-extend for W instructions */
 399     tcg_gen_ext32s_tl(t, t);
 400     gen_set_gpr(a->rd, t);
 401     tcg_temp_free(t);
 402     return true;
 403 }
 404
 405 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 406 {
 407     TCGv t = tcg_temp_new();
 408     gen_get_gpr(t, a->rs1);
 409     tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
 410     gen_set_gpr(a->rd, t);
 411     tcg_temp_free(t);
 412     return true;
 413 }
 414
 415 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 416 {
 417     gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
 418     return true;
 419 }
 420
 421 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 422 {
 423     gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
 424     return true;
 425 }
 426
 427 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 428 {
 429     gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
 430     return true;
 431 }
 432
 433 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 434 {
 435     gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
 436     return true;
 437 }
 438
 439 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 440 {
 441     gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
 442     return true;
 443 }
 444 #endif
 445
 446 static bool trans_fence(DisasContext *ctx, arg_fence *a)
 447 {
 448     /* FENCE is a full memory barrier. */
 449     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
 450     return true;
 451 }
 452
 453 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 454 {
 455     /*
 456      * FENCE_I is a no-op in QEMU,
 457      * however we need to end the translation block
 458      */
 459     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
 460     tcg_gen_exit_tb(NULL, 0);
 461     ctx->base.is_jmp = DISAS_NORETURN;
 462     return true;
 463 }
 464
 465 #define RISCV_OP_CSR_PRE do {\
 466     source1 = tcg_temp_new(); \
 467     csr_store = tcg_temp_new(); \
 468     dest = tcg_temp_new(); \
 469     rs1_pass = tcg_temp_new(); \
 470     gen_get_gpr(source1, a->rs1); \
 471     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
 472     tcg_gen_movi_tl(rs1_pass, a->rs1); \
 473     tcg_gen_movi_tl(csr_store, a->csr); \
 474     gen_io_start();\
 475 } while (0)
 476
 477 #define RISCV_OP_CSR_POST do {\
 478     gen_io_end(); \
 479     gen_set_gpr(a->rd, dest); \
 480     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
 481     tcg_gen_exit_tb(NULL, 0); \
 482     ctx->base.is_jmp = DISAS_NORETURN; \
 483     tcg_temp_free(source1); \
 484     tcg_temp_free(csr_store); \
 485     tcg_temp_free(dest); \
 486     tcg_temp_free(rs1_pass); \
 487 } while (0)
 488
 489
 490 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 491 {
 492     TCGv source1, csr_store, dest, rs1_pass;
 493     RISCV_OP_CSR_PRE;
 494     gen_helper_csrrw(dest, cpu_env, source1, csr_store);
 495     RISCV_OP_CSR_POST;
 496     return true;
 497 }
 498
 499 static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
 500 {
 501     TCGv source1, csr_store, dest, rs1_pass;
 502     RISCV_OP_CSR_PRE;
 503     gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
 504     RISCV_OP_CSR_POST;
 505     return true;
 506 }
 507
 508 static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
 509 {
 510     TCGv source1, csr_store, dest, rs1_pass;
 511     RISCV_OP_CSR_PRE;
 512     gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
 513     RISCV_OP_CSR_POST;
 514     return true;
 515 }
 516
 517 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
 518 {
 519     TCGv source1, csr_store, dest, rs1_pass;
 520     RISCV_OP_CSR_PRE;
 521     gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
 522     RISCV_OP_CSR_POST;
 523     return true;
 524 }
 525
 526 static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
 527 {
 528     TCGv source1, csr_store, dest, rs1_pass;
 529     RISCV_OP_CSR_PRE;
 530     gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
 531     RISCV_OP_CSR_POST;
 532     return true;
 533 }
 534
 535 static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
 536 {
 537     TCGv source1, csr_store, dest, rs1_pass;
 538     RISCV_OP_CSR_PRE;
 539     gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
 540     RISCV_OP_CSR_POST;
 541     return true;
 542 }