target/riscv/insn_trans/trans_rvi.inc.c

   1 /*
   2  * RISC-V translation routines for the RVXI Base Integer Instruction Set.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   6  *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 static bool trans_lui(DisasContext *ctx, arg_lui *a)
  22 {
  23     if (a->rd != 0) {
  24         tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
  25     }
  26     return true;
  27 }
  28
  29 static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
  30 {
  31     if (a->rd != 0) {
  32         tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
  33     }
  34     return true;
  35 }
  36
  37 static bool trans_jal(DisasContext *ctx, arg_jal *a)
  38 {
  39     gen_jal(ctx, a->rd, a->imm);
  40     return true;
  41 }
  42
  43 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
  44 {
  45     gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
  46     return true;
  47 }
  48
  49 static bool trans_beq(DisasContext *ctx, arg_beq *a)
  50 {
  51     gen_branch(ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
  52     return true;
  53 }
  54
  55 static bool trans_bne(DisasContext *ctx, arg_bne *a)
  56 {
  57     gen_branch(ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
  58     return true;
  59 }
  60
  61 static bool trans_blt(DisasContext *ctx, arg_blt *a)
  62 {
  63     gen_branch(ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
  64     return true;
  65 }
  66
  67 static bool trans_bge(DisasContext *ctx, arg_bge *a)
  68 {
  69     gen_branch(ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
  70     return true;
  71 }
  72
  73 static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
  74 {
  75     gen_branch(ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
  76     return true;
  77 }
  78
  79 static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
  80 {
  81
  82     gen_branch(ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
  83     return true;
  84 }
  85
  86 static bool trans_lb(DisasContext *ctx, arg_lb *a)
  87 {
  88     gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
  89     return true;
  90 }
  91
  92 static bool trans_lh(DisasContext *ctx, arg_lh *a)
  93 {
  94     gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
  95     return true;
  96 }
  97
  98 static bool trans_lw(DisasContext *ctx, arg_lw *a)
  99 {
 100     gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
 101     return true;
 102 }
 103
 104 static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
 105 {
 106     gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
 107     return true;
 108 }
 109
 110 static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
 111 {
 112     gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
 113     return true;
 114 }
 115
 116 static bool trans_sb(DisasContext *ctx, arg_sb *a)
 117 {
 118     gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
 119     return true;
 120 }
 121
 122 static bool trans_sh(DisasContext *ctx, arg_sh *a)
 123 {
 124     gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
 125     return true;
 126 }
 127
 128 static bool trans_sw(DisasContext *ctx, arg_sw *a)
 129 {
 130     gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
 131     return true;
 132 }
 133
 134 #ifdef TARGET_RISCV64
 135 static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
 136 {
 137     gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
 138     return true;
 139 }
 140
 141 static bool trans_ld(DisasContext *ctx, arg_ld *a)
 142 {
 143     gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
 144     return true;
 145 }
 146
 147 static bool trans_sd(DisasContext *ctx, arg_sd *a)
 148 {
 149     gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
 150     return true;
 151 }
 152 #endif
 153
 154 static bool trans_addi(DisasContext *ctx, arg_addi *a)
 155 {
 156     gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
 157     return true;
 158 }
 159
 160 static bool trans_slti(DisasContext *ctx, arg_slti *a)
 161 {
 162     gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
 163     return true;
 164 }
 165
 166 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
 167 {
 168     gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
 169     return true;
 170 }
 171
 172 static bool trans_xori(DisasContext *ctx, arg_xori *a)
 173 {
 174     gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
 175     return true;
 176 }
 177 static bool trans_ori(DisasContext *ctx, arg_ori *a)
 178 {
 179     gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
 180     return true;
 181 }
 182 static bool trans_andi(DisasContext *ctx, arg_andi *a)
 183 {
 184     gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
 185     return true;
 186 }
 187 static bool trans_slli(DisasContext *ctx, arg_slli *a)
 188 {
 189     gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
 190     return true;
 191 }
 192
 193 static bool trans_srli(DisasContext *ctx, arg_srli *a)
 194 {
 195     gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
 196     return true;
 197 }
 198
 199 static bool trans_srai(DisasContext *ctx, arg_srai *a)
 200 {
 201     gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
 202     return true;
 203 }
 204
 205 static bool trans_add(DisasContext *ctx, arg_add *a)
 206 {
 207     gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
 208     return true;
 209 }
 210
 211 static bool trans_sub(DisasContext *ctx, arg_sub *a)
 212 {
 213     gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
 214     return true;
 215 }
 216
 217 static bool trans_sll(DisasContext *ctx, arg_sll *a)
 218 {
 219     gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
 220     return true;
 221 }
 222
 223 static bool trans_slt(DisasContext *ctx, arg_slt *a)
 224 {
 225     gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
 226     return true;
 227 }
 228
 229 static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
 230 {
 231     gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
 232     return true;
 233 }
 234
 235 static bool trans_xor(DisasContext *ctx, arg_xor *a)
 236 {
 237     gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
 238     return true;
 239 }
 240
 241 static bool trans_srl(DisasContext *ctx, arg_srl *a)
 242 {
 243     gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
 244     return true;
 245 }
 246
 247 static bool trans_sra(DisasContext *ctx, arg_sra *a)
 248 {
 249     gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
 250     return true;
 251 }
 252
 253 static bool trans_or(DisasContext *ctx, arg_or *a)
 254 {
 255     gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
 256     return true;
 257 }
 258
 259 static bool trans_and(DisasContext *ctx, arg_and *a)
 260 {
 261     gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
 262     return true;
 263 }
 264
 265 #ifdef TARGET_RISCV64
 266 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 267 {
 268     gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
 269     return true;
 270 }
 271
 272 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 273 {
 274     gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
 275     return true;
 276 }
 277
 278 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 279 {
 280     gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
 281     return true;
 282 }
 283
 284 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 285 {
 286     gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
 287                   a->shamt | 0x400);
 288     return true;
 289 }
 290
 291 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 292 {
 293     gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
 294     return true;
 295 }
 296
 297 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 298 {
 299     gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
 300     return true;
 301 }
 302
 303 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 304 {
 305     gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
 306     return true;
 307 }
 308
 309 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 310 {
 311     gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
 312     return true;
 313 }
 314
 315 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 316 {
 317     gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
 318     return true;
 319 }
 320 #endif
 321
 322 static bool trans_fence(DisasContext *ctx, arg_fence *a)
 323 {
 324     /* FENCE is a full memory barrier. */
 325     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
 326     return true;
 327 }
 328
 329 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 330 {
 331     /*
 332      * FENCE_I is a no-op in QEMU,
 333      * however we need to end the translation block
 334      */
 335     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
 336     tcg_gen_exit_tb(NULL, 0);
 337     ctx->base.is_jmp = DISAS_NORETURN;
 338     return true;
 339 }
 340
 341 #define RISCV_OP_CSR_PRE do {\
 342     source1 = tcg_temp_new(); \
 343     csr_store = tcg_temp_new(); \
 344     dest = tcg_temp_new(); \
 345     rs1_pass = tcg_temp_new(); \
 346     gen_get_gpr(source1, a->rs1); \
 347     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
 348     tcg_gen_movi_tl(rs1_pass, a->rs1); \
 349     tcg_gen_movi_tl(csr_store, a->csr); \
 350     gen_io_start();\
 351 } while (0)
 352
 353 #define RISCV_OP_CSR_POST do {\
 354     gen_io_end(); \
 355     gen_set_gpr(a->rd, dest); \
 356     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
 357     tcg_gen_exit_tb(NULL, 0); \
 358     ctx->base.is_jmp = DISAS_NORETURN; \
 359     tcg_temp_free(source1); \
 360     tcg_temp_free(csr_store); \
 361     tcg_temp_free(dest); \
 362     tcg_temp_free(rs1_pass); \
 363 } while (0)
 364
 365
 366 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 367 {
 368     TCGv source1, csr_store, dest, rs1_pass;
 369     RISCV_OP_CSR_PRE;
 370     gen_helper_csrrw(dest, cpu_env, source1, csr_store);
 371     RISCV_OP_CSR_POST;
 372     return true;
 373 }
 374
 375 static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
 376 {
 377     TCGv source1, csr_store, dest, rs1_pass;
 378     RISCV_OP_CSR_PRE;
 379     gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
 380     RISCV_OP_CSR_POST;
 381     return true;
 382 }
 383
 384 static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
 385 {
 386     TCGv source1, csr_store, dest, rs1_pass;
 387     RISCV_OP_CSR_PRE;
 388     gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
 389     RISCV_OP_CSR_POST;
 390     return true;
 391 }
 392
 393 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
 394 {
 395     TCGv source1, csr_store, dest, rs1_pass;
 396     RISCV_OP_CSR_PRE;
 397     gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
 398     RISCV_OP_CSR_POST;
 399     return true;
 400 }
 401
 402 static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
 403 {
 404     TCGv source1, csr_store, dest, rs1_pass;
 405     RISCV_OP_CSR_PRE;
 406     gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
 407     RISCV_OP_CSR_POST;
 408     return true;
 409 }
 410
 411 static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
 412 {
 413     TCGv source1, csr_store, dest, rs1_pass;
 414     RISCV_OP_CSR_PRE;
 415     gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
 416     RISCV_OP_CSR_POST;
 417     return true;
 418 }