2 * RISC-V VMState Description
4 * Copyright (c) 2020 Huawei Technologies Co., Ltd
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/error-report.h"
22 #include "sysemu/kvm.h"
23 #include "migration/cpu.h"
25 static bool pmp_needed(void *opaque
)
27 RISCVCPU
*cpu
= opaque
;
28 CPURISCVState
*env
= &cpu
->env
;
30 return riscv_feature(env
, RISCV_FEATURE_PMP
);
33 static int pmp_post_load(void *opaque
, int version_id
)
35 RISCVCPU
*cpu
= opaque
;
36 CPURISCVState
*env
= &cpu
->env
;
39 for (i
= 0; i
< MAX_RISCV_PMPS
; i
++) {
40 pmp_update_rule_addr(env
, i
);
42 pmp_update_rule_nums(env
);
47 static const VMStateDescription vmstate_pmp_entry
= {
48 .name
= "cpu/pmp/entry",
50 .minimum_version_id
= 1,
51 .fields
= (VMStateField
[]) {
52 VMSTATE_UINTTL(addr_reg
, pmp_entry_t
),
53 VMSTATE_UINT8(cfg_reg
, pmp_entry_t
),
58 static const VMStateDescription vmstate_pmp
= {
61 .minimum_version_id
= 1,
63 .post_load
= pmp_post_load
,
64 .fields
= (VMStateField
[]) {
65 VMSTATE_STRUCT_ARRAY(env
.pmp_state
.pmp
, RISCVCPU
, MAX_RISCV_PMPS
,
66 0, vmstate_pmp_entry
, pmp_entry_t
),
71 static bool hyper_needed(void *opaque
)
73 RISCVCPU
*cpu
= opaque
;
74 CPURISCVState
*env
= &cpu
->env
;
76 return riscv_has_ext(env
, RVH
);
79 static const VMStateDescription vmstate_hyper
= {
82 .minimum_version_id
= 1,
83 .needed
= hyper_needed
,
84 .fields
= (VMStateField
[]) {
85 VMSTATE_UINTTL(env
.hstatus
, RISCVCPU
),
86 VMSTATE_UINTTL(env
.hedeleg
, RISCVCPU
),
87 VMSTATE_UINTTL(env
.hideleg
, RISCVCPU
),
88 VMSTATE_UINTTL(env
.hcounteren
, RISCVCPU
),
89 VMSTATE_UINTTL(env
.htval
, RISCVCPU
),
90 VMSTATE_UINTTL(env
.htinst
, RISCVCPU
),
91 VMSTATE_UINTTL(env
.hgatp
, RISCVCPU
),
92 VMSTATE_UINT64(env
.htimedelta
, RISCVCPU
),
94 VMSTATE_UINT64(env
.vsstatus
, RISCVCPU
),
95 VMSTATE_UINTTL(env
.vstvec
, RISCVCPU
),
96 VMSTATE_UINTTL(env
.vsscratch
, RISCVCPU
),
97 VMSTATE_UINTTL(env
.vsepc
, RISCVCPU
),
98 VMSTATE_UINTTL(env
.vscause
, RISCVCPU
),
99 VMSTATE_UINTTL(env
.vstval
, RISCVCPU
),
100 VMSTATE_UINTTL(env
.vsatp
, RISCVCPU
),
102 VMSTATE_UINTTL(env
.mtval2
, RISCVCPU
),
103 VMSTATE_UINTTL(env
.mtinst
, RISCVCPU
),
105 VMSTATE_UINTTL(env
.stvec_hs
, RISCVCPU
),
106 VMSTATE_UINTTL(env
.sscratch_hs
, RISCVCPU
),
107 VMSTATE_UINTTL(env
.sepc_hs
, RISCVCPU
),
108 VMSTATE_UINTTL(env
.scause_hs
, RISCVCPU
),
109 VMSTATE_UINTTL(env
.stval_hs
, RISCVCPU
),
110 VMSTATE_UINTTL(env
.satp_hs
, RISCVCPU
),
111 VMSTATE_UINT64(env
.mstatus_hs
, RISCVCPU
),
113 VMSTATE_END_OF_LIST()
117 static bool vector_needed(void *opaque
)
119 RISCVCPU
*cpu
= opaque
;
120 CPURISCVState
*env
= &cpu
->env
;
122 return riscv_has_ext(env
, RVV
);
125 static const VMStateDescription vmstate_vector
= {
126 .name
= "cpu/vector",
128 .minimum_version_id
= 1,
129 .needed
= vector_needed
,
130 .fields
= (VMStateField
[]) {
131 VMSTATE_UINT64_ARRAY(env
.vreg
, RISCVCPU
, 32 * RV_VLEN_MAX
/ 64),
132 VMSTATE_UINTTL(env
.vxrm
, RISCVCPU
),
133 VMSTATE_UINTTL(env
.vxsat
, RISCVCPU
),
134 VMSTATE_UINTTL(env
.vl
, RISCVCPU
),
135 VMSTATE_UINTTL(env
.vstart
, RISCVCPU
),
136 VMSTATE_UINTTL(env
.vtype
, RISCVCPU
),
137 VMSTATE_END_OF_LIST()
141 static bool pointermasking_needed(void *opaque
)
143 RISCVCPU
*cpu
= opaque
;
144 CPURISCVState
*env
= &cpu
->env
;
146 return riscv_has_ext(env
, RVJ
);
149 static const VMStateDescription vmstate_pointermasking
= {
150 .name
= "cpu/pointer_masking",
152 .minimum_version_id
= 1,
153 .needed
= pointermasking_needed
,
154 .fields
= (VMStateField
[]) {
155 VMSTATE_UINTTL(env
.mmte
, RISCVCPU
),
156 VMSTATE_UINTTL(env
.mpmmask
, RISCVCPU
),
157 VMSTATE_UINTTL(env
.mpmbase
, RISCVCPU
),
158 VMSTATE_UINTTL(env
.spmmask
, RISCVCPU
),
159 VMSTATE_UINTTL(env
.spmbase
, RISCVCPU
),
160 VMSTATE_UINTTL(env
.upmmask
, RISCVCPU
),
161 VMSTATE_UINTTL(env
.upmbase
, RISCVCPU
),
163 VMSTATE_END_OF_LIST()
167 static bool rv128_needed(void *opaque
)
169 RISCVCPU
*cpu
= opaque
;
170 CPURISCVState
*env
= &cpu
->env
;
172 return env
->misa_mxl_max
== MXL_RV128
;
175 static const VMStateDescription vmstate_rv128
= {
178 .minimum_version_id
= 1,
179 .needed
= rv128_needed
,
180 .fields
= (VMStateField
[]) {
181 VMSTATE_UINTTL_ARRAY(env
.gprh
, RISCVCPU
, 32),
182 VMSTATE_END_OF_LIST()
186 const VMStateDescription vmstate_riscv_cpu
= {
189 .minimum_version_id
= 3,
190 .fields
= (VMStateField
[]) {
191 VMSTATE_UINTTL_ARRAY(env
.gpr
, RISCVCPU
, 32),
192 VMSTATE_UINT64_ARRAY(env
.fpr
, RISCVCPU
, 32),
193 VMSTATE_UINTTL(env
.pc
, RISCVCPU
),
194 VMSTATE_UINTTL(env
.load_res
, RISCVCPU
),
195 VMSTATE_UINTTL(env
.load_val
, RISCVCPU
),
196 VMSTATE_UINTTL(env
.frm
, RISCVCPU
),
197 VMSTATE_UINTTL(env
.badaddr
, RISCVCPU
),
198 VMSTATE_UINTTL(env
.guest_phys_fault_addr
, RISCVCPU
),
199 VMSTATE_UINTTL(env
.priv_ver
, RISCVCPU
),
200 VMSTATE_UINTTL(env
.vext_ver
, RISCVCPU
),
201 VMSTATE_UINT32(env
.misa_mxl
, RISCVCPU
),
202 VMSTATE_UINT32(env
.misa_ext
, RISCVCPU
),
203 VMSTATE_UINT32(env
.misa_mxl_max
, RISCVCPU
),
204 VMSTATE_UINT32(env
.misa_ext_mask
, RISCVCPU
),
205 VMSTATE_UINT32(env
.features
, RISCVCPU
),
206 VMSTATE_UINTTL(env
.priv
, RISCVCPU
),
207 VMSTATE_UINTTL(env
.virt
, RISCVCPU
),
208 VMSTATE_UINTTL(env
.resetvec
, RISCVCPU
),
209 VMSTATE_UINTTL(env
.mhartid
, RISCVCPU
),
210 VMSTATE_UINT64(env
.mstatus
, RISCVCPU
),
211 VMSTATE_UINTTL(env
.mip
, RISCVCPU
),
212 VMSTATE_UINT32(env
.miclaim
, RISCVCPU
),
213 VMSTATE_UINTTL(env
.mie
, RISCVCPU
),
214 VMSTATE_UINTTL(env
.mideleg
, RISCVCPU
),
215 VMSTATE_UINTTL(env
.satp
, RISCVCPU
),
216 VMSTATE_UINTTL(env
.stval
, RISCVCPU
),
217 VMSTATE_UINTTL(env
.medeleg
, RISCVCPU
),
218 VMSTATE_UINTTL(env
.stvec
, RISCVCPU
),
219 VMSTATE_UINTTL(env
.sepc
, RISCVCPU
),
220 VMSTATE_UINTTL(env
.scause
, RISCVCPU
),
221 VMSTATE_UINTTL(env
.mtvec
, RISCVCPU
),
222 VMSTATE_UINTTL(env
.mepc
, RISCVCPU
),
223 VMSTATE_UINTTL(env
.mcause
, RISCVCPU
),
224 VMSTATE_UINTTL(env
.mtval
, RISCVCPU
),
225 VMSTATE_UINTTL(env
.scounteren
, RISCVCPU
),
226 VMSTATE_UINTTL(env
.mcounteren
, RISCVCPU
),
227 VMSTATE_UINTTL(env
.sscratch
, RISCVCPU
),
228 VMSTATE_UINTTL(env
.mscratch
, RISCVCPU
),
229 VMSTATE_UINT64(env
.mfromhost
, RISCVCPU
),
230 VMSTATE_UINT64(env
.mtohost
, RISCVCPU
),
231 VMSTATE_UINT64(env
.timecmp
, RISCVCPU
),
233 VMSTATE_END_OF_LIST()
235 .subsections
= (const VMStateDescription
* []) {
239 &vmstate_pointermasking
,