target/riscv/machine.c

   1 /*
   2  * RISC-V VMState Description
   3  *
   4  * Copyright (c) 2020 Huawei Technologies Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "qemu/error-report.h"
  22 #include "sysemu/kvm.h"
  23 #include "migration/cpu.h"
  24
  25 static bool pmp_needed(void *opaque)
  26 {
  27     RISCVCPU *cpu = opaque;
  28     CPURISCVState *env = &cpu->env;
  29
  30     return riscv_feature(env, RISCV_FEATURE_PMP);
  31 }
  32
  33 static int pmp_post_load(void *opaque, int version_id)
  34 {
  35     RISCVCPU *cpu = opaque;
  36     CPURISCVState *env = &cpu->env;
  37     int i;
  38
  39     for (i = 0; i < MAX_RISCV_PMPS; i++) {
  40         pmp_update_rule_addr(env, i);
  41     }
  42     pmp_update_rule_nums(env);
  43
  44     return 0;
  45 }
  46
  47 static const VMStateDescription vmstate_pmp_entry = {
  48     .name = "cpu/pmp/entry",
  49     .version_id = 1,
  50     .minimum_version_id = 1,
  51     .fields = (VMStateField[]) {
  52         VMSTATE_UINTTL(addr_reg, pmp_entry_t),
  53         VMSTATE_UINT8(cfg_reg, pmp_entry_t),
  54         VMSTATE_END_OF_LIST()
  55     }
  56 };
  57
  58 static const VMStateDescription vmstate_pmp = {
  59     .name = "cpu/pmp",
  60     .version_id = 1,
  61     .minimum_version_id = 1,
  62     .needed = pmp_needed,
  63     .post_load = pmp_post_load,
  64     .fields = (VMStateField[]) {
  65         VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
  66                              0, vmstate_pmp_entry, pmp_entry_t),
  67         VMSTATE_END_OF_LIST()
  68     }
  69 };
  70
  71 static bool hyper_needed(void *opaque)
  72 {
  73     RISCVCPU *cpu = opaque;
  74     CPURISCVState *env = &cpu->env;
  75
  76     return riscv_has_ext(env, RVH);
  77 }
  78
  79 static const VMStateDescription vmstate_hyper = {
  80     .name = "cpu/hyper",
  81     .version_id = 1,
  82     .minimum_version_id = 1,
  83     .needed = hyper_needed,
  84     .fields = (VMStateField[]) {
  85         VMSTATE_UINTTL(env.hstatus, RISCVCPU),
  86         VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
  87         VMSTATE_UINTTL(env.hideleg, RISCVCPU),
  88         VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
  89         VMSTATE_UINTTL(env.htval, RISCVCPU),
  90         VMSTATE_UINTTL(env.htinst, RISCVCPU),
  91         VMSTATE_UINTTL(env.hgatp, RISCVCPU),
  92         VMSTATE_UINT64(env.htimedelta, RISCVCPU),
  93
  94         VMSTATE_UINT64(env.vsstatus, RISCVCPU),
  95         VMSTATE_UINTTL(env.vstvec, RISCVCPU),
  96         VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
  97         VMSTATE_UINTTL(env.vsepc, RISCVCPU),
  98         VMSTATE_UINTTL(env.vscause, RISCVCPU),
  99         VMSTATE_UINTTL(env.vstval, RISCVCPU),
 100         VMSTATE_UINTTL(env.vsatp, RISCVCPU),
 101
 102         VMSTATE_UINTTL(env.mtval2, RISCVCPU),
 103         VMSTATE_UINTTL(env.mtinst, RISCVCPU),
 104
 105         VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
 106         VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
 107         VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
 108         VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
 109         VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
 110         VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
 111         VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
 112
 113         VMSTATE_END_OF_LIST()
 114     }
 115 };
 116
 117 static bool vector_needed(void *opaque)
 118 {
 119     RISCVCPU *cpu = opaque;
 120     CPURISCVState *env = &cpu->env;
 121
 122     return riscv_has_ext(env, RVV);
 123 }
 124
 125 static const VMStateDescription vmstate_vector = {
 126     .name = "cpu/vector",
 127     .version_id = 2,
 128     .minimum_version_id = 2,
 129     .needed = vector_needed,
 130     .fields = (VMStateField[]) {
 131             VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
 132             VMSTATE_UINTTL(env.vxrm, RISCVCPU),
 133             VMSTATE_UINTTL(env.vxsat, RISCVCPU),
 134             VMSTATE_UINTTL(env.vl, RISCVCPU),
 135             VMSTATE_UINTTL(env.vstart, RISCVCPU),
 136             VMSTATE_UINTTL(env.vtype, RISCVCPU),
 137             VMSTATE_BOOL(env.vill, RISCVCPU),
 138             VMSTATE_END_OF_LIST()
 139         }
 140 };
 141
 142 static bool pointermasking_needed(void *opaque)
 143 {
 144     RISCVCPU *cpu = opaque;
 145     CPURISCVState *env = &cpu->env;
 146
 147     return riscv_has_ext(env, RVJ);
 148 }
 149
 150 static const VMStateDescription vmstate_pointermasking = {
 151     .name = "cpu/pointer_masking",
 152     .version_id = 1,
 153     .minimum_version_id = 1,
 154     .needed = pointermasking_needed,
 155     .fields = (VMStateField[]) {
 156         VMSTATE_UINTTL(env.mmte, RISCVCPU),
 157         VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
 158         VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
 159         VMSTATE_UINTTL(env.spmmask, RISCVCPU),
 160         VMSTATE_UINTTL(env.spmbase, RISCVCPU),
 161         VMSTATE_UINTTL(env.upmmask, RISCVCPU),
 162         VMSTATE_UINTTL(env.upmbase, RISCVCPU),
 163
 164         VMSTATE_END_OF_LIST()
 165     }
 166 };
 167
 168 static bool rv128_needed(void *opaque)
 169 {
 170     RISCVCPU *cpu = opaque;
 171     CPURISCVState *env = &cpu->env;
 172
 173     return env->misa_mxl_max == MXL_RV128;
 174 }
 175
 176 static const VMStateDescription vmstate_rv128 = {
 177     .name = "cpu/rv128",
 178     .version_id = 1,
 179     .minimum_version_id = 1,
 180     .needed = rv128_needed,
 181     .fields = (VMStateField[]) {
 182         VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
 183         VMSTATE_UINT64(env.mscratchh, RISCVCPU),
 184         VMSTATE_UINT64(env.sscratchh, RISCVCPU),
 185         VMSTATE_END_OF_LIST()
 186     }
 187 };
 188
 189 static bool kvmtimer_needed(void *opaque)
 190 {
 191     return kvm_enabled();
 192 }
 193
 194 static int cpu_post_load(void *opaque, int version_id)
 195 {
 196     RISCVCPU *cpu = opaque;
 197     CPURISCVState *env = &cpu->env;
 198
 199     env->kvm_timer_dirty = true;
 200     return 0;
 201 }
 202
 203 static const VMStateDescription vmstate_kvmtimer = {
 204     .name = "cpu/kvmtimer",
 205     .version_id = 1,
 206     .minimum_version_id = 1,
 207     .needed = kvmtimer_needed,
 208     .post_load = cpu_post_load,
 209     .fields = (VMStateField[]) {
 210         VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
 211         VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
 212         VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
 213
 214         VMSTATE_END_OF_LIST()
 215     }
 216 };
 217
 218 static int riscv_cpu_post_load(void *opaque, int version_id)
 219 {
 220     RISCVCPU *cpu = opaque;
 221     CPURISCVState *env = &cpu->env;
 222
 223     env->xl = cpu_recompute_xl(env);
 224     riscv_cpu_update_mask(env);
 225     return 0;
 226 }
 227
 228 const VMStateDescription vmstate_riscv_cpu = {
 229     .name = "cpu",
 230     .version_id = 3,
 231     .minimum_version_id = 3,
 232     .post_load = riscv_cpu_post_load,
 233     .fields = (VMStateField[]) {
 234         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
 235         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
 236         VMSTATE_UINTTL(env.pc, RISCVCPU),
 237         VMSTATE_UINTTL(env.load_res, RISCVCPU),
 238         VMSTATE_UINTTL(env.load_val, RISCVCPU),
 239         VMSTATE_UINTTL(env.frm, RISCVCPU),
 240         VMSTATE_UINTTL(env.badaddr, RISCVCPU),
 241         VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
 242         VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
 243         VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
 244         VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
 245         VMSTATE_UINT32(env.misa_ext, RISCVCPU),
 246         VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
 247         VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
 248         VMSTATE_UINT32(env.features, RISCVCPU),
 249         VMSTATE_UINTTL(env.priv, RISCVCPU),
 250         VMSTATE_UINTTL(env.virt, RISCVCPU),
 251         VMSTATE_UINTTL(env.resetvec, RISCVCPU),
 252         VMSTATE_UINTTL(env.mhartid, RISCVCPU),
 253         VMSTATE_UINT64(env.mstatus, RISCVCPU),
 254         VMSTATE_UINTTL(env.mip, RISCVCPU),
 255         VMSTATE_UINT32(env.miclaim, RISCVCPU),
 256         VMSTATE_UINTTL(env.mie, RISCVCPU),
 257         VMSTATE_UINTTL(env.mideleg, RISCVCPU),
 258         VMSTATE_UINTTL(env.satp, RISCVCPU),
 259         VMSTATE_UINTTL(env.stval, RISCVCPU),
 260         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
 261         VMSTATE_UINTTL(env.stvec, RISCVCPU),
 262         VMSTATE_UINTTL(env.sepc, RISCVCPU),
 263         VMSTATE_UINTTL(env.scause, RISCVCPU),
 264         VMSTATE_UINTTL(env.mtvec, RISCVCPU),
 265         VMSTATE_UINTTL(env.mepc, RISCVCPU),
 266         VMSTATE_UINTTL(env.mcause, RISCVCPU),
 267         VMSTATE_UINTTL(env.mtval, RISCVCPU),
 268         VMSTATE_UINTTL(env.scounteren, RISCVCPU),
 269         VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
 270         VMSTATE_UINTTL(env.sscratch, RISCVCPU),
 271         VMSTATE_UINTTL(env.mscratch, RISCVCPU),
 272         VMSTATE_UINT64(env.mfromhost, RISCVCPU),
 273         VMSTATE_UINT64(env.mtohost, RISCVCPU),
 274         VMSTATE_UINT64(env.timecmp, RISCVCPU),
 275
 276         VMSTATE_END_OF_LIST()
 277     },
 278     .subsections = (const VMStateDescription * []) {
 279         &vmstate_pmp,
 280         &vmstate_hyper,
 281         &vmstate_vector,
 282         &vmstate_pointermasking,
 283         &vmstate_rv128,
 284         &vmstate_kvmtimer,
 285         NULL
 286     }
 287 };