target/riscv/meson.build

   1 # FIXME extra_args should accept files()
   2 dir = meson.current_source_dir()
   3
   4 gen = [
   5   decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
   6   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
   7   decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
   8 ]
   9
  10 riscv_ss = ss.source_set()
  11 riscv_ss.add(gen)
  12 riscv_ss.add(files(
  13   'cpu.c',
  14   'cpu_helper.c',
  15   'csr.c',
  16   'fpu_helper.c',
  17   'gdbstub.c',
  18   'op_helper.c',
  19   'vector_helper.c',
  20   'bitmanip_helper.c',
  21   'translate.c',
  22   'm128_helper.c',
  23   'crypto_helper.c'
  24 ))
  25 riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
  26
  27 riscv_softmmu_ss = ss.source_set()
  28 riscv_softmmu_ss.add(files(
  29   'arch_dump.c',
  30   'pmp.c',
  31   'debug.c',
  32   'monitor.c',
  33   'machine.c'
  34 ))
  35
  36 target_arch += {'riscv': riscv_ss}
  37 target_softmmu_arch += {'riscv': riscv_softmmu_ss}