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2 * QEMU RISC-V PMP (Physical Memory Protection)
4 * Author: Daire McNamara, daire.mcnamara@emdalo.com
5 * Ivan Griffin, ivan.griffin@emdalo.com
7 * This provides a RISC-V Physical Memory Protection implementation
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2 or later, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
23 * PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
26 #include "qemu/osdep.h"
28 #include "qapi/error.h"
30 #include "qemu-common.h"
32 #ifndef CONFIG_USER_ONLY
34 #define RISCV_DEBUG_PMP 0
35 #define PMP_DEBUG(fmt, ...) \
37 if (RISCV_DEBUG_PMP) { \
38 qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
42 static void pmp_write_cfg(CPURISCVState
*env
, uint32_t addr_index
,
44 static uint8_t pmp_read_cfg(CPURISCVState
*env
, uint32_t addr_index
);
45 static void pmp_update_rule(CPURISCVState
*env
, uint32_t pmp_index
);
48 * Accessor method to extract address matching type 'a field' from cfg reg
50 static inline uint8_t pmp_get_a_field(uint8_t cfg
)
57 * Check whether a PMP is locked or not.
59 static inline int pmp_is_locked(CPURISCVState
*env
, uint32_t pmp_index
)
62 if (env
->pmp_state
.pmp
[pmp_index
].cfg_reg
& PMP_LOCK
) {
66 /* Top PMP has no 'next' to check */
67 if ((pmp_index
+ 1u) >= MAX_RISCV_PMPS
) {
71 /* In TOR mode, need to check the lock bit of the next pmp
72 * (if there is a next)
74 const uint8_t a_field
=
75 pmp_get_a_field(env
->pmp_state
.pmp
[pmp_index
+ 1].cfg_reg
);
76 if ((env
->pmp_state
.pmp
[pmp_index
+ 1u].cfg_reg
& PMP_LOCK
) &&
77 (PMP_AMATCH_TOR
== a_field
)) {
85 * Count the number of active rules.
87 static inline uint32_t pmp_get_num_rules(CPURISCVState
*env
)
89 return env
->pmp_state
.num_rules
;
93 * Accessor to get the cfg reg for a specific PMP/HART
95 static inline uint8_t pmp_read_cfg(CPURISCVState
*env
, uint32_t pmp_index
)
97 if (pmp_index
< MAX_RISCV_PMPS
) {
98 return env
->pmp_state
.pmp
[pmp_index
].cfg_reg
;
106 * Accessor to set the cfg reg for a specific PMP/HART
107 * Bounds checks and relevant lock bit.
109 static void pmp_write_cfg(CPURISCVState
*env
, uint32_t pmp_index
, uint8_t val
)
111 if (pmp_index
< MAX_RISCV_PMPS
) {
112 if (!pmp_is_locked(env
, pmp_index
)) {
113 env
->pmp_state
.pmp
[pmp_index
].cfg_reg
= val
;
114 pmp_update_rule(env
, pmp_index
);
116 qemu_log_mask(LOG_GUEST_ERROR
, "ignoring pmpcfg write - locked\n");
119 qemu_log_mask(LOG_GUEST_ERROR
,
120 "ignoring pmpcfg write - out of bounds\n");
124 static void pmp_decode_napot(target_ulong a
, target_ulong
*sa
, target_ulong
*ea
)
127 aaaa...aaa0 8-byte NAPOT range
128 aaaa...aa01 16-byte NAPOT range
129 aaaa...a011 32-byte NAPOT range
131 aa01...1111 2^XLEN-byte NAPOT range
132 a011...1111 2^(XLEN+1)-byte NAPOT range
133 0111...1111 2^(XLEN+2)-byte NAPOT range
141 target_ulong t1
= ctz64(~a
);
142 target_ulong base
= (a
& ~(((target_ulong
)1 << t1
) - 1)) << 2;
143 target_ulong range
= ((target_ulong
)1 << (t1
+ 3)) - 1;
150 /* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
151 * end address values.
152 * This function is called relatively infrequently whereas the check that
153 * an address is within a pmp rule is called often, so optimise that one
155 static void pmp_update_rule(CPURISCVState
*env
, uint32_t pmp_index
)
159 env
->pmp_state
.num_rules
= 0;
161 uint8_t this_cfg
= env
->pmp_state
.pmp
[pmp_index
].cfg_reg
;
162 target_ulong this_addr
= env
->pmp_state
.pmp
[pmp_index
].addr_reg
;
163 target_ulong prev_addr
= 0u;
164 target_ulong sa
= 0u;
165 target_ulong ea
= 0u;
167 if (pmp_index
>= 1u) {
168 prev_addr
= env
->pmp_state
.pmp
[pmp_index
- 1].addr_reg
;
171 switch (pmp_get_a_field(this_cfg
)) {
178 sa
= prev_addr
<< 2; /* shift up from [xx:0] to [xx+2:2] */
179 ea
= (this_addr
<< 2) - 1u;
183 sa
= this_addr
<< 2; /* shift up from [xx:0] to [xx+2:2] */
184 ea
= (this_addr
+ 4u) - 1u;
187 case PMP_AMATCH_NAPOT
:
188 pmp_decode_napot(this_addr
, &sa
, &ea
);
197 env
->pmp_state
.addr
[pmp_index
].sa
= sa
;
198 env
->pmp_state
.addr
[pmp_index
].ea
= ea
;
200 for (i
= 0; i
< MAX_RISCV_PMPS
; i
++) {
201 const uint8_t a_field
=
202 pmp_get_a_field(env
->pmp_state
.pmp
[i
].cfg_reg
);
203 if (PMP_AMATCH_OFF
!= a_field
) {
204 env
->pmp_state
.num_rules
++;
209 static int pmp_is_in_range(CPURISCVState
*env
, int pmp_index
, target_ulong addr
)
213 if ((addr
>= env
->pmp_state
.addr
[pmp_index
].sa
)
214 && (addr
<= env
->pmp_state
.addr
[pmp_index
].ea
)) {
229 * Check if the address has required RWX privs to complete desired operation
231 bool pmp_hart_has_privs(CPURISCVState
*env
, target_ulong addr
,
232 target_ulong size
, pmp_priv_t privs
)
238 pmp_priv_t allowed_privs
= 0;
240 /* Short cut if no rules */
241 if (0 == pmp_get_num_rules(env
)) {
245 /* 1.10 draft priv spec states there is an implicit order
247 for (i
= 0; i
< MAX_RISCV_PMPS
; i
++) {
248 s
= pmp_is_in_range(env
, i
, addr
);
249 e
= pmp_is_in_range(env
, i
, addr
+ size
);
251 /* partially inside */
253 qemu_log_mask(LOG_GUEST_ERROR
,
254 "pmp violation - access is partially inside\n");
260 const uint8_t a_field
=
261 pmp_get_a_field(env
->pmp_state
.pmp
[i
].cfg_reg
);
263 if (PMP_AMATCH_OFF
== a_field
) {
267 allowed_privs
= PMP_READ
| PMP_WRITE
| PMP_EXEC
;
268 if ((env
->priv
!= PRV_M
) || pmp_is_locked(env
, i
)) {
269 allowed_privs
&= env
->pmp_state
.pmp
[i
].cfg_reg
;
272 if ((privs
& allowed_privs
) == privs
) {
282 /* No rule matched */
284 if (env
->priv
== PRV_M
) {
285 ret
= 1; /* Privileged spec v1.10 states if no PMP entry matches an
286 * M-Mode access, the access succeeds */
288 ret
= 0; /* Other modes are not allowed to succeed if they don't
289 * match a rule, but there are rules. We've checked for
290 * no rule earlier in this function. */
294 return ret
== 1 ? true : false;
299 * Handle a write to a pmpcfg CSP
301 void pmpcfg_csr_write(CPURISCVState
*env
, uint32_t reg_index
,
307 PMP_DEBUG("hart " TARGET_FMT_ld
": reg%d, val: 0x" TARGET_FMT_lx
,
308 env
->mhartid
, reg_index
, val
);
310 if ((reg_index
& 1) && (sizeof(target_ulong
) == 8)) {
311 qemu_log_mask(LOG_GUEST_ERROR
,
312 "ignoring pmpcfg write - incorrect address\n");
316 for (i
= 0; i
< sizeof(target_ulong
); i
++) {
317 cfg_val
= (val
>> 8 * i
) & 0xff;
318 pmp_write_cfg(env
, (reg_index
* sizeof(target_ulong
)) + i
,
325 * Handle a read from a pmpcfg CSP
327 target_ulong
pmpcfg_csr_read(CPURISCVState
*env
, uint32_t reg_index
)
330 target_ulong cfg_val
= 0;
331 target_ulong val
= 0;
333 for (i
= 0; i
< sizeof(target_ulong
); i
++) {
334 val
= pmp_read_cfg(env
, (reg_index
* sizeof(target_ulong
)) + i
);
335 cfg_val
|= (val
<< (i
* 8));
338 PMP_DEBUG("hart " TARGET_FMT_ld
": reg%d, val: 0x" TARGET_FMT_lx
,
339 env
->mhartid
, reg_index
, cfg_val
);
346 * Handle a write to a pmpaddr CSP
348 void pmpaddr_csr_write(CPURISCVState
*env
, uint32_t addr_index
,
351 PMP_DEBUG("hart " TARGET_FMT_ld
": addr%d, val: 0x" TARGET_FMT_lx
,
352 env
->mhartid
, addr_index
, val
);
354 if (addr_index
< MAX_RISCV_PMPS
) {
355 if (!pmp_is_locked(env
, addr_index
)) {
356 env
->pmp_state
.pmp
[addr_index
].addr_reg
= val
;
357 pmp_update_rule(env
, addr_index
);
359 qemu_log_mask(LOG_GUEST_ERROR
,
360 "ignoring pmpaddr write - locked\n");
363 qemu_log_mask(LOG_GUEST_ERROR
,
364 "ignoring pmpaddr write - out of bounds\n");
370 * Handle a read from a pmpaddr CSP
372 target_ulong
pmpaddr_csr_read(CPURISCVState
*env
, uint32_t addr_index
)
374 PMP_DEBUG("hart " TARGET_FMT_ld
": addr%d, val: 0x" TARGET_FMT_lx
,
375 env
->mhartid
, addr_index
,
376 env
->pmp_state
.pmp
[addr_index
].addr_reg
);
377 if (addr_index
< MAX_RISCV_PMPS
) {
378 return env
->pmp_state
.pmp
[addr_index
].addr_reg
;
380 qemu_log_mask(LOG_GUEST_ERROR
,
381 "ignoring pmpaddr read - out of bounds\n");